2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll3 = {
43 .clkr.hw.init = &(struct clk_init_data){
45 .parent_names = (const char *[]){ "pxo" },
51 static struct clk_pll pll8 = {
59 .clkr.hw.init = &(struct clk_init_data){
61 .parent_names = (const char *[]){ "pxo" },
67 static struct clk_regmap pll8_vote = {
69 .enable_mask = BIT(8),
70 .hw.init = &(struct clk_init_data){
72 .parent_names = (const char *[]){ "pll8" },
74 .ops = &clk_pll_vote_ops,
78 static struct clk_pll pll14 = {
86 .clkr.hw.init = &(struct clk_init_data){
88 .parent_names = (const char *[]){ "pxo" },
94 static struct clk_regmap pll14_vote = {
96 .enable_mask = BIT(14),
97 .hw.init = &(struct clk_init_data){
99 .parent_names = (const char *[]){ "pll14" },
101 .ops = &clk_pll_vote_ops,
109 static const u8 gcc_pxo_pll8_map[] = {
114 static const char *gcc_pxo_pll8[] = {
119 static const u8 gcc_pxo_pll8_cxo_map[] = {
125 static const char *gcc_pxo_pll8_cxo[] = {
131 static struct freq_tbl clk_tbl_gsbi_uart[] = {
132 { 1843200, P_PLL8, 2, 6, 625 },
133 { 3686400, P_PLL8, 2, 12, 625 },
134 { 7372800, P_PLL8, 2, 24, 625 },
135 { 14745600, P_PLL8, 2, 48, 625 },
136 { 16000000, P_PLL8, 4, 1, 6 },
137 { 24000000, P_PLL8, 4, 1, 4 },
138 { 32000000, P_PLL8, 4, 1, 3 },
139 { 40000000, P_PLL8, 1, 5, 48 },
140 { 46400000, P_PLL8, 1, 29, 240 },
141 { 48000000, P_PLL8, 4, 1, 2 },
142 { 51200000, P_PLL8, 1, 2, 15 },
143 { 56000000, P_PLL8, 1, 7, 48 },
144 { 58982400, P_PLL8, 1, 96, 625 },
145 { 64000000, P_PLL8, 2, 1, 3 },
149 static struct clk_rcg gsbi1_uart_src = {
154 .mnctr_reset_bit = 7,
155 .mnctr_mode_shift = 5,
166 .parent_map = gcc_pxo_pll8_map,
168 .freq_tbl = clk_tbl_gsbi_uart,
170 .enable_reg = 0x29d4,
171 .enable_mask = BIT(11),
172 .hw.init = &(struct clk_init_data){
173 .name = "gsbi1_uart_src",
174 .parent_names = gcc_pxo_pll8,
177 .flags = CLK_SET_PARENT_GATE,
182 static struct clk_branch gsbi1_uart_clk = {
186 .enable_reg = 0x29d4,
187 .enable_mask = BIT(9),
188 .hw.init = &(struct clk_init_data){
189 .name = "gsbi1_uart_clk",
190 .parent_names = (const char *[]){
194 .ops = &clk_branch_ops,
195 .flags = CLK_SET_RATE_PARENT,
200 static struct clk_rcg gsbi2_uart_src = {
205 .mnctr_reset_bit = 7,
206 .mnctr_mode_shift = 5,
217 .parent_map = gcc_pxo_pll8_map,
219 .freq_tbl = clk_tbl_gsbi_uart,
221 .enable_reg = 0x29f4,
222 .enable_mask = BIT(11),
223 .hw.init = &(struct clk_init_data){
224 .name = "gsbi2_uart_src",
225 .parent_names = gcc_pxo_pll8,
228 .flags = CLK_SET_PARENT_GATE,
233 static struct clk_branch gsbi2_uart_clk = {
237 .enable_reg = 0x29f4,
238 .enable_mask = BIT(9),
239 .hw.init = &(struct clk_init_data){
240 .name = "gsbi2_uart_clk",
241 .parent_names = (const char *[]){
245 .ops = &clk_branch_ops,
246 .flags = CLK_SET_RATE_PARENT,
251 static struct clk_rcg gsbi3_uart_src = {
256 .mnctr_reset_bit = 7,
257 .mnctr_mode_shift = 5,
268 .parent_map = gcc_pxo_pll8_map,
270 .freq_tbl = clk_tbl_gsbi_uart,
272 .enable_reg = 0x2a14,
273 .enable_mask = BIT(11),
274 .hw.init = &(struct clk_init_data){
275 .name = "gsbi3_uart_src",
276 .parent_names = gcc_pxo_pll8,
279 .flags = CLK_SET_PARENT_GATE,
284 static struct clk_branch gsbi3_uart_clk = {
288 .enable_reg = 0x2a14,
289 .enable_mask = BIT(9),
290 .hw.init = &(struct clk_init_data){
291 .name = "gsbi3_uart_clk",
292 .parent_names = (const char *[]){
296 .ops = &clk_branch_ops,
297 .flags = CLK_SET_RATE_PARENT,
302 static struct clk_rcg gsbi4_uart_src = {
307 .mnctr_reset_bit = 7,
308 .mnctr_mode_shift = 5,
319 .parent_map = gcc_pxo_pll8_map,
321 .freq_tbl = clk_tbl_gsbi_uart,
323 .enable_reg = 0x2a34,
324 .enable_mask = BIT(11),
325 .hw.init = &(struct clk_init_data){
326 .name = "gsbi4_uart_src",
327 .parent_names = gcc_pxo_pll8,
330 .flags = CLK_SET_PARENT_GATE,
335 static struct clk_branch gsbi4_uart_clk = {
339 .enable_reg = 0x2a34,
340 .enable_mask = BIT(9),
341 .hw.init = &(struct clk_init_data){
342 .name = "gsbi4_uart_clk",
343 .parent_names = (const char *[]){
347 .ops = &clk_branch_ops,
348 .flags = CLK_SET_RATE_PARENT,
353 static struct clk_rcg gsbi5_uart_src = {
358 .mnctr_reset_bit = 7,
359 .mnctr_mode_shift = 5,
370 .parent_map = gcc_pxo_pll8_map,
372 .freq_tbl = clk_tbl_gsbi_uart,
374 .enable_reg = 0x2a54,
375 .enable_mask = BIT(11),
376 .hw.init = &(struct clk_init_data){
377 .name = "gsbi5_uart_src",
378 .parent_names = gcc_pxo_pll8,
381 .flags = CLK_SET_PARENT_GATE,
386 static struct clk_branch gsbi5_uart_clk = {
390 .enable_reg = 0x2a54,
391 .enable_mask = BIT(9),
392 .hw.init = &(struct clk_init_data){
393 .name = "gsbi5_uart_clk",
394 .parent_names = (const char *[]){
398 .ops = &clk_branch_ops,
399 .flags = CLK_SET_RATE_PARENT,
404 static struct clk_rcg gsbi6_uart_src = {
409 .mnctr_reset_bit = 7,
410 .mnctr_mode_shift = 5,
421 .parent_map = gcc_pxo_pll8_map,
423 .freq_tbl = clk_tbl_gsbi_uart,
425 .enable_reg = 0x2a74,
426 .enable_mask = BIT(11),
427 .hw.init = &(struct clk_init_data){
428 .name = "gsbi6_uart_src",
429 .parent_names = gcc_pxo_pll8,
432 .flags = CLK_SET_PARENT_GATE,
437 static struct clk_branch gsbi6_uart_clk = {
441 .enable_reg = 0x2a74,
442 .enable_mask = BIT(9),
443 .hw.init = &(struct clk_init_data){
444 .name = "gsbi6_uart_clk",
445 .parent_names = (const char *[]){
449 .ops = &clk_branch_ops,
450 .flags = CLK_SET_RATE_PARENT,
455 static struct clk_rcg gsbi7_uart_src = {
460 .mnctr_reset_bit = 7,
461 .mnctr_mode_shift = 5,
472 .parent_map = gcc_pxo_pll8_map,
474 .freq_tbl = clk_tbl_gsbi_uart,
476 .enable_reg = 0x2a94,
477 .enable_mask = BIT(11),
478 .hw.init = &(struct clk_init_data){
479 .name = "gsbi7_uart_src",
480 .parent_names = gcc_pxo_pll8,
483 .flags = CLK_SET_PARENT_GATE,
488 static struct clk_branch gsbi7_uart_clk = {
492 .enable_reg = 0x2a94,
493 .enable_mask = BIT(9),
494 .hw.init = &(struct clk_init_data){
495 .name = "gsbi7_uart_clk",
496 .parent_names = (const char *[]){
500 .ops = &clk_branch_ops,
501 .flags = CLK_SET_RATE_PARENT,
506 static struct clk_rcg gsbi8_uart_src = {
511 .mnctr_reset_bit = 7,
512 .mnctr_mode_shift = 5,
523 .parent_map = gcc_pxo_pll8_map,
525 .freq_tbl = clk_tbl_gsbi_uart,
527 .enable_reg = 0x2ab4,
528 .enable_mask = BIT(11),
529 .hw.init = &(struct clk_init_data){
530 .name = "gsbi8_uart_src",
531 .parent_names = gcc_pxo_pll8,
534 .flags = CLK_SET_PARENT_GATE,
539 static struct clk_branch gsbi8_uart_clk = {
543 .enable_reg = 0x2ab4,
544 .enable_mask = BIT(9),
545 .hw.init = &(struct clk_init_data){
546 .name = "gsbi8_uart_clk",
547 .parent_names = (const char *[]){ "gsbi8_uart_src" },
549 .ops = &clk_branch_ops,
550 .flags = CLK_SET_RATE_PARENT,
555 static struct clk_rcg gsbi9_uart_src = {
560 .mnctr_reset_bit = 7,
561 .mnctr_mode_shift = 5,
572 .parent_map = gcc_pxo_pll8_map,
574 .freq_tbl = clk_tbl_gsbi_uart,
576 .enable_reg = 0x2ad4,
577 .enable_mask = BIT(11),
578 .hw.init = &(struct clk_init_data){
579 .name = "gsbi9_uart_src",
580 .parent_names = gcc_pxo_pll8,
583 .flags = CLK_SET_PARENT_GATE,
588 static struct clk_branch gsbi9_uart_clk = {
592 .enable_reg = 0x2ad4,
593 .enable_mask = BIT(9),
594 .hw.init = &(struct clk_init_data){
595 .name = "gsbi9_uart_clk",
596 .parent_names = (const char *[]){ "gsbi9_uart_src" },
598 .ops = &clk_branch_ops,
599 .flags = CLK_SET_RATE_PARENT,
604 static struct clk_rcg gsbi10_uart_src = {
609 .mnctr_reset_bit = 7,
610 .mnctr_mode_shift = 5,
621 .parent_map = gcc_pxo_pll8_map,
623 .freq_tbl = clk_tbl_gsbi_uart,
625 .enable_reg = 0x2af4,
626 .enable_mask = BIT(11),
627 .hw.init = &(struct clk_init_data){
628 .name = "gsbi10_uart_src",
629 .parent_names = gcc_pxo_pll8,
632 .flags = CLK_SET_PARENT_GATE,
637 static struct clk_branch gsbi10_uart_clk = {
641 .enable_reg = 0x2af4,
642 .enable_mask = BIT(9),
643 .hw.init = &(struct clk_init_data){
644 .name = "gsbi10_uart_clk",
645 .parent_names = (const char *[]){ "gsbi10_uart_src" },
647 .ops = &clk_branch_ops,
648 .flags = CLK_SET_RATE_PARENT,
653 static struct clk_rcg gsbi11_uart_src = {
658 .mnctr_reset_bit = 7,
659 .mnctr_mode_shift = 5,
670 .parent_map = gcc_pxo_pll8_map,
672 .freq_tbl = clk_tbl_gsbi_uart,
674 .enable_reg = 0x2b14,
675 .enable_mask = BIT(11),
676 .hw.init = &(struct clk_init_data){
677 .name = "gsbi11_uart_src",
678 .parent_names = gcc_pxo_pll8,
681 .flags = CLK_SET_PARENT_GATE,
686 static struct clk_branch gsbi11_uart_clk = {
690 .enable_reg = 0x2b14,
691 .enable_mask = BIT(9),
692 .hw.init = &(struct clk_init_data){
693 .name = "gsbi11_uart_clk",
694 .parent_names = (const char *[]){ "gsbi11_uart_src" },
696 .ops = &clk_branch_ops,
697 .flags = CLK_SET_RATE_PARENT,
702 static struct clk_rcg gsbi12_uart_src = {
707 .mnctr_reset_bit = 7,
708 .mnctr_mode_shift = 5,
719 .parent_map = gcc_pxo_pll8_map,
721 .freq_tbl = clk_tbl_gsbi_uart,
723 .enable_reg = 0x2b34,
724 .enable_mask = BIT(11),
725 .hw.init = &(struct clk_init_data){
726 .name = "gsbi12_uart_src",
727 .parent_names = gcc_pxo_pll8,
730 .flags = CLK_SET_PARENT_GATE,
735 static struct clk_branch gsbi12_uart_clk = {
739 .enable_reg = 0x2b34,
740 .enable_mask = BIT(9),
741 .hw.init = &(struct clk_init_data){
742 .name = "gsbi12_uart_clk",
743 .parent_names = (const char *[]){ "gsbi12_uart_src" },
745 .ops = &clk_branch_ops,
746 .flags = CLK_SET_RATE_PARENT,
751 static struct freq_tbl clk_tbl_gsbi_qup[] = {
752 { 1100000, P_PXO, 1, 2, 49 },
753 { 5400000, P_PXO, 1, 1, 5 },
754 { 10800000, P_PXO, 1, 2, 5 },
755 { 15060000, P_PLL8, 1, 2, 51 },
756 { 24000000, P_PLL8, 4, 1, 4 },
757 { 25600000, P_PLL8, 1, 1, 15 },
758 { 27000000, P_PXO, 1, 0, 0 },
759 { 48000000, P_PLL8, 4, 1, 2 },
760 { 51200000, P_PLL8, 1, 2, 15 },
764 static struct clk_rcg gsbi1_qup_src = {
769 .mnctr_reset_bit = 7,
770 .mnctr_mode_shift = 5,
781 .parent_map = gcc_pxo_pll8_map,
783 .freq_tbl = clk_tbl_gsbi_qup,
785 .enable_reg = 0x29cc,
786 .enable_mask = BIT(11),
787 .hw.init = &(struct clk_init_data){
788 .name = "gsbi1_qup_src",
789 .parent_names = gcc_pxo_pll8,
792 .flags = CLK_SET_PARENT_GATE,
797 static struct clk_branch gsbi1_qup_clk = {
801 .enable_reg = 0x29cc,
802 .enable_mask = BIT(9),
803 .hw.init = &(struct clk_init_data){
804 .name = "gsbi1_qup_clk",
805 .parent_names = (const char *[]){ "gsbi1_qup_src" },
807 .ops = &clk_branch_ops,
808 .flags = CLK_SET_RATE_PARENT,
813 static struct clk_rcg gsbi2_qup_src = {
818 .mnctr_reset_bit = 7,
819 .mnctr_mode_shift = 5,
830 .parent_map = gcc_pxo_pll8_map,
832 .freq_tbl = clk_tbl_gsbi_qup,
834 .enable_reg = 0x29ec,
835 .enable_mask = BIT(11),
836 .hw.init = &(struct clk_init_data){
837 .name = "gsbi2_qup_src",
838 .parent_names = gcc_pxo_pll8,
841 .flags = CLK_SET_PARENT_GATE,
846 static struct clk_branch gsbi2_qup_clk = {
850 .enable_reg = 0x29ec,
851 .enable_mask = BIT(9),
852 .hw.init = &(struct clk_init_data){
853 .name = "gsbi2_qup_clk",
854 .parent_names = (const char *[]){ "gsbi2_qup_src" },
856 .ops = &clk_branch_ops,
857 .flags = CLK_SET_RATE_PARENT,
862 static struct clk_rcg gsbi3_qup_src = {
867 .mnctr_reset_bit = 7,
868 .mnctr_mode_shift = 5,
879 .parent_map = gcc_pxo_pll8_map,
881 .freq_tbl = clk_tbl_gsbi_qup,
883 .enable_reg = 0x2a0c,
884 .enable_mask = BIT(11),
885 .hw.init = &(struct clk_init_data){
886 .name = "gsbi3_qup_src",
887 .parent_names = gcc_pxo_pll8,
890 .flags = CLK_SET_PARENT_GATE,
895 static struct clk_branch gsbi3_qup_clk = {
899 .enable_reg = 0x2a0c,
900 .enable_mask = BIT(9),
901 .hw.init = &(struct clk_init_data){
902 .name = "gsbi3_qup_clk",
903 .parent_names = (const char *[]){ "gsbi3_qup_src" },
905 .ops = &clk_branch_ops,
906 .flags = CLK_SET_RATE_PARENT,
911 static struct clk_rcg gsbi4_qup_src = {
916 .mnctr_reset_bit = 7,
917 .mnctr_mode_shift = 5,
928 .parent_map = gcc_pxo_pll8_map,
930 .freq_tbl = clk_tbl_gsbi_qup,
932 .enable_reg = 0x2a2c,
933 .enable_mask = BIT(11),
934 .hw.init = &(struct clk_init_data){
935 .name = "gsbi4_qup_src",
936 .parent_names = gcc_pxo_pll8,
939 .flags = CLK_SET_PARENT_GATE,
944 static struct clk_branch gsbi4_qup_clk = {
948 .enable_reg = 0x2a2c,
949 .enable_mask = BIT(9),
950 .hw.init = &(struct clk_init_data){
951 .name = "gsbi4_qup_clk",
952 .parent_names = (const char *[]){ "gsbi4_qup_src" },
954 .ops = &clk_branch_ops,
955 .flags = CLK_SET_RATE_PARENT,
960 static struct clk_rcg gsbi5_qup_src = {
965 .mnctr_reset_bit = 7,
966 .mnctr_mode_shift = 5,
977 .parent_map = gcc_pxo_pll8_map,
979 .freq_tbl = clk_tbl_gsbi_qup,
981 .enable_reg = 0x2a4c,
982 .enable_mask = BIT(11),
983 .hw.init = &(struct clk_init_data){
984 .name = "gsbi5_qup_src",
985 .parent_names = gcc_pxo_pll8,
988 .flags = CLK_SET_PARENT_GATE,
993 static struct clk_branch gsbi5_qup_clk = {
997 .enable_reg = 0x2a4c,
998 .enable_mask = BIT(9),
999 .hw.init = &(struct clk_init_data){
1000 .name = "gsbi5_qup_clk",
1001 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1003 .ops = &clk_branch_ops,
1004 .flags = CLK_SET_RATE_PARENT,
1009 static struct clk_rcg gsbi6_qup_src = {
1014 .mnctr_reset_bit = 7,
1015 .mnctr_mode_shift = 5,
1026 .parent_map = gcc_pxo_pll8_map,
1028 .freq_tbl = clk_tbl_gsbi_qup,
1030 .enable_reg = 0x2a6c,
1031 .enable_mask = BIT(11),
1032 .hw.init = &(struct clk_init_data){
1033 .name = "gsbi6_qup_src",
1034 .parent_names = gcc_pxo_pll8,
1036 .ops = &clk_rcg_ops,
1037 .flags = CLK_SET_PARENT_GATE,
1042 static struct clk_branch gsbi6_qup_clk = {
1046 .enable_reg = 0x2a6c,
1047 .enable_mask = BIT(9),
1048 .hw.init = &(struct clk_init_data){
1049 .name = "gsbi6_qup_clk",
1050 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1052 .ops = &clk_branch_ops,
1053 .flags = CLK_SET_RATE_PARENT,
1058 static struct clk_rcg gsbi7_qup_src = {
1063 .mnctr_reset_bit = 7,
1064 .mnctr_mode_shift = 5,
1075 .parent_map = gcc_pxo_pll8_map,
1077 .freq_tbl = clk_tbl_gsbi_qup,
1079 .enable_reg = 0x2a8c,
1080 .enable_mask = BIT(11),
1081 .hw.init = &(struct clk_init_data){
1082 .name = "gsbi7_qup_src",
1083 .parent_names = gcc_pxo_pll8,
1085 .ops = &clk_rcg_ops,
1086 .flags = CLK_SET_PARENT_GATE,
1091 static struct clk_branch gsbi7_qup_clk = {
1095 .enable_reg = 0x2a8c,
1096 .enable_mask = BIT(9),
1097 .hw.init = &(struct clk_init_data){
1098 .name = "gsbi7_qup_clk",
1099 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1101 .ops = &clk_branch_ops,
1102 .flags = CLK_SET_RATE_PARENT,
1107 static struct clk_rcg gsbi8_qup_src = {
1112 .mnctr_reset_bit = 7,
1113 .mnctr_mode_shift = 5,
1124 .parent_map = gcc_pxo_pll8_map,
1126 .freq_tbl = clk_tbl_gsbi_qup,
1128 .enable_reg = 0x2aac,
1129 .enable_mask = BIT(11),
1130 .hw.init = &(struct clk_init_data){
1131 .name = "gsbi8_qup_src",
1132 .parent_names = gcc_pxo_pll8,
1134 .ops = &clk_rcg_ops,
1135 .flags = CLK_SET_PARENT_GATE,
1140 static struct clk_branch gsbi8_qup_clk = {
1144 .enable_reg = 0x2aac,
1145 .enable_mask = BIT(9),
1146 .hw.init = &(struct clk_init_data){
1147 .name = "gsbi8_qup_clk",
1148 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1150 .ops = &clk_branch_ops,
1151 .flags = CLK_SET_RATE_PARENT,
1156 static struct clk_rcg gsbi9_qup_src = {
1161 .mnctr_reset_bit = 7,
1162 .mnctr_mode_shift = 5,
1173 .parent_map = gcc_pxo_pll8_map,
1175 .freq_tbl = clk_tbl_gsbi_qup,
1177 .enable_reg = 0x2acc,
1178 .enable_mask = BIT(11),
1179 .hw.init = &(struct clk_init_data){
1180 .name = "gsbi9_qup_src",
1181 .parent_names = gcc_pxo_pll8,
1183 .ops = &clk_rcg_ops,
1184 .flags = CLK_SET_PARENT_GATE,
1189 static struct clk_branch gsbi9_qup_clk = {
1193 .enable_reg = 0x2acc,
1194 .enable_mask = BIT(9),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "gsbi9_qup_clk",
1197 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1199 .ops = &clk_branch_ops,
1200 .flags = CLK_SET_RATE_PARENT,
1205 static struct clk_rcg gsbi10_qup_src = {
1210 .mnctr_reset_bit = 7,
1211 .mnctr_mode_shift = 5,
1222 .parent_map = gcc_pxo_pll8_map,
1224 .freq_tbl = clk_tbl_gsbi_qup,
1226 .enable_reg = 0x2aec,
1227 .enable_mask = BIT(11),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "gsbi10_qup_src",
1230 .parent_names = gcc_pxo_pll8,
1232 .ops = &clk_rcg_ops,
1233 .flags = CLK_SET_PARENT_GATE,
1238 static struct clk_branch gsbi10_qup_clk = {
1242 .enable_reg = 0x2aec,
1243 .enable_mask = BIT(9),
1244 .hw.init = &(struct clk_init_data){
1245 .name = "gsbi10_qup_clk",
1246 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1248 .ops = &clk_branch_ops,
1249 .flags = CLK_SET_RATE_PARENT,
1254 static struct clk_rcg gsbi11_qup_src = {
1259 .mnctr_reset_bit = 7,
1260 .mnctr_mode_shift = 5,
1271 .parent_map = gcc_pxo_pll8_map,
1273 .freq_tbl = clk_tbl_gsbi_qup,
1275 .enable_reg = 0x2b0c,
1276 .enable_mask = BIT(11),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gsbi11_qup_src",
1279 .parent_names = gcc_pxo_pll8,
1281 .ops = &clk_rcg_ops,
1282 .flags = CLK_SET_PARENT_GATE,
1287 static struct clk_branch gsbi11_qup_clk = {
1291 .enable_reg = 0x2b0c,
1292 .enable_mask = BIT(9),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "gsbi11_qup_clk",
1295 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1297 .ops = &clk_branch_ops,
1298 .flags = CLK_SET_RATE_PARENT,
1303 static struct clk_rcg gsbi12_qup_src = {
1308 .mnctr_reset_bit = 7,
1309 .mnctr_mode_shift = 5,
1320 .parent_map = gcc_pxo_pll8_map,
1322 .freq_tbl = clk_tbl_gsbi_qup,
1324 .enable_reg = 0x2b2c,
1325 .enable_mask = BIT(11),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "gsbi12_qup_src",
1328 .parent_names = gcc_pxo_pll8,
1330 .ops = &clk_rcg_ops,
1331 .flags = CLK_SET_PARENT_GATE,
1336 static struct clk_branch gsbi12_qup_clk = {
1340 .enable_reg = 0x2b2c,
1341 .enable_mask = BIT(9),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "gsbi12_qup_clk",
1344 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1346 .ops = &clk_branch_ops,
1347 .flags = CLK_SET_RATE_PARENT,
1352 static const struct freq_tbl clk_tbl_gp[] = {
1353 { 9600000, P_CXO, 2, 0, 0 },
1354 { 13500000, P_PXO, 2, 0, 0 },
1355 { 19200000, P_CXO, 1, 0, 0 },
1356 { 27000000, P_PXO, 1, 0, 0 },
1357 { 64000000, P_PLL8, 2, 1, 3 },
1358 { 76800000, P_PLL8, 1, 1, 5 },
1359 { 96000000, P_PLL8, 4, 0, 0 },
1360 { 128000000, P_PLL8, 3, 0, 0 },
1361 { 192000000, P_PLL8, 2, 0, 0 },
1365 static struct clk_rcg gp0_src = {
1370 .mnctr_reset_bit = 7,
1371 .mnctr_mode_shift = 5,
1382 .parent_map = gcc_pxo_pll8_cxo_map,
1384 .freq_tbl = clk_tbl_gp,
1386 .enable_reg = 0x2d24,
1387 .enable_mask = BIT(11),
1388 .hw.init = &(struct clk_init_data){
1390 .parent_names = gcc_pxo_pll8_cxo,
1392 .ops = &clk_rcg_ops,
1393 .flags = CLK_SET_PARENT_GATE,
1398 static struct clk_branch gp0_clk = {
1402 .enable_reg = 0x2d24,
1403 .enable_mask = BIT(9),
1404 .hw.init = &(struct clk_init_data){
1406 .parent_names = (const char *[]){ "gp0_src" },
1408 .ops = &clk_branch_ops,
1409 .flags = CLK_SET_RATE_PARENT,
1414 static struct clk_rcg gp1_src = {
1419 .mnctr_reset_bit = 7,
1420 .mnctr_mode_shift = 5,
1431 .parent_map = gcc_pxo_pll8_cxo_map,
1433 .freq_tbl = clk_tbl_gp,
1435 .enable_reg = 0x2d44,
1436 .enable_mask = BIT(11),
1437 .hw.init = &(struct clk_init_data){
1439 .parent_names = gcc_pxo_pll8_cxo,
1441 .ops = &clk_rcg_ops,
1442 .flags = CLK_SET_RATE_GATE,
1447 static struct clk_branch gp1_clk = {
1451 .enable_reg = 0x2d44,
1452 .enable_mask = BIT(9),
1453 .hw.init = &(struct clk_init_data){
1455 .parent_names = (const char *[]){ "gp1_src" },
1457 .ops = &clk_branch_ops,
1458 .flags = CLK_SET_RATE_PARENT,
1463 static struct clk_rcg gp2_src = {
1468 .mnctr_reset_bit = 7,
1469 .mnctr_mode_shift = 5,
1480 .parent_map = gcc_pxo_pll8_cxo_map,
1482 .freq_tbl = clk_tbl_gp,
1484 .enable_reg = 0x2d64,
1485 .enable_mask = BIT(11),
1486 .hw.init = &(struct clk_init_data){
1488 .parent_names = gcc_pxo_pll8_cxo,
1490 .ops = &clk_rcg_ops,
1491 .flags = CLK_SET_RATE_GATE,
1496 static struct clk_branch gp2_clk = {
1500 .enable_reg = 0x2d64,
1501 .enable_mask = BIT(9),
1502 .hw.init = &(struct clk_init_data){
1504 .parent_names = (const char *[]){ "gp2_src" },
1506 .ops = &clk_branch_ops,
1507 .flags = CLK_SET_RATE_PARENT,
1512 static struct clk_branch pmem_clk = {
1518 .enable_reg = 0x25a0,
1519 .enable_mask = BIT(4),
1520 .hw.init = &(struct clk_init_data){
1522 .ops = &clk_branch_ops,
1523 .flags = CLK_IS_ROOT,
1528 static struct clk_rcg prng_src = {
1536 .parent_map = gcc_pxo_pll8_map,
1539 .hw.init = &(struct clk_init_data){
1541 .parent_names = gcc_pxo_pll8,
1543 .ops = &clk_rcg_ops,
1548 static struct clk_branch prng_clk = {
1550 .halt_check = BRANCH_HALT_VOTED,
1553 .enable_reg = 0x3080,
1554 .enable_mask = BIT(10),
1555 .hw.init = &(struct clk_init_data){
1557 .parent_names = (const char *[]){ "prng_src" },
1559 .ops = &clk_branch_ops,
1564 static const struct freq_tbl clk_tbl_sdc[] = {
1565 { 144000, P_PXO, 3, 2, 125 },
1566 { 400000, P_PLL8, 4, 1, 240 },
1567 { 16000000, P_PLL8, 4, 1, 6 },
1568 { 17070000, P_PLL8, 1, 2, 45 },
1569 { 20210000, P_PLL8, 1, 1, 19 },
1570 { 24000000, P_PLL8, 4, 1, 4 },
1571 { 48000000, P_PLL8, 4, 1, 2 },
1572 { 64000000, P_PLL8, 3, 1, 2 },
1573 { 96000000, P_PLL8, 4, 0, 0 },
1574 { 192000000, P_PLL8, 2, 0, 0 },
1578 static struct clk_rcg sdc1_src = {
1583 .mnctr_reset_bit = 7,
1584 .mnctr_mode_shift = 5,
1595 .parent_map = gcc_pxo_pll8_map,
1597 .freq_tbl = clk_tbl_sdc,
1599 .enable_reg = 0x282c,
1600 .enable_mask = BIT(11),
1601 .hw.init = &(struct clk_init_data){
1603 .parent_names = gcc_pxo_pll8,
1605 .ops = &clk_rcg_ops,
1606 .flags = CLK_SET_RATE_GATE,
1611 static struct clk_branch sdc1_clk = {
1615 .enable_reg = 0x282c,
1616 .enable_mask = BIT(9),
1617 .hw.init = &(struct clk_init_data){
1619 .parent_names = (const char *[]){ "sdc1_src" },
1621 .ops = &clk_branch_ops,
1622 .flags = CLK_SET_RATE_PARENT,
1627 static struct clk_rcg sdc2_src = {
1632 .mnctr_reset_bit = 7,
1633 .mnctr_mode_shift = 5,
1644 .parent_map = gcc_pxo_pll8_map,
1646 .freq_tbl = clk_tbl_sdc,
1648 .enable_reg = 0x284c,
1649 .enable_mask = BIT(11),
1650 .hw.init = &(struct clk_init_data){
1652 .parent_names = gcc_pxo_pll8,
1654 .ops = &clk_rcg_ops,
1655 .flags = CLK_SET_RATE_GATE,
1660 static struct clk_branch sdc2_clk = {
1664 .enable_reg = 0x284c,
1665 .enable_mask = BIT(9),
1666 .hw.init = &(struct clk_init_data){
1668 .parent_names = (const char *[]){ "sdc2_src" },
1670 .ops = &clk_branch_ops,
1671 .flags = CLK_SET_RATE_PARENT,
1676 static struct clk_rcg sdc3_src = {
1681 .mnctr_reset_bit = 7,
1682 .mnctr_mode_shift = 5,
1693 .parent_map = gcc_pxo_pll8_map,
1695 .freq_tbl = clk_tbl_sdc,
1697 .enable_reg = 0x286c,
1698 .enable_mask = BIT(11),
1699 .hw.init = &(struct clk_init_data){
1701 .parent_names = gcc_pxo_pll8,
1703 .ops = &clk_rcg_ops,
1704 .flags = CLK_SET_RATE_GATE,
1709 static struct clk_branch sdc3_clk = {
1713 .enable_reg = 0x286c,
1714 .enable_mask = BIT(9),
1715 .hw.init = &(struct clk_init_data){
1717 .parent_names = (const char *[]){ "sdc3_src" },
1719 .ops = &clk_branch_ops,
1720 .flags = CLK_SET_RATE_PARENT,
1725 static struct clk_rcg sdc4_src = {
1730 .mnctr_reset_bit = 7,
1731 .mnctr_mode_shift = 5,
1742 .parent_map = gcc_pxo_pll8_map,
1744 .freq_tbl = clk_tbl_sdc,
1746 .enable_reg = 0x288c,
1747 .enable_mask = BIT(11),
1748 .hw.init = &(struct clk_init_data){
1750 .parent_names = gcc_pxo_pll8,
1752 .ops = &clk_rcg_ops,
1753 .flags = CLK_SET_RATE_GATE,
1758 static struct clk_branch sdc4_clk = {
1762 .enable_reg = 0x288c,
1763 .enable_mask = BIT(9),
1764 .hw.init = &(struct clk_init_data){
1766 .parent_names = (const char *[]){ "sdc4_src" },
1768 .ops = &clk_branch_ops,
1769 .flags = CLK_SET_RATE_PARENT,
1774 static struct clk_rcg sdc5_src = {
1779 .mnctr_reset_bit = 7,
1780 .mnctr_mode_shift = 5,
1791 .parent_map = gcc_pxo_pll8_map,
1793 .freq_tbl = clk_tbl_sdc,
1795 .enable_reg = 0x28ac,
1796 .enable_mask = BIT(11),
1797 .hw.init = &(struct clk_init_data){
1799 .parent_names = gcc_pxo_pll8,
1801 .ops = &clk_rcg_ops,
1802 .flags = CLK_SET_RATE_GATE,
1807 static struct clk_branch sdc5_clk = {
1811 .enable_reg = 0x28ac,
1812 .enable_mask = BIT(9),
1813 .hw.init = &(struct clk_init_data){
1815 .parent_names = (const char *[]){ "sdc5_src" },
1817 .ops = &clk_branch_ops,
1818 .flags = CLK_SET_RATE_PARENT,
1823 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1824 { 105000, P_PXO, 1, 1, 256 },
1828 static struct clk_rcg tsif_ref_src = {
1833 .mnctr_reset_bit = 7,
1834 .mnctr_mode_shift = 5,
1845 .parent_map = gcc_pxo_pll8_map,
1847 .freq_tbl = clk_tbl_tsif_ref,
1849 .enable_reg = 0x2710,
1850 .enable_mask = BIT(11),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "tsif_ref_src",
1853 .parent_names = gcc_pxo_pll8,
1855 .ops = &clk_rcg_ops,
1856 .flags = CLK_SET_RATE_GATE,
1861 static struct clk_branch tsif_ref_clk = {
1865 .enable_reg = 0x2710,
1866 .enable_mask = BIT(9),
1867 .hw.init = &(struct clk_init_data){
1868 .name = "tsif_ref_clk",
1869 .parent_names = (const char *[]){ "tsif_ref_src" },
1871 .ops = &clk_branch_ops,
1872 .flags = CLK_SET_RATE_PARENT,
1877 static const struct freq_tbl clk_tbl_usb[] = {
1878 { 60000000, P_PLL8, 1, 5, 32 },
1882 static struct clk_rcg usb_hs1_xcvr_src = {
1887 .mnctr_reset_bit = 7,
1888 .mnctr_mode_shift = 5,
1899 .parent_map = gcc_pxo_pll8_map,
1901 .freq_tbl = clk_tbl_usb,
1903 .enable_reg = 0x290c,
1904 .enable_mask = BIT(11),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "usb_hs1_xcvr_src",
1907 .parent_names = gcc_pxo_pll8,
1909 .ops = &clk_rcg_ops,
1910 .flags = CLK_SET_RATE_GATE,
1915 static struct clk_branch usb_hs1_xcvr_clk = {
1919 .enable_reg = 0x290c,
1920 .enable_mask = BIT(9),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "usb_hs1_xcvr_clk",
1923 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1925 .ops = &clk_branch_ops,
1926 .flags = CLK_SET_RATE_PARENT,
1931 static struct clk_rcg usb_hsic_xcvr_fs_src = {
1936 .mnctr_reset_bit = 7,
1937 .mnctr_mode_shift = 5,
1948 .parent_map = gcc_pxo_pll8_map,
1950 .freq_tbl = clk_tbl_usb,
1952 .enable_reg = 0x2928,
1953 .enable_mask = BIT(11),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "usb_hsic_xcvr_fs_src",
1956 .parent_names = gcc_pxo_pll8,
1958 .ops = &clk_rcg_ops,
1959 .flags = CLK_SET_RATE_GATE,
1964 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
1966 static struct clk_branch usb_hsic_xcvr_fs_clk = {
1970 .enable_reg = 0x2928,
1971 .enable_mask = BIT(9),
1972 .hw.init = &(struct clk_init_data){
1973 .name = "usb_hsic_xcvr_fs_clk",
1974 .parent_names = usb_hsic_xcvr_fs_src_p,
1976 .ops = &clk_branch_ops,
1977 .flags = CLK_SET_RATE_PARENT,
1982 static struct clk_branch usb_hsic_system_clk = {
1986 .enable_reg = 0x292c,
1987 .enable_mask = BIT(4),
1988 .hw.init = &(struct clk_init_data){
1989 .parent_names = usb_hsic_xcvr_fs_src_p,
1991 .name = "usb_hsic_system_clk",
1992 .ops = &clk_branch_ops,
1993 .flags = CLK_SET_RATE_PARENT,
1998 static struct clk_branch usb_hsic_hsic_clk = {
2002 .enable_reg = 0x2b44,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data){
2005 .parent_names = (const char *[]){ "pll14_vote" },
2007 .name = "usb_hsic_hsic_clk",
2008 .ops = &clk_branch_ops,
2013 static struct clk_branch usb_hsic_hsio_cal_clk = {
2017 .enable_reg = 0x2b48,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "usb_hsic_hsio_cal_clk",
2021 .ops = &clk_branch_ops,
2022 .flags = CLK_IS_ROOT,
2027 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2032 .mnctr_reset_bit = 7,
2033 .mnctr_mode_shift = 5,
2044 .parent_map = gcc_pxo_pll8_map,
2046 .freq_tbl = clk_tbl_usb,
2048 .enable_reg = 0x2968,
2049 .enable_mask = BIT(11),
2050 .hw.init = &(struct clk_init_data){
2051 .name = "usb_fs1_xcvr_fs_src",
2052 .parent_names = gcc_pxo_pll8,
2054 .ops = &clk_rcg_ops,
2055 .flags = CLK_SET_RATE_GATE,
2060 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2062 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2066 .enable_reg = 0x2968,
2067 .enable_mask = BIT(9),
2068 .hw.init = &(struct clk_init_data){
2069 .name = "usb_fs1_xcvr_fs_clk",
2070 .parent_names = usb_fs1_xcvr_fs_src_p,
2072 .ops = &clk_branch_ops,
2073 .flags = CLK_SET_RATE_PARENT,
2078 static struct clk_branch usb_fs1_system_clk = {
2082 .enable_reg = 0x296c,
2083 .enable_mask = BIT(4),
2084 .hw.init = &(struct clk_init_data){
2085 .parent_names = usb_fs1_xcvr_fs_src_p,
2087 .name = "usb_fs1_system_clk",
2088 .ops = &clk_branch_ops,
2089 .flags = CLK_SET_RATE_PARENT,
2094 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2099 .mnctr_reset_bit = 7,
2100 .mnctr_mode_shift = 5,
2111 .parent_map = gcc_pxo_pll8_map,
2113 .freq_tbl = clk_tbl_usb,
2115 .enable_reg = 0x2988,
2116 .enable_mask = BIT(11),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "usb_fs2_xcvr_fs_src",
2119 .parent_names = gcc_pxo_pll8,
2121 .ops = &clk_rcg_ops,
2122 .flags = CLK_SET_RATE_GATE,
2127 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2129 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2133 .enable_reg = 0x2988,
2134 .enable_mask = BIT(9),
2135 .hw.init = &(struct clk_init_data){
2136 .name = "usb_fs2_xcvr_fs_clk",
2137 .parent_names = usb_fs2_xcvr_fs_src_p,
2139 .ops = &clk_branch_ops,
2140 .flags = CLK_SET_RATE_PARENT,
2145 static struct clk_branch usb_fs2_system_clk = {
2149 .enable_reg = 0x298c,
2150 .enable_mask = BIT(4),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "usb_fs2_system_clk",
2153 .parent_names = usb_fs2_xcvr_fs_src_p,
2155 .ops = &clk_branch_ops,
2156 .flags = CLK_SET_RATE_PARENT,
2161 static struct clk_branch ce1_core_clk = {
2167 .enable_reg = 0x2724,
2168 .enable_mask = BIT(4),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "ce1_core_clk",
2171 .ops = &clk_branch_ops,
2172 .flags = CLK_IS_ROOT,
2177 static struct clk_branch ce1_h_clk = {
2181 .enable_reg = 0x2720,
2182 .enable_mask = BIT(4),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "ce1_h_clk",
2185 .ops = &clk_branch_ops,
2186 .flags = CLK_IS_ROOT,
2191 static struct clk_branch dma_bam_h_clk = {
2197 .enable_reg = 0x25c0,
2198 .enable_mask = BIT(4),
2199 .hw.init = &(struct clk_init_data){
2200 .name = "dma_bam_h_clk",
2201 .ops = &clk_branch_ops,
2202 .flags = CLK_IS_ROOT,
2207 static struct clk_branch gsbi1_h_clk = {
2213 .enable_reg = 0x29c0,
2214 .enable_mask = BIT(4),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "gsbi1_h_clk",
2217 .ops = &clk_branch_ops,
2218 .flags = CLK_IS_ROOT,
2223 static struct clk_branch gsbi2_h_clk = {
2229 .enable_reg = 0x29e0,
2230 .enable_mask = BIT(4),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "gsbi2_h_clk",
2233 .ops = &clk_branch_ops,
2234 .flags = CLK_IS_ROOT,
2239 static struct clk_branch gsbi3_h_clk = {
2245 .enable_reg = 0x2a00,
2246 .enable_mask = BIT(4),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "gsbi3_h_clk",
2249 .ops = &clk_branch_ops,
2250 .flags = CLK_IS_ROOT,
2255 static struct clk_branch gsbi4_h_clk = {
2261 .enable_reg = 0x2a20,
2262 .enable_mask = BIT(4),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "gsbi4_h_clk",
2265 .ops = &clk_branch_ops,
2266 .flags = CLK_IS_ROOT,
2271 static struct clk_branch gsbi5_h_clk = {
2277 .enable_reg = 0x2a40,
2278 .enable_mask = BIT(4),
2279 .hw.init = &(struct clk_init_data){
2280 .name = "gsbi5_h_clk",
2281 .ops = &clk_branch_ops,
2282 .flags = CLK_IS_ROOT,
2287 static struct clk_branch gsbi6_h_clk = {
2293 .enable_reg = 0x2a60,
2294 .enable_mask = BIT(4),
2295 .hw.init = &(struct clk_init_data){
2296 .name = "gsbi6_h_clk",
2297 .ops = &clk_branch_ops,
2298 .flags = CLK_IS_ROOT,
2303 static struct clk_branch gsbi7_h_clk = {
2309 .enable_reg = 0x2a80,
2310 .enable_mask = BIT(4),
2311 .hw.init = &(struct clk_init_data){
2312 .name = "gsbi7_h_clk",
2313 .ops = &clk_branch_ops,
2314 .flags = CLK_IS_ROOT,
2319 static struct clk_branch gsbi8_h_clk = {
2325 .enable_reg = 0x2aa0,
2326 .enable_mask = BIT(4),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gsbi8_h_clk",
2329 .ops = &clk_branch_ops,
2330 .flags = CLK_IS_ROOT,
2335 static struct clk_branch gsbi9_h_clk = {
2341 .enable_reg = 0x2ac0,
2342 .enable_mask = BIT(4),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gsbi9_h_clk",
2345 .ops = &clk_branch_ops,
2346 .flags = CLK_IS_ROOT,
2351 static struct clk_branch gsbi10_h_clk = {
2357 .enable_reg = 0x2ae0,
2358 .enable_mask = BIT(4),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "gsbi10_h_clk",
2361 .ops = &clk_branch_ops,
2362 .flags = CLK_IS_ROOT,
2367 static struct clk_branch gsbi11_h_clk = {
2373 .enable_reg = 0x2b00,
2374 .enable_mask = BIT(4),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "gsbi11_h_clk",
2377 .ops = &clk_branch_ops,
2378 .flags = CLK_IS_ROOT,
2383 static struct clk_branch gsbi12_h_clk = {
2389 .enable_reg = 0x2b20,
2390 .enable_mask = BIT(4),
2391 .hw.init = &(struct clk_init_data){
2392 .name = "gsbi12_h_clk",
2393 .ops = &clk_branch_ops,
2394 .flags = CLK_IS_ROOT,
2399 static struct clk_branch tsif_h_clk = {
2405 .enable_reg = 0x2700,
2406 .enable_mask = BIT(4),
2407 .hw.init = &(struct clk_init_data){
2408 .name = "tsif_h_clk",
2409 .ops = &clk_branch_ops,
2410 .flags = CLK_IS_ROOT,
2415 static struct clk_branch usb_fs1_h_clk = {
2419 .enable_reg = 0x2960,
2420 .enable_mask = BIT(4),
2421 .hw.init = &(struct clk_init_data){
2422 .name = "usb_fs1_h_clk",
2423 .ops = &clk_branch_ops,
2424 .flags = CLK_IS_ROOT,
2429 static struct clk_branch usb_fs2_h_clk = {
2433 .enable_reg = 0x2980,
2434 .enable_mask = BIT(4),
2435 .hw.init = &(struct clk_init_data){
2436 .name = "usb_fs2_h_clk",
2437 .ops = &clk_branch_ops,
2438 .flags = CLK_IS_ROOT,
2443 static struct clk_branch usb_hs1_h_clk = {
2449 .enable_reg = 0x2900,
2450 .enable_mask = BIT(4),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "usb_hs1_h_clk",
2453 .ops = &clk_branch_ops,
2454 .flags = CLK_IS_ROOT,
2459 static struct clk_branch usb_hsic_h_clk = {
2463 .enable_reg = 0x2920,
2464 .enable_mask = BIT(4),
2465 .hw.init = &(struct clk_init_data){
2466 .name = "usb_hsic_h_clk",
2467 .ops = &clk_branch_ops,
2468 .flags = CLK_IS_ROOT,
2473 static struct clk_branch sdc1_h_clk = {
2479 .enable_reg = 0x2820,
2480 .enable_mask = BIT(4),
2481 .hw.init = &(struct clk_init_data){
2482 .name = "sdc1_h_clk",
2483 .ops = &clk_branch_ops,
2484 .flags = CLK_IS_ROOT,
2489 static struct clk_branch sdc2_h_clk = {
2495 .enable_reg = 0x2840,
2496 .enable_mask = BIT(4),
2497 .hw.init = &(struct clk_init_data){
2498 .name = "sdc2_h_clk",
2499 .ops = &clk_branch_ops,
2500 .flags = CLK_IS_ROOT,
2505 static struct clk_branch sdc3_h_clk = {
2511 .enable_reg = 0x2860,
2512 .enable_mask = BIT(4),
2513 .hw.init = &(struct clk_init_data){
2514 .name = "sdc3_h_clk",
2515 .ops = &clk_branch_ops,
2516 .flags = CLK_IS_ROOT,
2521 static struct clk_branch sdc4_h_clk = {
2527 .enable_reg = 0x2880,
2528 .enable_mask = BIT(4),
2529 .hw.init = &(struct clk_init_data){
2530 .name = "sdc4_h_clk",
2531 .ops = &clk_branch_ops,
2532 .flags = CLK_IS_ROOT,
2537 static struct clk_branch sdc5_h_clk = {
2543 .enable_reg = 0x28a0,
2544 .enable_mask = BIT(4),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "sdc5_h_clk",
2547 .ops = &clk_branch_ops,
2548 .flags = CLK_IS_ROOT,
2553 static struct clk_branch adm0_clk = {
2555 .halt_check = BRANCH_HALT_VOTED,
2558 .enable_reg = 0x3080,
2559 .enable_mask = BIT(2),
2560 .hw.init = &(struct clk_init_data){
2562 .ops = &clk_branch_ops,
2563 .flags = CLK_IS_ROOT,
2568 static struct clk_branch adm0_pbus_clk = {
2572 .halt_check = BRANCH_HALT_VOTED,
2575 .enable_reg = 0x3080,
2576 .enable_mask = BIT(3),
2577 .hw.init = &(struct clk_init_data){
2578 .name = "adm0_pbus_clk",
2579 .ops = &clk_branch_ops,
2580 .flags = CLK_IS_ROOT,
2585 static struct clk_branch pmic_arb0_h_clk = {
2587 .halt_check = BRANCH_HALT_VOTED,
2590 .enable_reg = 0x3080,
2591 .enable_mask = BIT(8),
2592 .hw.init = &(struct clk_init_data){
2593 .name = "pmic_arb0_h_clk",
2594 .ops = &clk_branch_ops,
2595 .flags = CLK_IS_ROOT,
2600 static struct clk_branch pmic_arb1_h_clk = {
2602 .halt_check = BRANCH_HALT_VOTED,
2605 .enable_reg = 0x3080,
2606 .enable_mask = BIT(9),
2607 .hw.init = &(struct clk_init_data){
2608 .name = "pmic_arb1_h_clk",
2609 .ops = &clk_branch_ops,
2610 .flags = CLK_IS_ROOT,
2615 static struct clk_branch pmic_ssbi2_clk = {
2617 .halt_check = BRANCH_HALT_VOTED,
2620 .enable_reg = 0x3080,
2621 .enable_mask = BIT(7),
2622 .hw.init = &(struct clk_init_data){
2623 .name = "pmic_ssbi2_clk",
2624 .ops = &clk_branch_ops,
2625 .flags = CLK_IS_ROOT,
2630 static struct clk_branch rpm_msg_ram_h_clk = {
2634 .halt_check = BRANCH_HALT_VOTED,
2637 .enable_reg = 0x3080,
2638 .enable_mask = BIT(6),
2639 .hw.init = &(struct clk_init_data){
2640 .name = "rpm_msg_ram_h_clk",
2641 .ops = &clk_branch_ops,
2642 .flags = CLK_IS_ROOT,
2647 static struct clk_regmap *gcc_msm8960_clks[] = {
2648 [PLL3] = &pll3.clkr,
2649 [PLL8] = &pll8.clkr,
2650 [PLL8_VOTE] = &pll8_vote,
2651 [PLL14] = &pll14.clkr,
2652 [PLL14_VOTE] = &pll14_vote,
2653 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2654 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2655 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2656 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2657 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2658 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2659 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2660 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2661 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2662 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2663 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2664 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2665 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2666 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2667 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2668 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2669 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2670 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2671 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2672 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2673 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2674 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2675 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2676 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2677 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2678 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2679 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2680 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2681 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2682 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2683 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2684 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2685 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2686 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2687 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2688 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2689 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2690 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2691 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2692 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2693 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2694 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2695 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2696 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2697 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2698 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2699 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2700 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2701 [GP0_SRC] = &gp0_src.clkr,
2702 [GP0_CLK] = &gp0_clk.clkr,
2703 [GP1_SRC] = &gp1_src.clkr,
2704 [GP1_CLK] = &gp1_clk.clkr,
2705 [GP2_SRC] = &gp2_src.clkr,
2706 [GP2_CLK] = &gp2_clk.clkr,
2707 [PMEM_A_CLK] = &pmem_clk.clkr,
2708 [PRNG_SRC] = &prng_src.clkr,
2709 [PRNG_CLK] = &prng_clk.clkr,
2710 [SDC1_SRC] = &sdc1_src.clkr,
2711 [SDC1_CLK] = &sdc1_clk.clkr,
2712 [SDC2_SRC] = &sdc2_src.clkr,
2713 [SDC2_CLK] = &sdc2_clk.clkr,
2714 [SDC3_SRC] = &sdc3_src.clkr,
2715 [SDC3_CLK] = &sdc3_clk.clkr,
2716 [SDC4_SRC] = &sdc4_src.clkr,
2717 [SDC4_CLK] = &sdc4_clk.clkr,
2718 [SDC5_SRC] = &sdc5_src.clkr,
2719 [SDC5_CLK] = &sdc5_clk.clkr,
2720 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2721 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2722 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2723 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2724 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
2725 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
2726 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
2727 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
2728 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
2729 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2730 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2731 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2732 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2733 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2734 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2735 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
2736 [CE1_H_CLK] = &ce1_h_clk.clkr,
2737 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2738 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2739 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2740 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2741 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2742 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2743 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2744 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2745 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2746 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2747 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2748 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2749 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2750 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2751 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2752 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2753 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2754 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
2755 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2756 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2757 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2758 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2759 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2760 [ADM0_CLK] = &adm0_clk.clkr,
2761 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2762 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2763 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2764 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2765 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2768 static const struct qcom_reset_map gcc_msm8960_resets[] = {
2769 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
2770 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
2771 [QDSS_STM_RESET] = { 0x2060, 6 },
2772 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2773 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2774 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2775 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2776 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
2777 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2778 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2779 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2780 [ADM0_C2_RESET] = { 0x220c, 4},
2781 [ADM0_C1_RESET] = { 0x220c, 3},
2782 [ADM0_C0_RESET] = { 0x220c, 2},
2783 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2784 [ADM0_RESET] = { 0x220c },
2785 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2786 [QDSS_POR_RESET] = { 0x2260, 4 },
2787 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2788 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2789 [QDSS_AXI_RESET] = { 0x2260, 1 },
2790 [QDSS_DBG_RESET] = { 0x2260 },
2791 [PCIE_A_RESET] = { 0x22c0, 7 },
2792 [PCIE_AUX_RESET] = { 0x22c8, 7 },
2793 [PCIE_H_RESET] = { 0x22d0, 7 },
2794 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
2795 [SFAB_PCIE_S_RESET] = { 0x22d4 },
2796 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
2797 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
2798 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
2799 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2800 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2801 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2802 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2803 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2804 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2805 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2806 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2807 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2808 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2809 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2810 [PPSS_PROC_RESET] = { 0x2594, 1 },
2811 [PPSS_RESET] = { 0x2594},
2812 [DMA_BAM_RESET] = { 0x25c0, 7 },
2813 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2814 [SLIMBUS_H_RESET] = { 0x2620, 7 },
2815 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2816 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2817 [TSIF_H_RESET] = { 0x2700, 7 },
2818 [CE1_H_RESET] = { 0x2720, 7 },
2819 [CE1_CORE_RESET] = { 0x2724, 7 },
2820 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2821 [CE2_H_RESET] = { 0x2740, 7 },
2822 [CE2_CORE_RESET] = { 0x2744, 7 },
2823 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2824 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2825 [RPM_PROC_RESET] = { 0x27c0, 7 },
2826 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2827 [SDC1_RESET] = { 0x2830 },
2828 [SDC2_RESET] = { 0x2850 },
2829 [SDC3_RESET] = { 0x2870 },
2830 [SDC4_RESET] = { 0x2890 },
2831 [SDC5_RESET] = { 0x28b0 },
2832 [DFAB_A2_RESET] = { 0x28c0, 7 },
2833 [USB_HS1_RESET] = { 0x2910 },
2834 [USB_HSIC_RESET] = { 0x2934 },
2835 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2836 [USB_FS1_RESET] = { 0x2974 },
2837 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2838 [USB_FS2_RESET] = { 0x2994 },
2839 [GSBI1_RESET] = { 0x29dc },
2840 [GSBI2_RESET] = { 0x29fc },
2841 [GSBI3_RESET] = { 0x2a1c },
2842 [GSBI4_RESET] = { 0x2a3c },
2843 [GSBI5_RESET] = { 0x2a5c },
2844 [GSBI6_RESET] = { 0x2a7c },
2845 [GSBI7_RESET] = { 0x2a9c },
2846 [GSBI8_RESET] = { 0x2abc },
2847 [GSBI9_RESET] = { 0x2adc },
2848 [GSBI10_RESET] = { 0x2afc },
2849 [GSBI11_RESET] = { 0x2b1c },
2850 [GSBI12_RESET] = { 0x2b3c },
2851 [SPDM_RESET] = { 0x2b6c },
2852 [TLMM_H_RESET] = { 0x2ba0, 7 },
2853 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2854 [MSS_SLP_RESET] = { 0x2c60, 7 },
2855 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
2856 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
2857 [MSS_RESET] = { 0x2c64 },
2858 [SATA_H_RESET] = { 0x2c80, 7 },
2859 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
2860 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
2861 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
2862 [TSSC_RESET] = { 0x2ca0, 7 },
2863 [PDM_RESET] = { 0x2cc0, 12 },
2864 [MPM_H_RESET] = { 0x2da0, 7 },
2865 [MPM_RESET] = { 0x2da4 },
2866 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2867 [PRNG_RESET] = { 0x2e80, 12 },
2868 [RIVA_RESET] = { 0x35e0 },
2871 static struct clk_regmap *gcc_apq8064_clks[] = {
2872 [PLL8] = &pll8.clkr,
2873 [PLL8_VOTE] = &pll8_vote,
2874 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2875 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2876 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2877 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2878 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2881 static const struct regmap_config gcc_msm8960_regmap_config = {
2885 .max_register = 0x3660,
2889 static const struct qcom_cc_desc gcc_msm8960_desc = {
2890 .config = &gcc_msm8960_regmap_config,
2891 .clks = gcc_msm8960_clks,
2892 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
2893 .resets = gcc_msm8960_resets,
2894 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
2897 static const struct qcom_cc_desc gcc_apq8064_desc = {
2898 .config = &gcc_msm8960_regmap_config,
2899 .clks = gcc_apq8064_clks,
2900 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
2901 .resets = gcc_msm8960_resets,
2902 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
2905 static const struct of_device_id gcc_msm8960_match_table[] = {
2906 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
2907 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
2910 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
2912 static int gcc_msm8960_probe(struct platform_device *pdev)
2915 struct device *dev = &pdev->dev;
2916 const struct of_device_id *match;
2918 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
2922 /* Temporary until RPM clocks supported */
2923 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2925 return PTR_ERR(clk);
2927 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2929 return PTR_ERR(clk);
2931 return qcom_cc_probe(pdev, match->data);
2934 static int gcc_msm8960_remove(struct platform_device *pdev)
2936 qcom_cc_remove(pdev);
2940 static struct platform_driver gcc_msm8960_driver = {
2941 .probe = gcc_msm8960_probe,
2942 .remove = gcc_msm8960_remove,
2944 .name = "gcc-msm8960",
2945 .owner = THIS_MODULE,
2946 .of_match_table = gcc_msm8960_match_table,
2950 static int __init gcc_msm8960_init(void)
2952 return platform_driver_register(&gcc_msm8960_driver);
2954 core_initcall(gcc_msm8960_init);
2956 static void __exit gcc_msm8960_exit(void)
2958 platform_driver_unregister(&gcc_msm8960_driver);
2960 module_exit(gcc_msm8960_exit);
2962 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
2963 MODULE_LICENSE("GPL v2");
2964 MODULE_ALIAS("platform:gcc-msm8960");