2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/reset-controller.h>
20 #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21 #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
24 #include "clk-regmap.h"
27 #include "clk-branch.h"
39 #define P_DSI0PLL_BYTE 4
44 #define P_DSI1PLL_BYTE 5
47 static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
54 static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
61 static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
70 static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
79 static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
87 static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
95 static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
103 static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
111 static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
120 static const char *mmcc_xo_dsi_hdmi_edp[] = {
129 static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
138 static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
147 static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
152 [P_DSI0PLL_BYTE] = 1,
153 [P_DSI1PLL_BYTE] = 2,
156 static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
165 static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
173 static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
181 static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
190 static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
199 static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
209 static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
219 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
221 static struct clk_pll mmpll0 = {
225 .config_reg = 0x0014,
227 .status_reg = 0x001c,
229 .clkr.hw.init = &(struct clk_init_data){
231 .parent_names = (const char *[]){ "xo" },
237 static struct clk_regmap mmpll0_vote = {
238 .enable_reg = 0x0100,
239 .enable_mask = BIT(0),
240 .hw.init = &(struct clk_init_data){
241 .name = "mmpll0_vote",
242 .parent_names = (const char *[]){ "mmpll0" },
244 .ops = &clk_pll_vote_ops,
248 static struct clk_pll mmpll1 = {
252 .config_reg = 0x0050,
254 .status_reg = 0x005c,
256 .clkr.hw.init = &(struct clk_init_data){
258 .parent_names = (const char *[]){ "xo" },
264 static struct clk_regmap mmpll1_vote = {
265 .enable_reg = 0x0100,
266 .enable_mask = BIT(1),
267 .hw.init = &(struct clk_init_data){
268 .name = "mmpll1_vote",
269 .parent_names = (const char *[]){ "mmpll1" },
271 .ops = &clk_pll_vote_ops,
275 static struct clk_pll mmpll2 = {
279 .config_reg = 0x4110,
281 .status_reg = 0x411c,
282 .clkr.hw.init = &(struct clk_init_data){
284 .parent_names = (const char *[]){ "xo" },
290 static struct clk_pll mmpll3 = {
294 .config_reg = 0x0090,
296 .status_reg = 0x009c,
298 .clkr.hw.init = &(struct clk_init_data){
300 .parent_names = (const char *[]){ "xo" },
306 static struct clk_pll mmpll4 = {
310 .config_reg = 0x00b0,
312 .status_reg = 0x00bc,
313 .clkr.hw.init = &(struct clk_init_data){
315 .parent_names = (const char *[]){ "xo" },
321 static struct clk_rcg2 mmss_ahb_clk_src = {
324 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
325 .clkr.hw.init = &(struct clk_init_data){
326 .name = "mmss_ahb_clk_src",
327 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
329 .ops = &clk_rcg2_ops,
333 static struct freq_tbl ftbl_mmss_axi_clk[] = {
334 F(19200000, P_XO, 1, 0, 0),
335 F(37500000, P_GPLL0, 16, 0, 0),
336 F(50000000, P_GPLL0, 12, 0, 0),
337 F(75000000, P_GPLL0, 8, 0, 0),
338 F(100000000, P_GPLL0, 6, 0, 0),
339 F(150000000, P_GPLL0, 4, 0, 0),
340 F(333430000, P_MMPLL1, 3.5, 0, 0),
341 F(400000000, P_MMPLL0, 2, 0, 0),
342 F(466800000, P_MMPLL1, 2.5, 0, 0),
345 static struct clk_rcg2 mmss_axi_clk_src = {
348 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
349 .freq_tbl = ftbl_mmss_axi_clk,
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "mmss_axi_clk_src",
352 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
354 .ops = &clk_rcg2_ops,
358 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
359 F(19200000, P_XO, 1, 0, 0),
360 F(37500000, P_GPLL0, 16, 0, 0),
361 F(50000000, P_GPLL0, 12, 0, 0),
362 F(75000000, P_GPLL0, 8, 0, 0),
363 F(109090000, P_GPLL0, 5.5, 0, 0),
364 F(150000000, P_GPLL0, 4, 0, 0),
365 F(228570000, P_MMPLL0, 3.5, 0, 0),
366 F(320000000, P_MMPLL0, 2.5, 0, 0),
369 static struct clk_rcg2 ocmemnoc_clk_src = {
372 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
373 .freq_tbl = ftbl_ocmemnoc_clk,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "ocmemnoc_clk_src",
376 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
378 .ops = &clk_rcg2_ops,
382 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
383 F(100000000, P_GPLL0, 6, 0, 0),
384 F(200000000, P_MMPLL0, 4, 0, 0),
388 static struct clk_rcg2 csi0_clk_src = {
391 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
392 .freq_tbl = ftbl_camss_csi0_3_clk,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "csi0_clk_src",
395 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
397 .ops = &clk_rcg2_ops,
401 static struct clk_rcg2 csi1_clk_src = {
404 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
405 .freq_tbl = ftbl_camss_csi0_3_clk,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "csi1_clk_src",
408 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
410 .ops = &clk_rcg2_ops,
414 static struct clk_rcg2 csi2_clk_src = {
417 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
418 .freq_tbl = ftbl_camss_csi0_3_clk,
419 .clkr.hw.init = &(struct clk_init_data){
420 .name = "csi2_clk_src",
421 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
423 .ops = &clk_rcg2_ops,
427 static struct clk_rcg2 csi3_clk_src = {
430 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
431 .freq_tbl = ftbl_camss_csi0_3_clk,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "csi3_clk_src",
434 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
436 .ops = &clk_rcg2_ops,
440 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
441 F(37500000, P_GPLL0, 16, 0, 0),
442 F(50000000, P_GPLL0, 12, 0, 0),
443 F(60000000, P_GPLL0, 10, 0, 0),
444 F(80000000, P_GPLL0, 7.5, 0, 0),
445 F(100000000, P_GPLL0, 6, 0, 0),
446 F(109090000, P_GPLL0, 5.5, 0, 0),
447 F(133330000, P_GPLL0, 4.5, 0, 0),
448 F(200000000, P_GPLL0, 3, 0, 0),
449 F(228570000, P_MMPLL0, 3.5, 0, 0),
450 F(266670000, P_MMPLL0, 3, 0, 0),
451 F(320000000, P_MMPLL0, 2.5, 0, 0),
452 F(465000000, P_MMPLL4, 2, 0, 0),
453 F(600000000, P_GPLL0, 1, 0, 0),
457 static struct clk_rcg2 vfe0_clk_src = {
460 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
461 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
462 .clkr.hw.init = &(struct clk_init_data){
463 .name = "vfe0_clk_src",
464 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
466 .ops = &clk_rcg2_ops,
470 static struct clk_rcg2 vfe1_clk_src = {
473 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
474 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "vfe1_clk_src",
477 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
479 .ops = &clk_rcg2_ops,
483 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
484 F(37500000, P_GPLL0, 16, 0, 0),
485 F(60000000, P_GPLL0, 10, 0, 0),
486 F(75000000, P_GPLL0, 8, 0, 0),
487 F(85710000, P_GPLL0, 7, 0, 0),
488 F(100000000, P_GPLL0, 6, 0, 0),
489 F(150000000, P_GPLL0, 4, 0, 0),
490 F(160000000, P_MMPLL0, 5, 0, 0),
491 F(200000000, P_MMPLL0, 4, 0, 0),
492 F(228570000, P_MMPLL0, 3.5, 0, 0),
493 F(300000000, P_GPLL0, 2, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
498 static struct clk_rcg2 mdp_clk_src = {
501 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
502 .freq_tbl = ftbl_mdss_mdp_clk,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "mdp_clk_src",
505 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
507 .ops = &clk_rcg2_ops,
511 static struct clk_rcg2 gfx3d_clk_src = {
514 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "gfx3d_clk_src",
517 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
519 .ops = &clk_rcg2_ops,
523 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
524 F(75000000, P_GPLL0, 8, 0, 0),
525 F(133330000, P_GPLL0, 4.5, 0, 0),
526 F(200000000, P_GPLL0, 3, 0, 0),
527 F(228570000, P_MMPLL0, 3.5, 0, 0),
528 F(266670000, P_MMPLL0, 3, 0, 0),
529 F(320000000, P_MMPLL0, 2.5, 0, 0),
533 static struct clk_rcg2 jpeg0_clk_src = {
536 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
537 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "jpeg0_clk_src",
540 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
542 .ops = &clk_rcg2_ops,
546 static struct clk_rcg2 jpeg1_clk_src = {
549 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
550 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "jpeg1_clk_src",
553 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
555 .ops = &clk_rcg2_ops,
559 static struct clk_rcg2 jpeg2_clk_src = {
562 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
563 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "jpeg2_clk_src",
566 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
568 .ops = &clk_rcg2_ops,
572 static struct freq_tbl pixel_freq_tbl[] = {
573 { .src = P_DSI0PLL },
577 static struct clk_rcg2 pclk0_clk_src = {
581 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
582 .freq_tbl = pixel_freq_tbl,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "pclk0_clk_src",
585 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
587 .ops = &clk_pixel_ops,
588 .flags = CLK_SET_RATE_PARENT,
592 static struct clk_rcg2 pclk1_clk_src = {
596 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
597 .freq_tbl = pixel_freq_tbl,
598 .clkr.hw.init = &(struct clk_init_data){
599 .name = "pclk1_clk_src",
600 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
602 .ops = &clk_pixel_ops,
603 .flags = CLK_SET_RATE_PARENT,
607 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
608 F(50000000, P_GPLL0, 12, 0, 0),
609 F(100000000, P_GPLL0, 6, 0, 0),
610 F(133330000, P_GPLL0, 4.5, 0, 0),
611 F(200000000, P_MMPLL0, 4, 0, 0),
612 F(266670000, P_MMPLL0, 3, 0, 0),
613 F(465000000, P_MMPLL3, 2, 0, 0),
617 static struct clk_rcg2 vcodec0_clk_src = {
621 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
622 .freq_tbl = ftbl_venus0_vcodec0_clk,
623 .clkr.hw.init = &(struct clk_init_data){
624 .name = "vcodec0_clk_src",
625 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
627 .ops = &clk_rcg2_ops,
631 static struct freq_tbl ftbl_avsync_vp_clk[] = {
632 F(150000000, P_GPLL0, 4, 0, 0),
633 F(320000000, P_MMPLL0, 2.5, 0, 0),
637 static struct clk_rcg2 vp_clk_src = {
640 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
641 .freq_tbl = ftbl_avsync_vp_clk,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "vp_clk_src",
644 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
646 .ops = &clk_rcg2_ops,
650 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
651 F(19200000, P_XO, 1, 0, 0),
655 static struct clk_rcg2 cci_clk_src = {
659 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
660 .freq_tbl = ftbl_camss_cci_cci_clk,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "cci_clk_src",
663 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
665 .ops = &clk_rcg2_ops,
669 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
670 F(10000, P_XO, 16, 1, 120),
671 F(24000, P_XO, 16, 1, 50),
672 F(6000000, P_GPLL0, 10, 1, 10),
673 F(12000000, P_GPLL0, 10, 1, 5),
674 F(13000000, P_GPLL0, 4, 13, 150),
675 F(24000000, P_GPLL0, 5, 1, 5),
679 static struct clk_rcg2 camss_gp0_clk_src = {
683 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
684 .freq_tbl = ftbl_camss_gp0_1_clk,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "camss_gp0_clk_src",
687 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
689 .ops = &clk_rcg2_ops,
693 static struct clk_rcg2 camss_gp1_clk_src = {
697 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
698 .freq_tbl = ftbl_camss_gp0_1_clk,
699 .clkr.hw.init = &(struct clk_init_data){
700 .name = "camss_gp1_clk_src",
701 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
703 .ops = &clk_rcg2_ops,
707 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
708 F(4800000, P_XO, 4, 0, 0),
709 F(6000000, P_GPLL0, 10, 1, 10),
710 F(8000000, P_GPLL0, 15, 1, 5),
711 F(9600000, P_XO, 2, 0, 0),
712 F(16000000, P_MMPLL0, 10, 1, 5),
713 F(19200000, P_XO, 1, 0, 0),
714 F(24000000, P_GPLL0, 5, 1, 5),
715 F(32000000, P_MMPLL0, 5, 1, 5),
716 F(48000000, P_GPLL0, 12.5, 0, 0),
717 F(64000000, P_MMPLL0, 12.5, 0, 0),
721 static struct clk_rcg2 mclk0_clk_src = {
725 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
726 .freq_tbl = ftbl_camss_mclk0_3_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "mclk0_clk_src",
729 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
731 .ops = &clk_rcg2_ops,
735 static struct clk_rcg2 mclk1_clk_src = {
739 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
740 .freq_tbl = ftbl_camss_mclk0_3_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "mclk1_clk_src",
743 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
745 .ops = &clk_rcg2_ops,
749 static struct clk_rcg2 mclk2_clk_src = {
753 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
754 .freq_tbl = ftbl_camss_mclk0_3_clk,
755 .clkr.hw.init = &(struct clk_init_data){
756 .name = "mclk2_clk_src",
757 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
759 .ops = &clk_rcg2_ops,
763 static struct clk_rcg2 mclk3_clk_src = {
767 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
768 .freq_tbl = ftbl_camss_mclk0_3_clk,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "mclk3_clk_src",
771 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
773 .ops = &clk_rcg2_ops,
777 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
778 F(100000000, P_GPLL0, 6, 0, 0),
779 F(200000000, P_MMPLL0, 4, 0, 0),
783 static struct clk_rcg2 csi0phytimer_clk_src = {
786 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
787 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "csi0phytimer_clk_src",
790 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
792 .ops = &clk_rcg2_ops,
796 static struct clk_rcg2 csi1phytimer_clk_src = {
799 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
800 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "csi1phytimer_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
805 .ops = &clk_rcg2_ops,
809 static struct clk_rcg2 csi2phytimer_clk_src = {
812 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
813 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "csi2phytimer_clk_src",
816 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
818 .ops = &clk_rcg2_ops,
822 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
823 F(133330000, P_GPLL0, 4.5, 0, 0),
824 F(266670000, P_MMPLL0, 3, 0, 0),
825 F(320000000, P_MMPLL0, 2.5, 0, 0),
826 F(372000000, P_MMPLL4, 2.5, 0, 0),
827 F(465000000, P_MMPLL4, 2, 0, 0),
828 F(600000000, P_GPLL0, 1, 0, 0),
832 static struct clk_rcg2 cpp_clk_src = {
835 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
836 .freq_tbl = ftbl_camss_vfe_cpp_clk,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "cpp_clk_src",
839 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
841 .ops = &clk_rcg2_ops,
845 static struct freq_tbl byte_freq_tbl[] = {
846 { .src = P_DSI0PLL_BYTE },
850 static struct clk_rcg2 byte0_clk_src = {
853 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
854 .freq_tbl = byte_freq_tbl,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "byte0_clk_src",
857 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
859 .ops = &clk_byte_ops,
860 .flags = CLK_SET_RATE_PARENT,
864 static struct clk_rcg2 byte1_clk_src = {
867 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
868 .freq_tbl = byte_freq_tbl,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "byte1_clk_src",
871 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
873 .ops = &clk_byte_ops,
874 .flags = CLK_SET_RATE_PARENT,
878 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
879 F(19200000, P_XO, 1, 0, 0),
883 static struct clk_rcg2 edpaux_clk_src = {
886 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
887 .freq_tbl = ftbl_mdss_edpaux_clk,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "edpaux_clk_src",
890 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
892 .ops = &clk_rcg2_ops,
896 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
897 F(135000000, P_EDPLINK, 2, 0, 0),
898 F(270000000, P_EDPLINK, 11, 0, 0),
902 static struct clk_rcg2 edplink_clk_src = {
905 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
906 .freq_tbl = ftbl_mdss_edplink_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "edplink_clk_src",
909 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
911 .ops = &clk_rcg2_ops,
912 .flags = CLK_SET_RATE_PARENT,
916 static struct freq_tbl edp_pixel_freq_tbl[] = {
921 static struct clk_rcg2 edppixel_clk_src = {
925 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
926 .freq_tbl = edp_pixel_freq_tbl,
927 .clkr.hw.init = &(struct clk_init_data){
928 .name = "edppixel_clk_src",
929 .parent_names = mmcc_xo_dsi_hdmi_edp,
931 .ops = &clk_edp_pixel_ops,
935 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
936 F(19200000, P_XO, 1, 0, 0),
940 static struct clk_rcg2 esc0_clk_src = {
943 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
944 .freq_tbl = ftbl_mdss_esc0_1_clk,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "esc0_clk_src",
947 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
949 .ops = &clk_rcg2_ops,
953 static struct clk_rcg2 esc1_clk_src = {
956 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
957 .freq_tbl = ftbl_mdss_esc0_1_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "esc1_clk_src",
960 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
962 .ops = &clk_rcg2_ops,
966 static struct freq_tbl extpclk_freq_tbl[] = {
967 { .src = P_HDMIPLL },
971 static struct clk_rcg2 extpclk_clk_src = {
974 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
975 .freq_tbl = extpclk_freq_tbl,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "extpclk_clk_src",
978 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
980 .ops = &clk_byte_ops,
981 .flags = CLK_SET_RATE_PARENT,
985 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
986 F(19200000, P_XO, 1, 0, 0),
990 static struct clk_rcg2 hdmi_clk_src = {
993 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
994 .freq_tbl = ftbl_mdss_hdmi_clk,
995 .clkr.hw.init = &(struct clk_init_data){
996 .name = "hdmi_clk_src",
997 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
999 .ops = &clk_rcg2_ops,
1003 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1004 F(19200000, P_XO, 1, 0, 0),
1008 static struct clk_rcg2 vsync_clk_src = {
1011 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1012 .freq_tbl = ftbl_mdss_vsync_clk,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "vsync_clk_src",
1015 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1017 .ops = &clk_rcg2_ops,
1021 static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1022 F(50000000, P_GPLL0, 12, 0, 0),
1026 static struct clk_rcg2 rbcpr_clk_src = {
1029 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1030 .freq_tbl = ftbl_mmss_rbcpr_clk,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "rbcpr_clk_src",
1033 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1035 .ops = &clk_rcg2_ops,
1039 static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1040 F(19200000, P_XO, 1, 0, 0),
1044 static struct clk_rcg2 rbbmtimer_clk_src = {
1047 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1048 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1049 .clkr.hw.init = &(struct clk_init_data){
1050 .name = "rbbmtimer_clk_src",
1051 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1053 .ops = &clk_rcg2_ops,
1057 static struct freq_tbl ftbl_vpu_maple_clk[] = {
1058 F(50000000, P_GPLL0, 12, 0, 0),
1059 F(100000000, P_GPLL0, 6, 0, 0),
1060 F(133330000, P_GPLL0, 4.5, 0, 0),
1061 F(200000000, P_MMPLL0, 4, 0, 0),
1062 F(266670000, P_MMPLL0, 3, 0, 0),
1063 F(465000000, P_MMPLL3, 2, 0, 0),
1067 static struct clk_rcg2 maple_clk_src = {
1070 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1071 .freq_tbl = ftbl_vpu_maple_clk,
1072 .clkr.hw.init = &(struct clk_init_data){
1073 .name = "maple_clk_src",
1074 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1076 .ops = &clk_rcg2_ops,
1080 static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1081 F(50000000, P_GPLL0, 12, 0, 0),
1082 F(100000000, P_GPLL0, 6, 0, 0),
1083 F(200000000, P_MMPLL0, 4, 0, 0),
1084 F(320000000, P_MMPLL0, 2.5, 0, 0),
1085 F(400000000, P_MMPLL0, 2, 0, 0),
1089 static struct clk_rcg2 vdp_clk_src = {
1092 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1093 .freq_tbl = ftbl_vpu_vdp_clk,
1094 .clkr.hw.init = &(struct clk_init_data){
1095 .name = "vdp_clk_src",
1096 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1098 .ops = &clk_rcg2_ops,
1102 static struct freq_tbl ftbl_vpu_bus_clk[] = {
1103 F(40000000, P_GPLL0, 15, 0, 0),
1104 F(80000000, P_MMPLL0, 10, 0, 0),
1108 static struct clk_rcg2 vpu_bus_clk_src = {
1111 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1112 .freq_tbl = ftbl_vpu_bus_clk,
1113 .clkr.hw.init = &(struct clk_init_data){
1114 .name = "vpu_bus_clk_src",
1115 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1117 .ops = &clk_rcg2_ops,
1121 static struct clk_branch mmss_cxo_clk = {
1124 .enable_reg = 0x5104,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "mmss_cxo_clk",
1128 .parent_names = (const char *[]){ "xo" },
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_ops,
1136 static struct clk_branch mmss_sleepclk_clk = {
1139 .enable_reg = 0x5100,
1140 .enable_mask = BIT(0),
1141 .hw.init = &(struct clk_init_data){
1142 .name = "mmss_sleepclk_clk",
1143 .parent_names = (const char *[]){
1147 .flags = CLK_SET_RATE_PARENT,
1148 .ops = &clk_branch2_ops,
1153 static struct clk_branch avsync_ahb_clk = {
1156 .enable_reg = 0x2414,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "avsync_ahb_clk",
1160 .parent_names = (const char *[]){
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1170 static struct clk_branch avsync_edppixel_clk = {
1173 .enable_reg = 0x2418,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "avsync_edppixel_clk",
1177 .parent_names = (const char *[]){
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1187 static struct clk_branch avsync_extpclk_clk = {
1190 .enable_reg = 0x2410,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "avsync_extpclk_clk",
1194 .parent_names = (const char *[]){
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1204 static struct clk_branch avsync_pclk0_clk = {
1207 .enable_reg = 0x241c,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "avsync_pclk0_clk",
1211 .parent_names = (const char *[]){
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1221 static struct clk_branch avsync_pclk1_clk = {
1224 .enable_reg = 0x2420,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "avsync_pclk1_clk",
1228 .parent_names = (const char *[]){
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1238 static struct clk_branch avsync_vp_clk = {
1241 .enable_reg = 0x2404,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "avsync_vp_clk",
1245 .parent_names = (const char *[]){
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1255 static struct clk_branch camss_ahb_clk = {
1258 .enable_reg = 0x348c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "camss_ahb_clk",
1262 .parent_names = (const char *[]){
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1272 static struct clk_branch camss_cci_cci_ahb_clk = {
1275 .enable_reg = 0x3348,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "camss_cci_cci_ahb_clk",
1279 .parent_names = (const char *[]){
1283 .ops = &clk_branch2_ops,
1288 static struct clk_branch camss_cci_cci_clk = {
1291 .enable_reg = 0x3344,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "camss_cci_cci_clk",
1295 .parent_names = (const char *[]){
1299 .flags = CLK_SET_RATE_PARENT,
1300 .ops = &clk_branch2_ops,
1305 static struct clk_branch camss_csi0_ahb_clk = {
1308 .enable_reg = 0x30bc,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "camss_csi0_ahb_clk",
1312 .parent_names = (const char *[]){
1316 .ops = &clk_branch2_ops,
1321 static struct clk_branch camss_csi0_clk = {
1324 .enable_reg = 0x30b4,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "camss_csi0_clk",
1328 .parent_names = (const char *[]){
1332 .flags = CLK_SET_RATE_PARENT,
1333 .ops = &clk_branch2_ops,
1338 static struct clk_branch camss_csi0phy_clk = {
1341 .enable_reg = 0x30c4,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "camss_csi0phy_clk",
1345 .parent_names = (const char *[]){
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1355 static struct clk_branch camss_csi0pix_clk = {
1358 .enable_reg = 0x30e4,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "camss_csi0pix_clk",
1362 .parent_names = (const char *[]){
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1372 static struct clk_branch camss_csi0rdi_clk = {
1375 .enable_reg = 0x30d4,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "camss_csi0rdi_clk",
1379 .parent_names = (const char *[]){
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1389 static struct clk_branch camss_csi1_ahb_clk = {
1392 .enable_reg = 0x3128,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "camss_csi1_ahb_clk",
1396 .parent_names = (const char *[]){
1400 .flags = CLK_SET_RATE_PARENT,
1401 .ops = &clk_branch2_ops,
1406 static struct clk_branch camss_csi1_clk = {
1409 .enable_reg = 0x3124,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "camss_csi1_clk",
1413 .parent_names = (const char *[]){
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1423 static struct clk_branch camss_csi1phy_clk = {
1426 .enable_reg = 0x3134,
1427 .enable_mask = BIT(0),
1428 .hw.init = &(struct clk_init_data){
1429 .name = "camss_csi1phy_clk",
1430 .parent_names = (const char *[]){
1434 .flags = CLK_SET_RATE_PARENT,
1435 .ops = &clk_branch2_ops,
1440 static struct clk_branch camss_csi1pix_clk = {
1443 .enable_reg = 0x3154,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "camss_csi1pix_clk",
1447 .parent_names = (const char *[]){
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1457 static struct clk_branch camss_csi1rdi_clk = {
1460 .enable_reg = 0x3144,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "camss_csi1rdi_clk",
1464 .parent_names = (const char *[]){
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1474 static struct clk_branch camss_csi2_ahb_clk = {
1477 .enable_reg = 0x3188,
1478 .enable_mask = BIT(0),
1479 .hw.init = &(struct clk_init_data){
1480 .name = "camss_csi2_ahb_clk",
1481 .parent_names = (const char *[]){
1485 .ops = &clk_branch2_ops,
1490 static struct clk_branch camss_csi2_clk = {
1493 .enable_reg = 0x3184,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "camss_csi2_clk",
1497 .parent_names = (const char *[]){
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch camss_csi2phy_clk = {
1510 .enable_reg = 0x3194,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "camss_csi2phy_clk",
1514 .parent_names = (const char *[]){
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1524 static struct clk_branch camss_csi2pix_clk = {
1527 .enable_reg = 0x31b4,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "camss_csi2pix_clk",
1531 .parent_names = (const char *[]){
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1541 static struct clk_branch camss_csi2rdi_clk = {
1544 .enable_reg = 0x31a4,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "camss_csi2rdi_clk",
1548 .parent_names = (const char *[]){
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1558 static struct clk_branch camss_csi3_ahb_clk = {
1561 .enable_reg = 0x31e8,
1562 .enable_mask = BIT(0),
1563 .hw.init = &(struct clk_init_data){
1564 .name = "camss_csi3_ahb_clk",
1565 .parent_names = (const char *[]){
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch camss_csi3_clk = {
1577 .enable_reg = 0x31e4,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "camss_csi3_clk",
1581 .parent_names = (const char *[]){
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1591 static struct clk_branch camss_csi3phy_clk = {
1594 .enable_reg = 0x31f4,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "camss_csi3phy_clk",
1598 .parent_names = (const char *[]){
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1608 static struct clk_branch camss_csi3pix_clk = {
1611 .enable_reg = 0x3214,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "camss_csi3pix_clk",
1615 .parent_names = (const char *[]){
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1625 static struct clk_branch camss_csi3rdi_clk = {
1628 .enable_reg = 0x3204,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "camss_csi3rdi_clk",
1632 .parent_names = (const char *[]){
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1642 static struct clk_branch camss_csi_vfe0_clk = {
1645 .enable_reg = 0x3704,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "camss_csi_vfe0_clk",
1649 .parent_names = (const char *[]){
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch camss_csi_vfe1_clk = {
1662 .enable_reg = 0x3714,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "camss_csi_vfe1_clk",
1666 .parent_names = (const char *[]){
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch camss_gp0_clk = {
1679 .enable_reg = 0x3444,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "camss_gp0_clk",
1683 .parent_names = (const char *[]){
1684 "camss_gp0_clk_src",
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch camss_gp1_clk = {
1696 .enable_reg = 0x3474,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "camss_gp1_clk",
1700 .parent_names = (const char *[]){
1701 "camss_gp1_clk_src",
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1710 static struct clk_branch camss_ispif_ahb_clk = {
1713 .enable_reg = 0x3224,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "camss_ispif_ahb_clk",
1717 .parent_names = (const char *[]){
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1727 static struct clk_branch camss_jpeg_jpeg0_clk = {
1730 .enable_reg = 0x35a8,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "camss_jpeg_jpeg0_clk",
1734 .parent_names = (const char *[]){
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch camss_jpeg_jpeg1_clk = {
1747 .enable_reg = 0x35ac,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_jpeg_jpeg1_clk",
1751 .parent_names = (const char *[]){
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch camss_jpeg_jpeg2_clk = {
1764 .enable_reg = 0x35b0,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "camss_jpeg_jpeg2_clk",
1768 .parent_names = (const char *[]){
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1778 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1781 .enable_reg = 0x35b4,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "camss_jpeg_jpeg_ahb_clk",
1785 .parent_names = (const char *[]){
1789 .ops = &clk_branch2_ops,
1794 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1797 .enable_reg = 0x35b8,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "camss_jpeg_jpeg_axi_clk",
1801 .parent_names = (const char *[]){
1805 .ops = &clk_branch2_ops,
1810 static struct clk_branch camss_mclk0_clk = {
1813 .enable_reg = 0x3384,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "camss_mclk0_clk",
1817 .parent_names = (const char *[]){
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1827 static struct clk_branch camss_mclk1_clk = {
1830 .enable_reg = 0x33b4,
1831 .enable_mask = BIT(0),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "camss_mclk1_clk",
1834 .parent_names = (const char *[]){
1838 .flags = CLK_SET_RATE_PARENT,
1839 .ops = &clk_branch2_ops,
1844 static struct clk_branch camss_mclk2_clk = {
1847 .enable_reg = 0x33e4,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "camss_mclk2_clk",
1851 .parent_names = (const char *[]){
1855 .flags = CLK_SET_RATE_PARENT,
1856 .ops = &clk_branch2_ops,
1861 static struct clk_branch camss_mclk3_clk = {
1864 .enable_reg = 0x3414,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "camss_mclk3_clk",
1868 .parent_names = (const char *[]){
1872 .flags = CLK_SET_RATE_PARENT,
1873 .ops = &clk_branch2_ops,
1878 static struct clk_branch camss_micro_ahb_clk = {
1881 .enable_reg = 0x3494,
1882 .enable_mask = BIT(0),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "camss_micro_ahb_clk",
1885 .parent_names = (const char *[]){
1889 .ops = &clk_branch2_ops,
1894 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1897 .enable_reg = 0x3024,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "camss_phy0_csi0phytimer_clk",
1901 .parent_names = (const char *[]){
1902 "csi0phytimer_clk_src",
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1911 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1914 .enable_reg = 0x3054,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "camss_phy1_csi1phytimer_clk",
1918 .parent_names = (const char *[]){
1919 "csi1phytimer_clk_src",
1922 .flags = CLK_SET_RATE_PARENT,
1923 .ops = &clk_branch2_ops,
1928 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1931 .enable_reg = 0x3084,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "camss_phy2_csi2phytimer_clk",
1935 .parent_names = (const char *[]){
1936 "csi2phytimer_clk_src",
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1945 static struct clk_branch camss_top_ahb_clk = {
1948 .enable_reg = 0x3484,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "camss_top_ahb_clk",
1952 .parent_names = (const char *[]){
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1962 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1965 .enable_reg = 0x36b4,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "camss_vfe_cpp_ahb_clk",
1969 .parent_names = (const char *[]){
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_branch2_ops,
1979 static struct clk_branch camss_vfe_cpp_clk = {
1982 .enable_reg = 0x36b0,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "camss_vfe_cpp_clk",
1986 .parent_names = (const char *[]){
1990 .flags = CLK_SET_RATE_PARENT,
1991 .ops = &clk_branch2_ops,
1996 static struct clk_branch camss_vfe_vfe0_clk = {
1999 .enable_reg = 0x36a8,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "camss_vfe_vfe0_clk",
2003 .parent_names = (const char *[]){
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2013 static struct clk_branch camss_vfe_vfe1_clk = {
2016 .enable_reg = 0x36ac,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "camss_vfe_vfe1_clk",
2020 .parent_names = (const char *[]){
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2030 static struct clk_branch camss_vfe_vfe_ahb_clk = {
2033 .enable_reg = 0x36b8,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "camss_vfe_vfe_ahb_clk",
2037 .parent_names = (const char *[]){
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2047 static struct clk_branch camss_vfe_vfe_axi_clk = {
2050 .enable_reg = 0x36bc,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "camss_vfe_vfe_axi_clk",
2054 .parent_names = (const char *[]){
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2064 static struct clk_branch mdss_ahb_clk = {
2067 .enable_reg = 0x2308,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mdss_ahb_clk",
2071 .parent_names = (const char *[]){
2075 .flags = CLK_SET_RATE_PARENT,
2076 .ops = &clk_branch2_ops,
2081 static struct clk_branch mdss_axi_clk = {
2084 .enable_reg = 0x2310,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mdss_axi_clk",
2088 .parent_names = (const char *[]){
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2098 static struct clk_branch mdss_byte0_clk = {
2101 .enable_reg = 0x233c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mdss_byte0_clk",
2105 .parent_names = (const char *[]){
2109 .flags = CLK_SET_RATE_PARENT,
2110 .ops = &clk_branch2_ops,
2115 static struct clk_branch mdss_byte1_clk = {
2118 .enable_reg = 0x2340,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mdss_byte1_clk",
2122 .parent_names = (const char *[]){
2126 .flags = CLK_SET_RATE_PARENT,
2127 .ops = &clk_branch2_ops,
2132 static struct clk_branch mdss_edpaux_clk = {
2135 .enable_reg = 0x2334,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "mdss_edpaux_clk",
2139 .parent_names = (const char *[]){
2143 .flags = CLK_SET_RATE_PARENT,
2144 .ops = &clk_branch2_ops,
2149 static struct clk_branch mdss_edplink_clk = {
2152 .enable_reg = 0x2330,
2153 .enable_mask = BIT(0),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "mdss_edplink_clk",
2156 .parent_names = (const char *[]){
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2166 static struct clk_branch mdss_edppixel_clk = {
2169 .enable_reg = 0x232c,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "mdss_edppixel_clk",
2173 .parent_names = (const char *[]){
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2183 static struct clk_branch mdss_esc0_clk = {
2186 .enable_reg = 0x2344,
2187 .enable_mask = BIT(0),
2188 .hw.init = &(struct clk_init_data){
2189 .name = "mdss_esc0_clk",
2190 .parent_names = (const char *[]){
2194 .flags = CLK_SET_RATE_PARENT,
2195 .ops = &clk_branch2_ops,
2200 static struct clk_branch mdss_esc1_clk = {
2203 .enable_reg = 0x2348,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(struct clk_init_data){
2206 .name = "mdss_esc1_clk",
2207 .parent_names = (const char *[]){
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2217 static struct clk_branch mdss_extpclk_clk = {
2220 .enable_reg = 0x2324,
2221 .enable_mask = BIT(0),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "mdss_extpclk_clk",
2224 .parent_names = (const char *[]){
2228 .flags = CLK_SET_RATE_PARENT,
2229 .ops = &clk_branch2_ops,
2234 static struct clk_branch mdss_hdmi_ahb_clk = {
2237 .enable_reg = 0x230c,
2238 .enable_mask = BIT(0),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "mdss_hdmi_ahb_clk",
2241 .parent_names = (const char *[]){
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2251 static struct clk_branch mdss_hdmi_clk = {
2254 .enable_reg = 0x2338,
2255 .enable_mask = BIT(0),
2256 .hw.init = &(struct clk_init_data){
2257 .name = "mdss_hdmi_clk",
2258 .parent_names = (const char *[]){
2262 .flags = CLK_SET_RATE_PARENT,
2263 .ops = &clk_branch2_ops,
2268 static struct clk_branch mdss_mdp_clk = {
2271 .enable_reg = 0x231c,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "mdss_mdp_clk",
2275 .parent_names = (const char *[]){
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2285 static struct clk_branch mdss_mdp_lut_clk = {
2288 .enable_reg = 0x2320,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "mdss_mdp_lut_clk",
2292 .parent_names = (const char *[]){
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2302 static struct clk_branch mdss_pclk0_clk = {
2305 .enable_reg = 0x2314,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "mdss_pclk0_clk",
2309 .parent_names = (const char *[]){
2313 .flags = CLK_SET_RATE_PARENT,
2314 .ops = &clk_branch2_ops,
2319 static struct clk_branch mdss_pclk1_clk = {
2322 .enable_reg = 0x2318,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "mdss_pclk1_clk",
2326 .parent_names = (const char *[]){
2330 .flags = CLK_SET_RATE_PARENT,
2331 .ops = &clk_branch2_ops,
2336 static struct clk_branch mdss_vsync_clk = {
2339 .enable_reg = 0x2328,
2340 .enable_mask = BIT(0),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "mdss_vsync_clk",
2343 .parent_names = (const char *[]){
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2353 static struct clk_branch mmss_rbcpr_ahb_clk = {
2356 .enable_reg = 0x4088,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "mmss_rbcpr_ahb_clk",
2360 .parent_names = (const char *[]){
2364 .flags = CLK_SET_RATE_PARENT,
2365 .ops = &clk_branch2_ops,
2370 static struct clk_branch mmss_rbcpr_clk = {
2373 .enable_reg = 0x4084,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "mmss_rbcpr_clk",
2377 .parent_names = (const char *[]){
2381 .flags = CLK_SET_RATE_PARENT,
2382 .ops = &clk_branch2_ops,
2387 static struct clk_branch mmss_spdm_ahb_clk = {
2390 .enable_reg = 0x0230,
2391 .enable_mask = BIT(0),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "mmss_spdm_ahb_clk",
2394 .parent_names = (const char *[]){
2395 "mmss_spdm_ahb_div_clk",
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_branch2_ops,
2404 static struct clk_branch mmss_spdm_axi_clk = {
2407 .enable_reg = 0x0210,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "mmss_spdm_axi_clk",
2411 .parent_names = (const char *[]){
2412 "mmss_spdm_axi_div_clk",
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2421 static struct clk_branch mmss_spdm_csi0_clk = {
2424 .enable_reg = 0x023c,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "mmss_spdm_csi0_clk",
2428 .parent_names = (const char *[]){
2429 "mmss_spdm_csi0_div_clk",
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2438 static struct clk_branch mmss_spdm_gfx3d_clk = {
2441 .enable_reg = 0x022c,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "mmss_spdm_gfx3d_clk",
2445 .parent_names = (const char *[]){
2446 "mmss_spdm_gfx3d_div_clk",
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2455 static struct clk_branch mmss_spdm_jpeg0_clk = {
2458 .enable_reg = 0x0204,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "mmss_spdm_jpeg0_clk",
2462 .parent_names = (const char *[]){
2463 "mmss_spdm_jpeg0_div_clk",
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2472 static struct clk_branch mmss_spdm_jpeg1_clk = {
2475 .enable_reg = 0x0208,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "mmss_spdm_jpeg1_clk",
2479 .parent_names = (const char *[]){
2480 "mmss_spdm_jpeg1_div_clk",
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2489 static struct clk_branch mmss_spdm_jpeg2_clk = {
2492 .enable_reg = 0x0224,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mmss_spdm_jpeg2_clk",
2496 .parent_names = (const char *[]){
2497 "mmss_spdm_jpeg2_div_clk",
2500 .flags = CLK_SET_RATE_PARENT,
2501 .ops = &clk_branch2_ops,
2506 static struct clk_branch mmss_spdm_mdp_clk = {
2509 .enable_reg = 0x020c,
2510 .enable_mask = BIT(0),
2511 .hw.init = &(struct clk_init_data){
2512 .name = "mmss_spdm_mdp_clk",
2513 .parent_names = (const char *[]){
2514 "mmss_spdm_mdp_div_clk",
2517 .flags = CLK_SET_RATE_PARENT,
2518 .ops = &clk_branch2_ops,
2523 static struct clk_branch mmss_spdm_pclk0_clk = {
2526 .enable_reg = 0x0234,
2527 .enable_mask = BIT(0),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "mmss_spdm_pclk0_clk",
2530 .parent_names = (const char *[]){
2531 "mmss_spdm_pclk0_div_clk",
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2540 static struct clk_branch mmss_spdm_pclk1_clk = {
2543 .enable_reg = 0x0228,
2544 .enable_mask = BIT(0),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "mmss_spdm_pclk1_clk",
2547 .parent_names = (const char *[]){
2548 "mmss_spdm_pclk1_div_clk",
2551 .flags = CLK_SET_RATE_PARENT,
2552 .ops = &clk_branch2_ops,
2557 static struct clk_branch mmss_spdm_vcodec0_clk = {
2560 .enable_reg = 0x0214,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "mmss_spdm_vcodec0_clk",
2564 .parent_names = (const char *[]){
2565 "mmss_spdm_vcodec0_div_clk",
2568 .flags = CLK_SET_RATE_PARENT,
2569 .ops = &clk_branch2_ops,
2574 static struct clk_branch mmss_spdm_vfe0_clk = {
2577 .enable_reg = 0x0218,
2578 .enable_mask = BIT(0),
2579 .hw.init = &(struct clk_init_data){
2580 .name = "mmss_spdm_vfe0_clk",
2581 .parent_names = (const char *[]){
2582 "mmss_spdm_vfe0_div_clk",
2585 .flags = CLK_SET_RATE_PARENT,
2586 .ops = &clk_branch2_ops,
2591 static struct clk_branch mmss_spdm_vfe1_clk = {
2594 .enable_reg = 0x021c,
2595 .enable_mask = BIT(0),
2596 .hw.init = &(struct clk_init_data){
2597 .name = "mmss_spdm_vfe1_clk",
2598 .parent_names = (const char *[]){
2599 "mmss_spdm_vfe1_div_clk",
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2608 static struct clk_branch mmss_spdm_rm_axi_clk = {
2611 .enable_reg = 0x0304,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "mmss_spdm_rm_axi_clk",
2615 .parent_names = (const char *[]){
2619 .flags = CLK_SET_RATE_PARENT,
2620 .ops = &clk_branch2_ops,
2625 static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2628 .enable_reg = 0x0308,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "mmss_spdm_rm_ocmemnoc_clk",
2632 .parent_names = (const char *[]){
2636 .flags = CLK_SET_RATE_PARENT,
2637 .ops = &clk_branch2_ops,
2643 static struct clk_branch mmss_misc_ahb_clk = {
2646 .enable_reg = 0x502c,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "mmss_misc_ahb_clk",
2650 .parent_names = (const char *[]){
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2660 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2663 .enable_reg = 0x5024,
2664 .enable_mask = BIT(0),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "mmss_mmssnoc_ahb_clk",
2667 .parent_names = (const char *[]){
2671 .ops = &clk_branch2_ops,
2672 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2677 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2680 .enable_reg = 0x5028,
2681 .enable_mask = BIT(0),
2682 .hw.init = &(struct clk_init_data){
2683 .name = "mmss_mmssnoc_bto_ahb_clk",
2684 .parent_names = (const char *[]){
2688 .ops = &clk_branch2_ops,
2689 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2694 static struct clk_branch mmss_mmssnoc_axi_clk = {
2697 .enable_reg = 0x506c,
2698 .enable_mask = BIT(0),
2699 .hw.init = &(struct clk_init_data){
2700 .name = "mmss_mmssnoc_axi_clk",
2701 .parent_names = (const char *[]){
2705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2706 .ops = &clk_branch2_ops,
2711 static struct clk_branch mmss_s0_axi_clk = {
2714 .enable_reg = 0x5064,
2715 .enable_mask = BIT(0),
2716 .hw.init = &(struct clk_init_data){
2717 .name = "mmss_s0_axi_clk",
2718 .parent_names = (const char *[]){
2722 .ops = &clk_branch2_ops,
2723 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2728 static struct clk_branch ocmemcx_ahb_clk = {
2731 .enable_reg = 0x405c,
2732 .enable_mask = BIT(0),
2733 .hw.init = &(struct clk_init_data){
2734 .name = "ocmemcx_ahb_clk",
2735 .parent_names = (const char *[]){
2739 .flags = CLK_SET_RATE_PARENT,
2740 .ops = &clk_branch2_ops,
2745 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2748 .enable_reg = 0x4058,
2749 .enable_mask = BIT(0),
2750 .hw.init = &(struct clk_init_data){
2751 .name = "ocmemcx_ocmemnoc_clk",
2752 .parent_names = (const char *[]){
2756 .flags = CLK_SET_RATE_PARENT,
2757 .ops = &clk_branch2_ops,
2762 static struct clk_branch oxili_ocmemgx_clk = {
2765 .enable_reg = 0x402c,
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data){
2768 .name = "oxili_ocmemgx_clk",
2769 .parent_names = (const char *[]){
2773 .flags = CLK_SET_RATE_PARENT,
2774 .ops = &clk_branch2_ops,
2779 static struct clk_branch oxili_gfx3d_clk = {
2782 .enable_reg = 0x4028,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "oxili_gfx3d_clk",
2786 .parent_names = (const char *[]){
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2796 static struct clk_branch oxili_rbbmtimer_clk = {
2799 .enable_reg = 0x40b0,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "oxili_rbbmtimer_clk",
2803 .parent_names = (const char *[]){
2804 "rbbmtimer_clk_src",
2807 .flags = CLK_SET_RATE_PARENT,
2808 .ops = &clk_branch2_ops,
2813 static struct clk_branch oxilicx_ahb_clk = {
2816 .enable_reg = 0x403c,
2817 .enable_mask = BIT(0),
2818 .hw.init = &(struct clk_init_data){
2819 .name = "oxilicx_ahb_clk",
2820 .parent_names = (const char *[]){
2824 .flags = CLK_SET_RATE_PARENT,
2825 .ops = &clk_branch2_ops,
2830 static struct clk_branch venus0_ahb_clk = {
2833 .enable_reg = 0x1030,
2834 .enable_mask = BIT(0),
2835 .hw.init = &(struct clk_init_data){
2836 .name = "venus0_ahb_clk",
2837 .parent_names = (const char *[]){
2841 .flags = CLK_SET_RATE_PARENT,
2842 .ops = &clk_branch2_ops,
2847 static struct clk_branch venus0_axi_clk = {
2850 .enable_reg = 0x1034,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "venus0_axi_clk",
2854 .parent_names = (const char *[]){
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2864 static struct clk_branch venus0_core0_vcodec_clk = {
2867 .enable_reg = 0x1048,
2868 .enable_mask = BIT(0),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "venus0_core0_vcodec_clk",
2871 .parent_names = (const char *[]){
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2881 static struct clk_branch venus0_core1_vcodec_clk = {
2884 .enable_reg = 0x104c,
2885 .enable_mask = BIT(0),
2886 .hw.init = &(struct clk_init_data){
2887 .name = "venus0_core1_vcodec_clk",
2888 .parent_names = (const char *[]){
2892 .flags = CLK_SET_RATE_PARENT,
2893 .ops = &clk_branch2_ops,
2898 static struct clk_branch venus0_ocmemnoc_clk = {
2901 .enable_reg = 0x1038,
2902 .enable_mask = BIT(0),
2903 .hw.init = &(struct clk_init_data){
2904 .name = "venus0_ocmemnoc_clk",
2905 .parent_names = (const char *[]){
2909 .flags = CLK_SET_RATE_PARENT,
2910 .ops = &clk_branch2_ops,
2915 static struct clk_branch venus0_vcodec0_clk = {
2918 .enable_reg = 0x1028,
2919 .enable_mask = BIT(0),
2920 .hw.init = &(struct clk_init_data){
2921 .name = "venus0_vcodec0_clk",
2922 .parent_names = (const char *[]){
2926 .flags = CLK_SET_RATE_PARENT,
2927 .ops = &clk_branch2_ops,
2932 static struct clk_branch vpu_ahb_clk = {
2935 .enable_reg = 0x1430,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "vpu_ahb_clk",
2939 .parent_names = (const char *[]){
2943 .flags = CLK_SET_RATE_PARENT,
2944 .ops = &clk_branch2_ops,
2949 static struct clk_branch vpu_axi_clk = {
2952 .enable_reg = 0x143c,
2953 .enable_mask = BIT(0),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "vpu_axi_clk",
2956 .parent_names = (const char *[]){
2960 .flags = CLK_SET_RATE_PARENT,
2961 .ops = &clk_branch2_ops,
2966 static struct clk_branch vpu_bus_clk = {
2969 .enable_reg = 0x1440,
2970 .enable_mask = BIT(0),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "vpu_bus_clk",
2973 .parent_names = (const char *[]){
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2983 static struct clk_branch vpu_cxo_clk = {
2986 .enable_reg = 0x1434,
2987 .enable_mask = BIT(0),
2988 .hw.init = &(struct clk_init_data){
2989 .name = "vpu_cxo_clk",
2990 .parent_names = (const char *[]){ "xo" },
2992 .flags = CLK_SET_RATE_PARENT,
2993 .ops = &clk_branch2_ops,
2998 static struct clk_branch vpu_maple_clk = {
3001 .enable_reg = 0x142c,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "vpu_maple_clk",
3005 .parent_names = (const char *[]){
3009 .flags = CLK_SET_RATE_PARENT,
3010 .ops = &clk_branch2_ops,
3015 static struct clk_branch vpu_sleep_clk = {
3018 .enable_reg = 0x1438,
3019 .enable_mask = BIT(0),
3020 .hw.init = &(struct clk_init_data){
3021 .name = "vpu_sleep_clk",
3022 .parent_names = (const char *[]){
3026 .flags = CLK_SET_RATE_PARENT,
3027 .ops = &clk_branch2_ops,
3032 static struct clk_branch vpu_vdp_clk = {
3035 .enable_reg = 0x1428,
3036 .enable_mask = BIT(0),
3037 .hw.init = &(struct clk_init_data){
3038 .name = "vpu_vdp_clk",
3039 .parent_names = (const char *[]){
3043 .flags = CLK_SET_RATE_PARENT,
3044 .ops = &clk_branch2_ops,
3049 static const struct pll_config mmpll1_config = {
3054 .vco_mask = 0x3 << 20,
3056 .pre_div_mask = 0x7 << 12,
3057 .post_div_val = 0x0,
3058 .post_div_mask = 0x3 << 8,
3059 .mn_ena_mask = BIT(24),
3060 .main_output_mask = BIT(0),
3063 static const struct pll_config mmpll3_config = {
3068 .vco_mask = 0x3 << 20,
3070 .pre_div_mask = 0x7 << 12,
3071 .post_div_val = 0x0,
3072 .post_div_mask = 0x3 << 8,
3073 .mn_ena_mask = BIT(24),
3074 .main_output_mask = BIT(0),
3075 .aux_output_mask = BIT(1),
3078 static struct clk_regmap *mmcc_apq8084_clocks[] = {
3079 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3080 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3081 [MMPLL0] = &mmpll0.clkr,
3082 [MMPLL0_VOTE] = &mmpll0_vote,
3083 [MMPLL1] = &mmpll1.clkr,
3084 [MMPLL1_VOTE] = &mmpll1_vote,
3085 [MMPLL2] = &mmpll2.clkr,
3086 [MMPLL3] = &mmpll3.clkr,
3087 [MMPLL4] = &mmpll4.clkr,
3088 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3089 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3090 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3091 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3092 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3093 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3094 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3095 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3096 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3097 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3098 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3099 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3100 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3101 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3102 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3103 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3104 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3105 [VP_CLK_SRC] = &vp_clk_src.clkr,
3106 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3107 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3108 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3109 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3110 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3111 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3112 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3113 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3114 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3115 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3116 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3117 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3118 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3119 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3120 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3121 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3122 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3123 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3124 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3125 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3126 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3127 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3128 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3129 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3130 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3131 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3132 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3133 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3134 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3135 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3136 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3137 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3138 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3139 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3140 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3141 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3142 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3143 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3144 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3145 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3146 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3147 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3148 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3149 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3150 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3151 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3152 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3153 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3154 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3155 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3156 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3157 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3158 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3159 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3160 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3161 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3162 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3163 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3164 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3165 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3166 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3167 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3168 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3169 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3170 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3171 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3172 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3173 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3174 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3175 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3176 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3177 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3178 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3179 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3180 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3181 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3182 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3183 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3184 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3185 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3186 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3187 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3188 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3189 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3190 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3191 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3192 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3193 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3194 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3195 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3196 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3197 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3198 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3199 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3200 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3201 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3202 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3203 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3204 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3205 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3206 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3207 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3208 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3209 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3210 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3211 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3212 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3213 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3214 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3215 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3216 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3217 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3218 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3219 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3220 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3221 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3222 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3223 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3224 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3225 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3226 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3227 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3228 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3229 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3230 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3231 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3232 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3233 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3234 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3235 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3236 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3237 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3238 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3239 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3240 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3241 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3242 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3243 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3246 static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3247 [MMSS_SPDM_RESET] = { 0x0200 },
3248 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3249 [VENUS0_RESET] = { 0x1020 },
3250 [VPU_RESET] = { 0x1400 },
3251 [MDSS_RESET] = { 0x2300 },
3252 [AVSYNC_RESET] = { 0x2400 },
3253 [CAMSS_PHY0_RESET] = { 0x3020 },
3254 [CAMSS_PHY1_RESET] = { 0x3050 },
3255 [CAMSS_PHY2_RESET] = { 0x3080 },
3256 [CAMSS_CSI0_RESET] = { 0x30b0 },
3257 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3258 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3259 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3260 [CAMSS_CSI1_RESET] = { 0x3120 },
3261 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3262 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3263 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3264 [CAMSS_CSI2_RESET] = { 0x3180 },
3265 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3266 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3267 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3268 [CAMSS_CSI3_RESET] = { 0x31e0 },
3269 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3270 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3271 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3272 [CAMSS_ISPIF_RESET] = { 0x3220 },
3273 [CAMSS_CCI_RESET] = { 0x3340 },
3274 [CAMSS_MCLK0_RESET] = { 0x3380 },
3275 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3276 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3277 [CAMSS_MCLK3_RESET] = { 0x3410 },
3278 [CAMSS_GP0_RESET] = { 0x3440 },
3279 [CAMSS_GP1_RESET] = { 0x3470 },
3280 [CAMSS_TOP_RESET] = { 0x3480 },
3281 [CAMSS_AHB_RESET] = { 0x3488 },
3282 [CAMSS_MICRO_RESET] = { 0x3490 },
3283 [CAMSS_JPEG_RESET] = { 0x35a0 },
3284 [CAMSS_VFE_RESET] = { 0x36a0 },
3285 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3286 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3287 [OXILI_RESET] = { 0x4020 },
3288 [OXILICX_RESET] = { 0x4030 },
3289 [OCMEMCX_RESET] = { 0x4050 },
3290 [MMSS_RBCRP_RESET] = { 0x4080 },
3291 [MMSSNOCAHB_RESET] = { 0x5020 },
3292 [MMSSNOCAXI_RESET] = { 0x5060 },
3295 static const struct regmap_config mmcc_apq8084_regmap_config = {
3299 .max_register = 0x5104,
3303 static const struct qcom_cc_desc mmcc_apq8084_desc = {
3304 .config = &mmcc_apq8084_regmap_config,
3305 .clks = mmcc_apq8084_clocks,
3306 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3307 .resets = mmcc_apq8084_resets,
3308 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3311 static const struct of_device_id mmcc_apq8084_match_table[] = {
3312 { .compatible = "qcom,mmcc-apq8084" },
3315 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3317 static int mmcc_apq8084_probe(struct platform_device *pdev)
3320 struct regmap *regmap;
3322 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3326 regmap = dev_get_regmap(&pdev->dev, NULL);
3327 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3328 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3333 static int mmcc_apq8084_remove(struct platform_device *pdev)
3335 qcom_cc_remove(pdev);
3339 static struct platform_driver mmcc_apq8084_driver = {
3340 .probe = mmcc_apq8084_probe,
3341 .remove = mmcc_apq8084_remove,
3343 .name = "mmcc-apq8084",
3344 .of_match_table = mmcc_apq8084_match_table,
3347 module_platform_driver(mmcc_apq8084_driver);
3349 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3350 MODULE_LICENSE("GPL v2");
3351 MODULE_ALIAS("platform:mmcc-apq8084");