drivers/clk/renesas/r8a7795-cpg-mssr.c

   1 /*
   2  * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2015 Glider bvba
   5  *
   6  * Based on clk-rcar-gen3.c
   7  *
   8  * Copyright (C) 2015 Renesas Electronics Corp.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  */
  14
  15 #include <linux/bug.h>
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/device.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/of.h>
  24 #include <linux/slab.h>
  25
  26 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  27
  28 #include "renesas-cpg-mssr.h"
  29
  30 #define CPG_RCKCR       0x240
  31
  32 enum clk_ids {
  33         /* Core Clock Outputs exported to DT */
  34         LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
  35
  36         /* External Input Clocks */
  37         CLK_EXTAL,
  38         CLK_EXTALR,
  39
  40         /* Internal Core Clocks */
  41         CLK_MAIN,
  42         CLK_PLL0,
  43         CLK_PLL1,
  44         CLK_PLL2,
  45         CLK_PLL3,
  46         CLK_PLL4,
  47         CLK_PLL1_DIV2,
  48         CLK_PLL1_DIV4,
  49         CLK_S0,
  50         CLK_S1,
  51         CLK_S2,
  52         CLK_S3,
  53         CLK_SDSRC,
  54         CLK_SSPSRC,
  55         CLK_RINT,
  56
  57         /* Module Clocks */
  58         MOD_CLK_BASE
  59 };
  60
  61 enum r8a7795_clk_types {
  62         CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
  63         CLK_TYPE_GEN3_PLL0,
  64         CLK_TYPE_GEN3_PLL1,
  65         CLK_TYPE_GEN3_PLL2,
  66         CLK_TYPE_GEN3_PLL3,
  67         CLK_TYPE_GEN3_PLL4,
  68         CLK_TYPE_GEN3_SD,
  69         CLK_TYPE_GEN3_R,
  70 };
  71
  72 #define DEF_GEN3_SD(_name, _id, _parent, _offset)       \
  73         DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
  74
  75 static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
  76         /* External Clock Inputs */
  77         DEF_INPUT("extal",  CLK_EXTAL),
  78         DEF_INPUT("extalr", CLK_EXTALR),
  79
  80         /* Internal Core Clocks */
  81         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  82         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  83         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  84         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  85         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  86         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  87
  88         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  89         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  90         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  91         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  92         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  93         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  94
  95         /* Core Clock Outputs */
  96         DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  97         DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  98         DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  99         DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
 100         DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),
 101         DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),
 102         DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),
 103         DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),
 104         DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
 105         DEF_FIXED("s2d1",       R8A7795_CLK_S2D1,  CLK_S2,         1, 1),
 106         DEF_FIXED("s2d2",       R8A7795_CLK_S2D2,  CLK_S2,         2, 1),
 107         DEF_FIXED("s2d4",       R8A7795_CLK_S2D4,  CLK_S2,         4, 1),
 108         DEF_FIXED("s3d1",       R8A7795_CLK_S3D1,  CLK_S3,         1, 1),
 109         DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
 110         DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 111
 112         DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_PLL1_DIV2, 0x0074),
 113         DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_PLL1_DIV2, 0x0078),
 114         DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_PLL1_DIV2, 0x0268),
 115         DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_PLL1_DIV2, 0x026c),
 116
 117         DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 118         DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
 119
 120         DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
 121         DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
 122         DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
 123         DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 124
 125         DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),
 126         DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
 127
 128         DEF_BASE("r",           R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
 129 };
 130
 131 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
 132         DEF_MOD("scif5",                 202,   R8A7795_CLK_S3D4),
 133         DEF_MOD("scif4",                 203,   R8A7795_CLK_S3D4),
 134         DEF_MOD("scif3",                 204,   R8A7795_CLK_S3D4),
 135         DEF_MOD("scif1",                 206,   R8A7795_CLK_S3D4),
 136         DEF_MOD("scif0",                 207,   R8A7795_CLK_S3D4),
 137         DEF_MOD("msiof3",                208,   R8A7795_CLK_MSO),
 138         DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
 139         DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
 140         DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
 141         DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S3D1),
 142         DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S3D1),
 143         DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S3D1),
 144         DEF_MOD("scif2",                 310,   R8A7795_CLK_S3D4),
 145         DEF_MOD("sdif3",                 311,   R8A7795_CLK_SD3),
 146         DEF_MOD("sdif2",                 312,   R8A7795_CLK_SD2),
 147         DEF_MOD("sdif1",                 313,   R8A7795_CLK_SD1),
 148         DEF_MOD("sdif0",                 314,   R8A7795_CLK_SD0),
 149         DEF_MOD("pcie1",                 318,   R8A7795_CLK_S3D1),
 150         DEF_MOD("pcie0",                 319,   R8A7795_CLK_S3D1),
 151         DEF_MOD("usb3-if1",              327,   R8A7795_CLK_S3D1),
 152         DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
 153         DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
 154         DEF_MOD("usb-dmac1",             331,   R8A7795_CLK_S3D1),
 155         DEF_MOD("rwdt0",                 402,   R8A7795_CLK_R),
 156         DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
 157         DEF_MOD("intc-ap",               408,   R8A7795_CLK_S3D1),
 158         DEF_MOD("audmac0",               502,   R8A7795_CLK_S3D4),
 159         DEF_MOD("audmac1",               501,   R8A7795_CLK_S3D4),
 160         DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
 161         DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
 162         DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
 163         DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
 164         DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
 165         DEF_MOD("pwm",                   523,   R8A7795_CLK_S3D4),
 166         DEF_MOD("fcpvd3",                600,   R8A7795_CLK_S2D1),
 167         DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S2D1),
 168         DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S2D1),
 169         DEF_MOD("fcpvd0",                603,   R8A7795_CLK_S2D1),
 170         DEF_MOD("fcpvb1",                606,   R8A7795_CLK_S2D1),
 171         DEF_MOD("fcpvb0",                607,   R8A7795_CLK_S2D1),
 172         DEF_MOD("fcpvi2",                609,   R8A7795_CLK_S2D1),
 173         DEF_MOD("fcpvi1",                610,   R8A7795_CLK_S2D1),
 174         DEF_MOD("fcpvi0",                611,   R8A7795_CLK_S2D1),
 175         DEF_MOD("fcpf2",                 613,   R8A7795_CLK_S2D1),
 176         DEF_MOD("fcpf1",                 614,   R8A7795_CLK_S2D1),
 177         DEF_MOD("fcpf0",                 615,   R8A7795_CLK_S2D1),
 178         DEF_MOD("fcpci1",                616,   R8A7795_CLK_S2D1),
 179         DEF_MOD("fcpci0",                617,   R8A7795_CLK_S2D1),
 180         DEF_MOD("fcpcs",                 619,   R8A7795_CLK_S2D1),
 181         DEF_MOD("vspd3",                 620,   R8A7795_CLK_S2D1),
 182         DEF_MOD("vspd2",                 621,   R8A7795_CLK_S2D1),
 183         DEF_MOD("vspd1",                 622,   R8A7795_CLK_S2D1),
 184         DEF_MOD("vspd0",                 623,   R8A7795_CLK_S2D1),
 185         DEF_MOD("vspbc",                 624,   R8A7795_CLK_S2D1),
 186         DEF_MOD("vspbd",                 626,   R8A7795_CLK_S2D1),
 187         DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1),
 188         DEF_MOD("vspi1",                 630,   R8A7795_CLK_S2D1),
 189         DEF_MOD("vspi0",                 631,   R8A7795_CLK_S2D1),
 190         DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D4),
 191         DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
 192         DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
 193         DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
 194         DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0),
 195         DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
 196         DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
 197         DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
 198         DEF_MOD("du3",                   721,   R8A7795_CLK_S2D1),
 199         DEF_MOD("du2",                   722,   R8A7795_CLK_S2D1),
 200         DEF_MOD("du1",                   723,   R8A7795_CLK_S2D1),
 201         DEF_MOD("du0",                   724,   R8A7795_CLK_S2D1),
 202         DEF_MOD("lvds",                  727,   R8A7795_CLK_S2D1),
 203         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
 204         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
 205         DEF_MOD("vin7",                  804,   R8A7795_CLK_S2D1),
 206         DEF_MOD("vin6",                  805,   R8A7795_CLK_S2D1),
 207         DEF_MOD("vin5",                  806,   R8A7795_CLK_S2D1),
 208         DEF_MOD("vin4",                  807,   R8A7795_CLK_S2D1),
 209         DEF_MOD("vin3",                  808,   R8A7795_CLK_S2D1),
 210         DEF_MOD("vin2",                  809,   R8A7795_CLK_S2D1),
 211         DEF_MOD("vin1",                  810,   R8A7795_CLK_S2D1),
 212         DEF_MOD("vin0",                  811,   R8A7795_CLK_S2D1),
 213         DEF_MOD("etheravb",              812,   R8A7795_CLK_S3D2),
 214         DEF_MOD("sata0",                 815,   R8A7795_CLK_S3D2),
 215         DEF_MOD("gpio7",                 905,   R8A7795_CLK_CP),
 216         DEF_MOD("gpio6",                 906,   R8A7795_CLK_CP),
 217         DEF_MOD("gpio5",                 907,   R8A7795_CLK_CP),
 218         DEF_MOD("gpio4",                 908,   R8A7795_CLK_CP),
 219         DEF_MOD("gpio3",                 909,   R8A7795_CLK_CP),
 220         DEF_MOD("gpio2",                 910,   R8A7795_CLK_CP),
 221         DEF_MOD("gpio1",                 911,   R8A7795_CLK_CP),
 222         DEF_MOD("gpio0",                 912,   R8A7795_CLK_CP),
 223         DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
 224         DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
 225         DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
 226         DEF_MOD("i2c6",                  918,   R8A7795_CLK_S3D2),
 227         DEF_MOD("i2c5",                  919,   R8A7795_CLK_S3D2),
 228         DEF_MOD("i2c4",                  927,   R8A7795_CLK_S3D2),
 229         DEF_MOD("i2c3",                  928,   R8A7795_CLK_S3D2),
 230         DEF_MOD("i2c2",                  929,   R8A7795_CLK_S3D2),
 231         DEF_MOD("i2c1",                  930,   R8A7795_CLK_S3D2),
 232         DEF_MOD("i2c0",                  931,   R8A7795_CLK_S3D2),
 233         DEF_MOD("ssi-all",              1005,   R8A7795_CLK_S3D4),
 234         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 235         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 236         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 237         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 238         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 239         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 240         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 241         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 242         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 243         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 244         DEF_MOD("scu-all",              1017,   R8A7795_CLK_S3D4),
 245         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 246         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 247         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 248         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 249         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 250         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 251         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 252         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 253         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 254         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 255         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 256         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 257         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 258         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 259 };
 260
 261 static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
 262         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 263 };
 264
 265 /* -----------------------------------------------------------------------------
 266  * SDn Clock
 267  *
 268  */
 269 #define CPG_SD_STP_HCK          BIT(9)
 270 #define CPG_SD_STP_CK           BIT(8)
 271
 272 #define CPG_SD_STP_MASK         (CPG_SD_STP_HCK | CPG_SD_STP_CK)
 273 #define CPG_SD_FC_MASK          (0x7 << 2 | 0x3 << 0)
 274
 275 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
 276 { \
 277         .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
 278                ((stp_ck) ? CPG_SD_STP_CK : 0) | \
 279                ((sd_srcfc) << 2) | \
 280                ((sd_fc) << 0), \
 281         .div = (sd_div), \
 282 }
 283
 284 struct sd_div_table {
 285         u32 val;
 286         unsigned int div;
 287 };
 288
 289 struct sd_clock {
 290         struct clk_hw hw;
 291         void __iomem *reg;
 292         const struct sd_div_table *div_table;
 293         unsigned int div_num;
 294         unsigned int div_min;
 295         unsigned int div_max;
 296 };
 297
 298 /* SDn divider
 299  *                     sd_srcfc   sd_fc   div
 300  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 301  *-------------------------------------------------------------------
 302  *  0         0         0 (1)      1 (4)      4
 303  *  0         0         1 (2)      1 (4)      8
 304  *  1         0         2 (4)      1 (4)     16
 305  *  1         0         3 (8)      1 (4)     32
 306  *  1         0         4 (16)     1 (4)     64
 307  *  0         0         0 (1)      0 (2)      2
 308  *  0         0         1 (2)      0 (2)      4
 309  *  1         0         2 (4)      0 (2)      8
 310  *  1         0         3 (8)      0 (2)     16
 311  *  1         0         4 (16)     0 (2)     32
 312  */
 313 static const struct sd_div_table cpg_sd_div_table[] = {
 314 /*      CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
 315         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
 316         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
 317         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
 318         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
 319         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
 320         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
 321         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
 322         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
 323         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
 324         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
 325 };
 326
 327 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
 328
 329 static int cpg_sd_clock_enable(struct clk_hw *hw)
 330 {
 331         struct sd_clock *clock = to_sd_clock(hw);
 332         u32 val, sd_fc;
 333         unsigned int i;
 334
 335         val = clk_readl(clock->reg);
 336
 337         sd_fc = val & CPG_SD_FC_MASK;
 338         for (i = 0; i < clock->div_num; i++)
 339                 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
 340                         break;
 341
 342         if (i >= clock->div_num)
 343                 return -EINVAL;
 344
 345         val &= ~(CPG_SD_STP_MASK);
 346         val |= clock->div_table[i].val & CPG_SD_STP_MASK;
 347
 348         clk_writel(val, clock->reg);
 349
 350         return 0;
 351 }
 352
 353 static void cpg_sd_clock_disable(struct clk_hw *hw)
 354 {
 355         struct sd_clock *clock = to_sd_clock(hw);
 356
 357         clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
 358 }
 359
 360 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
 361 {
 362         struct sd_clock *clock = to_sd_clock(hw);
 363
 364         return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
 365 }
 366
 367 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
 368                                                 unsigned long parent_rate)
 369 {
 370         struct sd_clock *clock = to_sd_clock(hw);
 371         unsigned long rate = parent_rate;
 372         u32 val, sd_fc;
 373         unsigned int i;
 374
 375         val = clk_readl(clock->reg);
 376
 377         sd_fc = val & CPG_SD_FC_MASK;
 378         for (i = 0; i < clock->div_num; i++)
 379                 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
 380                         break;
 381
 382         if (i >= clock->div_num)
 383                 return -EINVAL;
 384
 385         return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
 386 }
 387
 388 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
 389                                           unsigned long rate,
 390                                           unsigned long parent_rate)
 391 {
 392         unsigned int div;
 393
 394         if (!rate)
 395                 rate = 1;
 396
 397         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 398
 399         return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
 400 }
 401
 402 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
 403                                       unsigned long *parent_rate)
 404 {
 405         struct sd_clock *clock = to_sd_clock(hw);
 406         unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
 407
 408         return DIV_ROUND_CLOSEST(*parent_rate, div);
 409 }
 410
 411 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 412                                    unsigned long parent_rate)
 413 {
 414         struct sd_clock *clock = to_sd_clock(hw);
 415         unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
 416         u32 val;
 417         unsigned int i;
 418
 419         for (i = 0; i < clock->div_num; i++)
 420                 if (div == clock->div_table[i].div)
 421                         break;
 422
 423         if (i >= clock->div_num)
 424                 return -EINVAL;
 425
 426         val = clk_readl(clock->reg);
 427         val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
 428         val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
 429         clk_writel(val, clock->reg);
 430
 431         return 0;
 432 }
 433
 434 static const struct clk_ops cpg_sd_clock_ops = {
 435         .enable = cpg_sd_clock_enable,
 436         .disable = cpg_sd_clock_disable,
 437         .is_enabled = cpg_sd_clock_is_enabled,
 438         .recalc_rate = cpg_sd_clock_recalc_rate,
 439         .round_rate = cpg_sd_clock_round_rate,
 440         .set_rate = cpg_sd_clock_set_rate,
 441 };
 442
 443 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
 444                                                void __iomem *base,
 445                                                const char *parent_name)
 446 {
 447         struct clk_init_data init;
 448         struct sd_clock *clock;
 449         struct clk *clk;
 450         unsigned int i;
 451
 452         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 453         if (!clock)
 454                 return ERR_PTR(-ENOMEM);
 455
 456         init.name = core->name;
 457         init.ops = &cpg_sd_clock_ops;
 458         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 459         init.parent_names = &parent_name;
 460         init.num_parents = 1;
 461
 462         clock->reg = base + core->offset;
 463         clock->hw.init = &init;
 464         clock->div_table = cpg_sd_div_table;
 465         clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
 466
 467         clock->div_max = clock->div_table[0].div;
 468         clock->div_min = clock->div_max;
 469         for (i = 1; i < clock->div_num; i++) {
 470                 clock->div_max = max(clock->div_max, clock->div_table[i].div);
 471                 clock->div_min = min(clock->div_min, clock->div_table[i].div);
 472         }
 473
 474         clk = clk_register(NULL, &clock->hw);
 475         if (IS_ERR(clk))
 476                 kfree(clock);
 477
 478         return clk;
 479 }
 480
 481 #define CPG_PLL0CR      0x00d8
 482 #define CPG_PLL2CR      0x002c
 483 #define CPG_PLL4CR      0x01f4
 484
 485 /*
 486  * CPG Clock Data
 487  */
 488
 489 /*
 490  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 491  * 14 13 19 17  (MHz)
 492  *-------------------------------------------------------------------
 493  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 494  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 495  * 0  0  1  0   Prohibited setting
 496  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 497  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 498  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 499  * 0  1  1  0   Prohibited setting
 500  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 501  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 502  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 503  * 1  0  1  0   Prohibited setting
 504  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 505  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 506  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 507  * 1  1  1  0   Prohibited setting
 508  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 509  */
 510 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 511                                          (((md) & BIT(13)) >> 11) | \
 512                                          (((md) & BIT(19)) >> 18) | \
 513                                          (((md) & BIT(17)) >> 17))
 514
 515 struct cpg_pll_config {
 516         unsigned int extal_div;
 517         unsigned int pll1_mult;
 518         unsigned int pll3_mult;
 519 };
 520
 521 static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
 522         /* EXTAL div    PLL1 mult       PLL3 mult */
 523         { 1,            192,            192,    },
 524         { 1,            192,            128,    },
 525         { 0, /* Prohibited setting */           },
 526         { 1,            192,            192,    },
 527         { 1,            160,            160,    },
 528         { 1,            160,            106,    },
 529         { 0, /* Prohibited setting */           },
 530         { 1,            160,            160,    },
 531         { 1,            128,            128,    },
 532         { 1,            128,            84,     },
 533         { 0, /* Prohibited setting */           },
 534         { 1,            128,            128,    },
 535         { 2,            192,            192,    },
 536         { 2,            192,            128,    },
 537         { 0, /* Prohibited setting */           },
 538         { 2,            192,            192,    },
 539 };
 540
 541 static const struct cpg_pll_config *cpg_pll_config __initdata;
 542
 543 static
 544 struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
 545                                              const struct cpg_core_clk *core,
 546                                              const struct cpg_mssr_info *info,
 547                                              struct clk **clks,
 548                                              void __iomem *base)
 549 {
 550         const struct clk *parent;
 551         unsigned int mult = 1;
 552         unsigned int div = 1;
 553         u32 value;
 554
 555         parent = clks[core->parent];
 556         if (IS_ERR(parent))
 557                 return ERR_CAST(parent);
 558
 559         switch (core->type) {
 560         case CLK_TYPE_GEN3_MAIN:
 561                 div = cpg_pll_config->extal_div;
 562                 break;
 563
 564         case CLK_TYPE_GEN3_PLL0:
 565                 /*
 566                  * PLL0 is a configurable multiplier clock. Register it as a
 567                  * fixed factor clock for now as there's no generic multiplier
 568                  * clock implementation and we currently have no need to change
 569                  * the multiplier value.
 570                  */
 571                 value = readl(base + CPG_PLL0CR);
 572                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 573                 break;
 574
 575         case CLK_TYPE_GEN3_PLL1:
 576                 mult = cpg_pll_config->pll1_mult;
 577                 break;
 578
 579         case CLK_TYPE_GEN3_PLL2:
 580                 /*
 581                  * PLL2 is a configurable multiplier clock. Register it as a
 582                  * fixed factor clock for now as there's no generic multiplier
 583                  * clock implementation and we currently have no need to change
 584                  * the multiplier value.
 585                  */
 586                 value = readl(base + CPG_PLL2CR);
 587                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 588                 break;
 589
 590         case CLK_TYPE_GEN3_PLL3:
 591                 mult = cpg_pll_config->pll3_mult;
 592                 break;
 593
 594         case CLK_TYPE_GEN3_PLL4:
 595                 /*
 596                  * PLL4 is a configurable multiplier clock. Register it as a
 597                  * fixed factor clock for now as there's no generic multiplier
 598                  * clock implementation and we currently have no need to change
 599                  * the multiplier value.
 600                  */
 601                 value = readl(base + CPG_PLL4CR);
 602                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 603                 break;
 604
 605         case CLK_TYPE_GEN3_SD:
 606                 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
 607
 608         case CLK_TYPE_GEN3_R:
 609                 /* RINT is default. Only if EXTALR is populated, we switch to it */
 610                 value = readl(base + CPG_RCKCR) & 0x3f;
 611
 612                 if (clk_get_rate(clks[CLK_EXTALR])) {
 613                         parent = clks[CLK_EXTALR];
 614                         value |= BIT(15);
 615                 }
 616
 617                 writel(value, base + CPG_RCKCR);
 618                 break;
 619
 620         default:
 621                 return ERR_PTR(-EINVAL);
 622         }
 623
 624         return clk_register_fixed_factor(NULL, core->name,
 625                                          __clk_get_name(parent), 0, mult, div);
 626 }
 627
 628 /*
 629  * Reset register definitions.
 630  */
 631 #define MODEMR  0xe6160060
 632
 633 static u32 rcar_gen3_read_mode_pins(void)
 634 {
 635         void __iomem *modemr = ioremap_nocache(MODEMR, 4);
 636         u32 mode;
 637
 638         BUG_ON(!modemr);
 639         mode = ioread32(modemr);
 640         iounmap(modemr);
 641
 642         return mode;
 643 }
 644
 645 static int __init r8a7795_cpg_mssr_init(struct device *dev)
 646 {
 647         u32 cpg_mode = rcar_gen3_read_mode_pins();
 648
 649         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 650         if (!cpg_pll_config->extal_div) {
 651                 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
 652                 return -EINVAL;
 653         }
 654
 655         return 0;
 656 }
 657
 658 const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
 659         /* Core Clocks */
 660         .core_clks = r8a7795_core_clks,
 661         .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
 662         .last_dt_core_clk = LAST_DT_CORE_CLK,
 663         .num_total_core_clks = MOD_CLK_BASE,
 664
 665         /* Module Clocks */
 666         .mod_clks = r8a7795_mod_clks,
 667         .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
 668         .num_hw_mod_clks = 12 * 32,
 669
 670         /* Critical Module Clocks */
 671         .crit_mod_clks = r8a7795_crit_mod_clks,
 672         .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
 673
 674         /* Callbacks */
 675         .init = r8a7795_cpg_mssr_init,
 676         .cpg_clk_register = r8a7795_cpg_clk_register,
 677 };