2 * Renesas Clock Pulse Generator / Module Standby and Software Reset
4 * Copyright (C) 2015 Glider bvba
6 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8 * Copyright (C) 2013 Ideas On Board SPRL
9 * Copyright (C) 2015 Renesas Electronics Corp.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/clk/renesas.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/mod_devicetable.h>
22 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_clock.h>
27 #include <linux/pm_domain.h>
28 #include <linux/slab.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "renesas-cpg-mssr.h"
36 #define WARN_DEBUG(x) do { } while (0)
38 #define WARN_DEBUG(x) WARN_ON(x)
43 * Module Standby and Software Reset register offets.
45 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
46 * R-Car Gen 2, and R-Car Gen 3.
47 * These are NOT valid for R-Car Gen1 and RZ/A1!
51 * Module Stop Status Register offsets
54 static const u16 mstpsr[] = {
55 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
56 0x9A0, 0x9A4, 0x9A8, 0x9AC,
59 #define MSTPSR(i) mstpsr[i]
63 * System Module Stop Control Register offsets
66 static const u16 smstpcr[] = {
67 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
68 0x990, 0x994, 0x998, 0x99C,
71 #define SMSTPCR(i) smstpcr[i]
75 * Software Reset Register offsets
78 static const u16 srcr[] = {
79 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
80 0x920, 0x924, 0x928, 0x92C,
83 #define SRCR(i) srcr[i]
86 /* Realtime Module Stop Control Register offsets */
87 #define RMSTPCR(i) (smstpcr[i] - 0x20)
89 /* Modem Module Stop Control Register offsets (r8a73a4) */
90 #define MMSTPCR(i) (smstpcr[i] + 0x20)
92 /* Software Reset Clearing Register offsets */
93 #define SRSTCLR(i) (0x940 + (i) * 4)
97 * Clock Pulse Generator / Module Standby and Software Reset Private Data
99 * @dev: CPG/MSSR device
100 * @base: CPG/MSSR register block base address
101 * @mstp_lock: protects writes to SMSTPCR
102 * @clks: Array containing all Core and Module Clocks
103 * @num_core_clks: Number of Core Clocks in clks[]
104 * @num_mod_clks: Number of Module Clocks in clks[]
105 * @last_dt_core_clk: ID of the last Core Clock exported to DT
107 struct cpg_mssr_priv {
110 spinlock_t mstp_lock;
113 unsigned int num_core_clks;
114 unsigned int num_mod_clks;
115 unsigned int last_dt_core_clk;
120 * struct mstp_clock - MSTP gating clock
121 * @hw: handle between common and hardware-specific interfaces
122 * @index: MSTP clock number
123 * @priv: CPG/MSSR private data
128 struct cpg_mssr_priv *priv;
131 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
133 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
135 struct mstp_clock *clock = to_mstp_clock(hw);
136 struct cpg_mssr_priv *priv = clock->priv;
137 unsigned int reg = clock->index / 32;
138 unsigned int bit = clock->index % 32;
139 struct device *dev = priv->dev;
140 u32 bitmask = BIT(bit);
145 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
146 enable ? "ON" : "OFF");
147 spin_lock_irqsave(&priv->mstp_lock, flags);
149 value = clk_readl(priv->base + SMSTPCR(reg));
154 clk_writel(value, priv->base + SMSTPCR(reg));
156 spin_unlock_irqrestore(&priv->mstp_lock, flags);
161 for (i = 1000; i > 0; --i) {
162 if (!(clk_readl(priv->base + MSTPSR(reg)) &
169 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
170 priv->base + SMSTPCR(reg), bit);
177 static int cpg_mstp_clock_enable(struct clk_hw *hw)
179 return cpg_mstp_clock_endisable(hw, true);
182 static void cpg_mstp_clock_disable(struct clk_hw *hw)
184 cpg_mstp_clock_endisable(hw, false);
187 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
189 struct mstp_clock *clock = to_mstp_clock(hw);
190 struct cpg_mssr_priv *priv = clock->priv;
193 value = clk_readl(priv->base + MSTPSR(clock->index / 32));
195 return !(value & BIT(clock->index % 32));
198 static const struct clk_ops cpg_mstp_clock_ops = {
199 .enable = cpg_mstp_clock_enable,
200 .disable = cpg_mstp_clock_disable,
201 .is_enabled = cpg_mstp_clock_is_enabled,
205 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
208 unsigned int clkidx = clkspec->args[1];
209 struct cpg_mssr_priv *priv = data;
210 struct device *dev = priv->dev;
215 switch (clkspec->args[0]) {
218 if (clkidx > priv->last_dt_core_clk) {
219 dev_err(dev, "Invalid %s clock index %u\n", type,
221 return ERR_PTR(-EINVAL);
223 clk = priv->clks[clkidx];
228 idx = MOD_CLK_PACK(clkidx);
229 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
230 dev_err(dev, "Invalid %s clock index %u\n", type,
232 return ERR_PTR(-EINVAL);
234 clk = priv->clks[priv->num_core_clks + idx];
238 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
239 return ERR_PTR(-EINVAL);
243 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
246 dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
247 clkspec->args[0], clkspec->args[1], clk, clk);
251 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
252 const struct cpg_mssr_info *info,
253 struct cpg_mssr_priv *priv)
255 struct clk *clk = NULL, *parent;
256 struct device *dev = priv->dev;
257 unsigned int id = core->id, div = core->div;
258 const char *parent_name;
260 WARN_DEBUG(id >= priv->num_core_clks);
261 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
263 switch (core->type) {
265 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
269 case CLK_TYPE_DIV6P1:
270 case CLK_TYPE_DIV6_RO:
271 WARN_DEBUG(core->parent >= priv->num_core_clks);
272 parent = priv->clks[core->parent];
273 if (IS_ERR(parent)) {
278 parent_name = __clk_get_name(parent);
280 if (core->type == CLK_TYPE_DIV6_RO)
281 /* Multiply with the DIV6 register value */
282 div *= (readl(priv->base + core->offset) & 0x3f) + 1;
284 if (core->type == CLK_TYPE_DIV6P1) {
285 clk = cpg_div6_register(core->name, 1, &parent_name,
286 priv->base + core->offset);
288 clk = clk_register_fixed_factor(NULL, core->name,
295 if (info->cpg_clk_register)
296 clk = info->cpg_clk_register(dev, core, info,
297 priv->clks, priv->base);
299 dev_err(dev, "%s has unsupported core clock type %u\n",
300 core->name, core->type);
304 if (IS_ERR_OR_NULL(clk))
307 dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
308 priv->clks[id] = clk;
312 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core,",
313 core->name, PTR_ERR(clk));
316 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
317 const struct cpg_mssr_info *info,
318 struct cpg_mssr_priv *priv)
320 struct mstp_clock *clock = NULL;
321 struct device *dev = priv->dev;
322 unsigned int id = mod->id;
323 struct clk_init_data init;
324 struct clk *parent, *clk;
325 const char *parent_name;
328 WARN_DEBUG(id < priv->num_core_clks);
329 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
330 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
331 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
333 parent = priv->clks[mod->parent];
334 if (IS_ERR(parent)) {
339 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
341 clk = ERR_PTR(-ENOMEM);
345 init.name = mod->name;
346 init.ops = &cpg_mstp_clock_ops;
347 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
348 for (i = 0; i < info->num_crit_mod_clks; i++)
349 if (id == info->crit_mod_clks[i]) {
350 #ifdef CLK_ENABLE_HAND_OFF
351 dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
353 init.flags |= CLK_ENABLE_HAND_OFF;
356 dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
363 parent_name = __clk_get_name(parent);
364 init.parent_names = &parent_name;
365 init.num_parents = 1;
367 clock->index = id - priv->num_core_clks;
369 clock->hw.init = &init;
371 clk = clk_register(NULL, &clock->hw);
375 dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
376 priv->clks[id] = clk;
380 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module,",
381 mod->name, PTR_ERR(clk));
385 struct cpg_mssr_clk_domain {
386 struct generic_pm_domain genpd;
387 struct device_node *np;
388 unsigned int num_core_pm_clks;
389 unsigned int core_pm_clks[0];
392 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
394 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
395 struct cpg_mssr_clk_domain *pd)
399 if (clkspec->np != pd->np || clkspec->args_count != 2)
402 switch (clkspec->args[0]) {
404 for (i = 0; i < pd->num_core_pm_clks; i++)
405 if (clkspec->args[1] == pd->core_pm_clks[i])
417 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
419 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
420 struct device_node *np = dev->of_node;
421 struct of_phandle_args clkspec;
427 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
428 return -EPROBE_DEFER;
431 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
433 if (cpg_mssr_is_pm_clk(&clkspec, pd))
436 of_node_put(clkspec.np);
443 clk = of_clk_get_from_provider(&clkspec);
444 of_node_put(clkspec.np);
449 error = pm_clk_create(dev);
451 dev_err(dev, "pm_clk_create failed %d\n", error);
455 error = pm_clk_add_clk(dev, clk);
457 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
470 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
472 if (!list_empty(&dev->power.subsys_data->clock_list))
476 static int __init cpg_mssr_add_clk_domain(struct device *dev,
477 const unsigned int *core_pm_clks,
478 unsigned int num_core_pm_clks)
480 struct device_node *np = dev->of_node;
481 struct generic_pm_domain *genpd;
482 struct cpg_mssr_clk_domain *pd;
483 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
485 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
490 pd->num_core_pm_clks = num_core_pm_clks;
491 memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
494 genpd->name = np->name;
495 genpd->flags = GENPD_FLAG_PM_CLK;
496 genpd->attach_dev = cpg_mssr_attach_dev;
497 genpd->detach_dev = cpg_mssr_detach_dev;
498 pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
499 cpg_mssr_clk_domain = pd;
501 of_genpd_add_provider_simple(np, genpd);
505 static const struct of_device_id cpg_mssr_match[] = {
506 #ifdef CONFIG_ARCH_R8A7795
508 .compatible = "renesas,r8a7795-cpg-mssr",
509 .data = &r8a7795_cpg_mssr_info,
515 static void cpg_mssr_del_clk_provider(void *data)
517 of_clk_del_provider(data);
520 static int __init cpg_mssr_probe(struct platform_device *pdev)
522 struct device *dev = &pdev->dev;
523 struct device_node *np = dev->of_node;
524 const struct cpg_mssr_info *info;
525 struct cpg_mssr_priv *priv;
526 unsigned int nclks, i;
527 struct resource *res;
531 info = of_match_node(cpg_mssr_match, np)->data;
533 error = info->init(dev);
538 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
543 spin_lock_init(&priv->mstp_lock);
545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
546 priv->base = devm_ioremap_resource(dev, res);
547 if (IS_ERR(priv->base))
548 return PTR_ERR(priv->base);
550 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
551 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
556 priv->num_core_clks = info->num_total_core_clks;
557 priv->num_mod_clks = info->num_hw_mod_clks;
558 priv->last_dt_core_clk = info->last_dt_core_clk;
560 for (i = 0; i < nclks; i++)
561 clks[i] = ERR_PTR(-ENOENT);
563 for (i = 0; i < info->num_core_clks; i++)
564 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
566 for (i = 0; i < info->num_mod_clks; i++)
567 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
569 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
573 error = devm_add_action_or_reset(dev,
574 cpg_mssr_del_clk_provider,
579 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
580 info->num_core_pm_clks);
587 static struct platform_driver cpg_mssr_driver = {
589 .name = "renesas-cpg-mssr",
590 .of_match_table = cpg_mssr_match,
594 static int __init cpg_mssr_init(void)
596 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
599 subsys_initcall(cpg_mssr_init);
601 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
602 MODULE_LICENSE("GPL v2");