2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/regmap.h>
28 #include <linux/reboot.h>
32 * Register a clock branch.
33 * Most clock branches have a form like
39 * sometimes without one of those components.
41 static struct clk *rockchip_clk_register_branch(const char *name,
42 const char **parent_names, u8 num_parents, void __iomem *base,
43 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
44 u8 div_shift, u8 div_width, u8 div_flags,
45 struct clk_div_table *div_table, int gate_offset,
46 u8 gate_shift, u8 gate_flags, unsigned long flags,
50 struct clk_mux *mux = NULL;
51 struct clk_gate *gate = NULL;
52 struct clk_divider *div = NULL;
53 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
56 if (num_parents > 1) {
57 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
59 return ERR_PTR(-ENOMEM);
61 mux->reg = base + muxdiv_offset;
62 mux->shift = mux_shift;
63 mux->mask = BIT(mux_width) - 1;
64 mux->flags = mux_flags;
66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
70 if (gate_offset >= 0) {
71 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
73 return ERR_PTR(-ENOMEM);
75 gate->flags = gate_flags;
76 gate->reg = base + gate_offset;
77 gate->bit_idx = gate_shift;
79 gate_ops = &clk_gate_ops;
83 div = kzalloc(sizeof(*div), GFP_KERNEL);
85 return ERR_PTR(-ENOMEM);
87 div->flags = div_flags;
88 div->reg = base + muxdiv_offset;
89 div->shift = div_shift;
90 div->width = div_width;
92 div->table = div_table;
93 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
98 clk = clk_register_composite(NULL, name, parent_names, num_parents,
99 mux ? &mux->hw : NULL, mux_ops,
100 div ? &div->hw : NULL, div_ops,
101 gate ? &gate->hw : NULL, gate_ops,
107 static struct clk *rockchip_clk_register_frac_branch(const char *name,
108 const char **parent_names, u8 num_parents, void __iomem *base,
109 int muxdiv_offset, u8 div_flags,
110 int gate_offset, u8 gate_shift, u8 gate_flags,
111 unsigned long flags, spinlock_t *lock)
114 struct clk_gate *gate = NULL;
115 struct clk_fractional_divider *div = NULL;
116 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
118 if (gate_offset >= 0) {
119 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
121 return ERR_PTR(-ENOMEM);
123 gate->flags = gate_flags;
124 gate->reg = base + gate_offset;
125 gate->bit_idx = gate_shift;
127 gate_ops = &clk_gate_ops;
130 if (muxdiv_offset < 0)
131 return ERR_PTR(-EINVAL);
133 div = kzalloc(sizeof(*div), GFP_KERNEL);
135 return ERR_PTR(-ENOMEM);
137 div->flags = div_flags;
138 div->reg = base + muxdiv_offset;
140 div->mmask = 0xffff0000;
144 div_ops = &clk_fractional_divider_ops;
146 clk = clk_register_composite(NULL, name, parent_names, num_parents,
149 gate ? &gate->hw : NULL, gate_ops,
155 static DEFINE_SPINLOCK(clk_lock);
156 static struct clk **clk_table;
157 static void __iomem *reg_base;
158 static struct clk_onecell_data clk_data;
159 static struct device_node *cru_node;
160 static struct regmap *grf;
162 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
163 unsigned long nr_clks)
167 grf = ERR_PTR(-EPROBE_DEFER);
169 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
171 pr_err("%s: could not allocate clock lookup table\n", __func__);
173 clk_data.clks = clk_table;
174 clk_data.clk_num = nr_clks;
175 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
178 struct regmap *rockchip_clk_get_grf(void)
181 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
185 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
191 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
192 unsigned int nr_pll, int grf_lock_offset)
197 for (idx = 0; idx < nr_pll; idx++, list++) {
198 clk = rockchip_clk_register_pll(list->type, list->name,
199 list->parent_names, list->num_parents,
200 reg_base, list->con_offset, grf_lock_offset,
201 list->lock_shift, list->mode_offset,
202 list->mode_shift, list->rate_table, &clk_lock);
204 pr_err("%s: failed to register clock %s\n", __func__,
209 rockchip_clk_add_lookup(clk, list->id);
213 void __init rockchip_clk_register_branches(
214 struct rockchip_clk_branch *list,
217 struct clk *clk = NULL;
221 for (idx = 0; idx < nr_clk; idx++, list++) {
224 /* catch simple muxes */
225 switch (list->branch_type) {
227 clk = clk_register_mux(NULL, list->name,
228 list->parent_names, list->num_parents,
229 flags, reg_base + list->muxdiv_offset,
230 list->mux_shift, list->mux_width,
231 list->mux_flags, &clk_lock);
235 clk = clk_register_divider_table(NULL,
236 list->name, list->parent_names[0],
237 flags, reg_base + list->muxdiv_offset,
238 list->div_shift, list->div_width,
239 list->div_flags, list->div_table,
242 clk = clk_register_divider(NULL, list->name,
243 list->parent_names[0], flags,
244 reg_base + list->muxdiv_offset,
245 list->div_shift, list->div_width,
246 list->div_flags, &clk_lock);
248 case branch_fraction_divider:
249 /* keep all gates untouched for now */
250 flags |= CLK_IGNORE_UNUSED;
252 clk = rockchip_clk_register_frac_branch(list->name,
253 list->parent_names, list->num_parents,
254 reg_base, list->muxdiv_offset, list->div_flags,
255 list->gate_offset, list->gate_shift,
256 list->gate_flags, flags, &clk_lock);
259 flags |= CLK_SET_RATE_PARENT;
261 /* keep all gates untouched for now */
262 flags |= CLK_IGNORE_UNUSED;
264 clk = clk_register_gate(NULL, list->name,
265 list->parent_names[0], flags,
266 reg_base + list->gate_offset,
267 list->gate_shift, list->gate_flags, &clk_lock);
269 case branch_composite:
270 /* keep all gates untouched for now */
271 flags |= CLK_IGNORE_UNUSED;
273 clk = rockchip_clk_register_branch(list->name,
274 list->parent_names, list->num_parents,
275 reg_base, list->muxdiv_offset, list->mux_shift,
276 list->mux_width, list->mux_flags,
277 list->div_shift, list->div_width,
278 list->div_flags, list->div_table,
279 list->gate_offset, list->gate_shift,
280 list->gate_flags, flags, &clk_lock);
284 /* none of the cases above matched */
286 pr_err("%s: unknown clock type %d\n",
287 __func__, list->branch_type);
292 pr_err("%s: failed to register clock %s: %ld\n",
293 __func__, list->name, PTR_ERR(clk));
297 rockchip_clk_add_lookup(clk, list->id);
301 void __init rockchip_clk_register_armclk(unsigned int lookup_id,
302 const char *name, const char **parent_names,
304 const struct rockchip_cpuclk_reg_data *reg_data,
305 const struct rockchip_cpuclk_rate_table *rates,
310 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
311 reg_data, rates, nrates, reg_base,
314 pr_err("%s: failed to register clock %s: %ld\n",
315 __func__, name, PTR_ERR(clk));
319 rockchip_clk_add_lookup(clk, lookup_id);
322 void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks)
326 /* Protect the clocks that needs to stay on */
327 for (i = 0; i < nclocks; i++) {
328 struct clk *clk = __clk_lookup(clocks[i]);
331 clk_prepare_enable(clk);
335 static unsigned int reg_restart;
336 static int rockchip_restart_notify(struct notifier_block *this,
337 unsigned long mode, void *cmd)
339 writel(0xfdb9, reg_base + reg_restart);
343 static struct notifier_block rockchip_restart_handler = {
344 .notifier_call = rockchip_restart_notify,
348 void __init rockchip_register_restart_notifier(unsigned int reg)
353 ret = register_restart_handler(&rockchip_restart_handler);
355 pr_err("%s: cannot register restart handler, %d\n",