2 * common clks module for all SiRF SoCs
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
10 #define MHZ (KHZ * KHZ)
12 static void *sirfsoc_clk_vbase;
13 static void *sirfsoc_rsc_vbase;
14 static struct clk_onecell_data clk_data;
17 * SiRFprimaII clock controller
18 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
19 * - 3 standard configurable plls: pll1, pll2 & pll3
20 * - 2 exclusive plls: usb phy pll and sata phy pll
21 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
23 * Each clock domain can select its own clock source from five clock sources,
24 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
25 * clock of the group clock.
26 * - dsp domain: gps, mf
27 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
28 * - sys domain: security
33 unsigned short regofs; /* register offset */
36 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
40 signed char enable_bit; /* enable bit: 0 ~ 63 */
41 unsigned short regofs; /* register offset */
44 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
48 signed char enable_bit; /* enable bit: 0 ~ 63 */
51 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
53 static int std_clk_is_enabled(struct clk_hw *hw);
54 static int std_clk_enable(struct clk_hw *hw);
55 static void std_clk_disable(struct clk_hw *hw);
57 static inline unsigned long clkc_readl(unsigned reg)
59 return readl(sirfsoc_clk_vbase + reg);
62 static inline void clkc_writel(u32 val, unsigned reg)
64 writel(val, sirfsoc_clk_vbase + reg);
71 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
72 unsigned long parent_rate)
74 unsigned long fin = parent_rate;
75 struct clk_pll *clk = to_pllclk(hw);
76 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
77 SIRFSOC_CLKC_PLL1_CFG0;
79 if (clkc_readl(regcfg2) & BIT(2)) {
83 /* fout = fin * nf / nr / od */
84 u32 cfg0 = clkc_readl(clk->regofs);
85 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
86 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
87 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
89 return fin / MHZ * nf / nr / od * MHZ;
93 static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
94 unsigned long *parent_rate)
96 unsigned long fin, nf, nr, od;
100 * fout = fin * nf / (nr * od);
101 * set od = 1, nr = fin/MHz, so fout = nf * MHz
103 rate = rate - rate % MHZ;
118 dividend = (u64)fin * nf;
119 do_div(dividend, nr * od);
121 return (long)dividend;
124 static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
125 unsigned long parent_rate)
127 struct clk_pll *clk = to_pllclk(hw);
128 unsigned long fin, nf, nr, od, reg;
131 * fout = fin * nf / (nr * od);
132 * set od = 1, nr = fin/MHz, so fout = nf * MHz
136 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
143 BUG_ON((fin % MHZ) || nr > BIT(6));
147 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
148 clkc_writel(reg, clk->regofs);
150 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
151 clkc_writel((nf >> 1) - 1, reg);
153 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
154 while (!(clkc_readl(reg) & BIT(6)))
160 static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
161 unsigned long *parent_rate)
164 * SiRF SoC has not cpu clock control,
165 * So bypass to it's parent pll.
167 struct clk *parent_clk = clk_get_parent(hw->clk);
168 struct clk *pll_parent_clk = clk_get_parent(parent_clk);
169 unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk);
170 return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate);
173 static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
174 unsigned long parent_rate)
177 * SiRF SoC has not cpu clock control,
178 * So return the parent pll rate.
180 struct clk *parent_clk = clk_get_parent(hw->clk);
181 return __clk_get_rate(parent_clk);
184 static struct clk_ops std_pll_ops = {
185 .recalc_rate = pll_clk_recalc_rate,
186 .round_rate = pll_clk_round_rate,
187 .set_rate = pll_clk_set_rate,
190 static const char *pll_clk_parents[] = {
194 static struct clk_init_data clk_pll1_init = {
197 .parent_names = pll_clk_parents,
198 .num_parents = ARRAY_SIZE(pll_clk_parents),
201 static struct clk_init_data clk_pll2_init = {
204 .parent_names = pll_clk_parents,
205 .num_parents = ARRAY_SIZE(pll_clk_parents),
208 static struct clk_init_data clk_pll3_init = {
211 .parent_names = pll_clk_parents,
212 .num_parents = ARRAY_SIZE(pll_clk_parents),
215 static struct clk_pll clk_pll1 = {
216 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
218 .init = &clk_pll1_init,
222 static struct clk_pll clk_pll2 = {
223 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
225 .init = &clk_pll2_init,
229 static struct clk_pll clk_pll3 = {
230 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
232 .init = &clk_pll3_init,
237 * usb uses specified pll
240 static int usb_pll_clk_enable(struct clk_hw *hw)
242 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
243 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
244 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
245 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
246 SIRFSOC_USBPHY_PLL_LOCK))
252 static void usb_pll_clk_disable(struct clk_hw *clk)
254 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
255 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
256 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
259 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
261 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
262 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
265 static struct clk_ops usb_pll_ops = {
266 .enable = usb_pll_clk_enable,
267 .disable = usb_pll_clk_disable,
268 .recalc_rate = usb_pll_clk_recalc_rate,
271 static struct clk_init_data clk_usb_pll_init = {
274 .parent_names = pll_clk_parents,
275 .num_parents = ARRAY_SIZE(pll_clk_parents),
278 static struct clk_hw usb_pll_clk_hw = {
279 .init = &clk_usb_pll_init,
283 * clock domains - cpu, mem, sys/io, dsp, gfx
286 static const char *dmn_clk_parents[] = {
294 static u8 dmn_clk_get_parent(struct clk_hw *hw)
296 struct clk_dmn *clk = to_dmnclk(hw);
297 u32 cfg = clkc_readl(clk->regofs);
299 /* parent of io domain can only be pll3 */
300 if (strcmp(hw->init->name, "io") == 0)
303 WARN_ON((cfg & (BIT(3) - 1)) > 4);
305 return cfg & (BIT(3) - 1);
308 static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
310 struct clk_dmn *clk = to_dmnclk(hw);
311 u32 cfg = clkc_readl(clk->regofs);
313 /* parent of io domain can only be pll3 */
314 if (strcmp(hw->init->name, "io") == 0)
317 cfg &= ~(BIT(3) - 1);
318 clkc_writel(cfg | parent, clk->regofs);
319 /* BIT(3) - switching status: 1 - busy, 0 - done */
320 while (clkc_readl(clk->regofs) & BIT(3))
326 static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
327 unsigned long parent_rate)
330 unsigned long fin = parent_rate;
331 struct clk_dmn *clk = to_dmnclk(hw);
333 u32 cfg = clkc_readl(clk->regofs);
336 /* fcd bypass mode */
340 * wait count: bit[19:16], hold count: bit[23:20]
342 u32 wait = (cfg >> 16) & (BIT(4) - 1);
343 u32 hold = (cfg >> 20) & (BIT(4) - 1);
345 return fin / (wait + hold + 2);
349 static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
350 unsigned long *parent_rate)
353 unsigned ratio, wait, hold;
354 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
361 if (ratio > BIT(bits + 1))
362 ratio = BIT(bits + 1);
364 wait = (ratio >> 1) - 1;
365 hold = ratio - wait - 2;
367 return fin / (wait + hold + 2);
370 static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
371 unsigned long parent_rate)
373 struct clk_dmn *clk = to_dmnclk(hw);
375 unsigned ratio, wait, hold, reg;
376 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
381 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
386 wait = (ratio >> 1) - 1;
387 hold = ratio - wait - 2;
389 reg = clkc_readl(clk->regofs);
390 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
391 reg |= (wait << 16) | (hold << 20) | BIT(25);
392 clkc_writel(reg, clk->regofs);
394 /* waiting FCD been effective */
395 while (clkc_readl(clk->regofs) & BIT(25))
401 static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
402 unsigned long parent_rate)
405 struct clk *cur_parent;
407 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
408 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
412 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
413 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
417 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
418 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
422 cur_parent = clk_get_parent(hw->clk);
424 /* switch to tmp pll before setting parent clock's rate */
425 if (cur_parent == clk_pll1.hw.clk) {
426 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
430 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
432 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
434 return ret2 ? ret2 : ret1;
437 static struct clk_ops msi_ops = {
438 .set_rate = dmn_clk_set_rate,
439 .round_rate = dmn_clk_round_rate,
440 .recalc_rate = dmn_clk_recalc_rate,
441 .set_parent = dmn_clk_set_parent,
442 .get_parent = dmn_clk_get_parent,
445 static struct clk_init_data clk_mem_init = {
448 .parent_names = dmn_clk_parents,
449 .num_parents = ARRAY_SIZE(dmn_clk_parents),
452 static struct clk_dmn clk_mem = {
453 .regofs = SIRFSOC_CLKC_MEM_CFG,
455 .init = &clk_mem_init,
459 static struct clk_init_data clk_sys_init = {
462 .parent_names = dmn_clk_parents,
463 .num_parents = ARRAY_SIZE(dmn_clk_parents),
464 .flags = CLK_SET_RATE_GATE,
467 static struct clk_dmn clk_sys = {
468 .regofs = SIRFSOC_CLKC_SYS_CFG,
470 .init = &clk_sys_init,
474 static struct clk_init_data clk_io_init = {
477 .parent_names = dmn_clk_parents,
478 .num_parents = ARRAY_SIZE(dmn_clk_parents),
481 static struct clk_dmn clk_io = {
482 .regofs = SIRFSOC_CLKC_IO_CFG,
484 .init = &clk_io_init,
488 static struct clk_ops cpu_ops = {
489 .set_parent = dmn_clk_set_parent,
490 .get_parent = dmn_clk_get_parent,
491 .set_rate = cpu_clk_set_rate,
492 .round_rate = cpu_clk_round_rate,
493 .recalc_rate = cpu_clk_recalc_rate,
496 static struct clk_init_data clk_cpu_init = {
499 .parent_names = dmn_clk_parents,
500 .num_parents = ARRAY_SIZE(dmn_clk_parents),
501 .flags = CLK_SET_RATE_PARENT,
504 static struct clk_dmn clk_cpu = {
505 .regofs = SIRFSOC_CLKC_CPU_CFG,
507 .init = &clk_cpu_init,
511 static struct clk_ops dmn_ops = {
512 .is_enabled = std_clk_is_enabled,
513 .enable = std_clk_enable,
514 .disable = std_clk_disable,
515 .set_rate = dmn_clk_set_rate,
516 .round_rate = dmn_clk_round_rate,
517 .recalc_rate = dmn_clk_recalc_rate,
518 .set_parent = dmn_clk_set_parent,
519 .get_parent = dmn_clk_get_parent,
522 /* dsp, gfx, mm, lcd and vpp domain */
524 static struct clk_init_data clk_dsp_init = {
527 .parent_names = dmn_clk_parents,
528 .num_parents = ARRAY_SIZE(dmn_clk_parents),
531 static struct clk_dmn clk_dsp = {
532 .regofs = SIRFSOC_CLKC_DSP_CFG,
535 .init = &clk_dsp_init,
539 static struct clk_init_data clk_gfx_init = {
542 .parent_names = dmn_clk_parents,
543 .num_parents = ARRAY_SIZE(dmn_clk_parents),
546 static struct clk_dmn clk_gfx = {
547 .regofs = SIRFSOC_CLKC_GFX_CFG,
550 .init = &clk_gfx_init,
554 static struct clk_init_data clk_mm_init = {
557 .parent_names = dmn_clk_parents,
558 .num_parents = ARRAY_SIZE(dmn_clk_parents),
561 static struct clk_dmn clk_mm = {
562 .regofs = SIRFSOC_CLKC_MM_CFG,
565 .init = &clk_mm_init,
570 * for atlas6, gfx2d holds the bit of prima2's clk_mm
572 #define clk_gfx2d clk_mm
574 static struct clk_init_data clk_lcd_init = {
577 .parent_names = dmn_clk_parents,
578 .num_parents = ARRAY_SIZE(dmn_clk_parents),
581 static struct clk_dmn clk_lcd = {
582 .regofs = SIRFSOC_CLKC_LCD_CFG,
585 .init = &clk_lcd_init,
589 static struct clk_init_data clk_vpp_init = {
592 .parent_names = dmn_clk_parents,
593 .num_parents = ARRAY_SIZE(dmn_clk_parents),
596 static struct clk_dmn clk_vpp = {
597 .regofs = SIRFSOC_CLKC_LCD_CFG,
600 .init = &clk_vpp_init,
604 static struct clk_init_data clk_mmc01_init = {
607 .parent_names = dmn_clk_parents,
608 .num_parents = ARRAY_SIZE(dmn_clk_parents),
611 static struct clk_init_data clk_mmc23_init = {
614 .parent_names = dmn_clk_parents,
615 .num_parents = ARRAY_SIZE(dmn_clk_parents),
618 static struct clk_init_data clk_mmc45_init = {
621 .parent_names = dmn_clk_parents,
622 .num_parents = ARRAY_SIZE(dmn_clk_parents),
626 * peripheral controllers in io domain
629 static int std_clk_is_enabled(struct clk_hw *hw)
633 struct clk_std *clk = to_stdclk(hw);
635 bit = clk->enable_bit % 32;
636 reg = clk->enable_bit / 32;
637 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
639 return !!(clkc_readl(reg) & BIT(bit));
642 static int std_clk_enable(struct clk_hw *hw)
646 struct clk_std *clk = to_stdclk(hw);
648 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
650 bit = clk->enable_bit % 32;
651 reg = clk->enable_bit / 32;
652 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
654 val = clkc_readl(reg) | BIT(bit);
655 clkc_writel(val, reg);
659 static void std_clk_disable(struct clk_hw *hw)
663 struct clk_std *clk = to_stdclk(hw);
665 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
667 bit = clk->enable_bit % 32;
668 reg = clk->enable_bit / 32;
669 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
671 val = clkc_readl(reg) & ~BIT(bit);
672 clkc_writel(val, reg);
675 static const char *std_clk_io_parents[] = {
679 static struct clk_ops ios_ops = {
680 .is_enabled = std_clk_is_enabled,
681 .enable = std_clk_enable,
682 .disable = std_clk_disable,
685 static struct clk_init_data clk_cphif_init = {
688 .parent_names = std_clk_io_parents,
689 .num_parents = ARRAY_SIZE(std_clk_io_parents),
692 static struct clk_std clk_cphif = {
695 .init = &clk_cphif_init,
699 static struct clk_init_data clk_dmac0_init = {
702 .parent_names = std_clk_io_parents,
703 .num_parents = ARRAY_SIZE(std_clk_io_parents),
706 static struct clk_std clk_dmac0 = {
709 .init = &clk_dmac0_init,
713 static struct clk_init_data clk_dmac1_init = {
716 .parent_names = std_clk_io_parents,
717 .num_parents = ARRAY_SIZE(std_clk_io_parents),
720 static struct clk_std clk_dmac1 = {
723 .init = &clk_dmac1_init,
727 static struct clk_init_data clk_audio_init = {
730 .parent_names = std_clk_io_parents,
731 .num_parents = ARRAY_SIZE(std_clk_io_parents),
734 static struct clk_std clk_audio = {
737 .init = &clk_audio_init,
741 static struct clk_init_data clk_uart0_init = {
744 .parent_names = std_clk_io_parents,
745 .num_parents = ARRAY_SIZE(std_clk_io_parents),
748 static struct clk_std clk_uart0 = {
751 .init = &clk_uart0_init,
755 static struct clk_init_data clk_uart1_init = {
758 .parent_names = std_clk_io_parents,
759 .num_parents = ARRAY_SIZE(std_clk_io_parents),
762 static struct clk_std clk_uart1 = {
765 .init = &clk_uart1_init,
769 static struct clk_init_data clk_uart2_init = {
772 .parent_names = std_clk_io_parents,
773 .num_parents = ARRAY_SIZE(std_clk_io_parents),
776 static struct clk_std clk_uart2 = {
779 .init = &clk_uart2_init,
783 static struct clk_init_data clk_usp0_init = {
786 .parent_names = std_clk_io_parents,
787 .num_parents = ARRAY_SIZE(std_clk_io_parents),
790 static struct clk_std clk_usp0 = {
793 .init = &clk_usp0_init,
797 static struct clk_init_data clk_usp1_init = {
800 .parent_names = std_clk_io_parents,
801 .num_parents = ARRAY_SIZE(std_clk_io_parents),
804 static struct clk_std clk_usp1 = {
807 .init = &clk_usp1_init,
811 static struct clk_init_data clk_usp2_init = {
814 .parent_names = std_clk_io_parents,
815 .num_parents = ARRAY_SIZE(std_clk_io_parents),
818 static struct clk_std clk_usp2 = {
821 .init = &clk_usp2_init,
825 static struct clk_init_data clk_vip_init = {
828 .parent_names = std_clk_io_parents,
829 .num_parents = ARRAY_SIZE(std_clk_io_parents),
832 static struct clk_std clk_vip = {
835 .init = &clk_vip_init,
839 static struct clk_init_data clk_spi0_init = {
842 .parent_names = std_clk_io_parents,
843 .num_parents = ARRAY_SIZE(std_clk_io_parents),
846 static struct clk_std clk_spi0 = {
849 .init = &clk_spi0_init,
853 static struct clk_init_data clk_spi1_init = {
856 .parent_names = std_clk_io_parents,
857 .num_parents = ARRAY_SIZE(std_clk_io_parents),
860 static struct clk_std clk_spi1 = {
863 .init = &clk_spi1_init,
867 static struct clk_init_data clk_tsc_init = {
870 .parent_names = std_clk_io_parents,
871 .num_parents = ARRAY_SIZE(std_clk_io_parents),
874 static struct clk_std clk_tsc = {
877 .init = &clk_tsc_init,
881 static struct clk_init_data clk_i2c0_init = {
884 .parent_names = std_clk_io_parents,
885 .num_parents = ARRAY_SIZE(std_clk_io_parents),
888 static struct clk_std clk_i2c0 = {
891 .init = &clk_i2c0_init,
895 static struct clk_init_data clk_i2c1_init = {
898 .parent_names = std_clk_io_parents,
899 .num_parents = ARRAY_SIZE(std_clk_io_parents),
902 static struct clk_std clk_i2c1 = {
905 .init = &clk_i2c1_init,
909 static struct clk_init_data clk_pwmc_init = {
912 .parent_names = std_clk_io_parents,
913 .num_parents = ARRAY_SIZE(std_clk_io_parents),
916 static struct clk_std clk_pwmc = {
919 .init = &clk_pwmc_init,
923 static struct clk_init_data clk_efuse_init = {
926 .parent_names = std_clk_io_parents,
927 .num_parents = ARRAY_SIZE(std_clk_io_parents),
930 static struct clk_std clk_efuse = {
933 .init = &clk_efuse_init,
937 static struct clk_init_data clk_pulse_init = {
940 .parent_names = std_clk_io_parents,
941 .num_parents = ARRAY_SIZE(std_clk_io_parents),
944 static struct clk_std clk_pulse = {
947 .init = &clk_pulse_init,
951 static const char *std_clk_dsp_parents[] = {
955 static struct clk_init_data clk_gps_init = {
958 .parent_names = std_clk_dsp_parents,
959 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
962 static struct clk_std clk_gps = {
965 .init = &clk_gps_init,
969 static struct clk_init_data clk_mf_init = {
972 .parent_names = std_clk_io_parents,
973 .num_parents = ARRAY_SIZE(std_clk_io_parents),
976 static struct clk_std clk_mf = {
979 .init = &clk_mf_init,
983 static const char *std_clk_sys_parents[] = {
987 static struct clk_init_data clk_security_init = {
990 .parent_names = std_clk_sys_parents,
991 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
994 static struct clk_std clk_security = {
997 .init = &clk_security_init,
1001 static const char *std_clk_usb_parents[] = {
1005 static struct clk_init_data clk_usb0_init = {
1008 .parent_names = std_clk_usb_parents,
1009 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1012 static struct clk_std clk_usb0 = {
1015 .init = &clk_usb0_init,
1019 static struct clk_init_data clk_usb1_init = {
1022 .parent_names = std_clk_usb_parents,
1023 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1026 static struct clk_std clk_usb1 = {
1029 .init = &clk_usb1_init,