drivers/clk/spear/spear1310_clock.c

   1 /*
   2  * arch/arm/mach-spear13xx/spear1310_clock.c
   3  *
   4  * SPEAr1310 machine clock framework source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/spinlock_types.h>
  20 #include <mach/spear.h>
  21 #include "clk.h"
  22
  23 #define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
  24 /* PLL related registers and bit values */
  25 #define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
  26         /* PLL_CFG bit values */
  27         #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
  28         #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
  29         #define SPEAR1310_RAS_SYNT2_3_CLK_MASK          2
  30         #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT         29
  31         #define SPEAR1310_RAS_SYNT_CLK_MASK             2
  32         #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT         27
  33         #define SPEAR1310_PLL_CLK_MASK                  2
  34         #define SPEAR1310_PLL3_CLK_SHIFT                24
  35         #define SPEAR1310_PLL2_CLK_SHIFT                22
  36         #define SPEAR1310_PLL1_CLK_SHIFT                20
  37
  38 #define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
  39 #define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
  40 #define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
  41 #define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
  42 #define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
  43 #define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
  44 #define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
  45 #define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
  46 #define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
  47         /* PERIP_CLK_CFG bit values */
  48         #define SPEAR1310_GPT_OSC24_VAL                 0
  49         #define SPEAR1310_GPT_APB_VAL                   1
  50         #define SPEAR1310_GPT_CLK_MASK                  1
  51         #define SPEAR1310_GPT3_CLK_SHIFT                11
  52         #define SPEAR1310_GPT2_CLK_SHIFT                10
  53         #define SPEAR1310_GPT1_CLK_SHIFT                9
  54         #define SPEAR1310_GPT0_CLK_SHIFT                8
  55         #define SPEAR1310_UART_CLK_PLL5_VAL             0
  56         #define SPEAR1310_UART_CLK_OSC24_VAL            1
  57         #define SPEAR1310_UART_CLK_SYNT_VAL             2
  58         #define SPEAR1310_UART_CLK_MASK                 2
  59         #define SPEAR1310_UART_CLK_SHIFT                4
  60
  61         #define SPEAR1310_AUX_CLK_PLL5_VAL              0
  62         #define SPEAR1310_AUX_CLK_SYNT_VAL              1
  63         #define SPEAR1310_CLCD_CLK_MASK                 2
  64         #define SPEAR1310_CLCD_CLK_SHIFT                2
  65         #define SPEAR1310_C3_CLK_MASK                   1
  66         #define SPEAR1310_C3_CLK_SHIFT                  1
  67
  68 #define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
  69         #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
  70         #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
  71         #define SPEAR1310_GMAC_PHY_CLK_MASK             1
  72         #define SPEAR1310_GMAC_PHY_CLK_SHIFT            3
  73         #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
  74         #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
  75
  76 #define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
  77         /* I2S_CLK_CFG register mask */
  78         #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
  79         #define SPEAR1310_I2S_SCLK_X_SHIFT              27
  80         #define SPEAR1310_I2S_SCLK_Y_MASK               0x1F
  81         #define SPEAR1310_I2S_SCLK_Y_SHIFT              22
  82         #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT         21
  83         #define SPEAR1310_I2S_SCLK_SYNTH_ENB            20
  84         #define SPEAR1310_I2S_PRS1_CLK_X_MASK           0xFF
  85         #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT          12
  86         #define SPEAR1310_I2S_PRS1_CLK_Y_MASK           0xFF
  87         #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT          4
  88         #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT         3
  89         #define SPEAR1310_I2S_REF_SEL_MASK              1
  90         #define SPEAR1310_I2S_REF_SHIFT                 2
  91         #define SPEAR1310_I2S_SRC_CLK_MASK              2
  92         #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
  93
  94 #define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
  95 #define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
  96 #define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
  97 #define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
  98 #define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
  99 #define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
 100 #define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
 101 #define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
 102 #define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
 103 #define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
 104 #define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
 105 #define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
 106         /* Check Fractional synthesizer reg masks */
 107
 108 #define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
 109         /* PERIP1_CLK_ENB register masks */
 110         #define SPEAR1310_RTC_CLK_ENB                   31
 111         #define SPEAR1310_ADC_CLK_ENB                   30
 112         #define SPEAR1310_C3_CLK_ENB                    29
 113         #define SPEAR1310_JPEG_CLK_ENB                  28
 114         #define SPEAR1310_CLCD_CLK_ENB                  27
 115         #define SPEAR1310_DMA_CLK_ENB                   25
 116         #define SPEAR1310_GPIO1_CLK_ENB                 24
 117         #define SPEAR1310_GPIO0_CLK_ENB                 23
 118         #define SPEAR1310_GPT1_CLK_ENB                  22
 119         #define SPEAR1310_GPT0_CLK_ENB                  21
 120         #define SPEAR1310_I2S0_CLK_ENB                  20
 121         #define SPEAR1310_I2S1_CLK_ENB                  19
 122         #define SPEAR1310_I2C0_CLK_ENB                  18
 123         #define SPEAR1310_SSP_CLK_ENB                   17
 124         #define SPEAR1310_UART_CLK_ENB                  15
 125         #define SPEAR1310_PCIE_SATA_2_CLK_ENB           14
 126         #define SPEAR1310_PCIE_SATA_1_CLK_ENB           13
 127         #define SPEAR1310_PCIE_SATA_0_CLK_ENB           12
 128         #define SPEAR1310_UOC_CLK_ENB                   11
 129         #define SPEAR1310_UHC1_CLK_ENB                  10
 130         #define SPEAR1310_UHC0_CLK_ENB                  9
 131         #define SPEAR1310_GMAC_CLK_ENB                  8
 132         #define SPEAR1310_CFXD_CLK_ENB                  7
 133         #define SPEAR1310_SDHCI_CLK_ENB                 6
 134         #define SPEAR1310_SMI_CLK_ENB                   5
 135         #define SPEAR1310_FSMC_CLK_ENB                  4
 136         #define SPEAR1310_SYSRAM0_CLK_ENB               3
 137         #define SPEAR1310_SYSRAM1_CLK_ENB               2
 138         #define SPEAR1310_SYSROM_CLK_ENB                1
 139         #define SPEAR1310_BUS_CLK_ENB                   0
 140
 141 #define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
 142         /* PERIP2_CLK_ENB register masks */
 143         #define SPEAR1310_THSENS_CLK_ENB                8
 144         #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
 145         #define SPEAR1310_ACP_CLK_ENB                   6
 146         #define SPEAR1310_GPT3_CLK_ENB                  5
 147         #define SPEAR1310_GPT2_CLK_ENB                  4
 148         #define SPEAR1310_KBD_CLK_ENB                   3
 149         #define SPEAR1310_CPU_DBG_CLK_ENB               2
 150         #define SPEAR1310_DDR_CORE_CLK_ENB              1
 151         #define SPEAR1310_DDR_CTRL_CLK_ENB              0
 152
 153 #define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
 154         /* RAS_CLK_ENB register masks */
 155         #define SPEAR1310_SYNT3_CLK_ENB                 17
 156         #define SPEAR1310_SYNT2_CLK_ENB                 16
 157         #define SPEAR1310_SYNT1_CLK_ENB                 15
 158         #define SPEAR1310_SYNT0_CLK_ENB                 14
 159         #define SPEAR1310_PCLK3_CLK_ENB                 13
 160         #define SPEAR1310_PCLK2_CLK_ENB                 12
 161         #define SPEAR1310_PCLK1_CLK_ENB                 11
 162         #define SPEAR1310_PCLK0_CLK_ENB                 10
 163         #define SPEAR1310_PLL3_CLK_ENB                  9
 164         #define SPEAR1310_PLL2_CLK_ENB                  8
 165         #define SPEAR1310_C125M_PAD_CLK_ENB             7
 166         #define SPEAR1310_C30M_CLK_ENB                  6
 167         #define SPEAR1310_C48M_CLK_ENB                  5
 168         #define SPEAR1310_OSC_25M_CLK_ENB               4
 169         #define SPEAR1310_OSC_32K_CLK_ENB               3
 170         #define SPEAR1310_OSC_24M_CLK_ENB               2
 171         #define SPEAR1310_PCLK_CLK_ENB                  1
 172         #define SPEAR1310_ACLK_CLK_ENB                  0
 173
 174 /* RAS Area Control Register */
 175 #define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
 176         #define SPEAR1310_SSP1_CLK_MASK                 3
 177         #define SPEAR1310_SSP1_CLK_SHIFT                26
 178         #define SPEAR1310_TDM_CLK_MASK                  1
 179         #define SPEAR1310_TDM2_CLK_SHIFT                24
 180         #define SPEAR1310_TDM1_CLK_SHIFT                23
 181         #define SPEAR1310_I2C_CLK_MASK                  1
 182         #define SPEAR1310_I2C7_CLK_SHIFT                22
 183         #define SPEAR1310_I2C6_CLK_SHIFT                21
 184         #define SPEAR1310_I2C5_CLK_SHIFT                20
 185         #define SPEAR1310_I2C4_CLK_SHIFT                19
 186         #define SPEAR1310_I2C3_CLK_SHIFT                18
 187         #define SPEAR1310_I2C2_CLK_SHIFT                17
 188         #define SPEAR1310_I2C1_CLK_SHIFT                16
 189         #define SPEAR1310_GPT64_CLK_MASK                1
 190         #define SPEAR1310_GPT64_CLK_SHIFT               15
 191         #define SPEAR1310_RAS_UART_CLK_MASK             1
 192         #define SPEAR1310_UART5_CLK_SHIFT               14
 193         #define SPEAR1310_UART4_CLK_SHIFT               13
 194         #define SPEAR1310_UART3_CLK_SHIFT               12
 195         #define SPEAR1310_UART2_CLK_SHIFT               11
 196         #define SPEAR1310_UART1_CLK_SHIFT               10
 197         #define SPEAR1310_PCI_CLK_MASK                  1
 198         #define SPEAR1310_PCI_CLK_SHIFT                 0
 199
 200 #define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
 201         #define SPEAR1310_PHY_CLK_MASK                  0x3
 202         #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
 203         #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
 204
 205 #define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
 206         #define SPEAR1310_CAN1_CLK_ENB                  25
 207         #define SPEAR1310_CAN0_CLK_ENB                  24
 208         #define SPEAR1310_GPT64_CLK_ENB                 23
 209         #define SPEAR1310_SSP1_CLK_ENB                  22
 210         #define SPEAR1310_I2C7_CLK_ENB                  21
 211         #define SPEAR1310_I2C6_CLK_ENB                  20
 212         #define SPEAR1310_I2C5_CLK_ENB                  19
 213         #define SPEAR1310_I2C4_CLK_ENB                  18
 214         #define SPEAR1310_I2C3_CLK_ENB                  17
 215         #define SPEAR1310_I2C2_CLK_ENB                  16
 216         #define SPEAR1310_I2C1_CLK_ENB                  15
 217         #define SPEAR1310_UART5_CLK_ENB                 14
 218         #define SPEAR1310_UART4_CLK_ENB                 13
 219         #define SPEAR1310_UART3_CLK_ENB                 12
 220         #define SPEAR1310_UART2_CLK_ENB                 11
 221         #define SPEAR1310_UART1_CLK_ENB                 10
 222         #define SPEAR1310_RS485_1_CLK_ENB               9
 223         #define SPEAR1310_RS485_0_CLK_ENB               8
 224         #define SPEAR1310_TDM2_CLK_ENB                  7
 225         #define SPEAR1310_TDM1_CLK_ENB                  6
 226         #define SPEAR1310_PCI_CLK_ENB                   5
 227         #define SPEAR1310_GMII_CLK_ENB                  4
 228         #define SPEAR1310_MII2_CLK_ENB                  3
 229         #define SPEAR1310_MII1_CLK_ENB                  2
 230         #define SPEAR1310_MII0_CLK_ENB                  1
 231         #define SPEAR1310_ESRAM_CLK_ENB                 0
 232
 233 static DEFINE_SPINLOCK(_lock);
 234
 235 /* pll rate configuration table, in ascending order of rates */
 236 static struct pll_rate_tbl pll_rtbl[] = {
 237         /* PCLK 24MHz */
 238         {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
 239         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
 240         {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
 241         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
 242         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
 243         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
 244         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 245 };
 246
 247 /* vco-pll4 rate configuration table, in ascending order of rates */
 248 static struct pll_rate_tbl pll4_rtbl[] = {
 249         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
 250         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
 251         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
 252         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 253 };
 254
 255 /* aux rate configuration table, in ascending order of rates */
 256 static struct aux_rate_tbl aux_rtbl[] = {
 257         /* For VCO1div2 = 500 MHz */
 258         {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
 259         {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
 260         {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
 261         {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
 262         {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
 263         {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
 264 };
 265
 266 /* gmac rate configuration table, in ascending order of rates */
 267 static struct aux_rate_tbl gmac_rtbl[] = {
 268         /* For gmac phy input clk */
 269         {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
 270         {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
 271         {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
 272         {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
 273 };
 274
 275 /* clcd rate configuration table, in ascending order of rates */
 276 static struct frac_rate_tbl clcd_rtbl[] = {
 277         {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
 278         {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
 279         {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
 280         {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
 281         {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
 282         {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
 283         {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
 284         {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
 285         {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
 286         {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
 287 };
 288
 289 /* i2s prescaler1 masks */
 290 static struct aux_clk_masks i2s_prs1_masks = {
 291         .eq_sel_mask = AUX_EQ_SEL_MASK,
 292         .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
 293         .eq1_mask = AUX_EQ1_SEL,
 294         .eq2_mask = AUX_EQ2_SEL,
 295         .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
 296         .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
 297         .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
 298         .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
 299 };
 300
 301 /* i2s sclk (bit clock) syynthesizers masks */
 302 static struct aux_clk_masks i2s_sclk_masks = {
 303         .eq_sel_mask = AUX_EQ_SEL_MASK,
 304         .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
 305         .eq1_mask = AUX_EQ1_SEL,
 306         .eq2_mask = AUX_EQ2_SEL,
 307         .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
 308         .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
 309         .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
 310         .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
 311         .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
 312 };
 313
 314 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 315 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 316         /* For parent clk = 49.152 MHz */
 317         {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
 318         {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
 319         {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
 320         {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
 321
 322         /*
 323          * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
 324          * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
 325          */
 326         {.xscale = 1, .yscale = 3, .eq = 0},
 327
 328         /* For parent clk = 49.152 MHz */
 329         {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
 330
 331         {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
 332 };
 333
 334 /* i2s sclk aux rate configuration table, in ascending order of rates */
 335 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
 336         /* For i2s_ref_clk = 12.288MHz */
 337         {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
 338         {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
 339 };
 340
 341 /* adc rate configuration table, in ascending order of rates */
 342 /* possible adc range is 2.5 MHz to 20 MHz. */
 343 static struct aux_rate_tbl adc_rtbl[] = {
 344         /* For ahb = 166.67 MHz */
 345         {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
 346         {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
 347         {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
 348         {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
 349 };
 350
 351 /* General synth rate configuration table, in ascending order of rates */
 352 static struct frac_rate_tbl gen_rtbl[] = {
 353         /* For vco1div4 = 250 MHz */
 354         {.div = 0x14000}, /* 25 MHz */
 355         {.div = 0x0A000}, /* 50 MHz */
 356         {.div = 0x05000}, /* 100 MHz */
 357         {.div = 0x02000}, /* 250 MHz */
 358 };
 359
 360 /* clock parents */
 361 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 362 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 363 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
 364 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
 365 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
 366         "osc_25m_clk", };
 367 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
 368 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
 369 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
 370 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
 371         "i2s_src_pad_clk", };
 372 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
 373 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 374         "pll3_clk", };
 375 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
 376         "pll2_clk", };
 377 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
 378         "ras_pll2_clk", "ras_syn0_clk", };
 379 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
 380         "ras_pll2_clk", "ras_syn0_clk", };
 381 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
 382 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
 383 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
 384         "ras_plclk0_clk", };
 385 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
 386 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
 387
 388 void __init spear1310_clk_init(void)
 389 {
 390         struct clk *clk, *clk1;
 391
 392         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 393                         32000);
 394         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 395
 396         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
 397                         24000000);
 398         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 399
 400         clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
 401                         25000000);
 402         clk_register_clkdev(clk, "osc_25m_clk", NULL);
 403
 404         clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
 405                         125000000);
 406         clk_register_clkdev(clk, "gmii_pad_clk", NULL);
 407
 408         clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
 409                         CLK_IS_ROOT, 12288000);
 410         clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
 411
 412         /* clock derived from 32 KHz osc clk */
 413         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 414                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
 415                         &_lock);
 416         clk_register_clkdev(clk, NULL, "e0580000.rtc");
 417
 418         /* clock derived from 24 or 25 MHz osc clk */
 419         /* vco-pll */
 420         clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
 421                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 422                         SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 423                         &_lock);
 424         clk_register_clkdev(clk, "vco1_mclk", NULL);
 425         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
 426                         0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
 427                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 428         clk_register_clkdev(clk, "vco1_clk", NULL);
 429         clk_register_clkdev(clk1, "pll1_clk", NULL);
 430
 431         clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
 432                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 433                         SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 434                         &_lock);
 435         clk_register_clkdev(clk, "vco2_mclk", NULL);
 436         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
 437                         0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
 438                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 439         clk_register_clkdev(clk, "vco2_clk", NULL);
 440         clk_register_clkdev(clk1, "pll2_clk", NULL);
 441
 442         clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
 443                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 444                         SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 445                         &_lock);
 446         clk_register_clkdev(clk, "vco3_mclk", NULL);
 447         clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
 448                         0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
 449                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 450         clk_register_clkdev(clk, "vco3_clk", NULL);
 451         clk_register_clkdev(clk1, "pll3_clk", NULL);
 452
 453         clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
 454                         0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
 455                         ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
 456         clk_register_clkdev(clk, "vco4_clk", NULL);
 457         clk_register_clkdev(clk1, "pll4_clk", NULL);
 458
 459         clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
 460                         48000000);
 461         clk_register_clkdev(clk, "pll5_clk", NULL);
 462
 463         clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
 464                         25000000);
 465         clk_register_clkdev(clk, "pll6_clk", NULL);
 466
 467         /* vco div n clocks */
 468         clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
 469                         2);
 470         clk_register_clkdev(clk, "vco1div2_clk", NULL);
 471
 472         clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
 473                         4);
 474         clk_register_clkdev(clk, "vco1div4_clk", NULL);
 475
 476         clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
 477                         2);
 478         clk_register_clkdev(clk, "vco2div2_clk", NULL);
 479
 480         clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
 481                         2);
 482         clk_register_clkdev(clk, "vco3div2_clk", NULL);
 483
 484         /* peripherals */
 485         clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
 486                         128);
 487         clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
 488                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
 489                         &_lock);
 490         clk_register_clkdev(clk, NULL, "spear_thermal");
 491
 492         /* clock derived from pll4 clk */
 493         clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
 494                         1);
 495         clk_register_clkdev(clk, "ddr_clk", NULL);
 496
 497         /* clock derived from pll1 clk */
 498         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
 499                         CLK_SET_RATE_PARENT, 1, 2);
 500         clk_register_clkdev(clk, "cpu_clk", NULL);
 501
 502         clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
 503                         2);
 504         clk_register_clkdev(clk, NULL, "ec800620.wdt");
 505
 506         clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
 507                         2);
 508         clk_register_clkdev(clk, NULL, "smp_twd");
 509
 510         clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 511                         6);
 512         clk_register_clkdev(clk, "ahb_clk", NULL);
 513
 514         clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
 515                         12);
 516         clk_register_clkdev(clk, "apb_clk", NULL);
 517
 518         /* gpt clocks */
 519         clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
 520                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 521                         SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 522                         &_lock);
 523         clk_register_clkdev(clk, "gpt0_mclk", NULL);
 524         clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
 525                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
 526                         &_lock);
 527         clk_register_clkdev(clk, NULL, "gpt0");
 528
 529         clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
 530                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 531                         SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 532                         &_lock);
 533         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 534         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 535                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
 536                         &_lock);
 537         clk_register_clkdev(clk, NULL, "gpt1");
 538
 539         clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
 540                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 541                         SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 542                         &_lock);
 543         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 544         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 545                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
 546                         &_lock);
 547         clk_register_clkdev(clk, NULL, "gpt2");
 548
 549         clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
 550                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 551                         SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 552                         &_lock);
 553         clk_register_clkdev(clk, "gpt3_mclk", NULL);
 554         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 555                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
 556                         &_lock);
 557         clk_register_clkdev(clk, NULL, "gpt3");
 558
 559         /* others */
 560         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
 561                         0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
 562                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 563         clk_register_clkdev(clk, "uart_syn_clk", NULL);
 564         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 565
 566         clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
 567                         ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
 568                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
 569                         SPEAR1310_UART_CLK_MASK, 0, &_lock);
 570         clk_register_clkdev(clk, "uart0_mclk", NULL);
 571
 572         clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
 573                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 574                         SPEAR1310_UART_CLK_ENB, 0, &_lock);
 575         clk_register_clkdev(clk, NULL, "e0000000.serial");
 576
 577         clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
 578                         "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
 579                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 580         clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
 581         clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
 582
 583         clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
 584                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 585                         SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
 586         clk_register_clkdev(clk, NULL, "b3000000.sdhci");
 587
 588         clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
 589                         0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
 590                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 591         clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
 592         clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
 593
 594         clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
 595                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 596                         SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
 597         clk_register_clkdev(clk, NULL, "b2800000.cf");
 598         clk_register_clkdev(clk, NULL, "arasan_xd");
 599
 600         clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
 601                         0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
 602                         ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 603         clk_register_clkdev(clk, "c3_syn_clk", NULL);
 604         clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
 605
 606         clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
 607                         ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
 608                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
 609                         SPEAR1310_C3_CLK_MASK, 0, &_lock);
 610         clk_register_clkdev(clk, "c3_mclk", NULL);
 611
 612         clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
 613                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
 614                         &_lock);
 615         clk_register_clkdev(clk, NULL, "c3");
 616
 617         /* gmac */
 618         clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
 619                         ARRAY_SIZE(gmac_phy_input_parents), 0,
 620                         SPEAR1310_GMAC_CLK_CFG,
 621                         SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 622                         SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 623         clk_register_clkdev(clk, "phy_input_mclk", NULL);
 624
 625         clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
 626                         0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
 627                         ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
 628         clk_register_clkdev(clk, "phy_syn_clk", NULL);
 629         clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
 630
 631         clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
 632                         ARRAY_SIZE(gmac_phy_parents), 0,
 633                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 634                         SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 635         clk_register_clkdev(clk, "stmmacphy.0", NULL);
 636
 637         /* clcd */
 638         clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
 639                         ARRAY_SIZE(clcd_synth_parents), 0,
 640                         SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 641                         SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 642         clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
 643
 644         clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
 645                         SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
 646                         ARRAY_SIZE(clcd_rtbl), &_lock);
 647         clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 648
 649         clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
 650                         ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
 651                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 652                         SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 653         clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
 654
 655         clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 656                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
 657                         &_lock);
 658         clk_register_clkdev(clk, NULL, "e1000000.clcd");
 659
 660         /* i2s */
 661         clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
 662                         ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
 663                         SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
 664                         0, &_lock);
 665         clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 666
 667         clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
 668                         SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
 669                         ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
 670         clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 671
 672         clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
 673                         ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
 674                         SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
 675                         SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
 676         clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
 677
 678         clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
 679                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
 680                         0, &_lock);
 681         clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 682
 683         clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
 684                         "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
 685                         &i2s_sclk_masks, i2s_sclk_rtbl,
 686                         ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
 687         clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
 688         clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
 689
 690         /* clock derived from ahb clk */
 691         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
 692                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
 693                         &_lock);
 694         clk_register_clkdev(clk, NULL, "e0280000.i2c");
 695
 696         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
 697                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
 698                         &_lock);
 699         clk_register_clkdev(clk, NULL, "ea800000.dma");
 700         clk_register_clkdev(clk, NULL, "eb000000.dma");
 701
 702         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
 703                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
 704                         &_lock);
 705         clk_register_clkdev(clk, NULL, "b2000000.jpeg");
 706
 707         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
 708                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
 709                         &_lock);
 710         clk_register_clkdev(clk, NULL, "e2000000.eth");
 711
 712         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
 713                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
 714                         &_lock);
 715         clk_register_clkdev(clk, NULL, "b0000000.flash");
 716
 717         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
 718                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
 719                         &_lock);
 720         clk_register_clkdev(clk, NULL, "ea000000.flash");
 721
 722         clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 723                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
 724                         &_lock);
 725         clk_register_clkdev(clk, NULL, "e4000000.ohci");
 726         clk_register_clkdev(clk, NULL, "e4800000.ehci");
 727
 728         clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 729                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
 730                         &_lock);
 731         clk_register_clkdev(clk, NULL, "e5000000.ohci");
 732         clk_register_clkdev(clk, NULL, "e5800000.ehci");
 733
 734         clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 735                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
 736                         &_lock);
 737         clk_register_clkdev(clk, NULL, "e3800000.otg");
 738
 739         clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 740                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 741                         0, &_lock);
 742         clk_register_clkdev(clk, NULL, "dw_pcie.0");
 743         clk_register_clkdev(clk, NULL, "b1000000.ahci");
 744
 745         clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 746                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 747                         0, &_lock);
 748         clk_register_clkdev(clk, NULL, "dw_pcie.1");
 749         clk_register_clkdev(clk, NULL, "b1800000.ahci");
 750
 751         clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 752                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 753                         0, &_lock);
 754         clk_register_clkdev(clk, NULL, "dw_pcie.2");
 755         clk_register_clkdev(clk, NULL, "b4000000.ahci");
 756
 757         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 758                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
 759                         &_lock);
 760         clk_register_clkdev(clk, "sysram0_clk", NULL);
 761
 762         clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
 763                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
 764                         &_lock);
 765         clk_register_clkdev(clk, "sysram1_clk", NULL);
 766
 767         clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
 768                         0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
 769                         ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
 770         clk_register_clkdev(clk, "adc_syn_clk", NULL);
 771         clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
 772
 773         clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
 774                         CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
 775                         SPEAR1310_ADC_CLK_ENB, 0, &_lock);
 776         clk_register_clkdev(clk, NULL, "e0080000.adc");
 777
 778         /* clock derived from apb clk */
 779         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
 780                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
 781                         &_lock);
 782         clk_register_clkdev(clk, NULL, "e0100000.spi");
 783
 784         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
 785                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
 786                         &_lock);
 787         clk_register_clkdev(clk, NULL, "e0600000.gpio");
 788
 789         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
 790                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
 791                         &_lock);
 792         clk_register_clkdev(clk, NULL, "e0680000.gpio");
 793
 794         clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
 795                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
 796                         &_lock);
 797         clk_register_clkdev(clk, NULL, "e0180000.i2s");
 798
 799         clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
 800                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
 801                         &_lock);
 802         clk_register_clkdev(clk, NULL, "e0200000.i2s");
 803
 804         clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
 805                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
 806                         &_lock);
 807         clk_register_clkdev(clk, NULL, "e0300000.kbd");
 808
 809         /* RAS clks */
 810         clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
 811                         ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG,
 812                         SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 813                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 814         clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
 815
 816         clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
 817                         ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG,
 818                         SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 819                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 820         clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
 821
 822         clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
 823                         SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 824                         &_lock);
 825         clk_register_clkdev(clk, "gen_syn0_clk", NULL);
 826
 827         clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
 828                         SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 829                         &_lock);
 830         clk_register_clkdev(clk, "gen_syn1_clk", NULL);
 831
 832         clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
 833                         SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 834                         &_lock);
 835         clk_register_clkdev(clk, "gen_syn2_clk", NULL);
 836
 837         clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
 838                         SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 839                         &_lock);
 840         clk_register_clkdev(clk, "gen_syn3_clk", NULL);
 841
 842         clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
 843                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
 844                         &_lock);
 845         clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
 846
 847         clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
 848                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
 849                         &_lock);
 850         clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
 851
 852         clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
 853                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
 854                         &_lock);
 855         clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
 856
 857         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 858                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
 859                         &_lock);
 860         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 861
 862         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
 863                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
 864                         &_lock);
 865         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
 866
 867         clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
 868                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
 869                         &_lock);
 870         clk_register_clkdev(clk, "ras_tx125_clk", NULL);
 871
 872         clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
 873                         30000000);
 874         clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
 875                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
 876                         &_lock);
 877         clk_register_clkdev(clk, "ras_30m_clk", NULL);
 878
 879         clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
 880                         48000000);
 881         clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
 882                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
 883                         &_lock);
 884         clk_register_clkdev(clk, "ras_48m_clk", NULL);
 885
 886         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
 887                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
 888                         &_lock);
 889         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 890
 891         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
 892                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
 893                         &_lock);
 894         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 895
 896         clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
 897                         50000000);
 898
 899         clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
 900                         50000000);
 901
 902         clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
 903                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
 904                         &_lock);
 905         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 906
 907         clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
 908                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
 909                         &_lock);
 910         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 911
 912         clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
 913                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
 914                         &_lock);
 915         clk_register_clkdev(clk, NULL, "5c400000.eth");
 916
 917         clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
 918                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
 919                         &_lock);
 920         clk_register_clkdev(clk, NULL, "5c500000.eth");
 921
 922         clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
 923                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
 924                         &_lock);
 925         clk_register_clkdev(clk, NULL, "5c600000.eth");
 926
 927         clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
 928                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
 929                         &_lock);
 930         clk_register_clkdev(clk, NULL, "5c700000.eth");
 931
 932         clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
 933                         smii_rgmii_phy_parents,
 934                         ARRAY_SIZE(smii_rgmii_phy_parents), 0,
 935                         SPEAR1310_RAS_CTRL_REG1,
 936                         SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 937                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 938         clk_register_clkdev(clk, "stmmacphy.1", NULL);
 939         clk_register_clkdev(clk, "stmmacphy.2", NULL);
 940         clk_register_clkdev(clk, "stmmacphy.4", NULL);
 941
 942         clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
 943                         ARRAY_SIZE(rmii_phy_parents), 0,
 944                         SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 945                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 946         clk_register_clkdev(clk, "stmmacphy.3", NULL);
 947
 948         clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
 949                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 950                         SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 951                         0, &_lock);
 952         clk_register_clkdev(clk, "uart1_mclk", NULL);
 953
 954         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
 955                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
 956                         &_lock);
 957         clk_register_clkdev(clk, NULL, "5c800000.serial");
 958
 959         clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
 960                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 961                         SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 962                         0, &_lock);
 963         clk_register_clkdev(clk, "uart2_mclk", NULL);
 964
 965         clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
 966                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
 967                         &_lock);
 968         clk_register_clkdev(clk, NULL, "5c900000.serial");
 969
 970         clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
 971                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 972                         SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 973                         0, &_lock);
 974         clk_register_clkdev(clk, "uart3_mclk", NULL);
 975
 976         clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
 977                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
 978                         &_lock);
 979         clk_register_clkdev(clk, NULL, "5ca00000.serial");
 980
 981         clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
 982                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 983                         SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 984                         0, &_lock);
 985         clk_register_clkdev(clk, "uart4_mclk", NULL);
 986
 987         clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
 988                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
 989                         &_lock);
 990         clk_register_clkdev(clk, NULL, "5cb00000.serial");
 991
 992         clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
 993                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 994                         SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 995                         0, &_lock);
 996         clk_register_clkdev(clk, "uart5_mclk", NULL);
 997
 998         clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
 999                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
1000                         &_lock);
1001         clk_register_clkdev(clk, NULL, "5cc00000.serial");
1002
1003         clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1004                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1005                         SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1006                         &_lock);
1007         clk_register_clkdev(clk, "i2c1_mclk", NULL);
1008
1009         clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
1010                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
1011                         &_lock);
1012         clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1013
1014         clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1015                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1016                         SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1017                         &_lock);
1018         clk_register_clkdev(clk, "i2c2_mclk", NULL);
1019
1020         clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1021                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1022                         &_lock);
1023         clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1024
1025         clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1026                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1027                         SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1028                         &_lock);
1029         clk_register_clkdev(clk, "i2c3_mclk", NULL);
1030
1031         clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1032                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1033                         &_lock);
1034         clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1035
1036         clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1037                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1038                         SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1039                         &_lock);
1040         clk_register_clkdev(clk, "i2c4_mclk", NULL);
1041
1042         clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1043                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1044                         &_lock);
1045         clk_register_clkdev(clk, NULL, "5d000000.i2c");
1046
1047         clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1048                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1049                         SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1050                         &_lock);
1051         clk_register_clkdev(clk, "i2c5_mclk", NULL);
1052
1053         clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1054                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1055                         &_lock);
1056         clk_register_clkdev(clk, NULL, "5d100000.i2c");
1057
1058         clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1059                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1060                         SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1061                         &_lock);
1062         clk_register_clkdev(clk, "i2c6_mclk", NULL);
1063
1064         clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1065                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1066                         &_lock);
1067         clk_register_clkdev(clk, NULL, "5d200000.i2c");
1068
1069         clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1070                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1071                         SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1072                         &_lock);
1073         clk_register_clkdev(clk, "i2c7_mclk", NULL);
1074
1075         clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1076                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1077                         &_lock);
1078         clk_register_clkdev(clk, NULL, "5d300000.i2c");
1079
1080         clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1081                         ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1082                         SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1083                         &_lock);
1084         clk_register_clkdev(clk, "ssp1_mclk", NULL);
1085
1086         clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1087                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1088                         &_lock);
1089         clk_register_clkdev(clk, NULL, "5d400000.spi");
1090
1091         clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1092                         ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1093                         SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1094                         &_lock);
1095         clk_register_clkdev(clk, "pci_mclk", NULL);
1096
1097         clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1098                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1099                         &_lock);
1100         clk_register_clkdev(clk, NULL, "pci");
1101
1102         clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1103                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1104                         SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1105                         &_lock);
1106         clk_register_clkdev(clk, "tdm1_mclk", NULL);
1107
1108         clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1109                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1110                         &_lock);
1111         clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1112
1113         clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1114                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1115                         SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1116                         &_lock);
1117         clk_register_clkdev(clk, "tdm2_mclk", NULL);
1118
1119         clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1120                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1121                         &_lock);
1122         clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1123 }