drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_MASK 0xf
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 6
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68 #define PLLE_BASE_ENABLE BIT(31)
  69
  70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  73 #define PLLE_MISC_READY BIT(15)
  74 #define PLLE_MISC_SETUP_EX_SHIFT 2
  75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  77                               PLLE_MISC_SETUP_EX_MASK)
  78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  79
  80 #define PLLE_SS_CTRL 0x68
  81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  84 #define PLLE_SS_CNTL_CENTER BIT(14)
  85 #define PLLE_SS_CNTL_INVERT BIT(15)
  86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  87                                 PLLE_SS_CNTL_SSC_BYP)
  88 #define PLLE_SS_MAX_MASK 0x1ff
  89 #define PLLE_SS_MAX_VAL 0x25
  90 #define PLLE_SS_INC_MASK (0xff << 16)
  91 #define PLLE_SS_INC_VAL (0x1 << 16)
  92 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  93 #define PLLE_SS_INCINTRV_VAL (0x20 << 24)
  94 #define PLLE_SS_COEFFICIENTS_MASK \
  95         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  96 #define PLLE_SS_COEFFICIENTS_VAL \
  97         (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
  98
  99 #define PLLE_AUX_PLLP_SEL       BIT(2)
 100 #define PLLE_AUX_USE_LOCKDET    BIT(3)
 101 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 102 #define PLLE_AUX_SS_SWCTL       BIT(6)
 103 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 104 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 105 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 106 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 107
 108 #define XUSBIO_PLL_CFG0         0x51c
 109 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 110 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 111 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 112 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 113 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 114
 115 #define SATA_PLL_CFG0           0x490
 116 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 117 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 118 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 119 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 120
 121 #define PLLE_MISC_PLLE_PTS      BIT(8)
 122 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 123 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 124 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 125 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 126 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 127 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 128
 129 #define PLLCX_MISC_STROBE       BIT(31)
 130 #define PLLCX_MISC_RESET        BIT(30)
 131 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 132 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 133 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 134 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 135 #define PLLCX_MISC_ALPHA_SHIFT 18
 136 #define PLLCX_MISC_DIV_LOW_RANGE \
 137                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 138                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 139 #define PLLCX_MISC_DIV_HIGH_RANGE \
 140                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 141                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 142 #define PLLCX_MISC_COEF_LOW_RANGE \
 143                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 144 #define PLLCX_MISC_KA_SHIFT 2
 145 #define PLLCX_MISC_KB_SHIFT 9
 146 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 147                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 148                             PLLCX_MISC_DIV_LOW_RANGE | \
 149                             PLLCX_MISC_RESET)
 150 #define PLLCX_MISC1_DEFAULT 0x000d2308
 151 #define PLLCX_MISC2_DEFAULT 0x30211200
 152 #define PLLCX_MISC3_DEFAULT 0x200
 153
 154 #define PMC_SATA_PWRGT 0x1ac
 155 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 156 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 157
 158 #define PLLSS_MISC_KCP          0
 159 #define PLLSS_MISC_KVCO         0
 160 #define PLLSS_MISC_SETUP        0
 161 #define PLLSS_EN_SDM            0
 162 #define PLLSS_EN_SSC            0
 163 #define PLLSS_EN_DITHER2        0
 164 #define PLLSS_EN_DITHER         1
 165 #define PLLSS_SDM_RESET         0
 166 #define PLLSS_CLAMP             0
 167 #define PLLSS_SDM_SSC_MAX       0
 168 #define PLLSS_SDM_SSC_MIN       0
 169 #define PLLSS_SDM_SSC_STEP      0
 170 #define PLLSS_SDM_DIN           0
 171 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 172                             (PLLSS_MISC_KVCO << 24) | \
 173                             PLLSS_MISC_SETUP)
 174 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 175                            (PLLSS_EN_SSC << 30) | \
 176                            (PLLSS_EN_DITHER2 << 29) | \
 177                            (PLLSS_EN_DITHER << 28) | \
 178                            (PLLSS_SDM_RESET) << 27 | \
 179                            (PLLSS_CLAMP << 22))
 180 #define PLLSS_CTRL1_DEFAULT \
 181                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 182 #define PLLSS_CTRL2_DEFAULT \
 183                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 184 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 185 #define PLLSS_REF_SRC_SEL_SHIFT 25
 186 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 187
 188 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 189 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 190 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 191 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 192 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 193 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 194
 195 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 196 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 197 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 198 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 199 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 200 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 201
 202 #define mask(w) ((1 << (w)) - 1)
 203 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 204 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 205 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 206                       mask(p->params->div_nmp->divp_width))
 207 #define sdm_din_mask(p) p->params->sdm_din_mask
 208 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 209
 210 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 211 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 212 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 213
 214 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 215 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 216 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 217
 218 #define divm_max(p) (divm_mask(p))
 219 #define divn_max(p) (divn_mask(p))
 220 #define divp_max(p) (1 << (divp_mask(p)))
 221
 222 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 223 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 224
 225 static struct div_nmp default_nmp = {
 226         .divn_shift = PLL_BASE_DIVN_SHIFT,
 227         .divn_width = PLL_BASE_DIVN_WIDTH,
 228         .divm_shift = PLL_BASE_DIVM_SHIFT,
 229         .divm_width = PLL_BASE_DIVM_WIDTH,
 230         .divp_shift = PLL_BASE_DIVP_SHIFT,
 231         .divp_width = PLL_BASE_DIVP_WIDTH,
 232 };
 233
 234 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 235 {
 236         u32 val;
 237
 238         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 239                 return;
 240
 241         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 242                 return;
 243
 244         val = pll_readl_misc(pll);
 245         val |= BIT(pll->params->lock_enable_bit_idx);
 246         pll_writel_misc(val, pll);
 247 }
 248
 249 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 250 {
 251         int i;
 252         u32 val, lock_mask;
 253         void __iomem *lock_addr;
 254
 255         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 256                 udelay(pll->params->lock_delay);
 257                 return 0;
 258         }
 259
 260         lock_addr = pll->clk_base;
 261         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 262                 lock_addr += pll->params->misc_reg;
 263         else
 264                 lock_addr += pll->params->base_reg;
 265
 266         lock_mask = pll->params->lock_mask;
 267
 268         for (i = 0; i < pll->params->lock_delay; i++) {
 269                 val = readl_relaxed(lock_addr);
 270                 if ((val & lock_mask) == lock_mask) {
 271                         udelay(PLL_POST_LOCK_DELAY);
 272                         return 0;
 273                 }
 274                 udelay(2); /* timeout = 2 * lock time */
 275         }
 276
 277         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 278                clk_hw_get_name(&pll->hw));
 279
 280         return -1;
 281 }
 282
 283 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 284 {
 285         return clk_pll_wait_for_lock(pll);
 286 }
 287
 288 static int clk_pll_is_enabled(struct clk_hw *hw)
 289 {
 290         struct tegra_clk_pll *pll = to_clk_pll(hw);
 291         u32 val;
 292
 293         if (pll->params->flags & TEGRA_PLLM) {
 294                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 295                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 296                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 297         }
 298
 299         val = pll_readl_base(pll);
 300
 301         return val & PLL_BASE_ENABLE ? 1 : 0;
 302 }
 303
 304 static void _clk_pll_enable(struct clk_hw *hw)
 305 {
 306         struct tegra_clk_pll *pll = to_clk_pll(hw);
 307         u32 val;
 308
 309         if (pll->params->iddq_reg) {
 310                 val = pll_readl(pll->params->iddq_reg, pll);
 311                 val &= ~BIT(pll->params->iddq_bit_idx);
 312                 pll_writel(val, pll->params->iddq_reg, pll);
 313                 udelay(2);
 314         }
 315
 316         if (pll->params->reset_reg) {
 317                 val = pll_readl(pll->params->reset_reg, pll);
 318                 val &= ~BIT(pll->params->reset_bit_idx);
 319                 pll_writel(val, pll->params->reset_reg, pll);
 320         }
 321
 322         clk_pll_enable_lock(pll);
 323
 324         val = pll_readl_base(pll);
 325         if (pll->params->flags & TEGRA_PLL_BYPASS)
 326                 val &= ~PLL_BASE_BYPASS;
 327         val |= PLL_BASE_ENABLE;
 328         pll_writel_base(val, pll);
 329
 330         if (pll->params->flags & TEGRA_PLLM) {
 331                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 332                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 333                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 334         }
 335 }
 336
 337 static void _clk_pll_disable(struct clk_hw *hw)
 338 {
 339         struct tegra_clk_pll *pll = to_clk_pll(hw);
 340         u32 val;
 341
 342         val = pll_readl_base(pll);
 343         if (pll->params->flags & TEGRA_PLL_BYPASS)
 344                 val &= ~PLL_BASE_BYPASS;
 345         val &= ~PLL_BASE_ENABLE;
 346         pll_writel_base(val, pll);
 347
 348         if (pll->params->flags & TEGRA_PLLM) {
 349                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 350                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 351                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 352         }
 353
 354         if (pll->params->reset_reg) {
 355                 val = pll_readl(pll->params->reset_reg, pll);
 356                 val |= BIT(pll->params->reset_bit_idx);
 357                 pll_writel(val, pll->params->reset_reg, pll);
 358         }
 359
 360         if (pll->params->iddq_reg) {
 361                 val = pll_readl(pll->params->iddq_reg, pll);
 362                 val |= BIT(pll->params->iddq_bit_idx);
 363                 pll_writel(val, pll->params->iddq_reg, pll);
 364                 udelay(2);
 365         }
 366 }
 367
 368 static int clk_pll_enable(struct clk_hw *hw)
 369 {
 370         struct tegra_clk_pll *pll = to_clk_pll(hw);
 371         unsigned long flags = 0;
 372         int ret;
 373
 374         if (pll->lock)
 375                 spin_lock_irqsave(pll->lock, flags);
 376
 377         _clk_pll_enable(hw);
 378
 379         ret = clk_pll_wait_for_lock(pll);
 380
 381         if (pll->lock)
 382                 spin_unlock_irqrestore(pll->lock, flags);
 383
 384         return ret;
 385 }
 386
 387 static void clk_pll_disable(struct clk_hw *hw)
 388 {
 389         struct tegra_clk_pll *pll = to_clk_pll(hw);
 390         unsigned long flags = 0;
 391
 392         if (pll->lock)
 393                 spin_lock_irqsave(pll->lock, flags);
 394
 395         _clk_pll_disable(hw);
 396
 397         if (pll->lock)
 398                 spin_unlock_irqrestore(pll->lock, flags);
 399 }
 400
 401 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 402 {
 403         struct tegra_clk_pll *pll = to_clk_pll(hw);
 404         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 405
 406         if (p_tohw) {
 407                 while (p_tohw->pdiv) {
 408                         if (p_div <= p_tohw->pdiv)
 409                                 return p_tohw->hw_val;
 410                         p_tohw++;
 411                 }
 412                 return -EINVAL;
 413         }
 414         return -EINVAL;
 415 }
 416
 417 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 418 {
 419         return _p_div_to_hw(&pll->hw, p_div);
 420 }
 421
 422 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 423 {
 424         struct tegra_clk_pll *pll = to_clk_pll(hw);
 425         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 426
 427         if (p_tohw) {
 428                 while (p_tohw->pdiv) {
 429                         if (p_div_hw == p_tohw->hw_val)
 430                                 return p_tohw->pdiv;
 431                         p_tohw++;
 432                 }
 433                 return -EINVAL;
 434         }
 435
 436         return 1 << p_div_hw;
 437 }
 438
 439 static int _get_table_rate(struct clk_hw *hw,
 440                            struct tegra_clk_pll_freq_table *cfg,
 441                            unsigned long rate, unsigned long parent_rate)
 442 {
 443         struct tegra_clk_pll *pll = to_clk_pll(hw);
 444         struct tegra_clk_pll_freq_table *sel;
 445         int p;
 446
 447         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 448                 if (sel->input_rate == parent_rate &&
 449                     sel->output_rate == rate)
 450                         break;
 451
 452         if (sel->input_rate == 0)
 453                 return -EINVAL;
 454
 455         if (pll->params->pdiv_tohw) {
 456                 p = _p_div_to_hw(hw, sel->p);
 457                 if (p < 0)
 458                         return p;
 459         } else {
 460                 p = ilog2(sel->p);
 461         }
 462
 463         cfg->input_rate = sel->input_rate;
 464         cfg->output_rate = sel->output_rate;
 465         cfg->m = sel->m;
 466         cfg->n = sel->n;
 467         cfg->p = p;
 468         cfg->cpcon = sel->cpcon;
 469         cfg->sdm_data = sel->sdm_data;
 470
 471         return 0;
 472 }
 473
 474 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 475                       unsigned long rate, unsigned long parent_rate)
 476 {
 477         struct tegra_clk_pll *pll = to_clk_pll(hw);
 478         unsigned long cfreq;
 479         u32 p_div = 0;
 480         int ret;
 481
 482         switch (parent_rate) {
 483         case 12000000:
 484         case 26000000:
 485                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 486                 break;
 487         case 13000000:
 488                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 489                 break;
 490         case 16800000:
 491         case 19200000:
 492                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 493                 break;
 494         case 9600000:
 495         case 28800000:
 496                 /*
 497                  * PLL_P_OUT1 rate is not listed in PLLA table
 498                  */
 499                 cfreq = parent_rate / (parent_rate / 1000000);
 500                 break;
 501         default:
 502                 pr_err("%s Unexpected reference rate %lu\n",
 503                        __func__, parent_rate);
 504                 BUG();
 505         }
 506
 507         /* Raise VCO to guarantee 0.5% accuracy */
 508         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 509              cfg->output_rate <<= 1)
 510                 p_div++;
 511
 512         cfg->m = parent_rate / cfreq;
 513         cfg->n = cfg->output_rate / cfreq;
 514         cfg->cpcon = OUT_OF_TABLE_CPCON;
 515
 516         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 517             (1 << p_div) > divp_max(pll)
 518             || cfg->output_rate > pll->params->vco_max) {
 519                 return -EINVAL;
 520         }
 521
 522         cfg->output_rate >>= p_div;
 523
 524         if (pll->params->pdiv_tohw) {
 525                 ret = _p_div_to_hw(hw, 1 << p_div);
 526                 if (ret < 0)
 527                         return ret;
 528                 else
 529                         cfg->p = ret;
 530         } else
 531                 cfg->p = p_div;
 532
 533         return 0;
 534 }
 535
 536 /*
 537  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 538  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 539  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 540  * to indicate that SDM is disabled.
 541  *
 542  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 543  */
 544 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 545                                  struct tegra_clk_pll_freq_table *cfg)
 546 {
 547         struct tegra_clk_pll *pll = to_clk_pll(hw);
 548         u32 val;
 549         bool enabled;
 550
 551         if (!pll->params->sdm_din_reg)
 552                 return;
 553
 554         if (cfg->sdm_data) {
 555                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 556                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 557                 pll_writel_sdm_din(val, pll);
 558         }
 559
 560         val = pll_readl_sdm_ctrl(pll);
 561         enabled = (val & sdm_en_mask(pll));
 562
 563         if (cfg->sdm_data == 0 && enabled)
 564                 val &= ~pll->params->sdm_ctrl_en_mask;
 565
 566         if (cfg->sdm_data != 0 && !enabled)
 567                 val |= pll->params->sdm_ctrl_en_mask;
 568
 569         pll_writel_sdm_ctrl(val, pll);
 570 }
 571
 572 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 573                             struct tegra_clk_pll_freq_table *cfg)
 574 {
 575         u32 val;
 576         struct tegra_clk_pll_params *params = pll->params;
 577         struct div_nmp *div_nmp = params->div_nmp;
 578
 579         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 580                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 581                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 582                 val = pll_override_readl(params->pmc_divp_reg, pll);
 583                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 584                 val |= cfg->p << div_nmp->override_divp_shift;
 585                 pll_override_writel(val, params->pmc_divp_reg, pll);
 586
 587                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 588                 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
 589                         ~(divn_mask(pll) << div_nmp->override_divn_shift);
 590                 val |= (cfg->m << div_nmp->override_divm_shift) |
 591                         (cfg->n << div_nmp->override_divn_shift);
 592                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 593         } else {
 594                 val = pll_readl_base(pll);
 595
 596                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 597                          divp_mask_shifted(pll));
 598
 599                 val |= (cfg->m << divm_shift(pll)) |
 600                        (cfg->n << divn_shift(pll)) |
 601                        (cfg->p << divp_shift(pll));
 602
 603                 pll_writel_base(val, pll);
 604
 605                 clk_pll_set_sdm_data(&pll->hw, cfg);
 606         }
 607 }
 608
 609 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 610                          struct tegra_clk_pll_freq_table *cfg)
 611 {
 612         u32 val;
 613         struct tegra_clk_pll_params *params = pll->params;
 614         struct div_nmp *div_nmp = params->div_nmp;
 615
 616         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 617                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 618                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 619                 val = pll_override_readl(params->pmc_divp_reg, pll);
 620                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 621
 622                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 623                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 624                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 625         }  else {
 626                 val = pll_readl_base(pll);
 627
 628                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 629                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 630                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 631
 632                 if (pll->params->sdm_din_reg) {
 633                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 634                                 val = pll_readl_sdm_din(pll);
 635                                 val &= sdm_din_mask(pll);
 636                                 cfg->sdm_data = sdin_din_to_data(val);
 637                         }
 638                 }
 639         }
 640 }
 641
 642 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 643                               struct tegra_clk_pll_freq_table *cfg,
 644                               unsigned long rate)
 645 {
 646         u32 val;
 647
 648         val = pll_readl_misc(pll);
 649
 650         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 651         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 652
 653         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 654                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 655                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 656                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 657         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 658                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 659                 if (rate >= (pll->params->vco_max >> 1))
 660                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 661         }
 662
 663         pll_writel_misc(val, pll);
 664 }
 665
 666 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 667 {
 668         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 669                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 670
 671                 val |= pll->params->ssc_ctrl_en_mask;
 672                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 673         }
 674 }
 675
 676 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 677 {
 678         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 679                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 680
 681                 val &= ~pll->params->ssc_ctrl_en_mask;
 682                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 683         }
 684 }
 685
 686 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 687                         unsigned long rate)
 688 {
 689         struct tegra_clk_pll *pll = to_clk_pll(hw);
 690         struct tegra_clk_pll_freq_table old_cfg;
 691         int state, ret = 0;
 692
 693         state = clk_pll_is_enabled(hw);
 694
 695         _get_pll_mnp(pll, &old_cfg);
 696
 697         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 698                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 699                 ret = pll->params->dyn_ramp(pll, cfg);
 700                 if (!ret)
 701                         return 0;
 702         }
 703
 704         if (state) {
 705                 pll_clk_stop_ss(pll);
 706                 _clk_pll_disable(hw);
 707         }
 708
 709         if (!pll->params->defaults_set && pll->params->set_defaults)
 710                 pll->params->set_defaults(pll);
 711
 712         _update_pll_mnp(pll, cfg);
 713
 714         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 715                 _update_pll_cpcon(pll, cfg, rate);
 716
 717         if (state) {
 718                 _clk_pll_enable(hw);
 719                 ret = clk_pll_wait_for_lock(pll);
 720                 pll_clk_start_ss(pll);
 721         }
 722
 723         return ret;
 724 }
 725
 726 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 727                         unsigned long parent_rate)
 728 {
 729         struct tegra_clk_pll *pll = to_clk_pll(hw);
 730         struct tegra_clk_pll_freq_table cfg, old_cfg;
 731         unsigned long flags = 0;
 732         int ret = 0;
 733
 734         if (pll->params->flags & TEGRA_PLL_FIXED) {
 735                 if (rate != pll->params->fixed_rate) {
 736                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 737                                 __func__, clk_hw_get_name(hw),
 738                                 pll->params->fixed_rate, rate);
 739                         return -EINVAL;
 740                 }
 741                 return 0;
 742         }
 743
 744         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 745             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 746                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 747                        clk_hw_get_name(hw), rate);
 748                 WARN_ON(1);
 749                 return -EINVAL;
 750         }
 751         if (pll->lock)
 752                 spin_lock_irqsave(pll->lock, flags);
 753
 754         _get_pll_mnp(pll, &old_cfg);
 755         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 756                 cfg.p = old_cfg.p;
 757
 758         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 759                 old_cfg.sdm_data != cfg.sdm_data)
 760                 ret = _program_pll(hw, &cfg, rate);
 761
 762         if (pll->lock)
 763                 spin_unlock_irqrestore(pll->lock, flags);
 764
 765         return ret;
 766 }
 767
 768 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 769                         unsigned long *prate)
 770 {
 771         struct tegra_clk_pll *pll = to_clk_pll(hw);
 772         struct tegra_clk_pll_freq_table cfg;
 773
 774         if (pll->params->flags & TEGRA_PLL_FIXED) {
 775                 /* PLLM/MB are used for memory; we do not change rate */
 776                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 777                         return clk_hw_get_rate(hw);
 778                 return pll->params->fixed_rate;
 779         }
 780
 781         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 782             pll->params->calc_rate(hw, &cfg, rate, *prate))
 783                 return -EINVAL;
 784
 785         return cfg.output_rate;
 786 }
 787
 788 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 789                                          unsigned long parent_rate)
 790 {
 791         struct tegra_clk_pll *pll = to_clk_pll(hw);
 792         struct tegra_clk_pll_freq_table cfg;
 793         u32 val;
 794         u64 rate = parent_rate;
 795         int pdiv;
 796
 797         val = pll_readl_base(pll);
 798
 799         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 800                 return parent_rate;
 801
 802         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 803             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 804                         !(val & PLL_BASE_OVERRIDE)) {
 805                 struct tegra_clk_pll_freq_table sel;
 806                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 807                                         parent_rate)) {
 808                         pr_err("Clock %s has unknown fixed frequency\n",
 809                                clk_hw_get_name(hw));
 810                         BUG();
 811                 }
 812                 return pll->params->fixed_rate;
 813         }
 814
 815         _get_pll_mnp(pll, &cfg);
 816
 817         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 818                 pdiv = 1;
 819         } else {
 820                 pdiv = _hw_to_p_div(hw, cfg.p);
 821                 if (pdiv < 0) {
 822                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 823                              clk_hw_get_name(hw), cfg.p);
 824                         pdiv = 1;
 825                 }
 826         }
 827
 828         if (pll->params->set_gain)
 829                 pll->params->set_gain(&cfg);
 830
 831         cfg.m *= pdiv;
 832
 833         rate *= cfg.n;
 834         do_div(rate, cfg.m);
 835
 836         return rate;
 837 }
 838
 839 static int clk_plle_training(struct tegra_clk_pll *pll)
 840 {
 841         u32 val;
 842         unsigned long timeout;
 843
 844         if (!pll->pmc)
 845                 return -ENOSYS;
 846
 847         /*
 848          * PLLE is already disabled, and setup cleared;
 849          * create falling edge on PLLE IDDQ input.
 850          */
 851         val = readl(pll->pmc + PMC_SATA_PWRGT);
 852         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 853         writel(val, pll->pmc + PMC_SATA_PWRGT);
 854
 855         val = readl(pll->pmc + PMC_SATA_PWRGT);
 856         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 857         writel(val, pll->pmc + PMC_SATA_PWRGT);
 858
 859         val = readl(pll->pmc + PMC_SATA_PWRGT);
 860         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 861         writel(val, pll->pmc + PMC_SATA_PWRGT);
 862
 863         val = pll_readl_misc(pll);
 864
 865         timeout = jiffies + msecs_to_jiffies(100);
 866         while (1) {
 867                 val = pll_readl_misc(pll);
 868                 if (val & PLLE_MISC_READY)
 869                         break;
 870                 if (time_after(jiffies, timeout)) {
 871                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 872                         return -EBUSY;
 873                 }
 874                 udelay(300);
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int clk_plle_enable(struct clk_hw *hw)
 881 {
 882         struct tegra_clk_pll *pll = to_clk_pll(hw);
 883         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
 884         struct tegra_clk_pll_freq_table sel;
 885         u32 val;
 886         int err;
 887
 888         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 889                 return -EINVAL;
 890
 891         clk_pll_disable(hw);
 892
 893         val = pll_readl_misc(pll);
 894         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 895         pll_writel_misc(val, pll);
 896
 897         val = pll_readl_misc(pll);
 898         if (!(val & PLLE_MISC_READY)) {
 899                 err = clk_plle_training(pll);
 900                 if (err)
 901                         return err;
 902         }
 903
 904         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 905                 /* configure dividers */
 906                 val = pll_readl_base(pll);
 907                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 908                          divm_mask_shifted(pll));
 909                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 910                 val |= sel.m << divm_shift(pll);
 911                 val |= sel.n << divn_shift(pll);
 912                 val |= sel.p << divp_shift(pll);
 913                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 914                 pll_writel_base(val, pll);
 915         }
 916
 917         val = pll_readl_misc(pll);
 918         val |= PLLE_MISC_SETUP_VALUE;
 919         val |= PLLE_MISC_LOCK_ENABLE;
 920         pll_writel_misc(val, pll);
 921
 922         val = readl(pll->clk_base + PLLE_SS_CTRL);
 923         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 924         val |= PLLE_SS_DISABLE;
 925         writel(val, pll->clk_base + PLLE_SS_CTRL);
 926
 927         val = pll_readl_base(pll);
 928         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 929         pll_writel_base(val, pll);
 930
 931         clk_pll_wait_for_lock(pll);
 932
 933         return 0;
 934 }
 935
 936 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 937                                          unsigned long parent_rate)
 938 {
 939         struct tegra_clk_pll *pll = to_clk_pll(hw);
 940         u32 val = pll_readl_base(pll);
 941         u32 divn = 0, divm = 0, divp = 0;
 942         u64 rate = parent_rate;
 943
 944         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
 945         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
 946         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
 947         divm *= divp;
 948
 949         rate *= divn;
 950         do_div(rate, divm);
 951         return rate;
 952 }
 953
 954 const struct clk_ops tegra_clk_pll_ops = {
 955         .is_enabled = clk_pll_is_enabled,
 956         .enable = clk_pll_enable,
 957         .disable = clk_pll_disable,
 958         .recalc_rate = clk_pll_recalc_rate,
 959         .round_rate = clk_pll_round_rate,
 960         .set_rate = clk_pll_set_rate,
 961 };
 962
 963 const struct clk_ops tegra_clk_plle_ops = {
 964         .recalc_rate = clk_plle_recalc_rate,
 965         .is_enabled = clk_pll_is_enabled,
 966         .disable = clk_pll_disable,
 967         .enable = clk_plle_enable,
 968 };
 969
 970 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
 971                            unsigned long parent_rate)
 972 {
 973         u16 mdiv = parent_rate / pll_params->cf_min;
 974
 975         if (pll_params->flags & TEGRA_MDIV_NEW)
 976                 return (!pll_params->mdiv_default ? mdiv :
 977                         min(mdiv, pll_params->mdiv_default));
 978
 979         if (pll_params->mdiv_default)
 980                 return pll_params->mdiv_default;
 981
 982         if (parent_rate > pll_params->cf_max)
 983                 return 2;
 984         else
 985                 return 1;
 986 }
 987
 988 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
 989                                 struct tegra_clk_pll_freq_table *cfg,
 990                                 unsigned long rate, unsigned long parent_rate)
 991 {
 992         struct tegra_clk_pll *pll = to_clk_pll(hw);
 993         unsigned int p;
 994         int p_div;
 995
 996         if (!rate)
 997                 return -EINVAL;
 998
 999         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1000         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1001         cfg->output_rate = rate * p;
1002         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1003         cfg->input_rate = parent_rate;
1004
1005         p_div = _p_div_to_hw(hw, p);
1006         if (p_div < 0)
1007                 return p_div;
1008
1009         cfg->p = p_div;
1010
1011         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1012                 return -EINVAL;
1013
1014         return 0;
1015 }
1016
1017 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1018         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1019         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1020         defined(CONFIG_ARCH_TEGRA_210_SOC)
1021
1022 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1023 {
1024         struct tegra_clk_pll *pll = to_clk_pll(hw);
1025
1026         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1027 }
1028
1029 static unsigned long _clip_vco_min(unsigned long vco_min,
1030                                    unsigned long parent_rate)
1031 {
1032         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1033 }
1034
1035 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1036                                void __iomem *clk_base,
1037                                unsigned long parent_rate)
1038 {
1039         u32 val;
1040         u32 step_a, step_b;
1041
1042         switch (parent_rate) {
1043         case 12000000:
1044         case 13000000:
1045         case 26000000:
1046                 step_a = 0x2B;
1047                 step_b = 0x0B;
1048                 break;
1049         case 16800000:
1050                 step_a = 0x1A;
1051                 step_b = 0x09;
1052                 break;
1053         case 19200000:
1054                 step_a = 0x12;
1055                 step_b = 0x08;
1056                 break;
1057         default:
1058                 pr_err("%s: Unexpected reference rate %lu\n",
1059                         __func__, parent_rate);
1060                 WARN_ON(1);
1061                 return -EINVAL;
1062         }
1063
1064         val = step_a << pll_params->stepa_shift;
1065         val |= step_b << pll_params->stepb_shift;
1066         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1067
1068         return 0;
1069 }
1070
1071 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1072                               struct tegra_clk_pll_freq_table *cfg,
1073                               unsigned long rate, unsigned long parent_rate)
1074 {
1075         struct tegra_clk_pll *pll = to_clk_pll(hw);
1076         int err = 0;
1077
1078         err = _get_table_rate(hw, cfg, rate, parent_rate);
1079         if (err < 0)
1080                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1081         else {
1082                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1083                         WARN_ON(1);
1084                         err = -EINVAL;
1085                         goto out;
1086                 }
1087         }
1088
1089         if (cfg->p >  pll->params->max_p)
1090                 err = -EINVAL;
1091
1092 out:
1093         return err;
1094 }
1095
1096 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1097                                 unsigned long parent_rate)
1098 {
1099         struct tegra_clk_pll *pll = to_clk_pll(hw);
1100         struct tegra_clk_pll_freq_table cfg, old_cfg;
1101         unsigned long flags = 0;
1102         int ret;
1103
1104         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1105         if (ret < 0)
1106                 return ret;
1107
1108         if (pll->lock)
1109                 spin_lock_irqsave(pll->lock, flags);
1110
1111         _get_pll_mnp(pll, &old_cfg);
1112         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1113                 cfg.p = old_cfg.p;
1114
1115         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1116                 ret = _program_pll(hw, &cfg, rate);
1117
1118         if (pll->lock)
1119                 spin_unlock_irqrestore(pll->lock, flags);
1120
1121         return ret;
1122 }
1123
1124 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1125                                 unsigned long *prate)
1126 {
1127         struct tegra_clk_pll *pll = to_clk_pll(hw);
1128         struct tegra_clk_pll_freq_table cfg;
1129         int ret, p_div;
1130         u64 output_rate = *prate;
1131
1132         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1133         if (ret < 0)
1134                 return ret;
1135
1136         p_div = _hw_to_p_div(hw, cfg.p);
1137         if (p_div < 0)
1138                 return p_div;
1139
1140         if (pll->params->set_gain)
1141                 pll->params->set_gain(&cfg);
1142
1143         output_rate *= cfg.n;
1144         do_div(output_rate, cfg.m * p_div);
1145
1146         return output_rate;
1147 }
1148
1149 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1150 {
1151         u32 val;
1152
1153         val = pll_readl_misc(pll);
1154         val |= PLLCX_MISC_STROBE;
1155         pll_writel_misc(val, pll);
1156         udelay(2);
1157
1158         val &= ~PLLCX_MISC_STROBE;
1159         pll_writel_misc(val, pll);
1160 }
1161
1162 static int clk_pllc_enable(struct clk_hw *hw)
1163 {
1164         struct tegra_clk_pll *pll = to_clk_pll(hw);
1165         u32 val;
1166         int ret;
1167         unsigned long flags = 0;
1168
1169         if (pll->lock)
1170                 spin_lock_irqsave(pll->lock, flags);
1171
1172         _clk_pll_enable(hw);
1173         udelay(2);
1174
1175         val = pll_readl_misc(pll);
1176         val &= ~PLLCX_MISC_RESET;
1177         pll_writel_misc(val, pll);
1178         udelay(2);
1179
1180         _pllcx_strobe(pll);
1181
1182         ret = clk_pll_wait_for_lock(pll);
1183
1184         if (pll->lock)
1185                 spin_unlock_irqrestore(pll->lock, flags);
1186
1187         return ret;
1188 }
1189
1190 static void _clk_pllc_disable(struct clk_hw *hw)
1191 {
1192         struct tegra_clk_pll *pll = to_clk_pll(hw);
1193         u32 val;
1194
1195         _clk_pll_disable(hw);
1196
1197         val = pll_readl_misc(pll);
1198         val |= PLLCX_MISC_RESET;
1199         pll_writel_misc(val, pll);
1200         udelay(2);
1201 }
1202
1203 static void clk_pllc_disable(struct clk_hw *hw)
1204 {
1205         struct tegra_clk_pll *pll = to_clk_pll(hw);
1206         unsigned long flags = 0;
1207
1208         if (pll->lock)
1209                 spin_lock_irqsave(pll->lock, flags);
1210
1211         _clk_pllc_disable(hw);
1212
1213         if (pll->lock)
1214                 spin_unlock_irqrestore(pll->lock, flags);
1215 }
1216
1217 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1218                                         unsigned long input_rate, u32 n)
1219 {
1220         u32 val, n_threshold;
1221
1222         switch (input_rate) {
1223         case 12000000:
1224                 n_threshold = 70;
1225                 break;
1226         case 13000000:
1227         case 26000000:
1228                 n_threshold = 71;
1229                 break;
1230         case 16800000:
1231                 n_threshold = 55;
1232                 break;
1233         case 19200000:
1234                 n_threshold = 48;
1235                 break;
1236         default:
1237                 pr_err("%s: Unexpected reference rate %lu\n",
1238                         __func__, input_rate);
1239                 return -EINVAL;
1240         }
1241
1242         val = pll_readl_misc(pll);
1243         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1244         val |= n <= n_threshold ?
1245                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1246         pll_writel_misc(val, pll);
1247
1248         return 0;
1249 }
1250
1251 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1252                                 unsigned long parent_rate)
1253 {
1254         struct tegra_clk_pll_freq_table cfg, old_cfg;
1255         struct tegra_clk_pll *pll = to_clk_pll(hw);
1256         unsigned long flags = 0;
1257         int state, ret = 0;
1258
1259         if (pll->lock)
1260                 spin_lock_irqsave(pll->lock, flags);
1261
1262         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1263         if (ret < 0)
1264                 goto out;
1265
1266         _get_pll_mnp(pll, &old_cfg);
1267
1268         if (cfg.m != old_cfg.m) {
1269                 WARN_ON(1);
1270                 goto out;
1271         }
1272
1273         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1274                 goto out;
1275
1276         state = clk_pll_is_enabled(hw);
1277         if (state)
1278                 _clk_pllc_disable(hw);
1279
1280         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1281         if (ret < 0)
1282                 goto out;
1283
1284         _update_pll_mnp(pll, &cfg);
1285
1286         if (state)
1287                 ret = clk_pllc_enable(hw);
1288
1289 out:
1290         if (pll->lock)
1291                 spin_unlock_irqrestore(pll->lock, flags);
1292
1293         return ret;
1294 }
1295
1296 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1297                              struct tegra_clk_pll_freq_table *cfg,
1298                              unsigned long rate, unsigned long parent_rate)
1299 {
1300         u16 m, n;
1301         u64 output_rate = parent_rate;
1302
1303         m = _pll_fixed_mdiv(pll->params, parent_rate);
1304         n = rate * m / parent_rate;
1305
1306         output_rate *= n;
1307         do_div(output_rate, m);
1308
1309         if (cfg) {
1310                 cfg->m = m;
1311                 cfg->n = n;
1312         }
1313
1314         return output_rate;
1315 }
1316
1317 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1318                                 unsigned long parent_rate)
1319 {
1320         struct tegra_clk_pll_freq_table cfg, old_cfg;
1321         struct tegra_clk_pll *pll = to_clk_pll(hw);
1322         unsigned long flags = 0;
1323         int state, ret = 0;
1324
1325         if (pll->lock)
1326                 spin_lock_irqsave(pll->lock, flags);
1327
1328         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1329         _get_pll_mnp(pll, &old_cfg);
1330         cfg.p = old_cfg.p;
1331
1332         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1333                 state = clk_pll_is_enabled(hw);
1334                 if (state)
1335                         _clk_pll_disable(hw);
1336
1337                 _update_pll_mnp(pll, &cfg);
1338
1339                 if (state) {
1340                         _clk_pll_enable(hw);
1341                         ret = clk_pll_wait_for_lock(pll);
1342                 }
1343         }
1344
1345         if (pll->lock)
1346                 spin_unlock_irqrestore(pll->lock, flags);
1347
1348         return ret;
1349 }
1350
1351 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1352                                          unsigned long parent_rate)
1353 {
1354         struct tegra_clk_pll_freq_table cfg;
1355         struct tegra_clk_pll *pll = to_clk_pll(hw);
1356         u64 rate = parent_rate;
1357
1358         _get_pll_mnp(pll, &cfg);
1359
1360         rate *= cfg.n;
1361         do_div(rate, cfg.m);
1362
1363         return rate;
1364 }
1365
1366 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1367                                  unsigned long *prate)
1368 {
1369         struct tegra_clk_pll *pll = to_clk_pll(hw);
1370
1371         return _pllre_calc_rate(pll, NULL, rate, *prate);
1372 }
1373
1374 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1375 {
1376         struct tegra_clk_pll *pll = to_clk_pll(hw);
1377         struct tegra_clk_pll_freq_table sel;
1378         u32 val;
1379         int ret;
1380         unsigned long flags = 0;
1381         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1382
1383         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1384                 return -EINVAL;
1385
1386         if (pll->lock)
1387                 spin_lock_irqsave(pll->lock, flags);
1388
1389         val = pll_readl_base(pll);
1390         val &= ~BIT(29); /* Disable lock override */
1391         pll_writel_base(val, pll);
1392
1393         val = pll_readl(pll->params->aux_reg, pll);
1394         val |= PLLE_AUX_ENABLE_SWCTL;
1395         val &= ~PLLE_AUX_SEQ_ENABLE;
1396         pll_writel(val, pll->params->aux_reg, pll);
1397         udelay(1);
1398
1399         val = pll_readl_misc(pll);
1400         val |= PLLE_MISC_LOCK_ENABLE;
1401         val |= PLLE_MISC_IDDQ_SW_CTRL;
1402         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1403         val |= PLLE_MISC_PLLE_PTS;
1404         val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
1405         pll_writel_misc(val, pll);
1406         udelay(5);
1407
1408         val = pll_readl(PLLE_SS_CTRL, pll);
1409         val |= PLLE_SS_DISABLE;
1410         pll_writel(val, PLLE_SS_CTRL, pll);
1411
1412         val = pll_readl_base(pll);
1413         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1414                  divm_mask_shifted(pll));
1415         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1416         val |= sel.m << divm_shift(pll);
1417         val |= sel.n << divn_shift(pll);
1418         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1419         pll_writel_base(val, pll);
1420         udelay(1);
1421
1422         _clk_pll_enable(hw);
1423         ret = clk_pll_wait_for_lock(pll);
1424
1425         if (ret < 0)
1426                 goto out;
1427
1428         val = pll_readl(PLLE_SS_CTRL, pll);
1429         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1430         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1431         val |= PLLE_SS_COEFFICIENTS_VAL;
1432         pll_writel(val, PLLE_SS_CTRL, pll);
1433         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1434         pll_writel(val, PLLE_SS_CTRL, pll);
1435         udelay(1);
1436         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1437         pll_writel(val, PLLE_SS_CTRL, pll);
1438         udelay(1);
1439
1440         /* Enable hw control of xusb brick pll */
1441         val = pll_readl_misc(pll);
1442         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1443         pll_writel_misc(val, pll);
1444
1445         val = pll_readl(pll->params->aux_reg, pll);
1446         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1447         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1448         pll_writel(val, pll->params->aux_reg, pll);
1449         udelay(1);
1450         val |= PLLE_AUX_SEQ_ENABLE;
1451         pll_writel(val, pll->params->aux_reg, pll);
1452
1453         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1454         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1455                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1456         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1457                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1458         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1459         udelay(1);
1460         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1461         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1462
1463         /* Enable hw control of SATA pll */
1464         val = pll_readl(SATA_PLL_CFG0, pll);
1465         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1466         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1467         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1468         pll_writel(val, SATA_PLL_CFG0, pll);
1469
1470         udelay(1);
1471
1472         val = pll_readl(SATA_PLL_CFG0, pll);
1473         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1474         pll_writel(val, SATA_PLL_CFG0, pll);
1475
1476 out:
1477         if (pll->lock)
1478                 spin_unlock_irqrestore(pll->lock, flags);
1479
1480         return ret;
1481 }
1482
1483 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1484 {
1485         struct tegra_clk_pll *pll = to_clk_pll(hw);
1486         unsigned long flags = 0;
1487         u32 val;
1488
1489         if (pll->lock)
1490                 spin_lock_irqsave(pll->lock, flags);
1491
1492         _clk_pll_disable(hw);
1493
1494         val = pll_readl_misc(pll);
1495         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1496         pll_writel_misc(val, pll);
1497         udelay(1);
1498
1499         if (pll->lock)
1500                 spin_unlock_irqrestore(pll->lock, flags);
1501 }
1502 #endif
1503
1504 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1505                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1506                 spinlock_t *lock)
1507 {
1508         struct tegra_clk_pll *pll;
1509
1510         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1511         if (!pll)
1512                 return ERR_PTR(-ENOMEM);
1513
1514         pll->clk_base = clk_base;
1515         pll->pmc = pmc;
1516
1517         pll->params = pll_params;
1518         pll->lock = lock;
1519
1520         if (!pll_params->div_nmp)
1521                 pll_params->div_nmp = &default_nmp;
1522
1523         return pll;
1524 }
1525
1526 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1527                 const char *name, const char *parent_name, unsigned long flags,
1528                 const struct clk_ops *ops)
1529 {
1530         struct clk_init_data init;
1531
1532         init.name = name;
1533         init.ops = ops;
1534         init.flags = flags;
1535         init.parent_names = (parent_name ? &parent_name : NULL);
1536         init.num_parents = (parent_name ? 1 : 0);
1537
1538         /* Default to _calc_rate if unspecified */
1539         if (!pll->params->calc_rate) {
1540                 if (pll->params->flags & TEGRA_PLLM)
1541                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1542                 else
1543                         pll->params->calc_rate = _calc_rate;
1544         }
1545
1546         if (pll->params->set_defaults)
1547                 pll->params->set_defaults(pll);
1548
1549         /* Data in .init is copied by clk_register(), so stack variable OK */
1550         pll->hw.init = &init;
1551
1552         return clk_register(NULL, &pll->hw);
1553 }
1554
1555 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1556                 void __iomem *clk_base, void __iomem *pmc,
1557                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1558                 spinlock_t *lock)
1559 {
1560         struct tegra_clk_pll *pll;
1561         struct clk *clk;
1562
1563         pll_params->flags |= TEGRA_PLL_BYPASS;
1564
1565         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1566         if (IS_ERR(pll))
1567                 return ERR_CAST(pll);
1568
1569         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1570                                       &tegra_clk_pll_ops);
1571         if (IS_ERR(clk))
1572                 kfree(pll);
1573
1574         return clk;
1575 }
1576
1577 static struct div_nmp pll_e_nmp = {
1578         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1579         .divn_width = PLLE_BASE_DIVN_WIDTH,
1580         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1581         .divm_width = PLLE_BASE_DIVM_WIDTH,
1582         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1583         .divp_width = PLLE_BASE_DIVP_WIDTH,
1584 };
1585
1586 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1587                 void __iomem *clk_base, void __iomem *pmc,
1588                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1589                 spinlock_t *lock)
1590 {
1591         struct tegra_clk_pll *pll;
1592         struct clk *clk;
1593
1594         pll_params->flags |= TEGRA_PLL_BYPASS;
1595
1596         if (!pll_params->div_nmp)
1597                 pll_params->div_nmp = &pll_e_nmp;
1598
1599         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1600         if (IS_ERR(pll))
1601                 return ERR_CAST(pll);
1602
1603         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1604                                       &tegra_clk_plle_ops);
1605         if (IS_ERR(clk))
1606                 kfree(pll);
1607
1608         return clk;
1609 }
1610
1611 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1612         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1613         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1614         defined(CONFIG_ARCH_TEGRA_210_SOC)
1615 static const struct clk_ops tegra_clk_pllxc_ops = {
1616         .is_enabled = clk_pll_is_enabled,
1617         .enable = clk_pll_enable,
1618         .disable = clk_pll_disable,
1619         .recalc_rate = clk_pll_recalc_rate,
1620         .round_rate = clk_pll_ramp_round_rate,
1621         .set_rate = clk_pllxc_set_rate,
1622 };
1623
1624 static const struct clk_ops tegra_clk_pllc_ops = {
1625         .is_enabled = clk_pll_is_enabled,
1626         .enable = clk_pllc_enable,
1627         .disable = clk_pllc_disable,
1628         .recalc_rate = clk_pll_recalc_rate,
1629         .round_rate = clk_pll_ramp_round_rate,
1630         .set_rate = clk_pllc_set_rate,
1631 };
1632
1633 static const struct clk_ops tegra_clk_pllre_ops = {
1634         .is_enabled = clk_pll_is_enabled,
1635         .enable = clk_pll_enable,
1636         .disable = clk_pll_disable,
1637         .recalc_rate = clk_pllre_recalc_rate,
1638         .round_rate = clk_pllre_round_rate,
1639         .set_rate = clk_pllre_set_rate,
1640 };
1641
1642 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1643         .is_enabled =  clk_pll_is_enabled,
1644         .enable = clk_plle_tegra114_enable,
1645         .disable = clk_plle_tegra114_disable,
1646         .recalc_rate = clk_pll_recalc_rate,
1647 };
1648
1649
1650 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1651                           void __iomem *clk_base, void __iomem *pmc,
1652                           unsigned long flags,
1653                           struct tegra_clk_pll_params *pll_params,
1654                           spinlock_t *lock)
1655 {
1656         struct tegra_clk_pll *pll;
1657         struct clk *clk, *parent;
1658         unsigned long parent_rate;
1659         u32 val, val_iddq;
1660
1661         parent = __clk_lookup(parent_name);
1662         if (!parent) {
1663                 WARN(1, "parent clk %s of %s must be registered first\n",
1664                         parent_name, name);
1665                 return ERR_PTR(-EINVAL);
1666         }
1667
1668         if (!pll_params->pdiv_tohw)
1669                 return ERR_PTR(-EINVAL);
1670
1671         parent_rate = clk_get_rate(parent);
1672
1673         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1674
1675         if (pll_params->adjust_vco)
1676                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1677                                                              parent_rate);
1678
1679         /*
1680          * If the pll has a set_defaults callback, it will take care of
1681          * configuring dynamic ramping and setting IDDQ in that path.
1682          */
1683         if (!pll_params->set_defaults) {
1684                 int err;
1685
1686                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1687                 if (err)
1688                         return ERR_PTR(err);
1689
1690                 val = readl_relaxed(clk_base + pll_params->base_reg);
1691                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1692
1693                 if (val & PLL_BASE_ENABLE)
1694                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1695                 else {
1696                         val_iddq |= BIT(pll_params->iddq_bit_idx);
1697                         writel_relaxed(val_iddq,
1698                                        clk_base + pll_params->iddq_reg);
1699                 }
1700         }
1701
1702         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1703         if (IS_ERR(pll))
1704                 return ERR_CAST(pll);
1705
1706         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1707                                       &tegra_clk_pllxc_ops);
1708         if (IS_ERR(clk))
1709                 kfree(pll);
1710
1711         return clk;
1712 }
1713
1714 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1715                           void __iomem *clk_base, void __iomem *pmc,
1716                           unsigned long flags,
1717                           struct tegra_clk_pll_params *pll_params,
1718                           spinlock_t *lock, unsigned long parent_rate)
1719 {
1720         u32 val;
1721         struct tegra_clk_pll *pll;
1722         struct clk *clk;
1723
1724         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1725
1726         if (pll_params->adjust_vco)
1727                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1728                                                              parent_rate);
1729
1730         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1731         if (IS_ERR(pll))
1732                 return ERR_CAST(pll);
1733
1734         /* program minimum rate by default */
1735
1736         val = pll_readl_base(pll);
1737         if (val & PLL_BASE_ENABLE)
1738                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
1739                                 BIT(pll_params->iddq_bit_idx));
1740         else {
1741                 int m;
1742
1743                 m = _pll_fixed_mdiv(pll_params, parent_rate);
1744                 val = m << divm_shift(pll);
1745                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
1746                 pll_writel_base(val, pll);
1747         }
1748
1749         /* disable lock override */
1750
1751         val = pll_readl_misc(pll);
1752         val &= ~BIT(29);
1753         pll_writel_misc(val, pll);
1754
1755         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1756                                       &tegra_clk_pllre_ops);
1757         if (IS_ERR(clk))
1758                 kfree(pll);
1759
1760         return clk;
1761 }
1762
1763 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1764                           void __iomem *clk_base, void __iomem *pmc,
1765                           unsigned long flags,
1766                           struct tegra_clk_pll_params *pll_params,
1767                           spinlock_t *lock)
1768 {
1769         struct tegra_clk_pll *pll;
1770         struct clk *clk, *parent;
1771         unsigned long parent_rate;
1772
1773         if (!pll_params->pdiv_tohw)
1774                 return ERR_PTR(-EINVAL);
1775
1776         parent = __clk_lookup(parent_name);
1777         if (!parent) {
1778                 WARN(1, "parent clk %s of %s must be registered first\n",
1779                         parent_name, name);
1780                 return ERR_PTR(-EINVAL);
1781         }
1782
1783         parent_rate = clk_get_rate(parent);
1784
1785         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1786
1787         if (pll_params->adjust_vco)
1788                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1789                                                              parent_rate);
1790
1791         pll_params->flags |= TEGRA_PLL_BYPASS;
1792         pll_params->flags |= TEGRA_PLLM;
1793         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1794         if (IS_ERR(pll))
1795                 return ERR_CAST(pll);
1796
1797         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1798                                       &tegra_clk_pll_ops);
1799         if (IS_ERR(clk))
1800                 kfree(pll);
1801
1802         return clk;
1803 }
1804
1805 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1806                           void __iomem *clk_base, void __iomem *pmc,
1807                           unsigned long flags,
1808                           struct tegra_clk_pll_params *pll_params,
1809                           spinlock_t *lock)
1810 {
1811         struct clk *parent, *clk;
1812         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
1813         struct tegra_clk_pll *pll;
1814         struct tegra_clk_pll_freq_table cfg;
1815         unsigned long parent_rate;
1816
1817         if (!p_tohw)
1818                 return ERR_PTR(-EINVAL);
1819
1820         parent = __clk_lookup(parent_name);
1821         if (!parent) {
1822                 WARN(1, "parent clk %s of %s must be registered first\n",
1823                         parent_name, name);
1824                 return ERR_PTR(-EINVAL);
1825         }
1826
1827         parent_rate = clk_get_rate(parent);
1828
1829         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1830
1831         pll_params->flags |= TEGRA_PLL_BYPASS;
1832         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1833         if (IS_ERR(pll))
1834                 return ERR_CAST(pll);
1835
1836         /*
1837          * Most of PLLC register fields are shadowed, and can not be read
1838          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
1839          * Initialize PLL to default state: disabled, reset; shadow registers
1840          * loaded with default parameters; dividers are preset for half of
1841          * minimum VCO rate (the latter assured that shadowed divider settings
1842          * are within supported range).
1843          */
1844
1845         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1846         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1847
1848         while (p_tohw->pdiv) {
1849                 if (p_tohw->pdiv == 2) {
1850                         cfg.p = p_tohw->hw_val;
1851                         break;
1852                 }
1853                 p_tohw++;
1854         }
1855
1856         if (!p_tohw->pdiv) {
1857                 WARN_ON(1);
1858                 return ERR_PTR(-EINVAL);
1859         }
1860
1861         pll_writel_base(0, pll);
1862         _update_pll_mnp(pll, &cfg);
1863
1864         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
1865         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
1866         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
1867         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
1868
1869         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1870
1871         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1872                                       &tegra_clk_pllc_ops);
1873         if (IS_ERR(clk))
1874                 kfree(pll);
1875
1876         return clk;
1877 }
1878
1879 struct clk *tegra_clk_register_plle_tegra114(const char *name,
1880                                 const char *parent_name,
1881                                 void __iomem *clk_base, unsigned long flags,
1882                                 struct tegra_clk_pll_params *pll_params,
1883                                 spinlock_t *lock)
1884 {
1885         struct tegra_clk_pll *pll;
1886         struct clk *clk;
1887         u32 val, val_aux;
1888
1889         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1890         if (IS_ERR(pll))
1891                 return ERR_CAST(pll);
1892
1893         /* ensure parent is set to pll_re_vco */
1894
1895         val = pll_readl_base(pll);
1896         val_aux = pll_readl(pll_params->aux_reg, pll);
1897
1898         if (val & PLL_BASE_ENABLE) {
1899                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1900                         (val_aux & PLLE_AUX_PLLP_SEL))
1901                         WARN(1, "pll_e enabled with unsupported parent %s\n",
1902                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1903                                         "pll_re_vco");
1904         } else {
1905                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1906                 pll_writel(val_aux, pll_params->aux_reg, pll);
1907         }
1908
1909         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1910                                       &tegra_clk_plle_tegra114_ops);
1911         if (IS_ERR(clk))
1912                 kfree(pll);
1913
1914         return clk;
1915 }
1916 #endif
1917
1918 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1919 static const struct clk_ops tegra_clk_pllss_ops = {
1920         .is_enabled = clk_pll_is_enabled,
1921         .enable = clk_pll_enable,
1922         .disable = clk_pll_disable,
1923         .recalc_rate = clk_pll_recalc_rate,
1924         .round_rate = clk_pll_ramp_round_rate,
1925         .set_rate = clk_pllxc_set_rate,
1926 };
1927
1928 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1929                                 void __iomem *clk_base, unsigned long flags,
1930                                 struct tegra_clk_pll_params *pll_params,
1931                                 spinlock_t *lock)
1932 {
1933         struct tegra_clk_pll *pll;
1934         struct clk *clk, *parent;
1935         struct tegra_clk_pll_freq_table cfg;
1936         unsigned long parent_rate;
1937         u32 val, val_iddq;
1938         int i;
1939
1940         if (!pll_params->div_nmp)
1941                 return ERR_PTR(-EINVAL);
1942
1943         parent = __clk_lookup(parent_name);
1944         if (!parent) {
1945                 WARN(1, "parent clk %s of %s must be registered first\n",
1946                         parent_name, name);
1947                 return ERR_PTR(-EINVAL);
1948         }
1949
1950         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1951         if (IS_ERR(pll))
1952                 return ERR_CAST(pll);
1953
1954         val = pll_readl_base(pll);
1955         val &= ~PLLSS_REF_SRC_SEL_MASK;
1956         pll_writel_base(val, pll);
1957
1958         parent_rate = clk_get_rate(parent);
1959
1960         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1961
1962         /* initialize PLL to minimum rate */
1963
1964         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1965         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1966
1967         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1968                 ;
1969         if (!i) {
1970                 kfree(pll);
1971                 return ERR_PTR(-EINVAL);
1972         }
1973
1974         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1975
1976         _update_pll_mnp(pll, &cfg);
1977
1978         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1979         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1980         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1981         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1982
1983         val = pll_readl_base(pll);
1984         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1985         if (val & PLL_BASE_ENABLE) {
1986                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
1987                         WARN(1, "%s is on but IDDQ set\n", name);
1988                         kfree(pll);
1989                         return ERR_PTR(-EINVAL);
1990                 }
1991         } else {
1992                 val_iddq |= BIT(pll_params->iddq_bit_idx);
1993                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1994         }
1995
1996         val &= ~PLLSS_LOCK_OVERRIDE;
1997         pll_writel_base(val, pll);
1998
1999         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2000                                         &tegra_clk_pllss_ops);
2001
2002         if (IS_ERR(clk))
2003                 kfree(pll);
2004
2005         return clk;
2006 }
2007 #endif
2008
2009 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2010 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2011 {
2012         struct tegra_clk_pll *pll = to_clk_pll(hw);
2013         struct tegra_clk_pll_freq_table sel;
2014         u32 val;
2015         int ret;
2016         unsigned long flags = 0;
2017         unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
2018
2019         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2020                 return -EINVAL;
2021
2022         if (pll->lock)
2023                 spin_lock_irqsave(pll->lock, flags);
2024
2025         val = pll_readl_base(pll);
2026         val &= ~BIT(30); /* Disable lock override */
2027         pll_writel_base(val, pll);
2028
2029         val = pll_readl(pll->params->aux_reg, pll);
2030         val |= PLLE_AUX_ENABLE_SWCTL;
2031         val &= ~PLLE_AUX_SEQ_ENABLE;
2032         pll_writel(val, pll->params->aux_reg, pll);
2033         udelay(1);
2034
2035         val = pll_readl_misc(pll);
2036         val |= PLLE_MISC_LOCK_ENABLE;
2037         val |= PLLE_MISC_IDDQ_SW_CTRL;
2038         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2039         val |= PLLE_MISC_PLLE_PTS;
2040         val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
2041         pll_writel_misc(val, pll);
2042         udelay(5);
2043
2044         val = pll_readl(PLLE_SS_CTRL, pll);
2045         val |= PLLE_SS_DISABLE;
2046         pll_writel(val, PLLE_SS_CTRL, pll);
2047
2048         val = pll_readl_base(pll);
2049         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2050                  divm_mask_shifted(pll));
2051         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2052         val |= sel.m << divm_shift(pll);
2053         val |= sel.n << divn_shift(pll);
2054         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2055         pll_writel_base(val, pll);
2056         udelay(1);
2057
2058         val = pll_readl_base(pll);
2059         val |= PLLE_BASE_ENABLE;
2060         pll_writel_base(val, pll);
2061
2062         ret = clk_pll_wait_for_lock(pll);
2063
2064         if (ret < 0)
2065                 goto out;
2066
2067         val = pll_readl(PLLE_SS_CTRL, pll);
2068         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2069         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2070         val |= PLLE_SS_COEFFICIENTS_VAL;
2071         pll_writel(val, PLLE_SS_CTRL, pll);
2072         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2073         pll_writel(val, PLLE_SS_CTRL, pll);
2074         udelay(1);
2075         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2076         pll_writel(val, PLLE_SS_CTRL, pll);
2077         udelay(1);
2078
2079         val = pll_readl_misc(pll);
2080         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2081         pll_writel_misc(val, pll);
2082
2083         val = pll_readl(pll->params->aux_reg, pll);
2084         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2085         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2086         pll_writel(val, pll->params->aux_reg, pll);
2087         udelay(1);
2088         val |= PLLE_AUX_SEQ_ENABLE;
2089         pll_writel(val, pll->params->aux_reg, pll);
2090
2091 out:
2092         if (pll->lock)
2093                 spin_unlock_irqrestore(pll->lock, flags);
2094
2095         return ret;
2096 }
2097
2098 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2099 {
2100         struct tegra_clk_pll *pll = to_clk_pll(hw);
2101         unsigned long flags = 0;
2102         u32 val;
2103
2104         if (pll->lock)
2105                 spin_lock_irqsave(pll->lock, flags);
2106
2107         val = pll_readl_base(pll);
2108         val &= ~PLLE_BASE_ENABLE;
2109         pll_writel_base(val, pll);
2110
2111         val = pll_readl_misc(pll);
2112         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2113         pll_writel_misc(val, pll);
2114         udelay(1);
2115
2116         if (pll->lock)
2117                 spin_unlock_irqrestore(pll->lock, flags);
2118 }
2119
2120 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2121 {
2122         struct tegra_clk_pll *pll = to_clk_pll(hw);
2123         u32 val;
2124
2125         val = pll_readl_base(pll);
2126
2127         return val & PLLE_BASE_ENABLE ? 1 : 0;
2128 }
2129
2130 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2131         .is_enabled =  clk_plle_tegra210_is_enabled,
2132         .enable = clk_plle_tegra210_enable,
2133         .disable = clk_plle_tegra210_disable,
2134         .recalc_rate = clk_pll_recalc_rate,
2135 };
2136
2137 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2138                                 const char *parent_name,
2139                                 void __iomem *clk_base, unsigned long flags,
2140                                 struct tegra_clk_pll_params *pll_params,
2141                                 spinlock_t *lock)
2142 {
2143         struct tegra_clk_pll *pll;
2144         struct clk *clk;
2145         u32 val, val_aux;
2146
2147         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2148         if (IS_ERR(pll))
2149                 return ERR_CAST(pll);
2150
2151         /* ensure parent is set to pll_re_vco */
2152
2153         val = pll_readl_base(pll);
2154         val_aux = pll_readl(pll_params->aux_reg, pll);
2155
2156         if (val & PLLE_BASE_ENABLE) {
2157                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2158                         (val_aux & PLLE_AUX_PLLP_SEL))
2159                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2160                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2161                                         "pll_re_vco");
2162         } else {
2163                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2164                 pll_writel(val_aux, pll_params->aux_reg, pll);
2165         }
2166
2167         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2168                                       &tegra_clk_plle_tegra210_ops);
2169         if (IS_ERR(clk))
2170                 kfree(pll);
2171
2172         return clk;
2173 }
2174
2175 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2176                         const char *parent_name, void __iomem *clk_base,
2177                         void __iomem *pmc, unsigned long flags,
2178                         struct tegra_clk_pll_params *pll_params,
2179                         spinlock_t *lock)
2180 {
2181         struct clk *parent, *clk;
2182         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2183         struct tegra_clk_pll *pll;
2184         unsigned long parent_rate;
2185
2186         if (!p_tohw)
2187                 return ERR_PTR(-EINVAL);
2188
2189         parent = __clk_lookup(parent_name);
2190         if (!parent) {
2191                 WARN(1, "parent clk %s of %s must be registered first\n",
2192                         name, parent_name);
2193                 return ERR_PTR(-EINVAL);
2194         }
2195
2196         parent_rate = clk_get_rate(parent);
2197
2198         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2199
2200         if (pll_params->adjust_vco)
2201                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2202                                                              parent_rate);
2203
2204         pll_params->flags |= TEGRA_PLL_BYPASS;
2205         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2206         if (IS_ERR(pll))
2207                 return ERR_CAST(pll);
2208
2209         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2210                                       &tegra_clk_pll_ops);
2211         if (IS_ERR(clk))
2212                 kfree(pll);
2213
2214         return clk;
2215 }
2216
2217 struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2218                         const char *parent_name, void __iomem *clk_base,
2219                         void __iomem *pmc, unsigned long flags,
2220                         struct tegra_clk_pll_params *pll_params,
2221                         spinlock_t *lock)
2222 {
2223         struct tegra_clk_pll *pll;
2224         struct clk *clk, *parent;
2225         unsigned long parent_rate;
2226
2227         parent = __clk_lookup(parent_name);
2228         if (!parent) {
2229                 WARN(1, "parent clk %s of %s must be registered first\n",
2230                         name, parent_name);
2231                 return ERR_PTR(-EINVAL);
2232         }
2233
2234         if (!pll_params->pdiv_tohw)
2235                 return ERR_PTR(-EINVAL);
2236
2237         parent_rate = clk_get_rate(parent);
2238
2239         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2240
2241         if (pll_params->adjust_vco)
2242                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2243                                                              parent_rate);
2244
2245         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2246         if (IS_ERR(pll))
2247                 return ERR_CAST(pll);
2248
2249         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2250                                       &tegra_clk_pll_ops);
2251         if (IS_ERR(clk))
2252                 kfree(pll);
2253
2254         return clk;
2255 }
2256
2257 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2258                                 const char *parent_name, void __iomem *clk_base,
2259                                 unsigned long flags,
2260                                 struct tegra_clk_pll_params *pll_params,
2261                                 spinlock_t *lock)
2262 {
2263         struct tegra_clk_pll *pll;
2264         struct clk *clk, *parent;
2265         struct tegra_clk_pll_freq_table cfg;
2266         unsigned long parent_rate;
2267         u32 val;
2268         int i;
2269
2270         if (!pll_params->div_nmp)
2271                 return ERR_PTR(-EINVAL);
2272
2273         parent = __clk_lookup(parent_name);
2274         if (!parent) {
2275                 WARN(1, "parent clk %s of %s must be registered first\n",
2276                         name, parent_name);
2277                 return ERR_PTR(-EINVAL);
2278         }
2279
2280         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2281         if (IS_ERR(pll))
2282                 return ERR_CAST(pll);
2283
2284         val = pll_readl_base(pll);
2285         val &= ~PLLSS_REF_SRC_SEL_MASK;
2286         pll_writel_base(val, pll);
2287
2288         parent_rate = clk_get_rate(parent);
2289
2290         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2291
2292         if (pll_params->adjust_vco)
2293                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2294                                                              parent_rate);
2295
2296         /* initialize PLL to minimum rate */
2297
2298         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2299         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2300
2301         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2302                 ;
2303         if (!i) {
2304                 kfree(pll);
2305                 return ERR_PTR(-EINVAL);
2306         }
2307
2308         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2309
2310         _update_pll_mnp(pll, &cfg);
2311
2312         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2313
2314         val = pll_readl_base(pll);
2315         if (val & PLL_BASE_ENABLE) {
2316                 if (val & BIT(pll_params->iddq_bit_idx)) {
2317                         WARN(1, "%s is on but IDDQ set\n", name);
2318                         kfree(pll);
2319                         return ERR_PTR(-EINVAL);
2320                 }
2321         } else
2322                 val |= BIT(pll_params->iddq_bit_idx);
2323
2324         val &= ~PLLSS_LOCK_OVERRIDE;
2325         pll_writel_base(val, pll);
2326
2327         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2328                                         &tegra_clk_pll_ops);
2329
2330         if (IS_ERR(clk))
2331                 kfree(pll);
2332
2333         return clk;
2334 }
2335
2336 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2337                           void __iomem *clk_base, void __iomem *pmc,
2338                           unsigned long flags,
2339                           struct tegra_clk_pll_params *pll_params,
2340                           spinlock_t *lock)
2341 {
2342         struct tegra_clk_pll *pll;
2343         struct clk *clk, *parent;
2344         unsigned long parent_rate;
2345
2346         if (!pll_params->pdiv_tohw)
2347                 return ERR_PTR(-EINVAL);
2348
2349         parent = __clk_lookup(parent_name);
2350         if (!parent) {
2351                 WARN(1, "parent clk %s of %s must be registered first\n",
2352                         parent_name, name);
2353                 return ERR_PTR(-EINVAL);
2354         }
2355
2356         parent_rate = clk_get_rate(parent);
2357
2358         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2359
2360         if (pll_params->adjust_vco)
2361                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2362                                                              parent_rate);
2363
2364         pll_params->flags |= TEGRA_PLL_BYPASS;
2365         pll_params->flags |= TEGRA_PLLMB;
2366         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2367         if (IS_ERR(pll))
2368                 return ERR_CAST(pll);
2369
2370         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2371                                       &tegra_clk_pll_ops);
2372         if (IS_ERR(clk))
2373                 kfree(pll);
2374
2375         return clk;
2376 }
2377 #endif