drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_MASK 0xf
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 6
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68 #define PLLE_BASE_ENABLE BIT(31)
  69
  70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  73 #define PLLE_MISC_READY BIT(15)
  74 #define PLLE_MISC_SETUP_EX_SHIFT 2
  75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  77                               PLLE_MISC_SETUP_EX_MASK)
  78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  79
  80 #define PLLE_SS_CTRL 0x68
  81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  84 #define PLLE_SS_CNTL_CENTER BIT(14)
  85 #define PLLE_SS_CNTL_INVERT BIT(15)
  86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  87                                 PLLE_SS_CNTL_SSC_BYP)
  88 #define PLLE_SS_MAX_MASK 0x1ff
  89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  91 #define PLLE_SS_INC_MASK (0xff << 16)
  92 #define PLLE_SS_INC_VAL (0x1 << 16)
  93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  96 #define PLLE_SS_COEFFICIENTS_MASK \
  97         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  99         (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
 100          PLLE_SS_INCINTRV_VAL_TEGRA114)
 101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
 102         (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
 103          PLLE_SS_INCINTRV_VAL_TEGRA210)
 104
 105 #define PLLE_AUX_PLLP_SEL       BIT(2)
 106 #define PLLE_AUX_USE_LOCKDET    BIT(3)
 107 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 108 #define PLLE_AUX_SS_SWCTL       BIT(6)
 109 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 111 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 113
 114 #define XUSBIO_PLL_CFG0         0x51c
 115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 120
 121 #define SATA_PLL_CFG0           0x490
 122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 124 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 125 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 126
 127 #define PLLE_MISC_PLLE_PTS      BIT(8)
 128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 129 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 131 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 132 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 133 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 134
 135 #define PLLCX_MISC_STROBE       BIT(31)
 136 #define PLLCX_MISC_RESET        BIT(30)
 137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 141 #define PLLCX_MISC_ALPHA_SHIFT 18
 142 #define PLLCX_MISC_DIV_LOW_RANGE \
 143                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 144                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 145 #define PLLCX_MISC_DIV_HIGH_RANGE \
 146                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 147                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 148 #define PLLCX_MISC_COEF_LOW_RANGE \
 149                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 150 #define PLLCX_MISC_KA_SHIFT 2
 151 #define PLLCX_MISC_KB_SHIFT 9
 152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 153                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 154                             PLLCX_MISC_DIV_LOW_RANGE | \
 155                             PLLCX_MISC_RESET)
 156 #define PLLCX_MISC1_DEFAULT 0x000d2308
 157 #define PLLCX_MISC2_DEFAULT 0x30211200
 158 #define PLLCX_MISC3_DEFAULT 0x200
 159
 160 #define PMC_SATA_PWRGT 0x1ac
 161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 163
 164 #define PLLSS_MISC_KCP          0
 165 #define PLLSS_MISC_KVCO         0
 166 #define PLLSS_MISC_SETUP        0
 167 #define PLLSS_EN_SDM            0
 168 #define PLLSS_EN_SSC            0
 169 #define PLLSS_EN_DITHER2        0
 170 #define PLLSS_EN_DITHER         1
 171 #define PLLSS_SDM_RESET         0
 172 #define PLLSS_CLAMP             0
 173 #define PLLSS_SDM_SSC_MAX       0
 174 #define PLLSS_SDM_SSC_MIN       0
 175 #define PLLSS_SDM_SSC_STEP      0
 176 #define PLLSS_SDM_DIN           0
 177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 178                             (PLLSS_MISC_KVCO << 24) | \
 179                             PLLSS_MISC_SETUP)
 180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 181                            (PLLSS_EN_SSC << 30) | \
 182                            (PLLSS_EN_DITHER2 << 29) | \
 183                            (PLLSS_EN_DITHER << 28) | \
 184                            (PLLSS_SDM_RESET) << 27 | \
 185                            (PLLSS_CLAMP << 22))
 186 #define PLLSS_CTRL1_DEFAULT \
 187                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 188 #define PLLSS_CTRL2_DEFAULT \
 189                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 190 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 191 #define PLLSS_REF_SRC_SEL_SHIFT 25
 192 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 193
 194 #define UTMIP_PLL_CFG1 0x484
 195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 202
 203 #define UTMIP_PLL_CFG2 0x488
 204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 215
 216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
 217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 225
 226 #define PLLU_HW_PWRDN_CFG0 0x530
 227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 233
 234 #define XUSB_PLL_CFG0 0x534
 235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 237
 238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
 239 #define PLLU_BASE_OVERRIDE BIT(24)
 240
 241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 247
 248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 254
 255 #define mask(w) ((1 << (w)) - 1)
 256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 259                       mask(p->params->div_nmp->divp_width))
 260 #define sdm_din_mask(p) p->params->sdm_din_mask
 261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 262
 263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 266
 267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 270
 271 #define divm_max(p) (divm_mask(p))
 272 #define divn_max(p) (divn_mask(p))
 273 #define divp_max(p) (1 << (divp_mask(p)))
 274
 275 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 276 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 277
 278 static struct div_nmp default_nmp = {
 279         .divn_shift = PLL_BASE_DIVN_SHIFT,
 280         .divn_width = PLL_BASE_DIVN_WIDTH,
 281         .divm_shift = PLL_BASE_DIVM_SHIFT,
 282         .divm_width = PLL_BASE_DIVM_WIDTH,
 283         .divp_shift = PLL_BASE_DIVP_SHIFT,
 284         .divp_width = PLL_BASE_DIVP_WIDTH,
 285 };
 286
 287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 288 {
 289         u32 val;
 290
 291         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 292                 return;
 293
 294         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 295                 return;
 296
 297         val = pll_readl_misc(pll);
 298         val |= BIT(pll->params->lock_enable_bit_idx);
 299         pll_writel_misc(val, pll);
 300 }
 301
 302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 303 {
 304         int i;
 305         u32 val, lock_mask;
 306         void __iomem *lock_addr;
 307
 308         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 309                 udelay(pll->params->lock_delay);
 310                 return 0;
 311         }
 312
 313         lock_addr = pll->clk_base;
 314         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 315                 lock_addr += pll->params->misc_reg;
 316         else
 317                 lock_addr += pll->params->base_reg;
 318
 319         lock_mask = pll->params->lock_mask;
 320
 321         for (i = 0; i < pll->params->lock_delay; i++) {
 322                 val = readl_relaxed(lock_addr);
 323                 if ((val & lock_mask) == lock_mask) {
 324                         udelay(PLL_POST_LOCK_DELAY);
 325                         return 0;
 326                 }
 327                 udelay(2); /* timeout = 2 * lock time */
 328         }
 329
 330         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 331                clk_hw_get_name(&pll->hw));
 332
 333         return -1;
 334 }
 335
 336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 337 {
 338         return clk_pll_wait_for_lock(pll);
 339 }
 340
 341 static int clk_pll_is_enabled(struct clk_hw *hw)
 342 {
 343         struct tegra_clk_pll *pll = to_clk_pll(hw);
 344         u32 val;
 345
 346         if (pll->params->flags & TEGRA_PLLM) {
 347                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 348                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 349                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 350         }
 351
 352         val = pll_readl_base(pll);
 353
 354         return val & PLL_BASE_ENABLE ? 1 : 0;
 355 }
 356
 357 static void _clk_pll_enable(struct clk_hw *hw)
 358 {
 359         struct tegra_clk_pll *pll = to_clk_pll(hw);
 360         u32 val;
 361
 362         if (pll->params->iddq_reg) {
 363                 val = pll_readl(pll->params->iddq_reg, pll);
 364                 val &= ~BIT(pll->params->iddq_bit_idx);
 365                 pll_writel(val, pll->params->iddq_reg, pll);
 366                 udelay(2);
 367         }
 368
 369         if (pll->params->reset_reg) {
 370                 val = pll_readl(pll->params->reset_reg, pll);
 371                 val &= ~BIT(pll->params->reset_bit_idx);
 372                 pll_writel(val, pll->params->reset_reg, pll);
 373         }
 374
 375         clk_pll_enable_lock(pll);
 376
 377         val = pll_readl_base(pll);
 378         if (pll->params->flags & TEGRA_PLL_BYPASS)
 379                 val &= ~PLL_BASE_BYPASS;
 380         val |= PLL_BASE_ENABLE;
 381         pll_writel_base(val, pll);
 382
 383         if (pll->params->flags & TEGRA_PLLM) {
 384                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 385                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 386                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 387         }
 388 }
 389
 390 static void _clk_pll_disable(struct clk_hw *hw)
 391 {
 392         struct tegra_clk_pll *pll = to_clk_pll(hw);
 393         u32 val;
 394
 395         val = pll_readl_base(pll);
 396         if (pll->params->flags & TEGRA_PLL_BYPASS)
 397                 val &= ~PLL_BASE_BYPASS;
 398         val &= ~PLL_BASE_ENABLE;
 399         pll_writel_base(val, pll);
 400
 401         if (pll->params->flags & TEGRA_PLLM) {
 402                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 403                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 404                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 405         }
 406
 407         if (pll->params->reset_reg) {
 408                 val = pll_readl(pll->params->reset_reg, pll);
 409                 val |= BIT(pll->params->reset_bit_idx);
 410                 pll_writel(val, pll->params->reset_reg, pll);
 411         }
 412
 413         if (pll->params->iddq_reg) {
 414                 val = pll_readl(pll->params->iddq_reg, pll);
 415                 val |= BIT(pll->params->iddq_bit_idx);
 416                 pll_writel(val, pll->params->iddq_reg, pll);
 417                 udelay(2);
 418         }
 419 }
 420
 421 static int clk_pll_enable(struct clk_hw *hw)
 422 {
 423         struct tegra_clk_pll *pll = to_clk_pll(hw);
 424         unsigned long flags = 0;
 425         int ret;
 426
 427         if (pll->lock)
 428                 spin_lock_irqsave(pll->lock, flags);
 429
 430         _clk_pll_enable(hw);
 431
 432         ret = clk_pll_wait_for_lock(pll);
 433
 434         if (pll->lock)
 435                 spin_unlock_irqrestore(pll->lock, flags);
 436
 437         return ret;
 438 }
 439
 440 static void clk_pll_disable(struct clk_hw *hw)
 441 {
 442         struct tegra_clk_pll *pll = to_clk_pll(hw);
 443         unsigned long flags = 0;
 444
 445         if (pll->lock)
 446                 spin_lock_irqsave(pll->lock, flags);
 447
 448         _clk_pll_disable(hw);
 449
 450         if (pll->lock)
 451                 spin_unlock_irqrestore(pll->lock, flags);
 452 }
 453
 454 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 455 {
 456         struct tegra_clk_pll *pll = to_clk_pll(hw);
 457         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 458
 459         if (p_tohw) {
 460                 while (p_tohw->pdiv) {
 461                         if (p_div <= p_tohw->pdiv)
 462                                 return p_tohw->hw_val;
 463                         p_tohw++;
 464                 }
 465                 return -EINVAL;
 466         }
 467         return -EINVAL;
 468 }
 469
 470 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 471 {
 472         return _p_div_to_hw(&pll->hw, p_div);
 473 }
 474
 475 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 476 {
 477         struct tegra_clk_pll *pll = to_clk_pll(hw);
 478         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 479
 480         if (p_tohw) {
 481                 while (p_tohw->pdiv) {
 482                         if (p_div_hw == p_tohw->hw_val)
 483                                 return p_tohw->pdiv;
 484                         p_tohw++;
 485                 }
 486                 return -EINVAL;
 487         }
 488
 489         return 1 << p_div_hw;
 490 }
 491
 492 static int _get_table_rate(struct clk_hw *hw,
 493                            struct tegra_clk_pll_freq_table *cfg,
 494                            unsigned long rate, unsigned long parent_rate)
 495 {
 496         struct tegra_clk_pll *pll = to_clk_pll(hw);
 497         struct tegra_clk_pll_freq_table *sel;
 498         int p;
 499
 500         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 501                 if (sel->input_rate == parent_rate &&
 502                     sel->output_rate == rate)
 503                         break;
 504
 505         if (sel->input_rate == 0)
 506                 return -EINVAL;
 507
 508         if (pll->params->pdiv_tohw) {
 509                 p = _p_div_to_hw(hw, sel->p);
 510                 if (p < 0)
 511                         return p;
 512         } else {
 513                 p = ilog2(sel->p);
 514         }
 515
 516         cfg->input_rate = sel->input_rate;
 517         cfg->output_rate = sel->output_rate;
 518         cfg->m = sel->m;
 519         cfg->n = sel->n;
 520         cfg->p = p;
 521         cfg->cpcon = sel->cpcon;
 522         cfg->sdm_data = sel->sdm_data;
 523
 524         return 0;
 525 }
 526
 527 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 528                       unsigned long rate, unsigned long parent_rate)
 529 {
 530         struct tegra_clk_pll *pll = to_clk_pll(hw);
 531         unsigned long cfreq;
 532         u32 p_div = 0;
 533         int ret;
 534
 535         switch (parent_rate) {
 536         case 12000000:
 537         case 26000000:
 538                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 539                 break;
 540         case 13000000:
 541                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 542                 break;
 543         case 16800000:
 544         case 19200000:
 545                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 546                 break;
 547         case 9600000:
 548         case 28800000:
 549                 /*
 550                  * PLL_P_OUT1 rate is not listed in PLLA table
 551                  */
 552                 cfreq = parent_rate / (parent_rate / 1000000);
 553                 break;
 554         default:
 555                 pr_err("%s Unexpected reference rate %lu\n",
 556                        __func__, parent_rate);
 557                 BUG();
 558         }
 559
 560         /* Raise VCO to guarantee 0.5% accuracy */
 561         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 562              cfg->output_rate <<= 1)
 563                 p_div++;
 564
 565         cfg->m = parent_rate / cfreq;
 566         cfg->n = cfg->output_rate / cfreq;
 567         cfg->cpcon = OUT_OF_TABLE_CPCON;
 568
 569         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 570             (1 << p_div) > divp_max(pll)
 571             || cfg->output_rate > pll->params->vco_max) {
 572                 return -EINVAL;
 573         }
 574
 575         cfg->output_rate >>= p_div;
 576
 577         if (pll->params->pdiv_tohw) {
 578                 ret = _p_div_to_hw(hw, 1 << p_div);
 579                 if (ret < 0)
 580                         return ret;
 581                 else
 582                         cfg->p = ret;
 583         } else
 584                 cfg->p = p_div;
 585
 586         return 0;
 587 }
 588
 589 /*
 590  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 591  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 592  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 593  * to indicate that SDM is disabled.
 594  *
 595  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 596  */
 597 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 598                                  struct tegra_clk_pll_freq_table *cfg)
 599 {
 600         struct tegra_clk_pll *pll = to_clk_pll(hw);
 601         u32 val;
 602         bool enabled;
 603
 604         if (!pll->params->sdm_din_reg)
 605                 return;
 606
 607         if (cfg->sdm_data) {
 608                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 609                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 610                 pll_writel_sdm_din(val, pll);
 611         }
 612
 613         val = pll_readl_sdm_ctrl(pll);
 614         enabled = (val & sdm_en_mask(pll));
 615
 616         if (cfg->sdm_data == 0 && enabled)
 617                 val &= ~pll->params->sdm_ctrl_en_mask;
 618
 619         if (cfg->sdm_data != 0 && !enabled)
 620                 val |= pll->params->sdm_ctrl_en_mask;
 621
 622         pll_writel_sdm_ctrl(val, pll);
 623 }
 624
 625 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 626                             struct tegra_clk_pll_freq_table *cfg)
 627 {
 628         u32 val;
 629         struct tegra_clk_pll_params *params = pll->params;
 630         struct div_nmp *div_nmp = params->div_nmp;
 631
 632         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 633                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 634                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 635                 val = pll_override_readl(params->pmc_divp_reg, pll);
 636                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 637                 val |= cfg->p << div_nmp->override_divp_shift;
 638                 pll_override_writel(val, params->pmc_divp_reg, pll);
 639
 640                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 641                 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
 642                         ~(divn_mask(pll) << div_nmp->override_divn_shift);
 643                 val |= (cfg->m << div_nmp->override_divm_shift) |
 644                         (cfg->n << div_nmp->override_divn_shift);
 645                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 646         } else {
 647                 val = pll_readl_base(pll);
 648
 649                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 650                          divp_mask_shifted(pll));
 651
 652                 val |= (cfg->m << divm_shift(pll)) |
 653                        (cfg->n << divn_shift(pll)) |
 654                        (cfg->p << divp_shift(pll));
 655
 656                 pll_writel_base(val, pll);
 657
 658                 clk_pll_set_sdm_data(&pll->hw, cfg);
 659         }
 660 }
 661
 662 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 663                          struct tegra_clk_pll_freq_table *cfg)
 664 {
 665         u32 val;
 666         struct tegra_clk_pll_params *params = pll->params;
 667         struct div_nmp *div_nmp = params->div_nmp;
 668
 669         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 670                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 671                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 672                 val = pll_override_readl(params->pmc_divp_reg, pll);
 673                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 674
 675                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 676                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 677                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 678         }  else {
 679                 val = pll_readl_base(pll);
 680
 681                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 682                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 683                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 684
 685                 if (pll->params->sdm_din_reg) {
 686                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 687                                 val = pll_readl_sdm_din(pll);
 688                                 val &= sdm_din_mask(pll);
 689                                 cfg->sdm_data = sdin_din_to_data(val);
 690                         }
 691                 }
 692         }
 693 }
 694
 695 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 696                               struct tegra_clk_pll_freq_table *cfg,
 697                               unsigned long rate)
 698 {
 699         u32 val;
 700
 701         val = pll_readl_misc(pll);
 702
 703         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 704         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 705
 706         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 707                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 708                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 709                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 710         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 711                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 712                 if (rate >= (pll->params->vco_max >> 1))
 713                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 714         }
 715
 716         pll_writel_misc(val, pll);
 717 }
 718
 719 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 720 {
 721         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 722                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 723
 724                 val |= pll->params->ssc_ctrl_en_mask;
 725                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 726         }
 727 }
 728
 729 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 730 {
 731         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 732                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 733
 734                 val &= ~pll->params->ssc_ctrl_en_mask;
 735                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 736         }
 737 }
 738
 739 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 740                         unsigned long rate)
 741 {
 742         struct tegra_clk_pll *pll = to_clk_pll(hw);
 743         struct tegra_clk_pll_freq_table old_cfg;
 744         int state, ret = 0;
 745
 746         state = clk_pll_is_enabled(hw);
 747
 748         _get_pll_mnp(pll, &old_cfg);
 749
 750         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 751                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 752                 ret = pll->params->dyn_ramp(pll, cfg);
 753                 if (!ret)
 754                         return 0;
 755         }
 756
 757         if (state) {
 758                 pll_clk_stop_ss(pll);
 759                 _clk_pll_disable(hw);
 760         }
 761
 762         if (!pll->params->defaults_set && pll->params->set_defaults)
 763                 pll->params->set_defaults(pll);
 764
 765         _update_pll_mnp(pll, cfg);
 766
 767         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 768                 _update_pll_cpcon(pll, cfg, rate);
 769
 770         if (state) {
 771                 _clk_pll_enable(hw);
 772                 ret = clk_pll_wait_for_lock(pll);
 773                 pll_clk_start_ss(pll);
 774         }
 775
 776         return ret;
 777 }
 778
 779 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 780                         unsigned long parent_rate)
 781 {
 782         struct tegra_clk_pll *pll = to_clk_pll(hw);
 783         struct tegra_clk_pll_freq_table cfg, old_cfg;
 784         unsigned long flags = 0;
 785         int ret = 0;
 786
 787         if (pll->params->flags & TEGRA_PLL_FIXED) {
 788                 if (rate != pll->params->fixed_rate) {
 789                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 790                                 __func__, clk_hw_get_name(hw),
 791                                 pll->params->fixed_rate, rate);
 792                         return -EINVAL;
 793                 }
 794                 return 0;
 795         }
 796
 797         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 798             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 799                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 800                        clk_hw_get_name(hw), rate);
 801                 WARN_ON(1);
 802                 return -EINVAL;
 803         }
 804         if (pll->lock)
 805                 spin_lock_irqsave(pll->lock, flags);
 806
 807         _get_pll_mnp(pll, &old_cfg);
 808         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 809                 cfg.p = old_cfg.p;
 810
 811         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 812                 old_cfg.sdm_data != cfg.sdm_data)
 813                 ret = _program_pll(hw, &cfg, rate);
 814
 815         if (pll->lock)
 816                 spin_unlock_irqrestore(pll->lock, flags);
 817
 818         return ret;
 819 }
 820
 821 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 822                         unsigned long *prate)
 823 {
 824         struct tegra_clk_pll *pll = to_clk_pll(hw);
 825         struct tegra_clk_pll_freq_table cfg;
 826
 827         if (pll->params->flags & TEGRA_PLL_FIXED) {
 828                 /* PLLM/MB are used for memory; we do not change rate */
 829                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 830                         return clk_hw_get_rate(hw);
 831                 return pll->params->fixed_rate;
 832         }
 833
 834         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 835             pll->params->calc_rate(hw, &cfg, rate, *prate))
 836                 return -EINVAL;
 837
 838         return cfg.output_rate;
 839 }
 840
 841 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 842                                          unsigned long parent_rate)
 843 {
 844         struct tegra_clk_pll *pll = to_clk_pll(hw);
 845         struct tegra_clk_pll_freq_table cfg;
 846         u32 val;
 847         u64 rate = parent_rate;
 848         int pdiv;
 849
 850         val = pll_readl_base(pll);
 851
 852         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 853                 return parent_rate;
 854
 855         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 856             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 857                         !(val & PLL_BASE_OVERRIDE)) {
 858                 struct tegra_clk_pll_freq_table sel;
 859                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 860                                         parent_rate)) {
 861                         pr_err("Clock %s has unknown fixed frequency\n",
 862                                clk_hw_get_name(hw));
 863                         BUG();
 864                 }
 865                 return pll->params->fixed_rate;
 866         }
 867
 868         _get_pll_mnp(pll, &cfg);
 869
 870         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 871                 pdiv = 1;
 872         } else {
 873                 pdiv = _hw_to_p_div(hw, cfg.p);
 874                 if (pdiv < 0) {
 875                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 876                              clk_hw_get_name(hw), cfg.p);
 877                         pdiv = 1;
 878                 }
 879         }
 880
 881         if (pll->params->set_gain)
 882                 pll->params->set_gain(&cfg);
 883
 884         cfg.m *= pdiv;
 885
 886         rate *= cfg.n;
 887         do_div(rate, cfg.m);
 888
 889         return rate;
 890 }
 891
 892 static int clk_plle_training(struct tegra_clk_pll *pll)
 893 {
 894         u32 val;
 895         unsigned long timeout;
 896
 897         if (!pll->pmc)
 898                 return -ENOSYS;
 899
 900         /*
 901          * PLLE is already disabled, and setup cleared;
 902          * create falling edge on PLLE IDDQ input.
 903          */
 904         val = readl(pll->pmc + PMC_SATA_PWRGT);
 905         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 906         writel(val, pll->pmc + PMC_SATA_PWRGT);
 907
 908         val = readl(pll->pmc + PMC_SATA_PWRGT);
 909         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 910         writel(val, pll->pmc + PMC_SATA_PWRGT);
 911
 912         val = readl(pll->pmc + PMC_SATA_PWRGT);
 913         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 914         writel(val, pll->pmc + PMC_SATA_PWRGT);
 915
 916         val = pll_readl_misc(pll);
 917
 918         timeout = jiffies + msecs_to_jiffies(100);
 919         while (1) {
 920                 val = pll_readl_misc(pll);
 921                 if (val & PLLE_MISC_READY)
 922                         break;
 923                 if (time_after(jiffies, timeout)) {
 924                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 925                         return -EBUSY;
 926                 }
 927                 udelay(300);
 928         }
 929
 930         return 0;
 931 }
 932
 933 static int clk_plle_enable(struct clk_hw *hw)
 934 {
 935         struct tegra_clk_pll *pll = to_clk_pll(hw);
 936         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 937         struct tegra_clk_pll_freq_table sel;
 938         u32 val;
 939         int err;
 940
 941         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 942                 return -EINVAL;
 943
 944         clk_pll_disable(hw);
 945
 946         val = pll_readl_misc(pll);
 947         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 948         pll_writel_misc(val, pll);
 949
 950         val = pll_readl_misc(pll);
 951         if (!(val & PLLE_MISC_READY)) {
 952                 err = clk_plle_training(pll);
 953                 if (err)
 954                         return err;
 955         }
 956
 957         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 958                 /* configure dividers */
 959                 val = pll_readl_base(pll);
 960                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 961                          divm_mask_shifted(pll));
 962                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 963                 val |= sel.m << divm_shift(pll);
 964                 val |= sel.n << divn_shift(pll);
 965                 val |= sel.p << divp_shift(pll);
 966                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 967                 pll_writel_base(val, pll);
 968         }
 969
 970         val = pll_readl_misc(pll);
 971         val |= PLLE_MISC_SETUP_VALUE;
 972         val |= PLLE_MISC_LOCK_ENABLE;
 973         pll_writel_misc(val, pll);
 974
 975         val = readl(pll->clk_base + PLLE_SS_CTRL);
 976         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 977         val |= PLLE_SS_DISABLE;
 978         writel(val, pll->clk_base + PLLE_SS_CTRL);
 979
 980         val = pll_readl_base(pll);
 981         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 982         pll_writel_base(val, pll);
 983
 984         clk_pll_wait_for_lock(pll);
 985
 986         return 0;
 987 }
 988
 989 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 990                                          unsigned long parent_rate)
 991 {
 992         struct tegra_clk_pll *pll = to_clk_pll(hw);
 993         u32 val = pll_readl_base(pll);
 994         u32 divn = 0, divm = 0, divp = 0;
 995         u64 rate = parent_rate;
 996
 997         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
 998         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
 999         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1000         divm *= divp;
1001
1002         rate *= divn;
1003         do_div(rate, divm);
1004         return rate;
1005 }
1006
1007 const struct clk_ops tegra_clk_pll_ops = {
1008         .is_enabled = clk_pll_is_enabled,
1009         .enable = clk_pll_enable,
1010         .disable = clk_pll_disable,
1011         .recalc_rate = clk_pll_recalc_rate,
1012         .round_rate = clk_pll_round_rate,
1013         .set_rate = clk_pll_set_rate,
1014 };
1015
1016 const struct clk_ops tegra_clk_plle_ops = {
1017         .recalc_rate = clk_plle_recalc_rate,
1018         .is_enabled = clk_pll_is_enabled,
1019         .disable = clk_pll_disable,
1020         .enable = clk_plle_enable,
1021 };
1022
1023 /*
1024  * Structure defining the fields for USB UTMI clocks Parameters.
1025  */
1026 struct utmi_clk_param {
1027         /* Oscillator Frequency in Hz */
1028         u32 osc_frequency;
1029         /* UTMIP PLL Enable Delay Count  */
1030         u8 enable_delay_count;
1031         /* UTMIP PLL Stable count */
1032         u8 stable_count;
1033         /*  UTMIP PLL Active delay count */
1034         u8 active_delay_count;
1035         /* UTMIP PLL Xtal frequency count */
1036         u8 xtal_freq_count;
1037 };
1038
1039 static const struct utmi_clk_param utmi_parameters[] = {
1040         {
1041                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1042                 .stable_count = 0x33, .active_delay_count = 0x05,
1043                 .xtal_freq_count = 0x7f
1044         }, {
1045                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1046                 .stable_count = 0x4b, .active_delay_count = 0x06,
1047                 .xtal_freq_count = 0xbb
1048         }, {
1049                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1050                 .stable_count = 0x2f, .active_delay_count = 0x04,
1051                 .xtal_freq_count = 0x76
1052         }, {
1053                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1054                 .stable_count = 0x66, .active_delay_count = 0x09,
1055                 .xtal_freq_count = 0xfe
1056         }, {
1057                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1058                 .stable_count = 0x41, .active_delay_count = 0x0a,
1059                 .xtal_freq_count = 0xa4
1060         }, {
1061                 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1062                 .stable_count = 0x0, .active_delay_count = 0x6,
1063                 .xtal_freq_count = 0x80
1064         },
1065 };
1066
1067 static int clk_pllu_enable(struct clk_hw *hw)
1068 {
1069         struct tegra_clk_pll *pll = to_clk_pll(hw);
1070         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1071         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1072         const struct utmi_clk_param *params = NULL;
1073         unsigned long flags = 0, input_rate;
1074         unsigned int i;
1075         int ret = 0;
1076         u32 value;
1077
1078         if (!osc) {
1079                 pr_err("%s: failed to get OSC clock\n", __func__);
1080                 return -EINVAL;
1081         }
1082
1083         input_rate = clk_hw_get_rate(osc);
1084
1085         if (pll->lock)
1086                 spin_lock_irqsave(pll->lock, flags);
1087
1088         _clk_pll_enable(hw);
1089
1090         ret = clk_pll_wait_for_lock(pll);
1091         if (ret < 0)
1092                 goto out;
1093
1094         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1095                 if (input_rate == utmi_parameters[i].osc_frequency) {
1096                         params = &utmi_parameters[i];
1097                         break;
1098                 }
1099         }
1100
1101         if (!params) {
1102                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1103                        input_rate);
1104                 ret = -EINVAL;
1105                 goto out;
1106         }
1107
1108         value = pll_readl_base(pll);
1109         value &= ~PLLU_BASE_OVERRIDE;
1110         pll_writel_base(value, pll);
1111
1112         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1113         /* Program UTMIP PLL stable and active counts */
1114         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1115         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1116         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1117         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1118         /* Remove power downs from UTMIP PLL control bits */
1119         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1120         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1121         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1122         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1123
1124         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1125         /* Program UTMIP PLL delay and oscillator frequency counts */
1126         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1127         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1128         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1129         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1130         /* Remove power downs from UTMIP PLL control bits */
1131         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1132         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1133         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1134         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1135
1136 out:
1137         if (pll->lock)
1138                 spin_unlock_irqrestore(pll->lock, flags);
1139
1140         return ret;
1141 }
1142
1143 static const struct clk_ops tegra_clk_pllu_ops = {
1144         .is_enabled = clk_pll_is_enabled,
1145         .enable = clk_pllu_enable,
1146         .disable = clk_pll_disable,
1147         .recalc_rate = clk_pll_recalc_rate,
1148 };
1149
1150 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1151                            unsigned long parent_rate)
1152 {
1153         u16 mdiv = parent_rate / pll_params->cf_min;
1154
1155         if (pll_params->flags & TEGRA_MDIV_NEW)
1156                 return (!pll_params->mdiv_default ? mdiv :
1157                         min(mdiv, pll_params->mdiv_default));
1158
1159         if (pll_params->mdiv_default)
1160                 return pll_params->mdiv_default;
1161
1162         if (parent_rate > pll_params->cf_max)
1163                 return 2;
1164         else
1165                 return 1;
1166 }
1167
1168 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1169                                 struct tegra_clk_pll_freq_table *cfg,
1170                                 unsigned long rate, unsigned long parent_rate)
1171 {
1172         struct tegra_clk_pll *pll = to_clk_pll(hw);
1173         unsigned int p;
1174         int p_div;
1175
1176         if (!rate)
1177                 return -EINVAL;
1178
1179         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1180         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1181         cfg->output_rate = rate * p;
1182         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1183         cfg->input_rate = parent_rate;
1184
1185         p_div = _p_div_to_hw(hw, p);
1186         if (p_div < 0)
1187                 return p_div;
1188
1189         cfg->p = p_div;
1190
1191         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1192                 return -EINVAL;
1193
1194         return 0;
1195 }
1196
1197 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1198         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1199         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1200         defined(CONFIG_ARCH_TEGRA_210_SOC)
1201
1202 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1203 {
1204         struct tegra_clk_pll *pll = to_clk_pll(hw);
1205
1206         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1207 }
1208
1209 static unsigned long _clip_vco_min(unsigned long vco_min,
1210                                    unsigned long parent_rate)
1211 {
1212         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1213 }
1214
1215 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1216                                void __iomem *clk_base,
1217                                unsigned long parent_rate)
1218 {
1219         u32 val;
1220         u32 step_a, step_b;
1221
1222         switch (parent_rate) {
1223         case 12000000:
1224         case 13000000:
1225         case 26000000:
1226                 step_a = 0x2B;
1227                 step_b = 0x0B;
1228                 break;
1229         case 16800000:
1230                 step_a = 0x1A;
1231                 step_b = 0x09;
1232                 break;
1233         case 19200000:
1234                 step_a = 0x12;
1235                 step_b = 0x08;
1236                 break;
1237         default:
1238                 pr_err("%s: Unexpected reference rate %lu\n",
1239                         __func__, parent_rate);
1240                 WARN_ON(1);
1241                 return -EINVAL;
1242         }
1243
1244         val = step_a << pll_params->stepa_shift;
1245         val |= step_b << pll_params->stepb_shift;
1246         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1247
1248         return 0;
1249 }
1250
1251 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1252                               struct tegra_clk_pll_freq_table *cfg,
1253                               unsigned long rate, unsigned long parent_rate)
1254 {
1255         struct tegra_clk_pll *pll = to_clk_pll(hw);
1256         int err = 0;
1257
1258         err = _get_table_rate(hw, cfg, rate, parent_rate);
1259         if (err < 0)
1260                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1261         else {
1262                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1263                         WARN_ON(1);
1264                         err = -EINVAL;
1265                         goto out;
1266                 }
1267         }
1268
1269         if (cfg->p >  pll->params->max_p)
1270                 err = -EINVAL;
1271
1272 out:
1273         return err;
1274 }
1275
1276 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1277                                 unsigned long parent_rate)
1278 {
1279         struct tegra_clk_pll *pll = to_clk_pll(hw);
1280         struct tegra_clk_pll_freq_table cfg, old_cfg;
1281         unsigned long flags = 0;
1282         int ret;
1283
1284         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1285         if (ret < 0)
1286                 return ret;
1287
1288         if (pll->lock)
1289                 spin_lock_irqsave(pll->lock, flags);
1290
1291         _get_pll_mnp(pll, &old_cfg);
1292         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1293                 cfg.p = old_cfg.p;
1294
1295         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1296                 ret = _program_pll(hw, &cfg, rate);
1297
1298         if (pll->lock)
1299                 spin_unlock_irqrestore(pll->lock, flags);
1300
1301         return ret;
1302 }
1303
1304 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1305                                 unsigned long *prate)
1306 {
1307         struct tegra_clk_pll *pll = to_clk_pll(hw);
1308         struct tegra_clk_pll_freq_table cfg;
1309         int ret, p_div;
1310         u64 output_rate = *prate;
1311
1312         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1313         if (ret < 0)
1314                 return ret;
1315
1316         p_div = _hw_to_p_div(hw, cfg.p);
1317         if (p_div < 0)
1318                 return p_div;
1319
1320         if (pll->params->set_gain)
1321                 pll->params->set_gain(&cfg);
1322
1323         output_rate *= cfg.n;
1324         do_div(output_rate, cfg.m * p_div);
1325
1326         return output_rate;
1327 }
1328
1329 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1330 {
1331         u32 val;
1332
1333         val = pll_readl_misc(pll);
1334         val |= PLLCX_MISC_STROBE;
1335         pll_writel_misc(val, pll);
1336         udelay(2);
1337
1338         val &= ~PLLCX_MISC_STROBE;
1339         pll_writel_misc(val, pll);
1340 }
1341
1342 static int clk_pllc_enable(struct clk_hw *hw)
1343 {
1344         struct tegra_clk_pll *pll = to_clk_pll(hw);
1345         u32 val;
1346         int ret;
1347         unsigned long flags = 0;
1348
1349         if (pll->lock)
1350                 spin_lock_irqsave(pll->lock, flags);
1351
1352         _clk_pll_enable(hw);
1353         udelay(2);
1354
1355         val = pll_readl_misc(pll);
1356         val &= ~PLLCX_MISC_RESET;
1357         pll_writel_misc(val, pll);
1358         udelay(2);
1359
1360         _pllcx_strobe(pll);
1361
1362         ret = clk_pll_wait_for_lock(pll);
1363
1364         if (pll->lock)
1365                 spin_unlock_irqrestore(pll->lock, flags);
1366
1367         return ret;
1368 }
1369
1370 static void _clk_pllc_disable(struct clk_hw *hw)
1371 {
1372         struct tegra_clk_pll *pll = to_clk_pll(hw);
1373         u32 val;
1374
1375         _clk_pll_disable(hw);
1376
1377         val = pll_readl_misc(pll);
1378         val |= PLLCX_MISC_RESET;
1379         pll_writel_misc(val, pll);
1380         udelay(2);
1381 }
1382
1383 static void clk_pllc_disable(struct clk_hw *hw)
1384 {
1385         struct tegra_clk_pll *pll = to_clk_pll(hw);
1386         unsigned long flags = 0;
1387
1388         if (pll->lock)
1389                 spin_lock_irqsave(pll->lock, flags);
1390
1391         _clk_pllc_disable(hw);
1392
1393         if (pll->lock)
1394                 spin_unlock_irqrestore(pll->lock, flags);
1395 }
1396
1397 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1398                                         unsigned long input_rate, u32 n)
1399 {
1400         u32 val, n_threshold;
1401
1402         switch (input_rate) {
1403         case 12000000:
1404                 n_threshold = 70;
1405                 break;
1406         case 13000000:
1407         case 26000000:
1408                 n_threshold = 71;
1409                 break;
1410         case 16800000:
1411                 n_threshold = 55;
1412                 break;
1413         case 19200000:
1414                 n_threshold = 48;
1415                 break;
1416         default:
1417                 pr_err("%s: Unexpected reference rate %lu\n",
1418                         __func__, input_rate);
1419                 return -EINVAL;
1420         }
1421
1422         val = pll_readl_misc(pll);
1423         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1424         val |= n <= n_threshold ?
1425                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1426         pll_writel_misc(val, pll);
1427
1428         return 0;
1429 }
1430
1431 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1432                                 unsigned long parent_rate)
1433 {
1434         struct tegra_clk_pll_freq_table cfg, old_cfg;
1435         struct tegra_clk_pll *pll = to_clk_pll(hw);
1436         unsigned long flags = 0;
1437         int state, ret = 0;
1438
1439         if (pll->lock)
1440                 spin_lock_irqsave(pll->lock, flags);
1441
1442         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1443         if (ret < 0)
1444                 goto out;
1445
1446         _get_pll_mnp(pll, &old_cfg);
1447
1448         if (cfg.m != old_cfg.m) {
1449                 WARN_ON(1);
1450                 goto out;
1451         }
1452
1453         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1454                 goto out;
1455
1456         state = clk_pll_is_enabled(hw);
1457         if (state)
1458                 _clk_pllc_disable(hw);
1459
1460         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1461         if (ret < 0)
1462                 goto out;
1463
1464         _update_pll_mnp(pll, &cfg);
1465
1466         if (state)
1467                 ret = clk_pllc_enable(hw);
1468
1469 out:
1470         if (pll->lock)
1471                 spin_unlock_irqrestore(pll->lock, flags);
1472
1473         return ret;
1474 }
1475
1476 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1477                              struct tegra_clk_pll_freq_table *cfg,
1478                              unsigned long rate, unsigned long parent_rate)
1479 {
1480         u16 m, n;
1481         u64 output_rate = parent_rate;
1482
1483         m = _pll_fixed_mdiv(pll->params, parent_rate);
1484         n = rate * m / parent_rate;
1485
1486         output_rate *= n;
1487         do_div(output_rate, m);
1488
1489         if (cfg) {
1490                 cfg->m = m;
1491                 cfg->n = n;
1492         }
1493
1494         return output_rate;
1495 }
1496
1497 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1498                                 unsigned long parent_rate)
1499 {
1500         struct tegra_clk_pll_freq_table cfg, old_cfg;
1501         struct tegra_clk_pll *pll = to_clk_pll(hw);
1502         unsigned long flags = 0;
1503         int state, ret = 0;
1504
1505         if (pll->lock)
1506                 spin_lock_irqsave(pll->lock, flags);
1507
1508         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1509         _get_pll_mnp(pll, &old_cfg);
1510         cfg.p = old_cfg.p;
1511
1512         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1513                 state = clk_pll_is_enabled(hw);
1514                 if (state)
1515                         _clk_pll_disable(hw);
1516
1517                 _update_pll_mnp(pll, &cfg);
1518
1519                 if (state) {
1520                         _clk_pll_enable(hw);
1521                         ret = clk_pll_wait_for_lock(pll);
1522                 }
1523         }
1524
1525         if (pll->lock)
1526                 spin_unlock_irqrestore(pll->lock, flags);
1527
1528         return ret;
1529 }
1530
1531 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1532                                          unsigned long parent_rate)
1533 {
1534         struct tegra_clk_pll_freq_table cfg;
1535         struct tegra_clk_pll *pll = to_clk_pll(hw);
1536         u64 rate = parent_rate;
1537
1538         _get_pll_mnp(pll, &cfg);
1539
1540         rate *= cfg.n;
1541         do_div(rate, cfg.m);
1542
1543         return rate;
1544 }
1545
1546 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1547                                  unsigned long *prate)
1548 {
1549         struct tegra_clk_pll *pll = to_clk_pll(hw);
1550
1551         return _pllre_calc_rate(pll, NULL, rate, *prate);
1552 }
1553
1554 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1555 {
1556         struct tegra_clk_pll *pll = to_clk_pll(hw);
1557         struct tegra_clk_pll_freq_table sel;
1558         u32 val;
1559         int ret;
1560         unsigned long flags = 0;
1561         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1562
1563         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1564                 return -EINVAL;
1565
1566         if (pll->lock)
1567                 spin_lock_irqsave(pll->lock, flags);
1568
1569         val = pll_readl_base(pll);
1570         val &= ~BIT(29); /* Disable lock override */
1571         pll_writel_base(val, pll);
1572
1573         val = pll_readl(pll->params->aux_reg, pll);
1574         val |= PLLE_AUX_ENABLE_SWCTL;
1575         val &= ~PLLE_AUX_SEQ_ENABLE;
1576         pll_writel(val, pll->params->aux_reg, pll);
1577         udelay(1);
1578
1579         val = pll_readl_misc(pll);
1580         val |= PLLE_MISC_LOCK_ENABLE;
1581         val |= PLLE_MISC_IDDQ_SW_CTRL;
1582         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1583         val |= PLLE_MISC_PLLE_PTS;
1584         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1585         pll_writel_misc(val, pll);
1586         udelay(5);
1587
1588         val = pll_readl(PLLE_SS_CTRL, pll);
1589         val |= PLLE_SS_DISABLE;
1590         pll_writel(val, PLLE_SS_CTRL, pll);
1591
1592         val = pll_readl_base(pll);
1593         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1594                  divm_mask_shifted(pll));
1595         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1596         val |= sel.m << divm_shift(pll);
1597         val |= sel.n << divn_shift(pll);
1598         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1599         pll_writel_base(val, pll);
1600         udelay(1);
1601
1602         _clk_pll_enable(hw);
1603         ret = clk_pll_wait_for_lock(pll);
1604
1605         if (ret < 0)
1606                 goto out;
1607
1608         val = pll_readl(PLLE_SS_CTRL, pll);
1609         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1610         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1611         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1612         pll_writel(val, PLLE_SS_CTRL, pll);
1613         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1614         pll_writel(val, PLLE_SS_CTRL, pll);
1615         udelay(1);
1616         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1617         pll_writel(val, PLLE_SS_CTRL, pll);
1618         udelay(1);
1619
1620         /* Enable hw control of xusb brick pll */
1621         val = pll_readl_misc(pll);
1622         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1623         pll_writel_misc(val, pll);
1624
1625         val = pll_readl(pll->params->aux_reg, pll);
1626         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1627         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1628         pll_writel(val, pll->params->aux_reg, pll);
1629         udelay(1);
1630         val |= PLLE_AUX_SEQ_ENABLE;
1631         pll_writel(val, pll->params->aux_reg, pll);
1632
1633         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1634         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1635                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1636         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1637                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1638         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1639         udelay(1);
1640         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1641         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1642
1643         /* Enable hw control of SATA pll */
1644         val = pll_readl(SATA_PLL_CFG0, pll);
1645         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1646         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1647         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1648         pll_writel(val, SATA_PLL_CFG0, pll);
1649
1650         udelay(1);
1651
1652         val = pll_readl(SATA_PLL_CFG0, pll);
1653         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1654         pll_writel(val, SATA_PLL_CFG0, pll);
1655
1656 out:
1657         if (pll->lock)
1658                 spin_unlock_irqrestore(pll->lock, flags);
1659
1660         return ret;
1661 }
1662
1663 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1664 {
1665         struct tegra_clk_pll *pll = to_clk_pll(hw);
1666         unsigned long flags = 0;
1667         u32 val;
1668
1669         if (pll->lock)
1670                 spin_lock_irqsave(pll->lock, flags);
1671
1672         _clk_pll_disable(hw);
1673
1674         val = pll_readl_misc(pll);
1675         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1676         pll_writel_misc(val, pll);
1677         udelay(1);
1678
1679         if (pll->lock)
1680                 spin_unlock_irqrestore(pll->lock, flags);
1681 }
1682
1683 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1684 {
1685         struct tegra_clk_pll *pll = to_clk_pll(hw);
1686         const struct utmi_clk_param *params = NULL;
1687         struct clk *osc = __clk_lookup("osc");
1688         unsigned long flags = 0, input_rate;
1689         unsigned int i;
1690         int ret = 0;
1691         u32 value;
1692
1693         if (!osc) {
1694                 pr_err("%s: failed to get OSC clock\n", __func__);
1695                 return -EINVAL;
1696         }
1697
1698         input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1699
1700         if (pll->lock)
1701                 spin_lock_irqsave(pll->lock, flags);
1702
1703         _clk_pll_enable(hw);
1704
1705         ret = clk_pll_wait_for_lock(pll);
1706         if (ret < 0)
1707                 goto out;
1708
1709         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1710                 if (input_rate == utmi_parameters[i].osc_frequency) {
1711                         params = &utmi_parameters[i];
1712                         break;
1713                 }
1714         }
1715
1716         if (!params) {
1717                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1718                        input_rate);
1719                 ret = -EINVAL;
1720                 goto out;
1721         }
1722
1723         value = pll_readl_base(pll);
1724         value &= ~PLLU_BASE_OVERRIDE;
1725         pll_writel_base(value, pll);
1726
1727         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1728         /* Program UTMIP PLL stable and active counts */
1729         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1730         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1731         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1732         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1733         /* Remove power downs from UTMIP PLL control bits */
1734         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1735         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1736         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1737         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1738
1739         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1740         /* Program UTMIP PLL delay and oscillator frequency counts */
1741         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1742         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1743         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1744         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1745         /* Remove power downs from UTMIP PLL control bits */
1746         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1747         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1748         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1749         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1750         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1751
1752         /* Setup HW control of UTMIPLL */
1753         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1754         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1755         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1756         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1757         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1758
1759         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1760         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1761         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1762         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1763
1764         udelay(1);
1765
1766         /*
1767          * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1768          * to USB2
1769          */
1770         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1771         value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1772         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1773         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1774
1775         udelay(1);
1776
1777         /* Enable HW control of UTMIPLL */
1778         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1779         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1780         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1781
1782 out:
1783         if (pll->lock)
1784                 spin_unlock_irqrestore(pll->lock, flags);
1785
1786         return ret;
1787 }
1788 #endif
1789
1790 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1791                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1792                 spinlock_t *lock)
1793 {
1794         struct tegra_clk_pll *pll;
1795
1796         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1797         if (!pll)
1798                 return ERR_PTR(-ENOMEM);
1799
1800         pll->clk_base = clk_base;
1801         pll->pmc = pmc;
1802
1803         pll->params = pll_params;
1804         pll->lock = lock;
1805
1806         if (!pll_params->div_nmp)
1807                 pll_params->div_nmp = &default_nmp;
1808
1809         return pll;
1810 }
1811
1812 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1813                 const char *name, const char *parent_name, unsigned long flags,
1814                 const struct clk_ops *ops)
1815 {
1816         struct clk_init_data init;
1817
1818         init.name = name;
1819         init.ops = ops;
1820         init.flags = flags;
1821         init.parent_names = (parent_name ? &parent_name : NULL);
1822         init.num_parents = (parent_name ? 1 : 0);
1823
1824         /* Default to _calc_rate if unspecified */
1825         if (!pll->params->calc_rate) {
1826                 if (pll->params->flags & TEGRA_PLLM)
1827                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1828                 else
1829                         pll->params->calc_rate = _calc_rate;
1830         }
1831
1832         if (pll->params->set_defaults)
1833                 pll->params->set_defaults(pll);
1834
1835         /* Data in .init is copied by clk_register(), so stack variable OK */
1836         pll->hw.init = &init;
1837
1838         return clk_register(NULL, &pll->hw);
1839 }
1840
1841 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1842                 void __iomem *clk_base, void __iomem *pmc,
1843                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1844                 spinlock_t *lock)
1845 {
1846         struct tegra_clk_pll *pll;
1847         struct clk *clk;
1848
1849         pll_params->flags |= TEGRA_PLL_BYPASS;
1850
1851         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1852         if (IS_ERR(pll))
1853                 return ERR_CAST(pll);
1854
1855         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1856                                       &tegra_clk_pll_ops);
1857         if (IS_ERR(clk))
1858                 kfree(pll);
1859
1860         return clk;
1861 }
1862
1863 static struct div_nmp pll_e_nmp = {
1864         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1865         .divn_width = PLLE_BASE_DIVN_WIDTH,
1866         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1867         .divm_width = PLLE_BASE_DIVM_WIDTH,
1868         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1869         .divp_width = PLLE_BASE_DIVP_WIDTH,
1870 };
1871
1872 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1873                 void __iomem *clk_base, void __iomem *pmc,
1874                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1875                 spinlock_t *lock)
1876 {
1877         struct tegra_clk_pll *pll;
1878         struct clk *clk;
1879
1880         pll_params->flags |= TEGRA_PLL_BYPASS;
1881
1882         if (!pll_params->div_nmp)
1883                 pll_params->div_nmp = &pll_e_nmp;
1884
1885         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1886         if (IS_ERR(pll))
1887                 return ERR_CAST(pll);
1888
1889         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1890                                       &tegra_clk_plle_ops);
1891         if (IS_ERR(clk))
1892                 kfree(pll);
1893
1894         return clk;
1895 }
1896
1897 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1898                 void __iomem *clk_base, unsigned long flags,
1899                 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1900 {
1901         struct tegra_clk_pll *pll;
1902         struct clk *clk;
1903
1904         pll_params->flags |= TEGRA_PLLU;
1905
1906         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1907         if (IS_ERR(pll))
1908                 return ERR_CAST(pll);
1909
1910         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1911                                       &tegra_clk_pllu_ops);
1912         if (IS_ERR(clk))
1913                 kfree(pll);
1914
1915         return clk;
1916 }
1917
1918 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1919         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1920         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1921         defined(CONFIG_ARCH_TEGRA_210_SOC)
1922 static const struct clk_ops tegra_clk_pllxc_ops = {
1923         .is_enabled = clk_pll_is_enabled,
1924         .enable = clk_pll_enable,
1925         .disable = clk_pll_disable,
1926         .recalc_rate = clk_pll_recalc_rate,
1927         .round_rate = clk_pll_ramp_round_rate,
1928         .set_rate = clk_pllxc_set_rate,
1929 };
1930
1931 static const struct clk_ops tegra_clk_pllc_ops = {
1932         .is_enabled = clk_pll_is_enabled,
1933         .enable = clk_pllc_enable,
1934         .disable = clk_pllc_disable,
1935         .recalc_rate = clk_pll_recalc_rate,
1936         .round_rate = clk_pll_ramp_round_rate,
1937         .set_rate = clk_pllc_set_rate,
1938 };
1939
1940 static const struct clk_ops tegra_clk_pllre_ops = {
1941         .is_enabled = clk_pll_is_enabled,
1942         .enable = clk_pll_enable,
1943         .disable = clk_pll_disable,
1944         .recalc_rate = clk_pllre_recalc_rate,
1945         .round_rate = clk_pllre_round_rate,
1946         .set_rate = clk_pllre_set_rate,
1947 };
1948
1949 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1950         .is_enabled =  clk_pll_is_enabled,
1951         .enable = clk_plle_tegra114_enable,
1952         .disable = clk_plle_tegra114_disable,
1953         .recalc_rate = clk_pll_recalc_rate,
1954 };
1955
1956 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1957         .is_enabled =  clk_pll_is_enabled,
1958         .enable = clk_pllu_tegra114_enable,
1959         .disable = clk_pll_disable,
1960         .recalc_rate = clk_pll_recalc_rate,
1961 };
1962
1963 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1964                           void __iomem *clk_base, void __iomem *pmc,
1965                           unsigned long flags,
1966                           struct tegra_clk_pll_params *pll_params,
1967                           spinlock_t *lock)
1968 {
1969         struct tegra_clk_pll *pll;
1970         struct clk *clk, *parent;
1971         unsigned long parent_rate;
1972         u32 val, val_iddq;
1973
1974         parent = __clk_lookup(parent_name);
1975         if (!parent) {
1976                 WARN(1, "parent clk %s of %s must be registered first\n",
1977                         parent_name, name);
1978                 return ERR_PTR(-EINVAL);
1979         }
1980
1981         if (!pll_params->pdiv_tohw)
1982                 return ERR_PTR(-EINVAL);
1983
1984         parent_rate = clk_get_rate(parent);
1985
1986         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1987
1988         if (pll_params->adjust_vco)
1989                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1990                                                              parent_rate);
1991
1992         /*
1993          * If the pll has a set_defaults callback, it will take care of
1994          * configuring dynamic ramping and setting IDDQ in that path.
1995          */
1996         if (!pll_params->set_defaults) {
1997                 int err;
1998
1999                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2000                 if (err)
2001                         return ERR_PTR(err);
2002
2003                 val = readl_relaxed(clk_base + pll_params->base_reg);
2004                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2005
2006                 if (val & PLL_BASE_ENABLE)
2007                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2008                 else {
2009                         val_iddq |= BIT(pll_params->iddq_bit_idx);
2010                         writel_relaxed(val_iddq,
2011                                        clk_base + pll_params->iddq_reg);
2012                 }
2013         }
2014
2015         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2016         if (IS_ERR(pll))
2017                 return ERR_CAST(pll);
2018
2019         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2020                                       &tegra_clk_pllxc_ops);
2021         if (IS_ERR(clk))
2022                 kfree(pll);
2023
2024         return clk;
2025 }
2026
2027 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2028                           void __iomem *clk_base, void __iomem *pmc,
2029                           unsigned long flags,
2030                           struct tegra_clk_pll_params *pll_params,
2031                           spinlock_t *lock, unsigned long parent_rate)
2032 {
2033         u32 val;
2034         struct tegra_clk_pll *pll;
2035         struct clk *clk;
2036
2037         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2038
2039         if (pll_params->adjust_vco)
2040                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2041                                                              parent_rate);
2042
2043         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2044         if (IS_ERR(pll))
2045                 return ERR_CAST(pll);
2046
2047         /* program minimum rate by default */
2048
2049         val = pll_readl_base(pll);
2050         if (val & PLL_BASE_ENABLE)
2051                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2052                                 BIT(pll_params->iddq_bit_idx));
2053         else {
2054                 int m;
2055
2056                 m = _pll_fixed_mdiv(pll_params, parent_rate);
2057                 val = m << divm_shift(pll);
2058                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2059                 pll_writel_base(val, pll);
2060         }
2061
2062         /* disable lock override */
2063
2064         val = pll_readl_misc(pll);
2065         val &= ~BIT(29);
2066         pll_writel_misc(val, pll);
2067
2068         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2069                                       &tegra_clk_pllre_ops);
2070         if (IS_ERR(clk))
2071                 kfree(pll);
2072
2073         return clk;
2074 }
2075
2076 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2077                           void __iomem *clk_base, void __iomem *pmc,
2078                           unsigned long flags,
2079                           struct tegra_clk_pll_params *pll_params,
2080                           spinlock_t *lock)
2081 {
2082         struct tegra_clk_pll *pll;
2083         struct clk *clk, *parent;
2084         unsigned long parent_rate;
2085
2086         if (!pll_params->pdiv_tohw)
2087                 return ERR_PTR(-EINVAL);
2088
2089         parent = __clk_lookup(parent_name);
2090         if (!parent) {
2091                 WARN(1, "parent clk %s of %s must be registered first\n",
2092                         parent_name, name);
2093                 return ERR_PTR(-EINVAL);
2094         }
2095
2096         parent_rate = clk_get_rate(parent);
2097
2098         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2099
2100         if (pll_params->adjust_vco)
2101                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2102                                                              parent_rate);
2103
2104         pll_params->flags |= TEGRA_PLL_BYPASS;
2105         pll_params->flags |= TEGRA_PLLM;
2106         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2107         if (IS_ERR(pll))
2108                 return ERR_CAST(pll);
2109
2110         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2111                                       &tegra_clk_pll_ops);
2112         if (IS_ERR(clk))
2113                 kfree(pll);
2114
2115         return clk;
2116 }
2117
2118 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2119                           void __iomem *clk_base, void __iomem *pmc,
2120                           unsigned long flags,
2121                           struct tegra_clk_pll_params *pll_params,
2122                           spinlock_t *lock)
2123 {
2124         struct clk *parent, *clk;
2125         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2126         struct tegra_clk_pll *pll;
2127         struct tegra_clk_pll_freq_table cfg;
2128         unsigned long parent_rate;
2129
2130         if (!p_tohw)
2131                 return ERR_PTR(-EINVAL);
2132
2133         parent = __clk_lookup(parent_name);
2134         if (!parent) {
2135                 WARN(1, "parent clk %s of %s must be registered first\n",
2136                         parent_name, name);
2137                 return ERR_PTR(-EINVAL);
2138         }
2139
2140         parent_rate = clk_get_rate(parent);
2141
2142         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2143
2144         pll_params->flags |= TEGRA_PLL_BYPASS;
2145         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2146         if (IS_ERR(pll))
2147                 return ERR_CAST(pll);
2148
2149         /*
2150          * Most of PLLC register fields are shadowed, and can not be read
2151          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2152          * Initialize PLL to default state: disabled, reset; shadow registers
2153          * loaded with default parameters; dividers are preset for half of
2154          * minimum VCO rate (the latter assured that shadowed divider settings
2155          * are within supported range).
2156          */
2157
2158         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2159         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2160
2161         while (p_tohw->pdiv) {
2162                 if (p_tohw->pdiv == 2) {
2163                         cfg.p = p_tohw->hw_val;
2164                         break;
2165                 }
2166                 p_tohw++;
2167         }
2168
2169         if (!p_tohw->pdiv) {
2170                 WARN_ON(1);
2171                 return ERR_PTR(-EINVAL);
2172         }
2173
2174         pll_writel_base(0, pll);
2175         _update_pll_mnp(pll, &cfg);
2176
2177         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2178         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2179         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2180         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2181
2182         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2183
2184         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2185                                       &tegra_clk_pllc_ops);
2186         if (IS_ERR(clk))
2187                 kfree(pll);
2188
2189         return clk;
2190 }
2191
2192 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2193                                 const char *parent_name,
2194                                 void __iomem *clk_base, unsigned long flags,
2195                                 struct tegra_clk_pll_params *pll_params,
2196                                 spinlock_t *lock)
2197 {
2198         struct tegra_clk_pll *pll;
2199         struct clk *clk;
2200         u32 val, val_aux;
2201
2202         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2203         if (IS_ERR(pll))
2204                 return ERR_CAST(pll);
2205
2206         /* ensure parent is set to pll_re_vco */
2207
2208         val = pll_readl_base(pll);
2209         val_aux = pll_readl(pll_params->aux_reg, pll);
2210
2211         if (val & PLL_BASE_ENABLE) {
2212                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2213                         (val_aux & PLLE_AUX_PLLP_SEL))
2214                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2215                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2216                                         "pll_re_vco");
2217         } else {
2218                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2219                 pll_writel(val_aux, pll_params->aux_reg, pll);
2220         }
2221
2222         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2223                                       &tegra_clk_plle_tegra114_ops);
2224         if (IS_ERR(clk))
2225                 kfree(pll);
2226
2227         return clk;
2228 }
2229
2230 struct clk *
2231 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2232                                  void __iomem *clk_base, unsigned long flags,
2233                                  struct tegra_clk_pll_params *pll_params,
2234                                  spinlock_t *lock)
2235 {
2236         struct tegra_clk_pll *pll;
2237         struct clk *clk;
2238
2239         pll_params->flags |= TEGRA_PLLU;
2240
2241         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2242         if (IS_ERR(pll))
2243                 return ERR_CAST(pll);
2244
2245         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2246                                       &tegra_clk_pllu_tegra114_ops);
2247         if (IS_ERR(clk))
2248                 kfree(pll);
2249
2250         return clk;
2251 }
2252 #endif
2253
2254 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
2255 static const struct clk_ops tegra_clk_pllss_ops = {
2256         .is_enabled = clk_pll_is_enabled,
2257         .enable = clk_pll_enable,
2258         .disable = clk_pll_disable,
2259         .recalc_rate = clk_pll_recalc_rate,
2260         .round_rate = clk_pll_ramp_round_rate,
2261         .set_rate = clk_pllxc_set_rate,
2262 };
2263
2264 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2265                                 void __iomem *clk_base, unsigned long flags,
2266                                 struct tegra_clk_pll_params *pll_params,
2267                                 spinlock_t *lock)
2268 {
2269         struct tegra_clk_pll *pll;
2270         struct clk *clk, *parent;
2271         struct tegra_clk_pll_freq_table cfg;
2272         unsigned long parent_rate;
2273         u32 val, val_iddq;
2274         int i;
2275
2276         if (!pll_params->div_nmp)
2277                 return ERR_PTR(-EINVAL);
2278
2279         parent = __clk_lookup(parent_name);
2280         if (!parent) {
2281                 WARN(1, "parent clk %s of %s must be registered first\n",
2282                         parent_name, name);
2283                 return ERR_PTR(-EINVAL);
2284         }
2285
2286         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2287         if (IS_ERR(pll))
2288                 return ERR_CAST(pll);
2289
2290         val = pll_readl_base(pll);
2291         val &= ~PLLSS_REF_SRC_SEL_MASK;
2292         pll_writel_base(val, pll);
2293
2294         parent_rate = clk_get_rate(parent);
2295
2296         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2297
2298         /* initialize PLL to minimum rate */
2299
2300         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2301         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2302
2303         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2304                 ;
2305         if (!i) {
2306                 kfree(pll);
2307                 return ERR_PTR(-EINVAL);
2308         }
2309
2310         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2311
2312         _update_pll_mnp(pll, &cfg);
2313
2314         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2315         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2316         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2317         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2318
2319         val = pll_readl_base(pll);
2320         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2321         if (val & PLL_BASE_ENABLE) {
2322                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2323                         WARN(1, "%s is on but IDDQ set\n", name);
2324                         kfree(pll);
2325                         return ERR_PTR(-EINVAL);
2326                 }
2327         } else {
2328                 val_iddq |= BIT(pll_params->iddq_bit_idx);
2329                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2330         }
2331
2332         val &= ~PLLSS_LOCK_OVERRIDE;
2333         pll_writel_base(val, pll);
2334
2335         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2336                                         &tegra_clk_pllss_ops);
2337
2338         if (IS_ERR(clk))
2339                 kfree(pll);
2340
2341         return clk;
2342 }
2343 #endif
2344
2345 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2346 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2347                           const char *parent_name, void __iomem *clk_base,
2348                           void __iomem *pmc, unsigned long flags,
2349                           struct tegra_clk_pll_params *pll_params,
2350                           spinlock_t *lock, unsigned long parent_rate)
2351 {
2352         u32 val;
2353         struct tegra_clk_pll *pll;
2354         struct clk *clk;
2355
2356         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2357
2358         if (pll_params->adjust_vco)
2359                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2360                                                              parent_rate);
2361
2362         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2363         if (IS_ERR(pll))
2364                 return ERR_CAST(pll);
2365
2366         /* program minimum rate by default */
2367
2368         val = pll_readl_base(pll);
2369         if (val & PLL_BASE_ENABLE)
2370                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2371                                 BIT(pll_params->iddq_bit_idx));
2372         else {
2373                 val = 0x4 << divm_shift(pll);
2374                 val |= 0x41 << divn_shift(pll);
2375                 pll_writel_base(val, pll);
2376         }
2377
2378         /* disable lock override */
2379
2380         val = pll_readl_misc(pll);
2381         val &= ~BIT(29);
2382         pll_writel_misc(val, pll);
2383
2384         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2385                                       &tegra_clk_pllre_ops);
2386         if (IS_ERR(clk))
2387                 kfree(pll);
2388
2389         return clk;
2390 }
2391
2392 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2393 {
2394         struct tegra_clk_pll *pll = to_clk_pll(hw);
2395         struct tegra_clk_pll_freq_table sel;
2396         u32 val;
2397         int ret = 0;
2398         unsigned long flags = 0;
2399         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2400
2401         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2402                 return -EINVAL;
2403
2404         if (pll->lock)
2405                 spin_lock_irqsave(pll->lock, flags);
2406
2407         val = pll_readl(pll->params->aux_reg, pll);
2408         if (val & PLLE_AUX_SEQ_ENABLE)
2409                 goto out;
2410
2411         val = pll_readl_base(pll);
2412         val &= ~BIT(30); /* Disable lock override */
2413         pll_writel_base(val, pll);
2414
2415         val = pll_readl_misc(pll);
2416         val |= PLLE_MISC_LOCK_ENABLE;
2417         val |= PLLE_MISC_IDDQ_SW_CTRL;
2418         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2419         val |= PLLE_MISC_PLLE_PTS;
2420         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2421         pll_writel_misc(val, pll);
2422         udelay(5);
2423
2424         val = pll_readl(PLLE_SS_CTRL, pll);
2425         val |= PLLE_SS_DISABLE;
2426         pll_writel(val, PLLE_SS_CTRL, pll);
2427
2428         val = pll_readl_base(pll);
2429         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2430                  divm_mask_shifted(pll));
2431         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2432         val |= sel.m << divm_shift(pll);
2433         val |= sel.n << divn_shift(pll);
2434         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2435         pll_writel_base(val, pll);
2436         udelay(1);
2437
2438         val = pll_readl_base(pll);
2439         val |= PLLE_BASE_ENABLE;
2440         pll_writel_base(val, pll);
2441
2442         ret = clk_pll_wait_for_lock(pll);
2443
2444         if (ret < 0)
2445                 goto out;
2446
2447         val = pll_readl(PLLE_SS_CTRL, pll);
2448         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2449         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2450         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2451         pll_writel(val, PLLE_SS_CTRL, pll);
2452         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2453         pll_writel(val, PLLE_SS_CTRL, pll);
2454         udelay(1);
2455         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2456         pll_writel(val, PLLE_SS_CTRL, pll);
2457         udelay(1);
2458
2459         val = pll_readl_misc(pll);
2460         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2461         pll_writel_misc(val, pll);
2462
2463         val = pll_readl(pll->params->aux_reg, pll);
2464         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2465         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2466         pll_writel(val, pll->params->aux_reg, pll);
2467         udelay(1);
2468         val |= PLLE_AUX_SEQ_ENABLE;
2469         pll_writel(val, pll->params->aux_reg, pll);
2470
2471 out:
2472         if (pll->lock)
2473                 spin_unlock_irqrestore(pll->lock, flags);
2474
2475         return ret;
2476 }
2477
2478 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2479 {
2480         struct tegra_clk_pll *pll = to_clk_pll(hw);
2481         unsigned long flags = 0;
2482         u32 val;
2483
2484         if (pll->lock)
2485                 spin_lock_irqsave(pll->lock, flags);
2486
2487         /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2488         val = pll_readl(pll->params->aux_reg, pll);
2489         if (val & PLLE_AUX_SEQ_ENABLE)
2490                 goto out;
2491
2492         val = pll_readl_base(pll);
2493         val &= ~PLLE_BASE_ENABLE;
2494         pll_writel_base(val, pll);
2495
2496         val = pll_readl(pll->params->aux_reg, pll);
2497         val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2498         pll_writel(val, pll->params->aux_reg, pll);
2499
2500         val = pll_readl_misc(pll);
2501         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2502         pll_writel_misc(val, pll);
2503         udelay(1);
2504
2505 out:
2506         if (pll->lock)
2507                 spin_unlock_irqrestore(pll->lock, flags);
2508 }
2509
2510 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2511 {
2512         struct tegra_clk_pll *pll = to_clk_pll(hw);
2513         u32 val;
2514
2515         val = pll_readl_base(pll);
2516
2517         return val & PLLE_BASE_ENABLE ? 1 : 0;
2518 }
2519
2520 static int clk_pllu_tegra210_enable(struct clk_hw *hw)
2521 {
2522         struct tegra_clk_pll *pll = to_clk_pll(hw);
2523         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
2524         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
2525         const struct utmi_clk_param *params = NULL;
2526         unsigned long flags = 0, input_rate;
2527         unsigned int i;
2528         int ret = 0;
2529         u32 value;
2530
2531         if (!osc) {
2532                 pr_err("%s: failed to get OSC clock\n", __func__);
2533                 return -EINVAL;
2534         }
2535
2536         input_rate = clk_hw_get_rate(osc);
2537
2538         if (pll->lock)
2539                 spin_lock_irqsave(pll->lock, flags);
2540
2541         _clk_pll_enable(hw);
2542
2543         ret = clk_pll_wait_for_lock(pll);
2544         if (ret < 0)
2545                 goto out;
2546
2547         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2548                 if (input_rate == utmi_parameters[i].osc_frequency) {
2549                         params = &utmi_parameters[i];
2550                         break;
2551                 }
2552         }
2553
2554         if (!params) {
2555                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2556                        input_rate);
2557                 ret = -EINVAL;
2558                 goto out;
2559         }
2560
2561         value = pll_readl_base(pll);
2562         value &= ~PLLU_BASE_OVERRIDE;
2563         pll_writel_base(value, pll);
2564
2565         /* Put PLLU under HW control */
2566         value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2567         value |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2568                  PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2569                  PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2570         value &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2571                    PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2572         writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2573
2574         value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2575         value &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY;
2576         writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2577
2578         udelay(1);
2579
2580         value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2581         value |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2582         writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2583
2584         udelay(1);
2585
2586         /* Disable PLLU clock branch to UTMIPLL since it uses OSC */
2587         value = pll_readl_base(pll);
2588         value &= ~PLLU_BASE_CLKENABLE_USB;
2589         pll_writel_base(value, pll);
2590
2591         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2592         if (value & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE) {
2593                 pr_debug("UTMIPLL already enabled\n");
2594                 goto out;
2595         }
2596
2597         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2598         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2599
2600         /* Program UTMIP PLL stable and active counts */
2601         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2602         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2603         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
2604         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2605         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
2606         value |= UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN;
2607         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2608
2609         /* Program UTMIP PLL delay and oscillator frequency counts */
2610         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2611         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2612         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
2613         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2614         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
2615         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2616
2617         /* Remove power downs from UTMIP PLL control bits */
2618         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2619         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2620         value |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2621         writel(value, pll->clk_base + UTMIP_PLL_CFG1);
2622
2623         udelay(1);
2624
2625         /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2626         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2627         value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2628         value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2629         value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2630         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2631         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2632         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2633         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2634
2635         /* Setup HW control of UTMIPLL */
2636         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2637         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2638         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2639         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2640
2641         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2642         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2643         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2644         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2645
2646         udelay(1);
2647
2648         value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2649         value &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2650         writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2651
2652         udelay(1);
2653
2654         /* Enable HW control of UTMIPLL */
2655         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2656         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2657         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2658
2659 out:
2660         if (pll->lock)
2661                 spin_unlock_irqrestore(pll->lock, flags);
2662
2663         return ret;
2664 }
2665
2666 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2667         .is_enabled =  clk_plle_tegra210_is_enabled,
2668         .enable = clk_plle_tegra210_enable,
2669         .disable = clk_plle_tegra210_disable,
2670         .recalc_rate = clk_pll_recalc_rate,
2671 };
2672
2673 static const struct clk_ops tegra_clk_pllu_tegra210_ops = {
2674         .is_enabled =  clk_pll_is_enabled,
2675         .enable = clk_pllu_tegra210_enable,
2676         .disable = clk_pll_disable,
2677         .recalc_rate = clk_pllre_recalc_rate,
2678 };
2679
2680 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2681                                 const char *parent_name,
2682                                 void __iomem *clk_base, unsigned long flags,
2683                                 struct tegra_clk_pll_params *pll_params,
2684                                 spinlock_t *lock)
2685 {
2686         struct tegra_clk_pll *pll;
2687         struct clk *clk;
2688         u32 val, val_aux;
2689
2690         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2691         if (IS_ERR(pll))
2692                 return ERR_CAST(pll);
2693
2694         /* ensure parent is set to pll_re_vco */
2695
2696         val = pll_readl_base(pll);
2697         val_aux = pll_readl(pll_params->aux_reg, pll);
2698
2699         if (val & PLLE_BASE_ENABLE) {
2700                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2701                         (val_aux & PLLE_AUX_PLLP_SEL))
2702                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2703                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2704                                         "pll_re_vco");
2705         } else {
2706                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2707                 pll_writel(val_aux, pll_params->aux_reg, pll);
2708         }
2709
2710         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2711                                       &tegra_clk_plle_tegra210_ops);
2712         if (IS_ERR(clk))
2713                 kfree(pll);
2714
2715         return clk;
2716 }
2717
2718 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2719                         const char *parent_name, void __iomem *clk_base,
2720                         void __iomem *pmc, unsigned long flags,
2721                         struct tegra_clk_pll_params *pll_params,
2722                         spinlock_t *lock)
2723 {
2724         struct clk *parent, *clk;
2725         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2726         struct tegra_clk_pll *pll;
2727         unsigned long parent_rate;
2728
2729         if (!p_tohw)
2730                 return ERR_PTR(-EINVAL);
2731
2732         parent = __clk_lookup(parent_name);
2733         if (!parent) {
2734                 WARN(1, "parent clk %s of %s must be registered first\n",
2735                         name, parent_name);
2736                 return ERR_PTR(-EINVAL);
2737         }
2738
2739         parent_rate = clk_get_rate(parent);
2740
2741         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2742
2743         if (pll_params->adjust_vco)
2744                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2745                                                              parent_rate);
2746
2747         pll_params->flags |= TEGRA_PLL_BYPASS;
2748         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2749         if (IS_ERR(pll))
2750                 return ERR_CAST(pll);
2751
2752         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2753                                       &tegra_clk_pll_ops);
2754         if (IS_ERR(clk))
2755                 kfree(pll);
2756
2757         return clk;
2758 }
2759
2760 struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2761                         const char *parent_name, void __iomem *clk_base,
2762                         void __iomem *pmc, unsigned long flags,
2763                         struct tegra_clk_pll_params *pll_params,
2764                         spinlock_t *lock)
2765 {
2766         struct tegra_clk_pll *pll;
2767         struct clk *clk, *parent;
2768         unsigned long parent_rate;
2769
2770         parent = __clk_lookup(parent_name);
2771         if (!parent) {
2772                 WARN(1, "parent clk %s of %s must be registered first\n",
2773                         name, parent_name);
2774                 return ERR_PTR(-EINVAL);
2775         }
2776
2777         if (!pll_params->pdiv_tohw)
2778                 return ERR_PTR(-EINVAL);
2779
2780         parent_rate = clk_get_rate(parent);
2781
2782         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2783
2784         if (pll_params->adjust_vco)
2785                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2786                                                              parent_rate);
2787
2788         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2789         if (IS_ERR(pll))
2790                 return ERR_CAST(pll);
2791
2792         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2793                                       &tegra_clk_pll_ops);
2794         if (IS_ERR(clk))
2795                 kfree(pll);
2796
2797         return clk;
2798 }
2799
2800 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2801                                 const char *parent_name, void __iomem *clk_base,
2802                                 unsigned long flags,
2803                                 struct tegra_clk_pll_params *pll_params,
2804                                 spinlock_t *lock)
2805 {
2806         struct tegra_clk_pll *pll;
2807         struct clk *clk, *parent;
2808         struct tegra_clk_pll_freq_table cfg;
2809         unsigned long parent_rate;
2810         u32 val;
2811         int i;
2812
2813         if (!pll_params->div_nmp)
2814                 return ERR_PTR(-EINVAL);
2815
2816         parent = __clk_lookup(parent_name);
2817         if (!parent) {
2818                 WARN(1, "parent clk %s of %s must be registered first\n",
2819                         name, parent_name);
2820                 return ERR_PTR(-EINVAL);
2821         }
2822
2823         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2824         if (IS_ERR(pll))
2825                 return ERR_CAST(pll);
2826
2827         val = pll_readl_base(pll);
2828         val &= ~PLLSS_REF_SRC_SEL_MASK;
2829         pll_writel_base(val, pll);
2830
2831         parent_rate = clk_get_rate(parent);
2832
2833         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2834
2835         if (pll_params->adjust_vco)
2836                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2837                                                              parent_rate);
2838
2839         /* initialize PLL to minimum rate */
2840
2841         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2842         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2843
2844         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2845                 ;
2846         if (!i) {
2847                 kfree(pll);
2848                 return ERR_PTR(-EINVAL);
2849         }
2850
2851         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2852
2853         _update_pll_mnp(pll, &cfg);
2854
2855         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2856
2857         val = pll_readl_base(pll);
2858         if (val & PLL_BASE_ENABLE) {
2859                 if (val & BIT(pll_params->iddq_bit_idx)) {
2860                         WARN(1, "%s is on but IDDQ set\n", name);
2861                         kfree(pll);
2862                         return ERR_PTR(-EINVAL);
2863                 }
2864         } else
2865                 val |= BIT(pll_params->iddq_bit_idx);
2866
2867         val &= ~PLLSS_LOCK_OVERRIDE;
2868         pll_writel_base(val, pll);
2869
2870         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2871                                         &tegra_clk_pll_ops);
2872
2873         if (IS_ERR(clk))
2874                 kfree(pll);
2875
2876         return clk;
2877 }
2878
2879 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2880                           void __iomem *clk_base, void __iomem *pmc,
2881                           unsigned long flags,
2882                           struct tegra_clk_pll_params *pll_params,
2883                           spinlock_t *lock)
2884 {
2885         struct tegra_clk_pll *pll;
2886         struct clk *clk, *parent;
2887         unsigned long parent_rate;
2888
2889         if (!pll_params->pdiv_tohw)
2890                 return ERR_PTR(-EINVAL);
2891
2892         parent = __clk_lookup(parent_name);
2893         if (!parent) {
2894                 WARN(1, "parent clk %s of %s must be registered first\n",
2895                         parent_name, name);
2896                 return ERR_PTR(-EINVAL);
2897         }
2898
2899         parent_rate = clk_get_rate(parent);
2900
2901         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2902
2903         if (pll_params->adjust_vco)
2904                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2905                                                              parent_rate);
2906
2907         pll_params->flags |= TEGRA_PLL_BYPASS;
2908         pll_params->flags |= TEGRA_PLLMB;
2909         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2910         if (IS_ERR(pll))
2911                 return ERR_CAST(pll);
2912
2913         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2914                                       &tegra_clk_pll_ops);
2915         if (IS_ERR(clk))
2916                 kfree(pll);
2917
2918         return clk;
2919 }
2920
2921 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
2922                 const char *parent_name, void __iomem *clk_base,
2923                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
2924                 spinlock_t *lock)
2925 {
2926         struct tegra_clk_pll *pll;
2927         struct clk *clk;
2928
2929         pll_params->flags |= TEGRA_PLLU;
2930
2931         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2932         if (IS_ERR(pll))
2933                 return ERR_CAST(pll);
2934
2935         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2936                                       &tegra_clk_pllu_tegra210_ops);
2937         if (IS_ERR(clk))
2938                 kfree(pll);
2939
2940         return clk;
2941 }
2942 #endif