2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
22 #include <linux/of_address.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/clk/tegra.h>
26 #include <dt-bindings/clock/tegra210-car.h>
32 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
33 * banks present in the Tegra210 CAR IP block. The banks are
34 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
35 * periph_regs[] in drivers/clk/tegra/clk.c
37 #define TEGRA210_CAR_BANK_COUNT 7
39 #define CLK_SOURCE_CSITE 0x1d4
40 #define CLK_SOURCE_EMC 0x19c
42 #define PLLC_BASE 0x80
44 #define PLLC_MISC0 0x88
45 #define PLLC_MISC1 0x8c
46 #define PLLC_MISC2 0x5d0
47 #define PLLC_MISC3 0x5d4
49 #define PLLC2_BASE 0x4e8
50 #define PLLC2_MISC0 0x4ec
51 #define PLLC2_MISC1 0x4f0
52 #define PLLC2_MISC2 0x4f4
53 #define PLLC2_MISC3 0x4f8
55 #define PLLC3_BASE 0x4fc
56 #define PLLC3_MISC0 0x500
57 #define PLLC3_MISC1 0x504
58 #define PLLC3_MISC2 0x508
59 #define PLLC3_MISC3 0x50c
61 #define PLLM_BASE 0x90
62 #define PLLM_MISC1 0x98
63 #define PLLM_MISC2 0x9c
64 #define PLLP_BASE 0xa0
65 #define PLLP_MISC0 0xac
66 #define PLLP_MISC1 0x680
67 #define PLLA_BASE 0xb0
68 #define PLLA_MISC0 0xbc
69 #define PLLA_MISC1 0xb8
70 #define PLLA_MISC2 0x5d8
71 #define PLLD_BASE 0xd0
72 #define PLLD_MISC0 0xdc
73 #define PLLD_MISC1 0xd8
74 #define PLLU_BASE 0xc0
75 #define PLLU_OUTA 0xc4
76 #define PLLU_MISC0 0xcc
77 #define PLLU_MISC1 0xc8
78 #define PLLX_BASE 0xe0
79 #define PLLX_MISC0 0xe4
80 #define PLLX_MISC1 0x510
81 #define PLLX_MISC2 0x514
82 #define PLLX_MISC3 0x518
83 #define PLLX_MISC4 0x5f0
84 #define PLLX_MISC5 0x5f4
85 #define PLLE_BASE 0xe8
86 #define PLLE_MISC0 0xec
87 #define PLLD2_BASE 0x4b8
88 #define PLLD2_MISC0 0x4bc
89 #define PLLD2_MISC1 0x570
90 #define PLLD2_MISC2 0x574
91 #define PLLD2_MISC3 0x578
92 #define PLLE_AUX 0x48c
93 #define PLLRE_BASE 0x4c4
94 #define PLLRE_MISC0 0x4c8
95 #define PLLDP_BASE 0x590
96 #define PLLDP_MISC 0x594
98 #define PLLC4_BASE 0x5a4
99 #define PLLC4_MISC0 0x5a8
100 #define PLLC4_OUT 0x5e4
101 #define PLLMB_BASE 0x5e8
102 #define PLLMB_MISC1 0x5ec
103 #define PLLA1_BASE 0x6a4
104 #define PLLA1_MISC0 0x6a8
105 #define PLLA1_MISC1 0x6ac
106 #define PLLA1_MISC2 0x6b0
107 #define PLLA1_MISC3 0x6b4
109 #define PLLU_IDDQ_BIT 31
110 #define PLLCX_IDDQ_BIT 27
111 #define PLLRE_IDDQ_BIT 24
112 #define PLLA_IDDQ_BIT 25
113 #define PLLD_IDDQ_BIT 20
114 #define PLLSS_IDDQ_BIT 18
115 #define PLLM_IDDQ_BIT 5
116 #define PLLMB_IDDQ_BIT 17
117 #define PLLXP_IDDQ_BIT 3
119 #define PLLCX_RESET_BIT 30
121 #define PLL_BASE_LOCK BIT(27)
122 #define PLLCX_BASE_LOCK BIT(26)
123 #define PLLE_MISC_LOCK BIT(11)
124 #define PLLRE_MISC_LOCK BIT(27)
126 #define PLL_MISC_LOCK_ENABLE 18
127 #define PLLC_MISC_LOCK_ENABLE 24
128 #define PLLDU_MISC_LOCK_ENABLE 22
129 #define PLLU_MISC_LOCK_ENABLE 29
130 #define PLLE_MISC_LOCK_ENABLE 9
131 #define PLLRE_MISC_LOCK_ENABLE 30
132 #define PLLSS_MISC_LOCK_ENABLE 30
133 #define PLLP_MISC_LOCK_ENABLE 18
134 #define PLLM_MISC_LOCK_ENABLE 4
135 #define PLLMB_MISC_LOCK_ENABLE 16
136 #define PLLA_MISC_LOCK_ENABLE 28
137 #define PLLU_MISC_LOCK_ENABLE 29
138 #define PLLD_MISC_LOCK_ENABLE 18
140 #define PLLA_SDM_DIN_MASK 0xffff
141 #define PLLA_SDM_EN_MASK BIT(26)
143 #define PLLD_SDM_EN_MASK BIT(16)
145 #define PLLD2_SDM_EN_MASK BIT(31)
146 #define PLLD2_SSC_EN_MASK BIT(30)
148 #define PLLDP_SS_CFG 0x598
149 #define PLLDP_SDM_EN_MASK BIT(31)
150 #define PLLDP_SSC_EN_MASK BIT(30)
151 #define PLLDP_SS_CTRL1 0x59c
152 #define PLLDP_SS_CTRL2 0x5a0
154 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
155 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
157 #define UTMIP_PLL_CFG2 0x488
158 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
159 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
160 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
167 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
169 #define UTMIP_PLL_CFG1 0x484
170 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
171 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
172 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
173 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
174 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
175 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
176 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
178 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
179 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
180 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
181 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
182 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
183 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
184 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
185 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
186 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
187 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
188 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
190 #define PLLU_HW_PWRDN_CFG0 0x530
191 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
192 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
193 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
194 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
195 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
196 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
198 #define XUSB_PLL_CFG0 0x534
199 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
200 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
202 #define SPARE_REG0 0x55c
203 #define CLK_M_DIVISOR_SHIFT 2
204 #define CLK_M_DIVISOR_MASK 0x3
207 * SDM fractional divisor is 16-bit 2's complement signed number within
208 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
209 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
210 * indicate that SDM is disabled.
212 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
214 #define PLL_SDM_COEFF BIT(13)
215 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
216 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
218 /* Tegra CPU clock and reset control regs */
219 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
221 #ifdef CONFIG_PM_SLEEP
222 static struct cpu_clk_suspend_context {
224 } tegra210_cpu_clk_sctx;
227 static void __iomem *clk_base;
228 static void __iomem *pmc_base;
230 static unsigned long osc_freq;
231 static unsigned long pll_ref_freq;
233 static DEFINE_SPINLOCK(pll_d_lock);
234 static DEFINE_SPINLOCK(pll_e_lock);
235 static DEFINE_SPINLOCK(pll_re_lock);
236 static DEFINE_SPINLOCK(pll_u_lock);
237 static DEFINE_SPINLOCK(emc_lock);
239 /* possible OSC frequencies in Hz */
240 static unsigned long tegra210_input_freq[] = {
245 static const char *mux_pllmcp_clkm[] = {
246 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
249 #define mux_pllmcp_clkm_idx NULL
251 #define PLL_ENABLE (1 << 30)
253 #define PLLCX_MISC1_IDDQ (1 << 27)
254 #define PLLCX_MISC0_RESET (1 << 30)
256 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
257 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
258 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
259 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
260 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
261 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
262 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
263 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
266 #define PLLA_BASE_IDDQ (1 << 25)
267 #define PLLA_BASE_LOCK (1 << 27)
269 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
270 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
272 #define PLLA_MISC2_EN_SDM (1 << 26)
273 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
275 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
276 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
277 #define PLLA_MISC2_DEFAULT_VALUE 0x0
278 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
281 #define PLLD_MISC0_EN_SDM (1 << 16)
282 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
283 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
284 #define PLLD_MISC0_IDDQ (1 << 20)
285 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
287 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
288 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
289 #define PLLD_MISC1_DEFAULT_VALUE 0x20
290 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
292 /* PLLD2 and PLLDP and PLLC4 */
293 #define PLLDSS_BASE_LOCK (1 << 27)
294 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
295 #define PLLDSS_BASE_IDDQ (1 << 18)
296 #define PLLDSS_BASE_REF_SEL_SHIFT 25
297 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
299 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
301 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
302 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
304 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
305 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
306 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
307 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
309 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
310 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
311 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
312 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
314 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
315 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
316 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
317 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
319 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
322 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
323 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
324 #define PLLRE_MISC0_LOCK (1 << 27)
325 #define PLLRE_MISC0_IDDQ (1 << 24)
327 #define PLLRE_BASE_DEFAULT_VALUE 0x0
328 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
330 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
331 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
334 #define PLLX_USE_DYN_RAMP 1
335 #define PLLX_BASE_LOCK (1 << 27)
337 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
338 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
340 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
341 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
342 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
343 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
344 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
345 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
346 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
347 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
348 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
350 #define PLLX_MISC3_IDDQ (0x1 << 3)
352 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
353 #define PLLX_MISC0_WRITE_MASK 0x10c40000
354 #define PLLX_MISC1_DEFAULT_VALUE 0x20
355 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
356 #define PLLX_MISC2_DEFAULT_VALUE 0x0
357 #define PLLX_MISC2_WRITE_MASK 0xffffff11
358 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
359 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
360 #define PLLX_MISC4_DEFAULT_VALUE 0x0
361 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
362 #define PLLX_MISC5_DEFAULT_VALUE 0x0
363 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
365 #define PLLX_HW_CTRL_CFG 0x548
366 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
369 #define PLLMB_BASE_LOCK (1 << 27)
371 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
372 #define PLLMB_MISC1_IDDQ (1 << 17)
373 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
375 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
376 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
379 #define PLLP_BASE_OVERRIDE (1 << 28)
380 #define PLLP_BASE_LOCK (1 << 27)
382 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
383 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
384 #define PLLP_MISC0_IDDQ (1 << 3)
386 #define PLLP_MISC1_HSIO_EN_SHIFT 29
387 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
388 #define PLLP_MISC1_XUSB_EN_SHIFT 28
389 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
391 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
392 #define PLLP_MISC1_DEFAULT_VALUE 0x0
394 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
395 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
398 #define PLLU_BASE_LOCK (1 << 27)
399 #define PLLU_BASE_OVERRIDE (1 << 24)
400 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
401 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
402 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
403 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
404 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
405 PLLU_BASE_CLKENABLE_HSIC |\
406 PLLU_BASE_CLKENABLE_ICUSB |\
407 PLLU_BASE_CLKENABLE_48M)
409 #define PLLU_MISC0_IDDQ (1 << 31)
410 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
411 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
413 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
414 #define PLLU_MISC1_DEFAULT_VALUE 0x0
416 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
417 #define PLLU_MISC1_WRITE_MASK 0x00000007
419 static inline void _pll_misc_chk_default(void __iomem *base,
420 struct tegra_clk_pll_params *params,
421 u8 misc_num, u32 default_val, u32 mask)
423 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
427 if (boot_val != default_val) {
428 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
429 misc_num, boot_val, default_val);
430 pr_warn(" (comparison mask = 0x%x)\n", mask);
431 params->defaults_set = false;
436 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
437 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
438 * that changes NDIV only, while PLL is already locked.
440 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
444 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
445 _pll_misc_chk_default(clk_base, params, 0, default_val,
446 PLLCX_MISC0_WRITE_MASK);
448 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
449 _pll_misc_chk_default(clk_base, params, 1, default_val,
450 PLLCX_MISC1_WRITE_MASK);
452 default_val = PLLCX_MISC2_DEFAULT_VALUE;
453 _pll_misc_chk_default(clk_base, params, 2, default_val,
454 PLLCX_MISC2_WRITE_MASK);
456 default_val = PLLCX_MISC3_DEFAULT_VALUE;
457 _pll_misc_chk_default(clk_base, params, 3, default_val,
458 PLLCX_MISC3_WRITE_MASK);
461 void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
463 pllcx->params->defaults_set = true;
465 if (readl_relaxed(clk_base + pllcx->params->base_reg) &
467 /* PLL is ON: only check if defaults already set */
468 pllcx_check_defaults(pllcx->params);
469 pr_warn("%s already enabled. Postponing set full defaults\n",
474 /* Defaults assert PLL reset, and set IDDQ */
475 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
476 clk_base + pllcx->params->ext_misc_reg[0]);
477 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
478 clk_base + pllcx->params->ext_misc_reg[1]);
479 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
480 clk_base + pllcx->params->ext_misc_reg[2]);
481 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
482 clk_base + pllcx->params->ext_misc_reg[3]);
486 void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
488 tegra210_pllcx_set_defaults("PLL_C", pllcx);
491 void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
493 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
496 void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
498 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
501 void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
503 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
508 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
509 * Fractional SDM is allowed to provide exact audio rates.
511 void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
514 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
516 plla->params->defaults_set = true;
518 if (val & PLL_ENABLE) {
520 * PLL is ON: check if defaults already set, then set those
521 * that can be updated in flight.
523 if (val & PLLA_BASE_IDDQ) {
524 pr_warn("PLL_A boot enabled with IDDQ set\n");
525 plla->params->defaults_set = false;
528 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
530 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
531 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
532 _pll_misc_chk_default(clk_base, plla->params, 0, val,
533 ~mask & PLLA_MISC0_WRITE_MASK);
535 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
536 _pll_misc_chk_default(clk_base, plla->params, 2, val,
537 PLLA_MISC2_EN_DYNRAMP);
539 /* Enable lock detect */
540 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
542 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
543 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
549 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
550 val |= PLLA_BASE_IDDQ;
551 writel_relaxed(val, clk_base + plla->params->base_reg);
552 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
553 clk_base + plla->params->ext_misc_reg[0]);
554 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
555 clk_base + plla->params->ext_misc_reg[2]);
561 * PLL with fractional SDM.
563 void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
568 plld->params->defaults_set = true;
570 if (readl_relaxed(clk_base + plld->params->base_reg) &
572 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
575 * PLL is ON: check if defaults already set, then set those
576 * that can be updated in flight.
578 val = PLLD_MISC1_DEFAULT_VALUE;
579 _pll_misc_chk_default(clk_base, plld->params, 1,
580 val, PLLD_MISC1_WRITE_MASK);
582 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
583 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
584 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
585 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
586 _pll_misc_chk_default(clk_base, plld->params, 0, val,
587 ~mask & PLLD_MISC0_WRITE_MASK);
589 /* Enable lock detect */
590 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
591 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
593 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
594 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
600 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
601 val &= PLLD_MISC0_DSI_CLKENABLE;
602 val |= PLLD_MISC0_DEFAULT_VALUE;
603 /* set IDDQ, enable lock detect, disable SDM */
604 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
605 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
606 plld->params->ext_misc_reg[1]);
612 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
614 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
615 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
618 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
620 plldss->params->defaults_set = true;
622 if (val & PLL_ENABLE) {
623 pr_warn("%s already enabled. Postponing set full defaults\n",
627 * PLL is ON: check if defaults already set, then set those
628 * that can be updated in flight.
630 if (val & PLLDSS_BASE_IDDQ) {
631 pr_warn("plldss boot enabled with IDDQ set\n");
632 plldss->params->defaults_set = false;
635 /* ignore lock enable */
636 default_val = misc0_val;
637 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
638 PLLDSS_MISC0_WRITE_MASK &
639 (~PLLDSS_MISC0_LOCK_ENABLE));
642 * If SSC is used, check all settings, otherwise just confirm
643 * that SSC is not used on boot as well. Do nothing when using
644 * this function for PLLC4 that has only MISC0.
646 if (plldss->params->ssc_ctrl_en_mask) {
647 default_val = misc1_val;
648 _pll_misc_chk_default(clk_base, plldss->params, 1,
649 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
650 default_val = misc2_val;
651 _pll_misc_chk_default(clk_base, plldss->params, 2,
652 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
653 default_val = misc3_val;
654 _pll_misc_chk_default(clk_base, plldss->params, 3,
655 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
656 } else if (plldss->params->ext_misc_reg[1]) {
657 default_val = misc1_val;
658 _pll_misc_chk_default(clk_base, plldss->params, 1,
659 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
660 (~PLLDSS_MISC1_CFG_EN_SDM));
663 /* Enable lock detect */
664 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
665 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
666 writel_relaxed(val, clk_base +
667 plldss->params->base_reg);
670 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
671 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
672 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
673 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
679 /* set IDDQ, enable lock detect, configure SDM/SSC */
680 val |= PLLDSS_BASE_IDDQ;
681 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
682 writel_relaxed(val, clk_base + plldss->params->base_reg);
684 /* When using this function for PLLC4 exit here */
685 if (!plldss->params->ext_misc_reg[1]) {
686 writel_relaxed(misc0_val, clk_base +
687 plldss->params->ext_misc_reg[0]);
692 writel_relaxed(misc0_val, clk_base +
693 plldss->params->ext_misc_reg[0]);
694 /* if SSC used set by 1st enable */
695 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
696 clk_base + plldss->params->ext_misc_reg[1]);
697 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
698 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
702 void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
704 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
705 PLLD2_MISC1_CFG_DEFAULT_VALUE,
706 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
707 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
710 void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
712 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
713 PLLDP_MISC1_CFG_DEFAULT_VALUE,
714 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
715 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
720 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
721 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
723 void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
725 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
730 * VCO is exposed to the clock tree directly along with post-divider output
732 void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
735 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
737 pllre->params->defaults_set = true;
739 if (val & PLL_ENABLE) {
740 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
743 * PLL is ON: check if defaults already set, then set those
744 * that can be updated in flight.
746 val &= PLLRE_BASE_DEFAULT_MASK;
747 if (val != PLLRE_BASE_DEFAULT_VALUE) {
748 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
749 val, PLLRE_BASE_DEFAULT_VALUE);
750 pr_warn("(comparison mask = 0x%x)\n",
751 PLLRE_BASE_DEFAULT_MASK);
752 pllre->params->defaults_set = false;
755 /* Ignore lock enable */
756 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
757 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
758 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
759 ~mask & PLLRE_MISC0_WRITE_MASK);
761 /* Enable lock detect */
762 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
764 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
765 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
771 /* set IDDQ, enable lock detect */
772 val &= ~PLLRE_BASE_DEFAULT_MASK;
773 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
774 writel_relaxed(val, clk_base + pllre->params->base_reg);
775 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
776 clk_base + pllre->params->ext_misc_reg[0]);
780 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
782 unsigned long input_rate;
785 if (!IS_ERR_OR_NULL(hw->clk))
786 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
788 input_rate = 38400000;
790 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
792 switch (input_rate) {
808 pr_err("%s: Unexpected reference rate %lu\n",
809 __func__, input_rate);
814 static void pllx_check_defaults(struct tegra_clk_pll *pll)
818 default_val = PLLX_MISC0_DEFAULT_VALUE;
819 /* ignore lock enable */
820 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
821 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
823 default_val = PLLX_MISC1_DEFAULT_VALUE;
824 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
825 PLLX_MISC1_WRITE_MASK);
827 /* ignore all but control bit */
828 default_val = PLLX_MISC2_DEFAULT_VALUE;
829 _pll_misc_chk_default(clk_base, pll->params, 2,
830 default_val, PLLX_MISC2_EN_DYNRAMP);
832 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
833 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
834 PLLX_MISC3_WRITE_MASK);
836 default_val = PLLX_MISC4_DEFAULT_VALUE;
837 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
838 PLLX_MISC4_WRITE_MASK);
840 default_val = PLLX_MISC5_DEFAULT_VALUE;
841 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
842 PLLX_MISC5_WRITE_MASK);
845 void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
850 pllx->params->defaults_set = true;
852 /* Get ready dyn ramp state machine settings */
853 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
854 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
855 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
856 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
857 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
859 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
860 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
863 * PLL is ON: check if defaults already set, then set those
864 * that can be updated in flight.
866 pllx_check_defaults(pllx);
868 /* Configure dyn ramp, disable lock override */
869 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
871 /* Enable lock detect */
872 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
873 val &= ~PLLX_MISC0_LOCK_ENABLE;
874 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
875 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
881 /* Enable lock detect and CPU output */
882 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
883 pllx->params->ext_misc_reg[0]);
886 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
887 pllx->params->ext_misc_reg[1]);
889 /* Configure dyn ramp state machine, disable lock override */
890 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
893 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
894 pllx->params->ext_misc_reg[3]);
897 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
898 pllx->params->ext_misc_reg[4]);
899 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
900 pllx->params->ext_misc_reg[5]);
905 void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
907 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
909 pllmb->params->defaults_set = true;
911 if (val & PLL_ENABLE) {
912 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
915 * PLL is ON: check if defaults already set, then set those
916 * that can be updated in flight.
918 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
919 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
920 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
921 ~mask & PLLMB_MISC1_WRITE_MASK);
923 /* Enable lock detect */
924 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
926 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
927 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
933 /* set IDDQ, enable lock detect */
934 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
935 clk_base + pllmb->params->ext_misc_reg[0]);
941 * VCO is exposed to the clock tree directly along with post-divider output.
942 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
945 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
949 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
950 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
951 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
953 mask |= PLLP_MISC0_IDDQ;
954 _pll_misc_chk_default(clk_base, pll->params, 0, val,
955 ~mask & PLLP_MISC0_WRITE_MASK);
957 /* Ignore branch controls */
958 val = PLLP_MISC1_DEFAULT_VALUE;
959 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
960 _pll_misc_chk_default(clk_base, pll->params, 1, val,
961 ~mask & PLLP_MISC1_WRITE_MASK);
964 void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
967 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
969 pllp->params->defaults_set = true;
971 if (val & PLL_ENABLE) {
972 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
975 * PLL is ON: check if defaults already set, then set those
976 * that can be updated in flight.
978 pllp_check_defaults(pllp, true);
980 /* Enable lock detect */
981 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
982 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
984 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
985 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
991 /* set IDDQ, enable lock detect */
992 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
993 clk_base + pllp->params->ext_misc_reg[0]);
995 /* Preserve branch control */
996 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
997 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
999 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1000 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1006 * VCO is exposed to the clock tree directly along with post-divider output.
1007 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1010 static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control)
1014 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1015 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1016 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1017 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1018 ~mask & PLLU_MISC0_WRITE_MASK);
1020 val = PLLU_MISC1_DEFAULT_VALUE;
1021 mask = PLLU_MISC1_LOCK_OVERRIDE;
1022 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1023 ~mask & PLLU_MISC1_WRITE_MASK);
1026 void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
1028 u32 val = readl_relaxed(clk_base + pllu->params->base_reg);
1030 pllu->params->defaults_set = true;
1032 if (val & PLL_ENABLE) {
1033 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1036 * PLL is ON: check if defaults already set, then set those
1037 * that can be updated in flight.
1039 pllu_check_defaults(pllu, false);
1041 /* Enable lock detect */
1042 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]);
1043 val &= ~PLLU_MISC0_LOCK_ENABLE;
1044 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1045 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[0]);
1047 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[1]);
1048 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1049 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1050 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[1]);
1056 /* set IDDQ, enable lock detect */
1057 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1058 clk_base + pllu->params->ext_misc_reg[0]);
1059 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1060 clk_base + pllu->params->ext_misc_reg[1]);
1064 #define mask(w) ((1 << (w)) - 1)
1065 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1066 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1067 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1068 mask(p->params->div_nmp->divp_width))
1070 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1071 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1072 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1074 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1075 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1076 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1078 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1079 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1085 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1086 udelay(PLL_LOCKDET_DELAY);
1087 val = readl_relaxed(clk_base + reg);
1088 if ((val & mask) == mask) {
1089 udelay(PLL_LOCKDET_DELAY);
1096 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1097 struct tegra_clk_pll_freq_table *cfg)
1099 u32 val, base, ndiv_new_mask;
1101 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1102 << PLLX_MISC2_NDIV_NEW_SHIFT;
1104 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1105 val &= (~ndiv_new_mask);
1106 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1107 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1110 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1111 val |= PLLX_MISC2_EN_DYNRAMP;
1112 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1115 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1116 PLLX_MISC2_DYNRAMP_DONE);
1118 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1119 (~divn_mask_shifted(pllx));
1120 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1121 writel_relaxed(base, clk_base + pllx->params->base_reg);
1124 val &= ~PLLX_MISC2_EN_DYNRAMP;
1125 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1128 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1129 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1130 cfg->input_rate / cfg->m * cfg->n /
1131 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1137 * Common configuration for PLLs with fixed input divider policy:
1138 * - always set fixed M-value based on the reference rate
1139 * - always set P-value value 1:1 for output rates above VCO minimum, and
1140 * choose minimum necessary P-value for output rates below VCO maximum
1141 * - calculate N-value based on selected M and P
1142 * - calculate SDM_DIN fractional part
1144 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1145 struct tegra_clk_pll_freq_table *cfg,
1146 unsigned long rate, unsigned long input_rate)
1148 struct tegra_clk_pll *pll = to_clk_pll(hw);
1149 struct tegra_clk_pll_params *params = pll->params;
1151 unsigned long cf, p_rate;
1157 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1158 p = DIV_ROUND_UP(params->vco_min, rate);
1159 p = params->round_p_to_pdiv(p, &pdiv);
1161 p = rate >= params->vco_min ? 1 : -EINVAL;
1164 if (IS_ERR_VALUE(p))
1167 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1170 /* Store P as HW value, as that is what is expected */
1171 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1174 if (p_rate > params->vco_max)
1175 p_rate = params->vco_max;
1176 cf = input_rate / cfg->m;
1177 cfg->n = p_rate / cf;
1180 if (params->sdm_ctrl_reg) {
1181 unsigned long rem = p_rate - cf * cfg->n;
1182 /* If ssc is enabled SDM enabled as well, even for integer n */
1183 if (rem || params->ssc_ctrl_reg) {
1184 u64 s = rem * PLL_SDM_COEFF;
1187 s -= PLL_SDM_COEFF / 2;
1188 cfg->sdm_data = sdin_din_to_data(s);
1192 cfg->input_rate = input_rate;
1193 cfg->output_rate = rate;
1199 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1201 * @cfg: struct tegra_clk_pll_freq_table * cfg
1204 * Fvco = Fref * NDIV / MDIV
1206 * For fractional mode:
1207 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1209 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1211 cfg->n = cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +
1212 sdin_data_to_din(cfg->sdm_data);
1213 cfg->m *= PLL_SDM_COEFF;
1216 unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1217 unsigned long parent_rate)
1219 unsigned long vco_min = params->vco_min;
1221 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1222 vco_min = min(vco_min, params->vco_min);
1227 static struct div_nmp pllx_nmp = {
1236 * PLL post divider maps - two types: quasi-linear and exponential
1239 #define PLL_QLIN_PDIV_MAX 16
1240 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1241 { .pdiv = 1, .hw_val = 0 },
1242 { .pdiv = 2, .hw_val = 1 },
1243 { .pdiv = 3, .hw_val = 2 },
1244 { .pdiv = 4, .hw_val = 3 },
1245 { .pdiv = 5, .hw_val = 4 },
1246 { .pdiv = 6, .hw_val = 5 },
1247 { .pdiv = 8, .hw_val = 6 },
1248 { .pdiv = 9, .hw_val = 7 },
1249 { .pdiv = 10, .hw_val = 8 },
1250 { .pdiv = 12, .hw_val = 9 },
1251 { .pdiv = 15, .hw_val = 10 },
1252 { .pdiv = 16, .hw_val = 11 },
1253 { .pdiv = 18, .hw_val = 12 },
1254 { .pdiv = 20, .hw_val = 13 },
1255 { .pdiv = 24, .hw_val = 14 },
1256 { .pdiv = 30, .hw_val = 15 },
1257 { .pdiv = 32, .hw_val = 16 },
1260 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1265 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1266 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1269 return pll_qlin_pdiv_to_hw[i].pdiv;
1277 #define PLL_EXPO_PDIV_MAX 7
1278 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1279 { .pdiv = 1, .hw_val = 0 },
1280 { .pdiv = 2, .hw_val = 1 },
1281 { .pdiv = 4, .hw_val = 2 },
1282 { .pdiv = 8, .hw_val = 3 },
1283 { .pdiv = 16, .hw_val = 4 },
1284 { .pdiv = 32, .hw_val = 5 },
1285 { .pdiv = 64, .hw_val = 6 },
1286 { .pdiv = 128, .hw_val = 7 },
1289 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1297 if (i <= PLL_EXPO_PDIV_MAX) {
1306 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1308 { 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */
1309 { 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */
1310 { 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */
1311 { 0, 0, 0, 0, 0, 0 },
1314 static struct tegra_clk_pll_params pll_x_params = {
1315 .input_min = 12000000,
1316 .input_max = 800000000,
1319 .vco_min = 1350000000,
1320 .vco_max = 3000000000UL,
1321 .base_reg = PLLX_BASE,
1322 .misc_reg = PLLX_MISC0,
1323 .lock_mask = PLL_BASE_LOCK,
1324 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1326 .ext_misc_reg[0] = PLLX_MISC0,
1327 .ext_misc_reg[1] = PLLX_MISC1,
1328 .ext_misc_reg[2] = PLLX_MISC2,
1329 .ext_misc_reg[3] = PLLX_MISC3,
1330 .ext_misc_reg[4] = PLLX_MISC4,
1331 .ext_misc_reg[5] = PLLX_MISC5,
1332 .iddq_reg = PLLX_MISC3,
1333 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1334 .max_p = PLL_QLIN_PDIV_MAX,
1336 .dyn_ramp_reg = PLLX_MISC2,
1339 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1340 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1341 .div_nmp = &pllx_nmp,
1342 .freq_table = pll_x_freq_table,
1343 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1344 .dyn_ramp = tegra210_pllx_dyn_ramp,
1345 .set_defaults = tegra210_pllx_set_defaults,
1346 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1349 static struct div_nmp pllc_nmp = {
1358 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1359 { 12000000, 510000000, 85, 1, 1, 0 },
1360 { 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */
1361 { 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */
1362 { 0, 0, 0, 0, 0, 0 },
1365 static struct tegra_clk_pll_params pll_c_params = {
1366 .input_min = 12000000,
1367 .input_max = 700000000,
1370 .vco_min = 600000000,
1371 .vco_max = 1200000000,
1372 .base_reg = PLLC_BASE,
1373 .misc_reg = PLLC_MISC0,
1374 .lock_mask = PLL_BASE_LOCK,
1376 .iddq_reg = PLLC_MISC1,
1377 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1378 .reset_reg = PLLC_MISC0,
1379 .reset_bit_idx = PLLCX_RESET_BIT,
1380 .max_p = PLL_QLIN_PDIV_MAX,
1381 .ext_misc_reg[0] = PLLC_MISC0,
1382 .ext_misc_reg[1] = PLLC_MISC1,
1383 .ext_misc_reg[2] = PLLC_MISC2,
1384 .ext_misc_reg[3] = PLLC_MISC3,
1385 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1386 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1388 .div_nmp = &pllc_nmp,
1389 .freq_table = pll_cx_freq_table,
1390 .flags = TEGRA_PLL_USE_LOCK,
1391 .set_defaults = _pllc_set_defaults,
1392 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1395 static struct div_nmp pllcx_nmp = {
1404 static struct tegra_clk_pll_params pll_c2_params = {
1405 .input_min = 12000000,
1406 .input_max = 700000000,
1409 .vco_min = 600000000,
1410 .vco_max = 1200000000,
1411 .base_reg = PLLC2_BASE,
1412 .misc_reg = PLLC2_MISC0,
1413 .iddq_reg = PLLC2_MISC1,
1414 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1415 .reset_reg = PLLC2_MISC0,
1416 .reset_bit_idx = PLLCX_RESET_BIT,
1417 .lock_mask = PLLCX_BASE_LOCK,
1419 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1420 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1422 .div_nmp = &pllcx_nmp,
1423 .max_p = PLL_QLIN_PDIV_MAX,
1424 .ext_misc_reg[0] = PLLC2_MISC0,
1425 .ext_misc_reg[1] = PLLC2_MISC1,
1426 .ext_misc_reg[2] = PLLC2_MISC2,
1427 .ext_misc_reg[3] = PLLC2_MISC3,
1428 .freq_table = pll_cx_freq_table,
1429 .flags = TEGRA_PLL_USE_LOCK,
1430 .set_defaults = _pllc2_set_defaults,
1431 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1434 static struct tegra_clk_pll_params pll_c3_params = {
1435 .input_min = 12000000,
1436 .input_max = 700000000,
1439 .vco_min = 600000000,
1440 .vco_max = 1200000000,
1441 .base_reg = PLLC3_BASE,
1442 .misc_reg = PLLC3_MISC0,
1443 .lock_mask = PLLCX_BASE_LOCK,
1445 .iddq_reg = PLLC3_MISC1,
1446 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1447 .reset_reg = PLLC3_MISC0,
1448 .reset_bit_idx = PLLCX_RESET_BIT,
1449 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1450 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1452 .div_nmp = &pllcx_nmp,
1453 .max_p = PLL_QLIN_PDIV_MAX,
1454 .ext_misc_reg[0] = PLLC3_MISC0,
1455 .ext_misc_reg[1] = PLLC3_MISC1,
1456 .ext_misc_reg[2] = PLLC3_MISC2,
1457 .ext_misc_reg[3] = PLLC3_MISC3,
1458 .freq_table = pll_cx_freq_table,
1459 .flags = TEGRA_PLL_USE_LOCK,
1460 .set_defaults = _pllc3_set_defaults,
1461 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1464 static struct div_nmp pllss_nmp = {
1473 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1474 { 12000000, 600000000, 50, 1, 0, 0 },
1475 { 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */
1476 { 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */
1477 { 0, 0, 0, 0, 0, 0 },
1480 static const struct clk_div_table pll_vco_post_div_table[] = {
1481 { .val = 0, .div = 1 },
1482 { .val = 1, .div = 2 },
1483 { .val = 2, .div = 3 },
1484 { .val = 3, .div = 4 },
1485 { .val = 4, .div = 5 },
1486 { .val = 5, .div = 6 },
1487 { .val = 6, .div = 8 },
1488 { .val = 7, .div = 10 },
1489 { .val = 8, .div = 12 },
1490 { .val = 9, .div = 16 },
1491 { .val = 10, .div = 12 },
1492 { .val = 11, .div = 16 },
1493 { .val = 12, .div = 20 },
1494 { .val = 13, .div = 24 },
1495 { .val = 14, .div = 32 },
1496 { .val = 0, .div = 0 },
1499 static struct tegra_clk_pll_params pll_c4_vco_params = {
1500 .input_min = 9600000,
1501 .input_max = 800000000,
1504 .vco_min = 500000000,
1505 .vco_max = 1080000000,
1506 .base_reg = PLLC4_BASE,
1507 .misc_reg = PLLC4_MISC0,
1508 .lock_mask = PLL_BASE_LOCK,
1510 .max_p = PLL_QLIN_PDIV_MAX,
1511 .ext_misc_reg[0] = PLLC4_MISC0,
1512 .iddq_reg = PLLC4_BASE,
1513 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1514 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1515 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1517 .div_nmp = &pllss_nmp,
1518 .freq_table = pll_c4_vco_freq_table,
1519 .set_defaults = tegra210_pllc4_set_defaults,
1520 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1521 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1524 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1525 { 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */
1526 { 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */
1527 { 38400000, 297600000, 93, 4, 2, 0 },
1528 { 38400000, 400000000, 125, 4, 2, 0 },
1529 { 38400000, 532800000, 111, 4, 1, 0 },
1530 { 38400000, 665600000, 104, 3, 1, 0 },
1531 { 38400000, 800000000, 125, 3, 1, 0 },
1532 { 38400000, 931200000, 97, 4, 0, 0 },
1533 { 38400000, 1065600000, 111, 4, 0, 0 },
1534 { 38400000, 1200000000, 125, 4, 0, 0 },
1535 { 38400000, 1331200000, 104, 3, 0, 0 },
1536 { 38400000, 1459200000, 76, 2, 0, 0 },
1537 { 38400000, 1600000000, 125, 3, 0, 0 },
1538 { 0, 0, 0, 0, 0, 0 },
1541 static struct div_nmp pllm_nmp = {
1544 .override_divm_shift = 0,
1547 .override_divn_shift = 8,
1550 .override_divp_shift = 27,
1553 static struct tegra_clk_pll_params pll_m_params = {
1554 .input_min = 9600000,
1555 .input_max = 500000000,
1558 .vco_min = 800000000,
1559 .vco_max = 1866000000,
1560 .base_reg = PLLM_BASE,
1561 .misc_reg = PLLM_MISC2,
1562 .lock_mask = PLL_BASE_LOCK,
1563 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1565 .iddq_reg = PLLM_MISC2,
1566 .iddq_bit_idx = PLLM_IDDQ_BIT,
1567 .max_p = PLL_QLIN_PDIV_MAX,
1568 .ext_misc_reg[0] = PLLM_MISC2,
1569 .ext_misc_reg[1] = PLLM_MISC1,
1570 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1571 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1572 .div_nmp = &pllm_nmp,
1573 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1574 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1575 .freq_table = pll_m_freq_table,
1576 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1577 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1580 static struct tegra_clk_pll_params pll_mb_params = {
1581 .input_min = 9600000,
1582 .input_max = 500000000,
1585 .vco_min = 800000000,
1586 .vco_max = 1866000000,
1587 .base_reg = PLLMB_BASE,
1588 .misc_reg = PLLMB_MISC1,
1589 .lock_mask = PLL_BASE_LOCK,
1591 .iddq_reg = PLLMB_MISC1,
1592 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1593 .max_p = PLL_QLIN_PDIV_MAX,
1594 .ext_misc_reg[0] = PLLMB_MISC1,
1595 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1596 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1597 .div_nmp = &pllm_nmp,
1598 .freq_table = pll_m_freq_table,
1599 .flags = TEGRA_PLL_USE_LOCK,
1600 .set_defaults = tegra210_pllmb_set_defaults,
1601 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1605 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1606 /* PLLE special case: use cpcon field to store cml divider value */
1607 { 672000000, 100000000, 125, 42, 0, 13 },
1608 { 624000000, 100000000, 125, 39, 0, 13 },
1609 { 336000000, 100000000, 125, 21, 0, 13 },
1610 { 312000000, 100000000, 200, 26, 0, 14 },
1611 { 38400000, 100000000, 125, 2, 0, 14 },
1612 { 12000000, 100000000, 200, 1, 0, 14 },
1613 { 0, 0, 0, 0, 0, 0 },
1616 static struct div_nmp plle_nmp = {
1625 static struct tegra_clk_pll_params pll_e_params = {
1626 .input_min = 12000000,
1627 .input_max = 800000000,
1630 .vco_min = 1600000000,
1631 .vco_max = 2500000000U,
1632 .base_reg = PLLE_BASE,
1633 .misc_reg = PLLE_MISC0,
1634 .aux_reg = PLLE_AUX,
1635 .lock_mask = PLLE_MISC_LOCK,
1636 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1638 .div_nmp = &plle_nmp,
1639 .freq_table = pll_e_freq_table,
1640 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1641 TEGRA_PLL_HAS_LOCK_ENABLE,
1642 .fixed_rate = 100000000,
1643 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1646 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1647 { 12000000, 672000000, 56, 1, 0, 0 },
1648 { 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */
1649 { 38400000, 672000000, 70, 4, 0, 0 },
1650 { 0, 0, 0, 0, 0, 0 },
1653 static struct div_nmp pllre_nmp = {
1662 static struct tegra_clk_pll_params pll_re_vco_params = {
1663 .input_min = 9600000,
1664 .input_max = 800000000,
1667 .vco_min = 350000000,
1668 .vco_max = 700000000,
1669 .base_reg = PLLRE_BASE,
1670 .misc_reg = PLLRE_MISC0,
1671 .lock_mask = PLLRE_MISC_LOCK,
1673 .max_p = PLL_QLIN_PDIV_MAX,
1674 .ext_misc_reg[0] = PLLRE_MISC0,
1675 .iddq_reg = PLLRE_MISC0,
1676 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1677 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1678 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1679 .div_nmp = &pllre_nmp,
1680 .freq_table = pll_re_vco_freq_table,
1681 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
1682 .set_defaults = tegra210_pllre_set_defaults,
1683 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1686 static struct div_nmp pllp_nmp = {
1695 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1696 { 12000000, 408000000, 34, 1, 0, 0 },
1697 { 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */
1698 { 0, 0, 0, 0, 0, 0 },
1701 static struct tegra_clk_pll_params pll_p_params = {
1702 .input_min = 9600000,
1703 .input_max = 800000000,
1706 .vco_min = 350000000,
1707 .vco_max = 700000000,
1708 .base_reg = PLLP_BASE,
1709 .misc_reg = PLLP_MISC0,
1710 .lock_mask = PLL_BASE_LOCK,
1712 .iddq_reg = PLLP_MISC0,
1713 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1714 .ext_misc_reg[0] = PLLP_MISC0,
1715 .ext_misc_reg[1] = PLLP_MISC1,
1716 .div_nmp = &pllp_nmp,
1717 .freq_table = pll_p_freq_table,
1718 .fixed_rate = 408000000,
1719 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1720 .set_defaults = tegra210_pllp_set_defaults,
1721 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1724 static struct tegra_clk_pll_params pll_a1_params = {
1725 .input_min = 12000000,
1726 .input_max = 700000000,
1729 .vco_min = 600000000,
1730 .vco_max = 1200000000,
1731 .base_reg = PLLA1_BASE,
1732 .misc_reg = PLLA1_MISC0,
1733 .lock_mask = PLLCX_BASE_LOCK,
1735 .iddq_reg = PLLA1_MISC0,
1736 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1737 .reset_reg = PLLA1_MISC0,
1738 .reset_bit_idx = PLLCX_RESET_BIT,
1739 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1740 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1741 .div_nmp = &pllc_nmp,
1742 .ext_misc_reg[0] = PLLA1_MISC0,
1743 .ext_misc_reg[1] = PLLA1_MISC1,
1744 .ext_misc_reg[2] = PLLA1_MISC2,
1745 .ext_misc_reg[3] = PLLA1_MISC3,
1746 .freq_table = pll_cx_freq_table,
1747 .flags = TEGRA_PLL_USE_LOCK,
1748 .set_defaults = _plla1_set_defaults,
1749 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1752 static struct div_nmp plla_nmp = {
1761 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
1762 { 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */
1763 { 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */
1764 { 12000000, 240000000, 60, 1, 2, 1, 0 },
1765 { 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */
1766 { 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */
1767 { 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */
1768 { 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */
1769 { 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */
1770 { 38400000, 240000000, 75, 3, 3, 1, 0 },
1771 { 0, 0, 0, 0, 0, 0, 0 },
1774 static struct tegra_clk_pll_params pll_a_params = {
1775 .input_min = 12000000,
1776 .input_max = 800000000,
1779 .vco_min = 500000000,
1780 .vco_max = 1000000000,
1781 .base_reg = PLLA_BASE,
1782 .misc_reg = PLLA_MISC0,
1783 .lock_mask = PLL_BASE_LOCK,
1785 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1786 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1787 .iddq_reg = PLLA_BASE,
1788 .iddq_bit_idx = PLLA_IDDQ_BIT,
1789 .div_nmp = &plla_nmp,
1790 .sdm_din_reg = PLLA_MISC1,
1791 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1792 .sdm_ctrl_reg = PLLA_MISC2,
1793 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
1794 .ext_misc_reg[0] = PLLA_MISC0,
1795 .ext_misc_reg[1] = PLLA_MISC1,
1796 .ext_misc_reg[2] = PLLA_MISC2,
1797 .freq_table = pll_a_freq_table,
1798 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
1799 .set_defaults = tegra210_plla_set_defaults,
1800 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1801 .set_gain = tegra210_clk_pll_set_gain,
1802 .adjust_vco = tegra210_clk_adjust_vco_min,
1805 static struct div_nmp plld_nmp = {
1814 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
1815 { 12000000, 594000000, 99, 1, 1, 0, 0 },
1816 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1817 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1818 { 0, 0, 0, 0, 0, 0, 0 },
1821 static struct tegra_clk_pll_params pll_d_params = {
1822 .input_min = 12000000,
1823 .input_max = 800000000,
1826 .vco_min = 750000000,
1827 .vco_max = 1500000000,
1828 .base_reg = PLLD_BASE,
1829 .misc_reg = PLLD_MISC0,
1830 .lock_mask = PLL_BASE_LOCK,
1832 .iddq_reg = PLLD_MISC0,
1833 .iddq_bit_idx = PLLD_IDDQ_BIT,
1834 .round_p_to_pdiv = pll_expo_p_to_pdiv,
1835 .pdiv_tohw = pll_expo_pdiv_to_hw,
1836 .div_nmp = &plld_nmp,
1837 .sdm_din_reg = PLLD_MISC0,
1838 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1839 .sdm_ctrl_reg = PLLD_MISC0,
1840 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
1841 .ext_misc_reg[0] = PLLD_MISC0,
1842 .ext_misc_reg[1] = PLLD_MISC1,
1843 .freq_table = pll_d_freq_table,
1844 .flags = TEGRA_PLL_USE_LOCK,
1846 .set_defaults = tegra210_plld_set_defaults,
1847 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1848 .set_gain = tegra210_clk_pll_set_gain,
1849 .adjust_vco = tegra210_clk_adjust_vco_min,
1852 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
1853 { 12000000, 594000000, 99, 1, 1, 0, 0xf000 },
1854 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1855 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1856 { 0, 0, 0, 0, 0, 0, 0 },
1859 /* s/w policy, always tegra_pll_ref */
1860 static struct tegra_clk_pll_params pll_d2_params = {
1861 .input_min = 12000000,
1862 .input_max = 800000000,
1865 .vco_min = 750000000,
1866 .vco_max = 1500000000,
1867 .base_reg = PLLD2_BASE,
1868 .misc_reg = PLLD2_MISC0,
1869 .lock_mask = PLL_BASE_LOCK,
1871 .iddq_reg = PLLD2_BASE,
1872 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1873 .sdm_din_reg = PLLD2_MISC3,
1874 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1875 .sdm_ctrl_reg = PLLD2_MISC1,
1876 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
1877 .ssc_ctrl_reg = PLLD2_MISC1,
1878 .ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK,
1879 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1880 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1881 .div_nmp = &pllss_nmp,
1882 .ext_misc_reg[0] = PLLD2_MISC0,
1883 .ext_misc_reg[1] = PLLD2_MISC1,
1884 .ext_misc_reg[2] = PLLD2_MISC2,
1885 .ext_misc_reg[3] = PLLD2_MISC3,
1886 .max_p = PLL_QLIN_PDIV_MAX,
1888 .freq_table = tegra210_pll_d2_freq_table,
1889 .set_defaults = tegra210_plld2_set_defaults,
1890 .flags = TEGRA_PLL_USE_LOCK,
1891 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1892 .set_gain = tegra210_clk_pll_set_gain,
1893 .adjust_vco = tegra210_clk_adjust_vco_min,
1896 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
1897 { 12000000, 270000000, 90, 1, 3, 0, 0xf000 },
1898 { 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */
1899 { 38400000, 270000000, 28, 1, 3, 0, 0xf400 },
1900 { 0, 0, 0, 0, 0, 0, 0 },
1903 static struct tegra_clk_pll_params pll_dp_params = {
1904 .input_min = 12000000,
1905 .input_max = 800000000,
1908 .vco_min = 750000000,
1909 .vco_max = 1500000000,
1910 .base_reg = PLLDP_BASE,
1911 .misc_reg = PLLDP_MISC,
1912 .lock_mask = PLL_BASE_LOCK,
1914 .iddq_reg = PLLDP_BASE,
1915 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1916 .sdm_din_reg = PLLDP_SS_CTRL2,
1917 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1918 .sdm_ctrl_reg = PLLDP_SS_CFG,
1919 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
1920 .ssc_ctrl_reg = PLLDP_SS_CFG,
1921 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
1922 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1923 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1924 .div_nmp = &pllss_nmp,
1925 .ext_misc_reg[0] = PLLDP_MISC,
1926 .ext_misc_reg[1] = PLLDP_SS_CFG,
1927 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
1928 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
1929 .max_p = PLL_QLIN_PDIV_MAX,
1931 .freq_table = pll_dp_freq_table,
1932 .set_defaults = tegra210_plldp_set_defaults,
1933 .flags = TEGRA_PLL_USE_LOCK,
1934 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1935 .set_gain = tegra210_clk_pll_set_gain,
1936 .adjust_vco = tegra210_clk_adjust_vco_min,
1939 static struct div_nmp pllu_nmp = {
1948 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
1949 { 12000000, 480000000, 40, 1, 0, 0 },
1950 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
1951 { 38400000, 480000000, 25, 2, 0, 0 },
1952 { 0, 0, 0, 0, 0, 0 },
1955 static struct tegra_clk_pll_params pll_u_vco_params = {
1956 .input_min = 9600000,
1957 .input_max = 800000000,
1960 .vco_min = 350000000,
1961 .vco_max = 700000000,
1962 .base_reg = PLLU_BASE,
1963 .misc_reg = PLLU_MISC0,
1964 .lock_mask = PLL_BASE_LOCK,
1966 .iddq_reg = PLLU_MISC0,
1967 .iddq_bit_idx = PLLU_IDDQ_BIT,
1968 .ext_misc_reg[0] = PLLU_MISC0,
1969 .ext_misc_reg[1] = PLLU_MISC1,
1970 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1971 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1972 .div_nmp = &pllu_nmp,
1973 .freq_table = pll_u_freq_table,
1974 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1975 .set_defaults = tegra210_pllu_set_defaults,
1976 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1979 struct utmi_clk_param {
1980 /* Oscillator Frequency in KHz */
1982 /* UTMIP PLL Enable Delay Count */
1983 u8 enable_delay_count;
1984 /* UTMIP PLL Stable count */
1986 /* UTMIP PLL Active delay count */
1987 u8 active_delay_count;
1988 /* UTMIP PLL Xtal frequency count */
1989 u16 xtal_freq_count;
1992 static const struct utmi_clk_param utmi_parameters[] = {
1994 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1995 .stable_count = 0x0, .active_delay_count = 0x6,
1996 .xtal_freq_count = 0x80
1998 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1999 .stable_count = 0x33, .active_delay_count = 0x05,
2000 .xtal_freq_count = 0x7f
2002 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2003 .stable_count = 0x4b, .active_delay_count = 0x06,
2004 .xtal_freq_count = 0xbb
2006 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2007 .stable_count = 0x2f, .active_delay_count = 0x08,
2008 .xtal_freq_count = 0x76
2010 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2011 .stable_count = 0x66, .active_delay_count = 0x09,
2012 .xtal_freq_count = 0xfe
2014 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2015 .stable_count = 0x41, .active_delay_count = 0x0a,
2016 .xtal_freq_count = 0xa4
2020 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2021 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2022 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2023 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2024 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2025 [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
2026 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2027 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2028 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2029 [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
2030 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2031 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2032 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2033 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2034 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2035 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2036 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2037 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2038 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2039 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2040 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2041 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2042 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2043 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2044 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2045 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2046 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2047 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2048 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2049 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2050 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2051 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2052 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2053 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2054 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2055 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2056 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2057 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2058 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2059 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2060 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2061 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2062 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2063 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2064 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2065 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2066 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2067 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2068 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2069 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2070 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2071 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2072 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2073 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2074 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2075 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2076 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2077 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2078 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2079 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2080 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2081 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2082 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2083 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2084 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2085 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2086 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2087 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2088 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2089 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2090 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2091 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2092 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2093 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2094 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2095 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2096 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2097 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2098 [tegra_clk_vfir] = { .dt_id = TEGRA210_CLK_VFIR, .present = true },
2099 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2100 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2101 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2102 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2103 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2104 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2105 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2106 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2107 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2108 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2109 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2110 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2111 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2112 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2113 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2114 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2115 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true },
2116 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2117 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2118 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2119 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2120 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2121 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2122 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2123 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2124 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2125 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2126 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2127 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2128 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2129 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2130 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2131 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2132 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2133 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2134 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2135 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2136 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2137 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2138 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2139 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2140 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2141 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2142 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2143 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2144 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2145 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2146 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2147 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2148 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2149 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2150 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2151 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2152 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2153 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2154 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2155 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2156 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2157 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
2158 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2159 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2160 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2161 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2162 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2163 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2164 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2165 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2166 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2167 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2168 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2169 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2170 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2171 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2172 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2173 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2174 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2175 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2176 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2177 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2178 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2179 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2180 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2181 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2182 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2183 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2184 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2185 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2186 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2187 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2188 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2189 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2190 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2191 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
2192 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2193 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2194 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2195 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2196 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2197 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2198 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2199 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2200 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2201 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2202 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2203 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2204 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2205 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2206 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2207 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2208 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2211 static struct tegra_devclk devclks[] __initdata = {
2212 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2213 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2214 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2215 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2216 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2217 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2218 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2219 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2220 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2221 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2222 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2223 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2224 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2225 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2226 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2227 { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 },
2228 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2229 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2230 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2231 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2232 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2233 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2234 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2235 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2236 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2237 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2238 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2239 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2240 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2241 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2242 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2243 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2244 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2245 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2246 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2247 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2248 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2249 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2250 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2251 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2252 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2253 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2254 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2255 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2256 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2257 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2258 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2259 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2260 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2261 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2262 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2263 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2264 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2265 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2266 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2267 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2268 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2269 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2270 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2271 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2272 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2273 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2274 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2275 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2276 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 },
2279 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2280 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2281 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2284 static struct clk **clks;
2286 static void tegra210_utmi_param_configure(void __iomem *clk_base)
2291 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2292 if (osc_freq == utmi_parameters[i].osc_frequency)
2296 if (i >= ARRAY_SIZE(utmi_parameters)) {
2297 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2302 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2303 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2304 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2305 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2306 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2307 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2308 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2310 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2311 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2312 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2315 reg = readl_relaxed(clk_base + PLLU_BASE);
2316 reg &= ~PLLU_BASE_CLKENABLE_USB;
2317 writel_relaxed(reg, clk_base + PLLU_BASE);
2319 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2320 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2321 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2325 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2327 /* Program UTMIP PLL stable and active counts */
2328 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2329 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2330 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2332 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2334 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
2335 active_delay_count);
2336 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2338 /* Program UTMIP PLL delay and oscillator frequency counts */
2339 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2340 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2342 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
2343 enable_delay_count);
2345 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2346 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
2349 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2350 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2352 /* Remove power downs from UTMIP PLL control bits */
2353 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2354 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2355 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2356 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2359 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2360 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2361 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2362 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2363 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2364 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2365 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2366 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2367 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2369 /* Setup HW control of UTMIPLL */
2370 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2371 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2372 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2373 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2375 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2376 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2377 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2378 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2382 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2383 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2384 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2388 /* Enable HW control UTMIPLL */
2389 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2390 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2391 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2394 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2395 void __iomem *pmc_base)
2400 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2402 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2405 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2406 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
2407 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
2410 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2412 periph_clk_enb_refcnt);
2413 clks[TEGRA210_CLK_DSIA] = clk;
2416 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2418 periph_clk_enb_refcnt);
2419 clks[TEGRA210_CLK_DSIB] = clk;
2422 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2423 ARRAY_SIZE(mux_pllmcp_clkm), 0,
2424 clk_base + CLK_SOURCE_EMC,
2425 29, 3, 0, &emc_lock);
2427 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
2429 clks[TEGRA210_CLK_MC] = clk;
2432 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
2434 clk_register_clkdev(clk, "cml0", NULL);
2435 clks[TEGRA210_CLK_CML0] = clk;
2438 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
2440 clk_register_clkdev(clk, "cml1", NULL);
2441 clks[TEGRA210_CLK_CML1] = clk;
2443 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
2446 static void __init tegra210_pll_init(void __iomem *clk_base,
2453 clk = tegra_clk_register_pllxc_tegra210("pll_c", "pll_ref", clk_base,
2454 pmc, 0, &pll_c_params, NULL);
2455 if (!WARN_ON(IS_ERR(clk)))
2456 clk_register_clkdev(clk, "pll_c", NULL);
2457 clks[TEGRA210_CLK_PLL_C] = clk;
2460 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
2461 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
2463 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
2464 clk_base + PLLC_OUT, 1, 0,
2465 CLK_SET_RATE_PARENT, 0, NULL);
2466 clk_register_clkdev(clk, "pll_c_out1", NULL);
2467 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
2470 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
2471 CLK_SET_RATE_PARENT, 1, 1);
2472 clk_register_clkdev(clk, "pll_c_ud", NULL);
2473 clks[TEGRA210_CLK_PLL_C_UD] = clk;
2476 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
2477 pmc, 0, &pll_c2_params, NULL);
2478 clk_register_clkdev(clk, "pll_c2", NULL);
2479 clks[TEGRA210_CLK_PLL_C2] = clk;
2482 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
2483 pmc, 0, &pll_c3_params, NULL);
2484 clk_register_clkdev(clk, "pll_c3", NULL);
2485 clks[TEGRA210_CLK_PLL_C3] = clk;
2488 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
2489 CLK_SET_RATE_GATE, &pll_m_params, NULL);
2490 clk_register_clkdev(clk, "pll_m", NULL);
2491 clks[TEGRA210_CLK_PLL_M] = clk;
2494 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
2495 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
2496 clk_register_clkdev(clk, "pll_mb", NULL);
2497 clks[TEGRA210_CLK_PLL_MB] = clk;
2499 clk_register_clkdev(clk, "pll_m_out1", NULL);
2500 clks[TEGRA210_CLK_PLL_M_OUT1] = clk;
2503 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
2504 CLK_SET_RATE_PARENT, 1, 1);
2505 clk_register_clkdev(clk, "pll_m_ud", NULL);
2506 clks[TEGRA210_CLK_PLL_M_UD] = clk;
2509 val = readl(clk_base + pll_u_vco_params.base_reg);
2510 val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
2511 writel(val, clk_base + pll_u_vco_params.base_reg);
2513 clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
2514 0, &pll_u_vco_params, &pll_u_lock, pll_ref_freq);
2515 clk_register_clkdev(clk, "pll_u_vco", NULL);
2516 clks[TEGRA210_CLK_PLL_U] = clk;
2519 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
2520 clk_base + PLLU_BASE, 16, 4, 0,
2521 pll_vco_post_div_table, NULL);
2522 clk_register_clkdev(clk, "pll_u_out", NULL);
2523 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
2526 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
2527 clk_base + PLLU_OUTA, 0,
2528 TEGRA_DIVIDER_ROUND_UP,
2529 8, 8, 1, &pll_u_lock);
2530 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
2531 clk_base + PLLU_OUTA, 1, 0,
2532 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
2533 clk_register_clkdev(clk, "pll_u_out1", NULL);
2534 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
2537 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
2538 clk_base + PLLU_OUTA, 0,
2539 TEGRA_DIVIDER_ROUND_UP,
2540 24, 8, 1, &pll_u_lock);
2541 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
2542 clk_base + PLLU_OUTA, 17, 16,
2543 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
2544 clk_register_clkdev(clk, "pll_u_out2", NULL);
2545 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
2547 tegra210_utmi_param_configure(clk_base);
2550 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
2551 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
2552 22, 0, &pll_u_lock);
2553 clk_register_clkdev(clk, "pll_u_480M", NULL);
2554 clks[TEGRA210_CLK_PLL_U_480M] = clk;
2557 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
2558 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
2560 clk_register_clkdev(clk, "pll_u_60M", NULL);
2561 clks[TEGRA210_CLK_PLL_U_60M] = clk;
2564 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
2565 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
2567 clk_register_clkdev(clk, "pll_u_48M", NULL);
2568 clks[TEGRA210_CLK_PLL_U_48M] = clk;
2571 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
2572 &pll_d_params, &pll_d_lock);
2573 clk_register_clkdev(clk, "pll_d", NULL);
2574 clks[TEGRA210_CLK_PLL_D] = clk;
2577 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
2578 CLK_SET_RATE_PARENT, 1, 2);
2579 clk_register_clkdev(clk, "pll_d_out0", NULL);
2580 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
2583 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
2584 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
2585 clk_register_clkdev(clk, "pll_re_vco", NULL);
2586 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
2588 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
2589 clk_base + PLLRE_BASE, 16, 5, 0,
2590 pll_vco_post_div_table, &pll_re_lock);
2591 clk_register_clkdev(clk, "pll_re_out", NULL);
2592 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
2595 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
2596 clk_base, 0, &pll_e_params, NULL);
2597 clk_register_clkdev(clk, "pll_e", NULL);
2598 clks[TEGRA210_CLK_PLL_E] = clk;
2601 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
2602 0, &pll_c4_vco_params, NULL, pll_ref_freq);
2603 clk_register_clkdev(clk, "pll_c4_vco", NULL);
2604 clks[TEGRA210_CLK_PLL_C4] = clk;
2607 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
2608 clk_base + PLLC4_BASE, 19, 4, 0,
2609 pll_vco_post_div_table, NULL);
2610 clk_register_clkdev(clk, "pll_c4_out0", NULL);
2611 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
2614 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
2615 CLK_SET_RATE_PARENT, 1, 3);
2616 clk_register_clkdev(clk, "pll_c4_out1", NULL);
2617 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
2620 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
2621 CLK_SET_RATE_PARENT, 1, 5);
2622 clk_register_clkdev(clk, "pll_c4_out2", NULL);
2623 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
2626 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
2627 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
2629 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
2630 clk_base + PLLC4_OUT, 1, 0,
2631 CLK_SET_RATE_PARENT, 0, NULL);
2632 clk_register_clkdev(clk, "pll_c4_out3", NULL);
2633 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
2636 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
2637 0, &pll_dp_params, NULL);
2638 clk_register_clkdev(clk, "pll_dp", NULL);
2639 clks[TEGRA210_CLK_PLL_DP] = clk;
2642 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
2643 0, &pll_d2_params, NULL);
2644 clk_register_clkdev(clk, "pll_d2", NULL);
2645 clks[TEGRA210_CLK_PLL_D2] = clk;
2648 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
2649 CLK_SET_RATE_PARENT, 1, 1);
2650 clk_register_clkdev(clk, "pll_d2_out0", NULL);
2651 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
2654 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
2655 CLK_SET_RATE_PARENT, 1, 2);
2656 clk_register_clkdev(clk, "pll_p_out2", NULL);
2657 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
2661 /* Tegra210 CPU clock and reset control functions */
2662 static void tegra210_wait_cpu_in_reset(u32 cpu)
2667 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2669 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2672 static void tegra210_disable_cpu_clock(u32 cpu)
2674 /* flow controller would take care in the power sequence. */
2677 #ifdef CONFIG_PM_SLEEP
2678 static void tegra210_cpu_clock_suspend(void)
2680 /* switch coresite to clk_m, save off original source */
2681 tegra210_cpu_clk_sctx.clk_csite_src =
2682 readl(clk_base + CLK_SOURCE_CSITE);
2683 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
2686 static void tegra210_cpu_clock_resume(void)
2688 writel(tegra210_cpu_clk_sctx.clk_csite_src,
2689 clk_base + CLK_SOURCE_CSITE);
2693 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
2694 .wait_for_reset = tegra210_wait_cpu_in_reset,
2695 .disable_clock = tegra210_disable_cpu_clock,
2696 #ifdef CONFIG_PM_SLEEP
2697 .suspend = tegra210_cpu_clock_suspend,
2698 .resume = tegra210_cpu_clock_resume,
2702 static const struct of_device_id pmc_match[] __initconst = {
2703 { .compatible = "nvidia,tegra210-pmc" },
2707 static struct tegra_clk_init_table init_table[] __initdata = {
2708 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
2709 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
2710 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
2711 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
2712 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
2713 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
2714 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
2715 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
2716 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
2717 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2718 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2719 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2720 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2721 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
2722 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
2723 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
2724 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 },
2725 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
2726 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
2727 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
2728 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
2729 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
2730 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
2731 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
2732 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
2733 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
2734 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
2735 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
2736 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
2737 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
2738 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
2739 { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
2740 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
2741 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
2742 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
2743 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
2744 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
2745 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
2746 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
2747 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
2748 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
2749 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
2750 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
2751 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
2752 /* This MUST be the last entry. */
2753 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
2757 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
2759 * Program an initial clock rate and enable or disable clocks needed
2760 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
2761 * called by assigning a pointer to it to tegra_clk_apply_init_table -
2762 * this will be called as an arch_initcall. No return value.
2764 static void __init tegra210_clock_apply_init_table(void)
2766 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
2770 * tegra210_clock_init - Tegra210-specific clock initialization
2771 * @np: struct device_node * of the DT node for the SoC CAR IP block
2773 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
2774 * to be called by the OF init code when a DT node with the
2775 * "nvidia,tegra210-car" string is encountered, and declared with
2776 * CLK_OF_DECLARE. No return value.
2778 static void __init tegra210_clock_init(struct device_node *np)
2780 struct device_node *node;
2781 u32 value, clk_m_div;
2783 clk_base = of_iomap(np, 0);
2785 pr_err("ioremap tegra210 CAR failed\n");
2789 node = of_find_matching_node(NULL, pmc_match);
2791 pr_err("Failed to find pmc node\n");
2796 pmc_base = of_iomap(node, 0);
2798 pr_err("Can't map pmc registers\n");
2803 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
2804 TEGRA210_CAR_BANK_COUNT);
2808 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
2809 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
2811 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
2812 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
2813 &osc_freq, &pll_ref_freq) < 0)
2816 tegra_fixed_clk_init(tegra210_clks);
2817 tegra210_pll_init(clk_base, pmc_base);
2818 tegra210_periph_clk_init(clk_base, pmc_base);
2819 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
2820 tegra210_audio_plls,
2821 ARRAY_SIZE(tegra210_audio_plls));
2822 tegra_pmc_clk_init(pmc_base, tegra210_clks);
2824 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
2825 value = clk_readl(clk_base + PLLD_BASE);
2827 clk_writel(value, clk_base + PLLD_BASE);
2829 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
2831 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
2833 tegra_add_of_provider(np);
2834 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2836 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
2838 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);