2 * DRA7 ATL (Audio Tracking Logic) clock driver
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/clk-provider.h>
20 #include <linux/slab.h>
23 #include <linux/of_address.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
27 #define DRA7_ATL_INSTANCES 4
29 #define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80))
30 #define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80))
31 #define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80))
32 #define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80))
33 #define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80))
34 #define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80))
35 #define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80))
37 #define DRA7_ATL_SWEN BIT(0)
38 #define DRA7_ATL_DIVIDER_MASK (0x1f)
39 #define DRA7_ATL_PCLKMUX BIT(0)
40 struct dra7_atl_clock_info;
42 struct dra7_atl_desc {
45 struct dra7_atl_clock_info *cinfo;
48 bool probed; /* the driver for the IP has been loaded */
49 bool valid; /* configured */
51 u32 bws; /* Baseband Word Select Mux */
52 u32 aws; /* Audio Word Select Mux */
53 u32 divider; /* Cached divider value */
56 struct dra7_atl_clock_info {
60 struct dra7_atl_desc *cdesc;
63 #define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw)
65 static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg,
68 __raw_writel(val, cinfo->iobase + reg);
71 static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg)
73 return __raw_readl(cinfo->iobase + reg);
76 static int atl_clk_enable(struct clk_hw *hw)
78 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
83 if (unlikely(!cdesc->valid))
84 dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n",
86 pm_runtime_get_sync(cdesc->cinfo->dev);
88 atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id),
90 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN);
93 cdesc->enabled = true;
98 static void atl_clk_disable(struct clk_hw *hw)
100 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
105 atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0);
106 pm_runtime_put_sync(cdesc->cinfo->dev);
109 cdesc->enabled = false;
112 static int atl_clk_is_enabled(struct clk_hw *hw)
114 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
116 return cdesc->enabled;
119 static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
120 unsigned long parent_rate)
122 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
124 return parent_rate / cdesc->divider;
127 static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
128 unsigned long *parent_rate)
132 divider = (*parent_rate + rate / 2) / rate;
133 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
134 divider = DRA7_ATL_DIVIDER_MASK + 1;
136 return *parent_rate / divider;
139 static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate,
140 unsigned long parent_rate)
142 struct dra7_atl_desc *cdesc = to_atl_desc(hw);
145 divider = ((parent_rate + rate / 2) / rate) - 1;
146 if (divider > DRA7_ATL_DIVIDER_MASK)
147 divider = DRA7_ATL_DIVIDER_MASK;
149 cdesc->divider = divider + 1;
154 const struct clk_ops atl_clk_ops = {
155 .enable = atl_clk_enable,
156 .disable = atl_clk_disable,
157 .is_enabled = atl_clk_is_enabled,
158 .recalc_rate = atl_clk_recalc_rate,
159 .round_rate = atl_clk_round_rate,
160 .set_rate = atl_clk_set_rate,
163 static void __init of_dra7_atl_clock_setup(struct device_node *node)
165 struct dra7_atl_desc *clk_hw = NULL;
166 struct clk_init_data init = { 0 };
167 const char **parent_names = NULL;
170 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
172 pr_err("%s: could not allocate dra7_atl_desc\n", __func__);
176 clk_hw->hw.init = &init;
178 init.name = node->name;
179 init.ops = &atl_clk_ops;
180 init.flags = CLK_IGNORE_UNUSED;
181 init.num_parents = of_clk_get_parent_count(node);
183 if (init.num_parents != 1) {
184 pr_err("%s: atl clock %s must have 1 parent\n", __func__,
189 parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
194 parent_names[0] = of_clk_get_parent_name(node, 0);
196 init.parent_names = parent_names;
198 clk = clk_register(NULL, &clk_hw->hw);
201 of_clk_add_provider(node, of_clk_src_simple_get, clk);
208 CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup);
210 static int of_dra7_atl_clk_probe(struct platform_device *pdev)
212 struct device_node *node = pdev->dev.of_node;
213 struct dra7_atl_clock_info *cinfo;
220 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
224 cinfo->iobase = of_iomap(node, 0);
225 cinfo->dev = &pdev->dev;
226 pm_runtime_enable(cinfo->dev);
228 pm_runtime_get_sync(cinfo->dev);
229 atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX);
231 for (i = 0; i < DRA7_ATL_INSTANCES; i++) {
232 struct device_node *cfg_node;
234 struct dra7_atl_desc *cdesc;
235 struct of_phandle_args clkspec;
239 rc = of_parse_phandle_with_args(node, "ti,provided-clocks",
243 pr_err("%s: failed to lookup atl clock %d\n", __func__,
248 clk = of_clk_get_from_provider(&clkspec);
250 cdesc = to_atl_desc(__clk_get_hw(clk));
251 cdesc->cinfo = cinfo;
254 /* Get configuration for the ATL instances */
255 snprintf(prop, sizeof(prop), "atl%u", i);
256 cfg_node = of_find_node_by_name(node, prop);
258 ret = of_property_read_u32(cfg_node, "bws",
260 ret |= of_property_read_u32(cfg_node, "aws",
264 atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i),
266 atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i),
271 cdesc->probed = true;
273 * Enable the clock if it has been asked prior to loading the
277 atl_clk_enable(__clk_get_hw(clk));
279 pm_runtime_put_sync(cinfo->dev);
284 static int of_dra7_atl_clk_remove(struct platform_device *pdev)
286 pm_runtime_disable(&pdev->dev);
291 static struct of_device_id of_dra7_atl_clk_match_tbl[] = {
292 { .compatible = "ti,dra7-atl", },
295 MODULE_DEVICE_TABLE(of, of_dra7_atl_clk_match_tbl);
297 static struct platform_driver dra7_atl_clk_driver = {
300 .owner = THIS_MODULE,
301 .of_match_table = of_dra7_atl_clk_match_tbl,
303 .probe = of_dra7_atl_clk_probe,
304 .remove = of_dra7_atl_clk_remove,
307 module_platform_driver(dra7_atl_clk_driver);
309 MODULE_DESCRIPTION("Clock driver for DRA7 Audio Tracking Logic");
310 MODULE_ALIAS("platform:dra7-atl-clock");
311 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
312 MODULE_LICENSE("GPL v2");