drivers/clocksource/exynos_mct.c

   1 /* linux/arch/arm/mach-exynos4/mct.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 MCT(Multi-Core Timer) support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/sched.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/cpu.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/delay.h>
  22 #include <linux/percpu.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_address.h>
  26 #include <linux/clocksource.h>
  27 #include <linux/sched_clock.h>
  28
  29 #define EXYNOS4_MCTREG(x)               (x)
  30 #define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
  31 #define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
  32 #define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
  33 #define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
  34 #define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
  35 #define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
  36 #define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
  37 #define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
  38 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
  39 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
  40 #define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
  41 #define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
  42 #define EXYNOS4_MCT_L_MASK              (0xffffff00)
  43
  44 #define MCT_L_TCNTB_OFFSET              (0x00)
  45 #define MCT_L_ICNTB_OFFSET              (0x08)
  46 #define MCT_L_TCON_OFFSET               (0x20)
  47 #define MCT_L_INT_CSTAT_OFFSET          (0x30)
  48 #define MCT_L_INT_ENB_OFFSET            (0x34)
  49 #define MCT_L_WSTAT_OFFSET              (0x40)
  50 #define MCT_G_TCON_START                (1 << 8)
  51 #define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
  52 #define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
  53 #define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
  54 #define MCT_L_TCON_INT_START            (1 << 1)
  55 #define MCT_L_TCON_TIMER_START          (1 << 0)
  56
  57 #define TICK_BASE_CNT   1
  58
  59 enum {
  60         MCT_INT_SPI,
  61         MCT_INT_PPI
  62 };
  63
  64 enum {
  65         MCT_G0_IRQ,
  66         MCT_G1_IRQ,
  67         MCT_G2_IRQ,
  68         MCT_G3_IRQ,
  69         MCT_L0_IRQ,
  70         MCT_L1_IRQ,
  71         MCT_L2_IRQ,
  72         MCT_L3_IRQ,
  73         MCT_L4_IRQ,
  74         MCT_L5_IRQ,
  75         MCT_L6_IRQ,
  76         MCT_L7_IRQ,
  77         MCT_NR_IRQS,
  78 };
  79
  80 static void __iomem *reg_base;
  81 static unsigned long clk_rate;
  82 static unsigned int mct_int_type;
  83 static int mct_irqs[MCT_NR_IRQS];
  84
  85 struct mct_clock_event_device {
  86         struct clock_event_device evt;
  87         unsigned long base;
  88         char name[10];
  89 };
  90
  91 static void exynos4_mct_write(unsigned int value, unsigned long offset)
  92 {
  93         unsigned long stat_addr;
  94         u32 mask;
  95         u32 i;
  96
  97         __raw_writel(value, reg_base + offset);
  98
  99         if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
 100                 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
 101                 switch (offset & EXYNOS4_MCT_L_MASK) {
 102                 case MCT_L_TCON_OFFSET:
 103                         mask = 1 << 3;          /* L_TCON write status */
 104                         break;
 105                 case MCT_L_ICNTB_OFFSET:
 106                         mask = 1 << 1;          /* L_ICNTB write status */
 107                         break;
 108                 case MCT_L_TCNTB_OFFSET:
 109                         mask = 1 << 0;          /* L_TCNTB write status */
 110                         break;
 111                 default:
 112                         return;
 113                 }
 114         } else {
 115                 switch (offset) {
 116                 case EXYNOS4_MCT_G_TCON:
 117                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 118                         mask = 1 << 16;         /* G_TCON write status */
 119                         break;
 120                 case EXYNOS4_MCT_G_COMP0_L:
 121                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 122                         mask = 1 << 0;          /* G_COMP0_L write status */
 123                         break;
 124                 case EXYNOS4_MCT_G_COMP0_U:
 125                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 126                         mask = 1 << 1;          /* G_COMP0_U write status */
 127                         break;
 128                 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
 129                         stat_addr = EXYNOS4_MCT_G_WSTAT;
 130                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
 131                         break;
 132                 case EXYNOS4_MCT_G_CNT_L:
 133                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 134                         mask = 1 << 0;          /* G_CNT_L write status */
 135                         break;
 136                 case EXYNOS4_MCT_G_CNT_U:
 137                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
 138                         mask = 1 << 1;          /* G_CNT_U write status */
 139                         break;
 140                 default:
 141                         return;
 142                 }
 143         }
 144
 145         /* Wait maximum 1 ms until written values are applied */
 146         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
 147                 if (__raw_readl(reg_base + stat_addr) & mask) {
 148                         __raw_writel(mask, reg_base + stat_addr);
 149                         return;
 150                 }
 151
 152         panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 153 }
 154
 155 /* Clocksource handling */
 156 static void exynos4_mct_frc_start(u32 hi, u32 lo)
 157 {
 158         u32 reg;
 159
 160         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
 161         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
 162
 163         reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
 164         reg |= MCT_G_TCON_START;
 165         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 166 }
 167
 168 static cycle_t exynos4_frc_read(struct clocksource *cs)
 169 {
 170         unsigned int lo, hi;
 171         u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
 172
 173         do {
 174                 hi = hi2;
 175                 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
 176                 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
 177         } while (hi != hi2);
 178
 179         return ((cycle_t)hi << 32) | lo;
 180 }
 181
 182 static void exynos4_frc_resume(struct clocksource *cs)
 183 {
 184         exynos4_mct_frc_start(0, 0);
 185 }
 186
 187 struct clocksource mct_frc = {
 188         .name           = "mct-frc",
 189         .rating         = 400,
 190         .read           = exynos4_frc_read,
 191         .mask           = CLOCKSOURCE_MASK(64),
 192         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 193         .resume         = exynos4_frc_resume,
 194 };
 195
 196 static u64 notrace exynos4_read_sched_clock(void)
 197 {
 198         return exynos4_frc_read(&mct_frc);
 199 }
 200
 201 static void __init exynos4_clocksource_init(void)
 202 {
 203         exynos4_mct_frc_start(0, 0);
 204
 205         if (clocksource_register_hz(&mct_frc, clk_rate))
 206                 panic("%s: can't register clocksource\n", mct_frc.name);
 207
 208         sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
 209 }
 210
 211 static void exynos4_mct_comp0_stop(void)
 212 {
 213         unsigned int tcon;
 214
 215         tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
 216         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 217
 218         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
 219         exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
 220 }
 221
 222 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
 223                                     unsigned long cycles)
 224 {
 225         unsigned int tcon;
 226         cycle_t comp_cycle;
 227
 228         tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
 229
 230         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 231                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
 232                 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
 233         }
 234
 235         comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
 236         exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
 237         exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
 238
 239         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
 240
 241         tcon |= MCT_G_TCON_COMP0_ENABLE;
 242         exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
 243 }
 244
 245 static int exynos4_comp_set_next_event(unsigned long cycles,
 246                                        struct clock_event_device *evt)
 247 {
 248         exynos4_mct_comp0_start(evt->mode, cycles);
 249
 250         return 0;
 251 }
 252
 253 static void exynos4_comp_set_mode(enum clock_event_mode mode,
 254                                   struct clock_event_device *evt)
 255 {
 256         unsigned long cycles_per_jiffy;
 257         exynos4_mct_comp0_stop();
 258
 259         switch (mode) {
 260         case CLOCK_EVT_MODE_PERIODIC:
 261                 cycles_per_jiffy =
 262                         (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
 263                 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
 264                 break;
 265
 266         case CLOCK_EVT_MODE_ONESHOT:
 267         case CLOCK_EVT_MODE_UNUSED:
 268         case CLOCK_EVT_MODE_SHUTDOWN:
 269         case CLOCK_EVT_MODE_RESUME:
 270                 break;
 271         }
 272 }
 273
 274 static struct clock_event_device mct_comp_device = {
 275         .name           = "mct-comp",
 276         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 277         .rating         = 250,
 278         .set_next_event = exynos4_comp_set_next_event,
 279         .set_mode       = exynos4_comp_set_mode,
 280 };
 281
 282 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
 283 {
 284         struct clock_event_device *evt = dev_id;
 285
 286         exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
 287
 288         evt->event_handler(evt);
 289
 290         return IRQ_HANDLED;
 291 }
 292
 293 static struct irqaction mct_comp_event_irq = {
 294         .name           = "mct_comp_irq",
 295         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 296         .handler        = exynos4_mct_comp_isr,
 297         .dev_id         = &mct_comp_device,
 298 };
 299
 300 static void exynos4_clockevent_init(void)
 301 {
 302         mct_comp_device.cpumask = cpumask_of(0);
 303         clockevents_config_and_register(&mct_comp_device, clk_rate,
 304                                         0xf, 0xffffffff);
 305         setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 306 }
 307
 308 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
 309
 310 /* Clock event handling */
 311 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 312 {
 313         unsigned long tmp;
 314         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
 315         unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 316
 317         tmp = __raw_readl(reg_base + offset);
 318         if (tmp & mask) {
 319                 tmp &= ~mask;
 320                 exynos4_mct_write(tmp, offset);
 321         }
 322 }
 323
 324 static void exynos4_mct_tick_start(unsigned long cycles,
 325                                    struct mct_clock_event_device *mevt)
 326 {
 327         unsigned long tmp;
 328
 329         exynos4_mct_tick_stop(mevt);
 330
 331         tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
 332
 333         /* update interrupt count buffer */
 334         exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
 335
 336         /* enable MCT tick interrupt */
 337         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 338
 339         tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
 340         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
 341                MCT_L_TCON_INTERVAL_MODE;
 342         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
 343 }
 344
 345 static int exynos4_tick_set_next_event(unsigned long cycles,
 346                                        struct clock_event_device *evt)
 347 {
 348         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 349
 350         exynos4_mct_tick_start(cycles, mevt);
 351
 352         return 0;
 353 }
 354
 355 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
 356                                          struct clock_event_device *evt)
 357 {
 358         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 359         unsigned long cycles_per_jiffy;
 360
 361         exynos4_mct_tick_stop(mevt);
 362
 363         switch (mode) {
 364         case CLOCK_EVT_MODE_PERIODIC:
 365                 cycles_per_jiffy =
 366                         (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
 367                 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
 368                 break;
 369
 370         case CLOCK_EVT_MODE_ONESHOT:
 371         case CLOCK_EVT_MODE_UNUSED:
 372         case CLOCK_EVT_MODE_SHUTDOWN:
 373         case CLOCK_EVT_MODE_RESUME:
 374                 break;
 375         }
 376 }
 377
 378 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 379 {
 380         struct clock_event_device *evt = &mevt->evt;
 381
 382         /*
 383          * This is for supporting oneshot mode.
 384          * Mct would generate interrupt periodically
 385          * without explicit stopping.
 386          */
 387         if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
 388                 exynos4_mct_tick_stop(mevt);
 389
 390         /* Clear the MCT tick interrupt */
 391         if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
 392                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
 393                 return 1;
 394         } else {
 395                 return 0;
 396         }
 397 }
 398
 399 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
 400 {
 401         struct mct_clock_event_device *mevt = dev_id;
 402         struct clock_event_device *evt = &mevt->evt;
 403
 404         exynos4_mct_tick_clear(mevt);
 405
 406         evt->event_handler(evt);
 407
 408         return IRQ_HANDLED;
 409 }
 410
 411 static int exynos4_local_timer_setup(struct clock_event_device *evt)
 412 {
 413         struct mct_clock_event_device *mevt;
 414         unsigned int cpu = smp_processor_id();
 415
 416         mevt = container_of(evt, struct mct_clock_event_device, evt);
 417
 418         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
 419         snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
 420
 421         evt->name = mevt->name;
 422         evt->cpumask = cpumask_of(cpu);
 423         evt->set_next_event = exynos4_tick_set_next_event;
 424         evt->set_mode = exynos4_tick_set_mode;
 425         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 426         evt->rating = 450;
 427
 428         exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 429
 430         if (mct_int_type == MCT_INT_SPI) {
 431                 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
 432                 if (request_irq(evt->irq, exynos4_mct_tick_isr,
 433                                 IRQF_TIMER | IRQF_NOBALANCING,
 434                                 evt->name, mevt)) {
 435                         pr_err("exynos-mct: cannot register IRQ %d\n",
 436                                 evt->irq);
 437                         return -EIO;
 438                 }
 439                 irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
 440         } else {
 441                 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
 442         }
 443         clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
 444                                         0xf, 0x7fffffff);
 445
 446         return 0;
 447 }
 448
 449 static void exynos4_local_timer_stop(struct clock_event_device *evt)
 450 {
 451         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 452         if (mct_int_type == MCT_INT_SPI)
 453                 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
 454         else
 455                 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 456 }
 457
 458 static int exynos4_mct_cpu_notify(struct notifier_block *self,
 459                                            unsigned long action, void *hcpu)
 460 {
 461         struct mct_clock_event_device *mevt;
 462
 463         /*
 464          * Grab cpu pointer in each case to avoid spurious
 465          * preemptible warnings
 466          */
 467         switch (action & ~CPU_TASKS_FROZEN) {
 468         case CPU_STARTING:
 469                 mevt = this_cpu_ptr(&percpu_mct_tick);
 470                 exynos4_local_timer_setup(&mevt->evt);
 471                 break;
 472         case CPU_DYING:
 473                 mevt = this_cpu_ptr(&percpu_mct_tick);
 474                 exynos4_local_timer_stop(&mevt->evt);
 475                 break;
 476         }
 477
 478         return NOTIFY_OK;
 479 }
 480
 481 static struct notifier_block exynos4_mct_cpu_nb = {
 482         .notifier_call = exynos4_mct_cpu_notify,
 483 };
 484
 485 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
 486 {
 487         int err;
 488         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
 489         struct clk *mct_clk, *tick_clk;
 490
 491         tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
 492                                 clk_get(NULL, "fin_pll");
 493         if (IS_ERR(tick_clk))
 494                 panic("%s: unable to determine tick clock rate\n", __func__);
 495         clk_rate = clk_get_rate(tick_clk);
 496
 497         mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
 498         if (IS_ERR(mct_clk))
 499                 panic("%s: unable to retrieve mct clock instance\n", __func__);
 500         clk_prepare_enable(mct_clk);
 501
 502         reg_base = base;
 503         if (!reg_base)
 504                 panic("%s: unable to ioremap mct address space\n", __func__);
 505
 506         if (mct_int_type == MCT_INT_PPI) {
 507
 508                 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
 509                                          exynos4_mct_tick_isr, "MCT",
 510                                          &percpu_mct_tick);
 511                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
 512                      mct_irqs[MCT_L0_IRQ], err);
 513         } else {
 514                 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
 515         }
 516
 517         err = register_cpu_notifier(&exynos4_mct_cpu_nb);
 518         if (err)
 519                 goto out_irq;
 520
 521         /* Immediately configure the timer on the boot CPU */
 522         exynos4_local_timer_setup(&mevt->evt);
 523         return;
 524
 525 out_irq:
 526         free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
 527 }
 528
 529 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
 530 {
 531         mct_irqs[MCT_G0_IRQ] = irq_g0;
 532         mct_irqs[MCT_L0_IRQ] = irq_l0;
 533         mct_irqs[MCT_L1_IRQ] = irq_l1;
 534         mct_int_type = MCT_INT_SPI;
 535
 536         exynos4_timer_resources(NULL, base);
 537         exynos4_clocksource_init();
 538         exynos4_clockevent_init();
 539 }
 540
 541 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
 542 {
 543         u32 nr_irqs, i;
 544
 545         mct_int_type = int_type;
 546
 547         /* This driver uses only one global timer interrupt */
 548         mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
 549
 550         /*
 551          * Find out the number of local irqs specified. The local
 552          * timer irqs are specified after the four global timer
 553          * irqs are specified.
 554          */
 555 #ifdef CONFIG_OF
 556         nr_irqs = of_irq_count(np);
 557 #else
 558         nr_irqs = 0;
 559 #endif
 560         for (i = MCT_L0_IRQ; i < nr_irqs; i++)
 561                 mct_irqs[i] = irq_of_parse_and_map(np, i);
 562
 563         exynos4_timer_resources(np, of_iomap(np, 0));
 564         exynos4_clocksource_init();
 565         exynos4_clockevent_init();
 566 }
 567
 568
 569 static void __init mct_init_spi(struct device_node *np)
 570 {
 571         return mct_init_dt(np, MCT_INT_SPI);
 572 }
 573
 574 static void __init mct_init_ppi(struct device_node *np)
 575 {
 576         return mct_init_dt(np, MCT_INT_PPI);
 577 }
 578 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
 579 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);