drivers/crypto/omap-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP AES HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) "%20s: " fmt, __func__
  17 #define prn(num) pr_debug(#num "=%d\n", num)
  18 #define prx(num) pr_debug(#num "=%x\n", num)
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_address.h>
  33 #include <linux/io.h>
  34 #include <linux/crypto.h>
  35 #include <linux/interrupt.h>
  36 #include <crypto/scatterwalk.h>
  37 #include <crypto/aes.h>
  38 #include <crypto/algapi.h>
  39 #include <crypto/engine.h>
  40
  41 #define DST_MAXBURST                    4
  42 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  43
  44 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
  45
  46 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  47    number. For example 7:0 */
  48 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  49 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  50
  51 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  52                                                 ((x ^ 0x01) * 0x04))
  53 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  54
  55 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  56 #define AES_REG_CTRL_CTR_WIDTH_MASK     GENMASK(8, 7)
  57 #define AES_REG_CTRL_CTR_WIDTH_32       0
  58 #define AES_REG_CTRL_CTR_WIDTH_64       BIT(7)
  59 #define AES_REG_CTRL_CTR_WIDTH_96       BIT(8)
  60 #define AES_REG_CTRL_CTR_WIDTH_128      GENMASK(8, 7)
  61 #define AES_REG_CTRL_CTR                BIT(6)
  62 #define AES_REG_CTRL_CBC                BIT(5)
  63 #define AES_REG_CTRL_KEY_SIZE           GENMASK(4, 3)
  64 #define AES_REG_CTRL_DIRECTION          BIT(2)
  65 #define AES_REG_CTRL_INPUT_READY        BIT(1)
  66 #define AES_REG_CTRL_OUTPUT_READY       BIT(0)
  67 #define AES_REG_CTRL_MASK               GENMASK(24, 2)
  68
  69 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  70
  71 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  72
  73 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  74 #define AES_REG_MASK_SIDLE              BIT(6)
  75 #define AES_REG_MASK_START              BIT(5)
  76 #define AES_REG_MASK_DMA_OUT_EN         BIT(3)
  77 #define AES_REG_MASK_DMA_IN_EN          BIT(2)
  78 #define AES_REG_MASK_SOFTRESET          BIT(1)
  79 #define AES_REG_AUTOIDLE                BIT(0)
  80
  81 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  82
  83 #define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  84 #define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  85 #define AES_REG_IRQ_DATA_IN            BIT(1)
  86 #define AES_REG_IRQ_DATA_OUT           BIT(2)
  87 #define DEFAULT_TIMEOUT         (5*HZ)
  88
  89 #define DEFAULT_AUTOSUSPEND_DELAY       1000
  90
  91 #define FLAGS_MODE_MASK         0x000f
  92 #define FLAGS_ENCRYPT           BIT(0)
  93 #define FLAGS_CBC               BIT(1)
  94 #define FLAGS_GIV               BIT(2)
  95 #define FLAGS_CTR               BIT(3)
  96
  97 #define FLAGS_INIT              BIT(4)
  98 #define FLAGS_FAST              BIT(5)
  99 #define FLAGS_BUSY              BIT(6)
 100
 101 #define AES_BLOCK_WORDS         (AES_BLOCK_SIZE >> 2)
 102
 103 struct omap_aes_ctx {
 104         struct omap_aes_dev *dd;
 105
 106         int             keylen;
 107         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
 108         unsigned long   flags;
 109 };
 110
 111 struct omap_aes_reqctx {
 112         unsigned long mode;
 113 };
 114
 115 #define OMAP_AES_QUEUE_LENGTH   1
 116 #define OMAP_AES_CACHE_SIZE     0
 117
 118 struct omap_aes_algs_info {
 119         struct crypto_alg       *algs_list;
 120         unsigned int            size;
 121         unsigned int            registered;
 122 };
 123
 124 struct omap_aes_pdata {
 125         struct omap_aes_algs_info       *algs_info;
 126         unsigned int    algs_info_size;
 127
 128         void            (*trigger)(struct omap_aes_dev *dd, int length);
 129
 130         u32             key_ofs;
 131         u32             iv_ofs;
 132         u32             ctrl_ofs;
 133         u32             data_ofs;
 134         u32             rev_ofs;
 135         u32             mask_ofs;
 136         u32             irq_enable_ofs;
 137         u32             irq_status_ofs;
 138
 139         u32             dma_enable_in;
 140         u32             dma_enable_out;
 141         u32             dma_start;
 142
 143         u32             major_mask;
 144         u32             major_shift;
 145         u32             minor_mask;
 146         u32             minor_shift;
 147 };
 148
 149 struct omap_aes_dev {
 150         struct list_head        list;
 151         unsigned long           phys_base;
 152         void __iomem            *io_base;
 153         struct omap_aes_ctx     *ctx;
 154         struct device           *dev;
 155         unsigned long           flags;
 156         int                     err;
 157
 158         struct tasklet_struct   done_task;
 159
 160         struct ablkcipher_request       *req;
 161         struct crypto_engine            *engine;
 162
 163         /*
 164          * total is used by PIO mode for book keeping so introduce
 165          * variable total_save as need it to calc page_order
 166          */
 167         size_t                          total;
 168         size_t                          total_save;
 169
 170         struct scatterlist              *in_sg;
 171         struct scatterlist              *out_sg;
 172
 173         /* Buffers for copying for unaligned cases */
 174         struct scatterlist              in_sgl;
 175         struct scatterlist              out_sgl;
 176         struct scatterlist              *orig_out;
 177         int                             sgs_copied;
 178
 179         struct scatter_walk             in_walk;
 180         struct scatter_walk             out_walk;
 181         struct dma_chan         *dma_lch_in;
 182         struct dma_chan         *dma_lch_out;
 183         int                     in_sg_len;
 184         int                     out_sg_len;
 185         int                     pio_only;
 186         const struct omap_aes_pdata     *pdata;
 187 };
 188
 189 /* keep registered devices data here */
 190 static LIST_HEAD(dev_list);
 191 static DEFINE_SPINLOCK(list_lock);
 192
 193 #ifdef DEBUG
 194 #define omap_aes_read(dd, offset)                               \
 195 ({                                                              \
 196         int _read_ret;                                          \
 197         _read_ret = __raw_readl(dd->io_base + offset);          \
 198         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 199                  offset, _read_ret);                            \
 200         _read_ret;                                              \
 201 })
 202 #else
 203 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 204 {
 205         return __raw_readl(dd->io_base + offset);
 206 }
 207 #endif
 208
 209 #ifdef DEBUG
 210 #define omap_aes_write(dd, offset, value)                               \
 211         do {                                                            \
 212                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 213                          offset, value);                                \
 214                 __raw_writel(value, dd->io_base + offset);              \
 215         } while (0)
 216 #else
 217 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 218                                   u32 value)
 219 {
 220         __raw_writel(value, dd->io_base + offset);
 221 }
 222 #endif
 223
 224 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 225                                         u32 value, u32 mask)
 226 {
 227         u32 val;
 228
 229         val = omap_aes_read(dd, offset);
 230         val &= ~mask;
 231         val |= value;
 232         omap_aes_write(dd, offset, val);
 233 }
 234
 235 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 236                                         u32 *value, int count)
 237 {
 238         for (; count--; value++, offset += 4)
 239                 omap_aes_write(dd, offset, *value);
 240 }
 241
 242 static int omap_aes_hw_init(struct omap_aes_dev *dd)
 243 {
 244         int err;
 245
 246         if (!(dd->flags & FLAGS_INIT)) {
 247                 dd->flags |= FLAGS_INIT;
 248                 dd->err = 0;
 249         }
 250
 251         err = pm_runtime_get_sync(dd->dev);
 252         if (err < 0) {
 253                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 254                 return err;
 255         }
 256
 257         return 0;
 258 }
 259
 260 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 261 {
 262         unsigned int key32;
 263         int i, err;
 264         u32 val;
 265
 266         err = omap_aes_hw_init(dd);
 267         if (err)
 268                 return err;
 269
 270         key32 = dd->ctx->keylen / sizeof(u32);
 271
 272         /* it seems a key should always be set even if it has not changed */
 273         for (i = 0; i < key32; i++) {
 274                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 275                         __le32_to_cpu(dd->ctx->key[i]));
 276         }
 277
 278         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 279                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 280
 281         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 282         if (dd->flags & FLAGS_CBC)
 283                 val |= AES_REG_CTRL_CBC;
 284         if (dd->flags & FLAGS_CTR)
 285                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
 286
 287         if (dd->flags & FLAGS_ENCRYPT)
 288                 val |= AES_REG_CTRL_DIRECTION;
 289
 290         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
 291
 292         return 0;
 293 }
 294
 295 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 296 {
 297         u32 mask, val;
 298
 299         val = dd->pdata->dma_start;
 300
 301         if (dd->dma_lch_out != NULL)
 302                 val |= dd->pdata->dma_enable_out;
 303         if (dd->dma_lch_in != NULL)
 304                 val |= dd->pdata->dma_enable_in;
 305
 306         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 307                dd->pdata->dma_start;
 308
 309         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 310
 311 }
 312
 313 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 314 {
 315         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 316         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 317
 318         omap_aes_dma_trigger_omap2(dd, length);
 319 }
 320
 321 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 322 {
 323         u32 mask;
 324
 325         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 326                dd->pdata->dma_start;
 327
 328         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 329 }
 330
 331 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 332 {
 333         struct omap_aes_dev *dd;
 334
 335         spin_lock_bh(&list_lock);
 336         dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
 337         list_move_tail(&dd->list, &dev_list);
 338         ctx->dd = dd;
 339         spin_unlock_bh(&list_lock);
 340
 341         return dd;
 342 }
 343
 344 static void omap_aes_dma_out_callback(void *data)
 345 {
 346         struct omap_aes_dev *dd = data;
 347
 348         /* dma_lch_out - completed */
 349         tasklet_schedule(&dd->done_task);
 350 }
 351
 352 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 353 {
 354         int err;
 355
 356         dd->dma_lch_out = NULL;
 357         dd->dma_lch_in = NULL;
 358
 359         dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
 360         if (IS_ERR(dd->dma_lch_in)) {
 361                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 362                 return PTR_ERR(dd->dma_lch_in);
 363         }
 364
 365         dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
 366         if (IS_ERR(dd->dma_lch_out)) {
 367                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 368                 err = PTR_ERR(dd->dma_lch_out);
 369                 goto err_dma_out;
 370         }
 371
 372         return 0;
 373
 374 err_dma_out:
 375         dma_release_channel(dd->dma_lch_in);
 376
 377         return err;
 378 }
 379
 380 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 381 {
 382         if (dd->pio_only)
 383                 return;
 384
 385         dma_release_channel(dd->dma_lch_out);
 386         dma_release_channel(dd->dma_lch_in);
 387 }
 388
 389 static void sg_copy_buf(void *buf, struct scatterlist *sg,
 390                               unsigned int start, unsigned int nbytes, int out)
 391 {
 392         struct scatter_walk walk;
 393
 394         if (!nbytes)
 395                 return;
 396
 397         scatterwalk_start(&walk, sg);
 398         scatterwalk_advance(&walk, start);
 399         scatterwalk_copychunks(buf, &walk, nbytes, out);
 400         scatterwalk_done(&walk, out, 0);
 401 }
 402
 403 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 404                 struct scatterlist *in_sg, struct scatterlist *out_sg,
 405                 int in_sg_len, int out_sg_len)
 406 {
 407         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 408         struct omap_aes_dev *dd = ctx->dd;
 409         struct dma_async_tx_descriptor *tx_in, *tx_out;
 410         struct dma_slave_config cfg;
 411         int ret;
 412
 413         if (dd->pio_only) {
 414                 scatterwalk_start(&dd->in_walk, dd->in_sg);
 415                 scatterwalk_start(&dd->out_walk, dd->out_sg);
 416
 417                 /* Enable DATAIN interrupt and let it take
 418                    care of the rest */
 419                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 420                 return 0;
 421         }
 422
 423         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 424
 425         memset(&cfg, 0, sizeof(cfg));
 426
 427         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 428         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 429         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 430         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 431         cfg.src_maxburst = DST_MAXBURST;
 432         cfg.dst_maxburst = DST_MAXBURST;
 433
 434         /* IN */
 435         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 436         if (ret) {
 437                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 438                         ret);
 439                 return ret;
 440         }
 441
 442         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 443                                         DMA_MEM_TO_DEV,
 444                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 445         if (!tx_in) {
 446                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 447                 return -EINVAL;
 448         }
 449
 450         /* No callback necessary */
 451         tx_in->callback_param = dd;
 452
 453         /* OUT */
 454         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 455         if (ret) {
 456                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 457                         ret);
 458                 return ret;
 459         }
 460
 461         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 462                                         DMA_DEV_TO_MEM,
 463                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 464         if (!tx_out) {
 465                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 466                 return -EINVAL;
 467         }
 468
 469         tx_out->callback = omap_aes_dma_out_callback;
 470         tx_out->callback_param = dd;
 471
 472         dmaengine_submit(tx_in);
 473         dmaengine_submit(tx_out);
 474
 475         dma_async_issue_pending(dd->dma_lch_in);
 476         dma_async_issue_pending(dd->dma_lch_out);
 477
 478         /* start DMA */
 479         dd->pdata->trigger(dd, dd->total);
 480
 481         return 0;
 482 }
 483
 484 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 485 {
 486         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 487                                         crypto_ablkcipher_reqtfm(dd->req));
 488         int err;
 489
 490         pr_debug("total: %d\n", dd->total);
 491
 492         if (!dd->pio_only) {
 493                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 494                                  DMA_TO_DEVICE);
 495                 if (!err) {
 496                         dev_err(dd->dev, "dma_map_sg() error\n");
 497                         return -EINVAL;
 498                 }
 499
 500                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 501                                  DMA_FROM_DEVICE);
 502                 if (!err) {
 503                         dev_err(dd->dev, "dma_map_sg() error\n");
 504                         return -EINVAL;
 505                 }
 506         }
 507
 508         err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 509                                  dd->out_sg_len);
 510         if (err && !dd->pio_only) {
 511                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 512                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 513                              DMA_FROM_DEVICE);
 514         }
 515
 516         return err;
 517 }
 518
 519 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 520 {
 521         struct ablkcipher_request *req = dd->req;
 522
 523         pr_debug("err: %d\n", err);
 524
 525         crypto_finalize_cipher_request(dd->engine, req, err);
 526
 527         pm_runtime_mark_last_busy(dd->dev);
 528         pm_runtime_put_autosuspend(dd->dev);
 529 }
 530
 531 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 532 {
 533         pr_debug("total: %d\n", dd->total);
 534
 535         omap_aes_dma_stop(dd);
 536
 537
 538         return 0;
 539 }
 540
 541 static int omap_aes_check_aligned(struct scatterlist *sg, int total)
 542 {
 543         int len = 0;
 544
 545         if (!IS_ALIGNED(total, AES_BLOCK_SIZE))
 546                 return -EINVAL;
 547
 548         while (sg) {
 549                 if (!IS_ALIGNED(sg->offset, 4))
 550                         return -1;
 551                 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
 552                         return -1;
 553
 554                 len += sg->length;
 555                 sg = sg_next(sg);
 556         }
 557
 558         if (len != total)
 559                 return -1;
 560
 561         return 0;
 562 }
 563
 564 static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
 565 {
 566         void *buf_in, *buf_out;
 567         int pages, total;
 568
 569         total = ALIGN(dd->total, AES_BLOCK_SIZE);
 570         pages = get_order(total);
 571
 572         buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
 573         buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
 574
 575         if (!buf_in || !buf_out) {
 576                 pr_err("Couldn't allocated pages for unaligned cases.\n");
 577                 return -1;
 578         }
 579
 580         dd->orig_out = dd->out_sg;
 581
 582         sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
 583
 584         sg_init_table(&dd->in_sgl, 1);
 585         sg_set_buf(&dd->in_sgl, buf_in, total);
 586         dd->in_sg = &dd->in_sgl;
 587         dd->in_sg_len = 1;
 588
 589         sg_init_table(&dd->out_sgl, 1);
 590         sg_set_buf(&dd->out_sgl, buf_out, total);
 591         dd->out_sg = &dd->out_sgl;
 592         dd->out_sg_len = 1;
 593
 594         return 0;
 595 }
 596
 597 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 598                                  struct ablkcipher_request *req)
 599 {
 600         if (req)
 601                 return crypto_transfer_cipher_request_to_engine(dd->engine, req);
 602
 603         return 0;
 604 }
 605
 606 static int omap_aes_prepare_req(struct crypto_engine *engine,
 607                                 struct ablkcipher_request *req)
 608 {
 609         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 610                         crypto_ablkcipher_reqtfm(req));
 611         struct omap_aes_dev *dd = ctx->dd;
 612         struct omap_aes_reqctx *rctx;
 613
 614         if (!dd)
 615                 return -ENODEV;
 616
 617         /* assign new request to device */
 618         dd->req = req;
 619         dd->total = req->nbytes;
 620         dd->total_save = req->nbytes;
 621         dd->in_sg = req->src;
 622         dd->out_sg = req->dst;
 623
 624         dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
 625         if (dd->in_sg_len < 0)
 626                 return dd->in_sg_len;
 627
 628         dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
 629         if (dd->out_sg_len < 0)
 630                 return dd->out_sg_len;
 631
 632         if (omap_aes_check_aligned(dd->in_sg, dd->total) ||
 633             omap_aes_check_aligned(dd->out_sg, dd->total)) {
 634                 if (omap_aes_copy_sgs(dd))
 635                         pr_err("Failed to copy SGs for unaligned cases\n");
 636                 dd->sgs_copied = 1;
 637         } else {
 638                 dd->sgs_copied = 0;
 639         }
 640
 641         rctx = ablkcipher_request_ctx(req);
 642         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 643         rctx->mode &= FLAGS_MODE_MASK;
 644         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 645
 646         dd->ctx = ctx;
 647         ctx->dd = dd;
 648
 649         return omap_aes_write_ctrl(dd);
 650 }
 651
 652 static int omap_aes_crypt_req(struct crypto_engine *engine,
 653                               struct ablkcipher_request *req)
 654 {
 655         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 656                         crypto_ablkcipher_reqtfm(req));
 657         struct omap_aes_dev *dd = ctx->dd;
 658
 659         if (!dd)
 660                 return -ENODEV;
 661
 662         return omap_aes_crypt_dma_start(dd);
 663 }
 664
 665 static void omap_aes_done_task(unsigned long data)
 666 {
 667         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 668         void *buf_in, *buf_out;
 669         int pages, len;
 670
 671         pr_debug("enter done_task\n");
 672
 673         if (!dd->pio_only) {
 674                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 675                                        DMA_FROM_DEVICE);
 676                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 677                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 678                              DMA_FROM_DEVICE);
 679                 omap_aes_crypt_dma_stop(dd);
 680         }
 681
 682         if (dd->sgs_copied) {
 683                 buf_in = sg_virt(&dd->in_sgl);
 684                 buf_out = sg_virt(&dd->out_sgl);
 685
 686                 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
 687
 688                 len = ALIGN(dd->total_save, AES_BLOCK_SIZE);
 689                 pages = get_order(len);
 690                 free_pages((unsigned long)buf_in, pages);
 691                 free_pages((unsigned long)buf_out, pages);
 692         }
 693
 694         omap_aes_finish_req(dd, 0);
 695
 696         pr_debug("exit\n");
 697 }
 698
 699 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 700 {
 701         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 702                         crypto_ablkcipher_reqtfm(req));
 703         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 704         struct omap_aes_dev *dd;
 705
 706         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 707                   !!(mode & FLAGS_ENCRYPT),
 708                   !!(mode & FLAGS_CBC));
 709
 710         dd = omap_aes_find_dev(ctx);
 711         if (!dd)
 712                 return -ENODEV;
 713
 714         rctx->mode = mode;
 715
 716         return omap_aes_handle_queue(dd, req);
 717 }
 718
 719 /* ********************** ALG API ************************************ */
 720
 721 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 722                            unsigned int keylen)
 723 {
 724         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 725
 726         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 727                    keylen != AES_KEYSIZE_256)
 728                 return -EINVAL;
 729
 730         pr_debug("enter, keylen: %d\n", keylen);
 731
 732         memcpy(ctx->key, key, keylen);
 733         ctx->keylen = keylen;
 734
 735         return 0;
 736 }
 737
 738 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 739 {
 740         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 741 }
 742
 743 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 744 {
 745         return omap_aes_crypt(req, 0);
 746 }
 747
 748 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 749 {
 750         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 751 }
 752
 753 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 754 {
 755         return omap_aes_crypt(req, FLAGS_CBC);
 756 }
 757
 758 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 759 {
 760         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 761 }
 762
 763 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 764 {
 765         return omap_aes_crypt(req, FLAGS_CTR);
 766 }
 767
 768 static int omap_aes_cra_init(struct crypto_tfm *tfm)
 769 {
 770         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 771
 772         return 0;
 773 }
 774
 775 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 776 {
 777 }
 778
 779 /* ********************** ALGS ************************************ */
 780
 781 static struct crypto_alg algs_ecb_cbc[] = {
 782 {
 783         .cra_name               = "ecb(aes)",
 784         .cra_driver_name        = "ecb-aes-omap",
 785         .cra_priority           = 300,
 786         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 787                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 788                                   CRYPTO_ALG_ASYNC,
 789         .cra_blocksize          = AES_BLOCK_SIZE,
 790         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 791         .cra_alignmask          = 0,
 792         .cra_type               = &crypto_ablkcipher_type,
 793         .cra_module             = THIS_MODULE,
 794         .cra_init               = omap_aes_cra_init,
 795         .cra_exit               = omap_aes_cra_exit,
 796         .cra_u.ablkcipher = {
 797                 .min_keysize    = AES_MIN_KEY_SIZE,
 798                 .max_keysize    = AES_MAX_KEY_SIZE,
 799                 .setkey         = omap_aes_setkey,
 800                 .encrypt        = omap_aes_ecb_encrypt,
 801                 .decrypt        = omap_aes_ecb_decrypt,
 802         }
 803 },
 804 {
 805         .cra_name               = "cbc(aes)",
 806         .cra_driver_name        = "cbc-aes-omap",
 807         .cra_priority           = 300,
 808         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 809                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 810                                   CRYPTO_ALG_ASYNC,
 811         .cra_blocksize          = AES_BLOCK_SIZE,
 812         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 813         .cra_alignmask          = 0,
 814         .cra_type               = &crypto_ablkcipher_type,
 815         .cra_module             = THIS_MODULE,
 816         .cra_init               = omap_aes_cra_init,
 817         .cra_exit               = omap_aes_cra_exit,
 818         .cra_u.ablkcipher = {
 819                 .min_keysize    = AES_MIN_KEY_SIZE,
 820                 .max_keysize    = AES_MAX_KEY_SIZE,
 821                 .ivsize         = AES_BLOCK_SIZE,
 822                 .setkey         = omap_aes_setkey,
 823                 .encrypt        = omap_aes_cbc_encrypt,
 824                 .decrypt        = omap_aes_cbc_decrypt,
 825         }
 826 }
 827 };
 828
 829 static struct crypto_alg algs_ctr[] = {
 830 {
 831         .cra_name               = "ctr(aes)",
 832         .cra_driver_name        = "ctr-aes-omap",
 833         .cra_priority           = 300,
 834         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 835                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 836                                   CRYPTO_ALG_ASYNC,
 837         .cra_blocksize          = AES_BLOCK_SIZE,
 838         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 839         .cra_alignmask          = 0,
 840         .cra_type               = &crypto_ablkcipher_type,
 841         .cra_module             = THIS_MODULE,
 842         .cra_init               = omap_aes_cra_init,
 843         .cra_exit               = omap_aes_cra_exit,
 844         .cra_u.ablkcipher = {
 845                 .min_keysize    = AES_MIN_KEY_SIZE,
 846                 .max_keysize    = AES_MAX_KEY_SIZE,
 847                 .geniv          = "eseqiv",
 848                 .ivsize         = AES_BLOCK_SIZE,
 849                 .setkey         = omap_aes_setkey,
 850                 .encrypt        = omap_aes_ctr_encrypt,
 851                 .decrypt        = omap_aes_ctr_decrypt,
 852         }
 853 } ,
 854 };
 855
 856 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 857         {
 858                 .algs_list      = algs_ecb_cbc,
 859                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 860         },
 861 };
 862
 863 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 864         .algs_info      = omap_aes_algs_info_ecb_cbc,
 865         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 866         .trigger        = omap_aes_dma_trigger_omap2,
 867         .key_ofs        = 0x1c,
 868         .iv_ofs         = 0x20,
 869         .ctrl_ofs       = 0x30,
 870         .data_ofs       = 0x34,
 871         .rev_ofs        = 0x44,
 872         .mask_ofs       = 0x48,
 873         .dma_enable_in  = BIT(2),
 874         .dma_enable_out = BIT(3),
 875         .dma_start      = BIT(5),
 876         .major_mask     = 0xf0,
 877         .major_shift    = 4,
 878         .minor_mask     = 0x0f,
 879         .minor_shift    = 0,
 880 };
 881
 882 #ifdef CONFIG_OF
 883 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 884         {
 885                 .algs_list      = algs_ecb_cbc,
 886                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 887         },
 888         {
 889                 .algs_list      = algs_ctr,
 890                 .size           = ARRAY_SIZE(algs_ctr),
 891         },
 892 };
 893
 894 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 895         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 896         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 897         .trigger        = omap_aes_dma_trigger_omap2,
 898         .key_ofs        = 0x1c,
 899         .iv_ofs         = 0x20,
 900         .ctrl_ofs       = 0x30,
 901         .data_ofs       = 0x34,
 902         .rev_ofs        = 0x44,
 903         .mask_ofs       = 0x48,
 904         .dma_enable_in  = BIT(2),
 905         .dma_enable_out = BIT(3),
 906         .dma_start      = BIT(5),
 907         .major_mask     = 0xf0,
 908         .major_shift    = 4,
 909         .minor_mask     = 0x0f,
 910         .minor_shift    = 0,
 911 };
 912
 913 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 914         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 915         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 916         .trigger        = omap_aes_dma_trigger_omap4,
 917         .key_ofs        = 0x3c,
 918         .iv_ofs         = 0x40,
 919         .ctrl_ofs       = 0x50,
 920         .data_ofs       = 0x60,
 921         .rev_ofs        = 0x80,
 922         .mask_ofs       = 0x84,
 923         .irq_status_ofs = 0x8c,
 924         .irq_enable_ofs = 0x90,
 925         .dma_enable_in  = BIT(5),
 926         .dma_enable_out = BIT(6),
 927         .major_mask     = 0x0700,
 928         .major_shift    = 8,
 929         .minor_mask     = 0x003f,
 930         .minor_shift    = 0,
 931 };
 932
 933 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
 934 {
 935         struct omap_aes_dev *dd = dev_id;
 936         u32 status, i;
 937         u32 *src, *dst;
 938
 939         status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
 940         if (status & AES_REG_IRQ_DATA_IN) {
 941                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 942
 943                 BUG_ON(!dd->in_sg);
 944
 945                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
 946
 947                 src = sg_virt(dd->in_sg) + _calc_walked(in);
 948
 949                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 950                         omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
 951
 952                         scatterwalk_advance(&dd->in_walk, 4);
 953                         if (dd->in_sg->length == _calc_walked(in)) {
 954                                 dd->in_sg = sg_next(dd->in_sg);
 955                                 if (dd->in_sg) {
 956                                         scatterwalk_start(&dd->in_walk,
 957                                                           dd->in_sg);
 958                                         src = sg_virt(dd->in_sg) +
 959                                               _calc_walked(in);
 960                                 }
 961                         } else {
 962                                 src++;
 963                         }
 964                 }
 965
 966                 /* Clear IRQ status */
 967                 status &= ~AES_REG_IRQ_DATA_IN;
 968                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
 969
 970                 /* Enable DATA_OUT interrupt */
 971                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
 972
 973         } else if (status & AES_REG_IRQ_DATA_OUT) {
 974                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 975
 976                 BUG_ON(!dd->out_sg);
 977
 978                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
 979
 980                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
 981
 982                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 983                         *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
 984                         scatterwalk_advance(&dd->out_walk, 4);
 985                         if (dd->out_sg->length == _calc_walked(out)) {
 986                                 dd->out_sg = sg_next(dd->out_sg);
 987                                 if (dd->out_sg) {
 988                                         scatterwalk_start(&dd->out_walk,
 989                                                           dd->out_sg);
 990                                         dst = sg_virt(dd->out_sg) +
 991                                               _calc_walked(out);
 992                                 }
 993                         } else {
 994                                 dst++;
 995                         }
 996                 }
 997
 998                 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
 999
1000                 /* Clear IRQ status */
1001                 status &= ~AES_REG_IRQ_DATA_OUT;
1002                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1003
1004                 if (!dd->total)
1005                         /* All bytes read! */
1006                         tasklet_schedule(&dd->done_task);
1007                 else
1008                         /* Enable DATA_IN interrupt for next block */
1009                         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1010         }
1011
1012         return IRQ_HANDLED;
1013 }
1014
1015 static const struct of_device_id omap_aes_of_match[] = {
1016         {
1017                 .compatible     = "ti,omap2-aes",
1018                 .data           = &omap_aes_pdata_omap2,
1019         },
1020         {
1021                 .compatible     = "ti,omap3-aes",
1022                 .data           = &omap_aes_pdata_omap3,
1023         },
1024         {
1025                 .compatible     = "ti,omap4-aes",
1026                 .data           = &omap_aes_pdata_omap4,
1027         },
1028         {},
1029 };
1030 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1031
1032 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1033                 struct device *dev, struct resource *res)
1034 {
1035         struct device_node *node = dev->of_node;
1036         const struct of_device_id *match;
1037         int err = 0;
1038
1039         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1040         if (!match) {
1041                 dev_err(dev, "no compatible OF match\n");
1042                 err = -EINVAL;
1043                 goto err;
1044         }
1045
1046         err = of_address_to_resource(node, 0, res);
1047         if (err < 0) {
1048                 dev_err(dev, "can't translate OF node address\n");
1049                 err = -EINVAL;
1050                 goto err;
1051         }
1052
1053         dd->pdata = match->data;
1054
1055 err:
1056         return err;
1057 }
1058 #else
1059 static const struct of_device_id omap_aes_of_match[] = {
1060         {},
1061 };
1062
1063 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1064                 struct device *dev, struct resource *res)
1065 {
1066         return -EINVAL;
1067 }
1068 #endif
1069
1070 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1071                 struct platform_device *pdev, struct resource *res)
1072 {
1073         struct device *dev = &pdev->dev;
1074         struct resource *r;
1075         int err = 0;
1076
1077         /* Get the base address */
1078         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1079         if (!r) {
1080                 dev_err(dev, "no MEM resource info\n");
1081                 err = -ENODEV;
1082                 goto err;
1083         }
1084         memcpy(res, r, sizeof(*res));
1085
1086         /* Only OMAP2/3 can be non-DT */
1087         dd->pdata = &omap_aes_pdata_omap2;
1088
1089 err:
1090         return err;
1091 }
1092
1093 static int omap_aes_probe(struct platform_device *pdev)
1094 {
1095         struct device *dev = &pdev->dev;
1096         struct omap_aes_dev *dd;
1097         struct crypto_alg *algp;
1098         struct resource res;
1099         int err = -ENOMEM, i, j, irq = -1;
1100         u32 reg;
1101
1102         dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1103         if (dd == NULL) {
1104                 dev_err(dev, "unable to alloc data struct.\n");
1105                 goto err_data;
1106         }
1107         dd->dev = dev;
1108         platform_set_drvdata(pdev, dd);
1109
1110         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1111                                omap_aes_get_res_pdev(dd, pdev, &res);
1112         if (err)
1113                 goto err_res;
1114
1115         dd->io_base = devm_ioremap_resource(dev, &res);
1116         if (IS_ERR(dd->io_base)) {
1117                 err = PTR_ERR(dd->io_base);
1118                 goto err_res;
1119         }
1120         dd->phys_base = res.start;
1121
1122         pm_runtime_use_autosuspend(dev);
1123         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1124
1125         pm_runtime_enable(dev);
1126         err = pm_runtime_get_sync(dev);
1127         if (err < 0) {
1128                 dev_err(dev, "%s: failed to get_sync(%d)\n",
1129                         __func__, err);
1130                 goto err_res;
1131         }
1132
1133         omap_aes_dma_stop(dd);
1134
1135         reg = omap_aes_read(dd, AES_REG_REV(dd));
1136
1137         pm_runtime_put_sync(dev);
1138
1139         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1140                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1141                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1142
1143         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1144
1145         err = omap_aes_dma_init(dd);
1146         if (err == -EPROBE_DEFER) {
1147                 goto err_irq;
1148         } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1149                 dd->pio_only = 1;
1150
1151                 irq = platform_get_irq(pdev, 0);
1152                 if (irq < 0) {
1153                         dev_err(dev, "can't get IRQ resource\n");
1154                         goto err_irq;
1155                 }
1156
1157                 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1158                                 dev_name(dev), dd);
1159                 if (err) {
1160                         dev_err(dev, "Unable to grab omap-aes IRQ\n");
1161                         goto err_irq;
1162                 }
1163         }
1164
1165
1166         INIT_LIST_HEAD(&dd->list);
1167         spin_lock(&list_lock);
1168         list_add_tail(&dd->list, &dev_list);
1169         spin_unlock(&list_lock);
1170
1171         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1172                 if (!dd->pdata->algs_info[i].registered) {
1173                         for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1174                                 algp = &dd->pdata->algs_info[i].algs_list[j];
1175
1176                                 pr_debug("reg alg: %s\n", algp->cra_name);
1177                                 INIT_LIST_HEAD(&algp->cra_list);
1178
1179                                 err = crypto_register_alg(algp);
1180                                 if (err)
1181                                         goto err_algs;
1182
1183                                 dd->pdata->algs_info[i].registered++;
1184                         }
1185                 }
1186         }
1187
1188         /* Initialize crypto engine */
1189         dd->engine = crypto_engine_alloc_init(dev, 1);
1190         if (!dd->engine)
1191                 goto err_algs;
1192
1193         dd->engine->prepare_cipher_request = omap_aes_prepare_req;
1194         dd->engine->cipher_one_request = omap_aes_crypt_req;
1195         err = crypto_engine_start(dd->engine);
1196         if (err)
1197                 goto err_engine;
1198
1199         return 0;
1200 err_engine:
1201         crypto_engine_exit(dd->engine);
1202 err_algs:
1203         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1204                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1205                         crypto_unregister_alg(
1206                                         &dd->pdata->algs_info[i].algs_list[j]);
1207
1208         omap_aes_dma_cleanup(dd);
1209 err_irq:
1210         tasklet_kill(&dd->done_task);
1211         pm_runtime_disable(dev);
1212 err_res:
1213         dd = NULL;
1214 err_data:
1215         dev_err(dev, "initialization failed.\n");
1216         return err;
1217 }
1218
1219 static int omap_aes_remove(struct platform_device *pdev)
1220 {
1221         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1222         int i, j;
1223
1224         if (!dd)
1225                 return -ENODEV;
1226
1227         spin_lock(&list_lock);
1228         list_del(&dd->list);
1229         spin_unlock(&list_lock);
1230
1231         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1232                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1233                         crypto_unregister_alg(
1234                                         &dd->pdata->algs_info[i].algs_list[j]);
1235
1236         crypto_engine_exit(dd->engine);
1237         tasklet_kill(&dd->done_task);
1238         omap_aes_dma_cleanup(dd);
1239         pm_runtime_disable(dd->dev);
1240         dd = NULL;
1241
1242         return 0;
1243 }
1244
1245 #ifdef CONFIG_PM_SLEEP
1246 static int omap_aes_suspend(struct device *dev)
1247 {
1248         pm_runtime_put_sync(dev);
1249         return 0;
1250 }
1251
1252 static int omap_aes_resume(struct device *dev)
1253 {
1254         pm_runtime_get_sync(dev);
1255         return 0;
1256 }
1257 #endif
1258
1259 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1260
1261 static struct platform_driver omap_aes_driver = {
1262         .probe  = omap_aes_probe,
1263         .remove = omap_aes_remove,
1264         .driver = {
1265                 .name   = "omap-aes",
1266                 .pm     = &omap_aes_pm_ops,
1267                 .of_match_table = omap_aes_of_match,
1268         },
1269 };
1270
1271 module_platform_driver(omap_aes_driver);
1272
1273 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1274 MODULE_LICENSE("GPL v2");
1275 MODULE_AUTHOR("Dmitry Kasatkin");
1276