drivers/crypto/omap-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP AES HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) "%20s: " fmt, __func__
  17 #define prn(num) pr_debug(#num "=%d\n", num)
  18 #define prx(num) pr_debug(#num "=%x\n", num)
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_address.h>
  33 #include <linux/io.h>
  34 #include <linux/crypto.h>
  35 #include <linux/interrupt.h>
  36 #include <crypto/scatterwalk.h>
  37 #include <crypto/aes.h>
  38 #include <crypto/algapi.h>
  39 #include <crypto/engine.h>
  40
  41 #define DST_MAXBURST                    4
  42 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  43
  44 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
  45
  46 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  47    number. For example 7:0 */
  48 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  49 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  50
  51 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  52                                                 ((x ^ 0x01) * 0x04))
  53 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  54
  55 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  56 #define AES_REG_CTRL_CTR_WIDTH_MASK     GENMASK(8, 7)
  57 #define AES_REG_CTRL_CTR_WIDTH_32       0
  58 #define AES_REG_CTRL_CTR_WIDTH_64       BIT(7)
  59 #define AES_REG_CTRL_CTR_WIDTH_96       BIT(8)
  60 #define AES_REG_CTRL_CTR_WIDTH_128      GENMASK(8, 7)
  61 #define AES_REG_CTRL_CTR                BIT(6)
  62 #define AES_REG_CTRL_CBC                BIT(5)
  63 #define AES_REG_CTRL_KEY_SIZE           GENMASK(4, 3)
  64 #define AES_REG_CTRL_DIRECTION          BIT(2)
  65 #define AES_REG_CTRL_INPUT_READY        BIT(1)
  66 #define AES_REG_CTRL_OUTPUT_READY       BIT(0)
  67 #define AES_REG_CTRL_MASK               GENMASK(24, 2)
  68
  69 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  70
  71 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  72
  73 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  74 #define AES_REG_MASK_SIDLE              BIT(6)
  75 #define AES_REG_MASK_START              BIT(5)
  76 #define AES_REG_MASK_DMA_OUT_EN         BIT(3)
  77 #define AES_REG_MASK_DMA_IN_EN          BIT(2)
  78 #define AES_REG_MASK_SOFTRESET          BIT(1)
  79 #define AES_REG_AUTOIDLE                BIT(0)
  80
  81 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  82
  83 #define AES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  84 #define AES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  85 #define AES_REG_IRQ_DATA_IN            BIT(1)
  86 #define AES_REG_IRQ_DATA_OUT           BIT(2)
  87 #define DEFAULT_TIMEOUT         (5*HZ)
  88
  89 #define DEFAULT_AUTOSUSPEND_DELAY       1000
  90
  91 #define FLAGS_MODE_MASK         0x000f
  92 #define FLAGS_ENCRYPT           BIT(0)
  93 #define FLAGS_CBC               BIT(1)
  94 #define FLAGS_GIV               BIT(2)
  95 #define FLAGS_CTR               BIT(3)
  96
  97 #define FLAGS_INIT              BIT(4)
  98 #define FLAGS_FAST              BIT(5)
  99 #define FLAGS_BUSY              BIT(6)
 100
 101 #define AES_BLOCK_WORDS         (AES_BLOCK_SIZE >> 2)
 102
 103 struct omap_aes_ctx {
 104         struct omap_aes_dev *dd;
 105
 106         int             keylen;
 107         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
 108         unsigned long   flags;
 109 };
 110
 111 struct omap_aes_reqctx {
 112         unsigned long mode;
 113 };
 114
 115 #define OMAP_AES_QUEUE_LENGTH   1
 116 #define OMAP_AES_CACHE_SIZE     0
 117
 118 struct omap_aes_algs_info {
 119         struct crypto_alg       *algs_list;
 120         unsigned int            size;
 121         unsigned int            registered;
 122 };
 123
 124 struct omap_aes_pdata {
 125         struct omap_aes_algs_info       *algs_info;
 126         unsigned int    algs_info_size;
 127
 128         void            (*trigger)(struct omap_aes_dev *dd, int length);
 129
 130         u32             key_ofs;
 131         u32             iv_ofs;
 132         u32             ctrl_ofs;
 133         u32             data_ofs;
 134         u32             rev_ofs;
 135         u32             mask_ofs;
 136         u32             irq_enable_ofs;
 137         u32             irq_status_ofs;
 138
 139         u32             dma_enable_in;
 140         u32             dma_enable_out;
 141         u32             dma_start;
 142
 143         u32             major_mask;
 144         u32             major_shift;
 145         u32             minor_mask;
 146         u32             minor_shift;
 147 };
 148
 149 struct omap_aes_dev {
 150         struct list_head        list;
 151         unsigned long           phys_base;
 152         void __iomem            *io_base;
 153         struct omap_aes_ctx     *ctx;
 154         struct device           *dev;
 155         unsigned long           flags;
 156         int                     err;
 157
 158         struct tasklet_struct   done_task;
 159
 160         struct ablkcipher_request       *req;
 161         struct crypto_engine            *engine;
 162
 163         /*
 164          * total is used by PIO mode for book keeping so introduce
 165          * variable total_save as need it to calc page_order
 166          */
 167         size_t                          total;
 168         size_t                          total_save;
 169
 170         struct scatterlist              *in_sg;
 171         struct scatterlist              *out_sg;
 172
 173         /* Buffers for copying for unaligned cases */
 174         struct scatterlist              in_sgl;
 175         struct scatterlist              out_sgl;
 176         struct scatterlist              *orig_out;
 177         int                             sgs_copied;
 178
 179         struct scatter_walk             in_walk;
 180         struct scatter_walk             out_walk;
 181         struct dma_chan         *dma_lch_in;
 182         struct dma_chan         *dma_lch_out;
 183         int                     in_sg_len;
 184         int                     out_sg_len;
 185         int                     pio_only;
 186         const struct omap_aes_pdata     *pdata;
 187 };
 188
 189 /* keep registered devices data here */
 190 static LIST_HEAD(dev_list);
 191 static DEFINE_SPINLOCK(list_lock);
 192
 193 #ifdef DEBUG
 194 #define omap_aes_read(dd, offset)                               \
 195 ({                                                              \
 196         int _read_ret;                                          \
 197         _read_ret = __raw_readl(dd->io_base + offset);          \
 198         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 199                  offset, _read_ret);                            \
 200         _read_ret;                                              \
 201 })
 202 #else
 203 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 204 {
 205         return __raw_readl(dd->io_base + offset);
 206 }
 207 #endif
 208
 209 #ifdef DEBUG
 210 #define omap_aes_write(dd, offset, value)                               \
 211         do {                                                            \
 212                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 213                          offset, value);                                \
 214                 __raw_writel(value, dd->io_base + offset);              \
 215         } while (0)
 216 #else
 217 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 218                                   u32 value)
 219 {
 220         __raw_writel(value, dd->io_base + offset);
 221 }
 222 #endif
 223
 224 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 225                                         u32 value, u32 mask)
 226 {
 227         u32 val;
 228
 229         val = omap_aes_read(dd, offset);
 230         val &= ~mask;
 231         val |= value;
 232         omap_aes_write(dd, offset, val);
 233 }
 234
 235 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 236                                         u32 *value, int count)
 237 {
 238         for (; count--; value++, offset += 4)
 239                 omap_aes_write(dd, offset, *value);
 240 }
 241
 242 static int omap_aes_hw_init(struct omap_aes_dev *dd)
 243 {
 244         int err;
 245
 246         if (!(dd->flags & FLAGS_INIT)) {
 247                 dd->flags |= FLAGS_INIT;
 248                 dd->err = 0;
 249         }
 250
 251         err = pm_runtime_get_sync(dd->dev);
 252         if (err < 0) {
 253                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 254                 return err;
 255         }
 256
 257         return 0;
 258 }
 259
 260 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 261 {
 262         unsigned int key32;
 263         int i, err;
 264         u32 val;
 265
 266         err = omap_aes_hw_init(dd);
 267         if (err)
 268                 return err;
 269
 270         key32 = dd->ctx->keylen / sizeof(u32);
 271
 272         /* it seems a key should always be set even if it has not changed */
 273         for (i = 0; i < key32; i++) {
 274                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 275                         __le32_to_cpu(dd->ctx->key[i]));
 276         }
 277
 278         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 279                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 280
 281         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 282         if (dd->flags & FLAGS_CBC)
 283                 val |= AES_REG_CTRL_CBC;
 284         if (dd->flags & FLAGS_CTR)
 285                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
 286
 287         if (dd->flags & FLAGS_ENCRYPT)
 288                 val |= AES_REG_CTRL_DIRECTION;
 289
 290         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
 291
 292         return 0;
 293 }
 294
 295 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 296 {
 297         u32 mask, val;
 298
 299         val = dd->pdata->dma_start;
 300
 301         if (dd->dma_lch_out != NULL)
 302                 val |= dd->pdata->dma_enable_out;
 303         if (dd->dma_lch_in != NULL)
 304                 val |= dd->pdata->dma_enable_in;
 305
 306         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 307                dd->pdata->dma_start;
 308
 309         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 310
 311 }
 312
 313 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 314 {
 315         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 316         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 317
 318         omap_aes_dma_trigger_omap2(dd, length);
 319 }
 320
 321 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 322 {
 323         u32 mask;
 324
 325         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 326                dd->pdata->dma_start;
 327
 328         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 329 }
 330
 331 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 332 {
 333         struct omap_aes_dev *dd = NULL, *tmp;
 334
 335         spin_lock_bh(&list_lock);
 336         if (!ctx->dd) {
 337                 list_for_each_entry(tmp, &dev_list, list) {
 338                         /* FIXME: take fist available aes core */
 339                         dd = tmp;
 340                         break;
 341                 }
 342                 ctx->dd = dd;
 343         } else {
 344                 /* already found before */
 345                 dd = ctx->dd;
 346         }
 347         spin_unlock_bh(&list_lock);
 348
 349         return dd;
 350 }
 351
 352 static void omap_aes_dma_out_callback(void *data)
 353 {
 354         struct omap_aes_dev *dd = data;
 355
 356         /* dma_lch_out - completed */
 357         tasklet_schedule(&dd->done_task);
 358 }
 359
 360 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 361 {
 362         int err;
 363
 364         dd->dma_lch_out = NULL;
 365         dd->dma_lch_in = NULL;
 366
 367         dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
 368         if (IS_ERR(dd->dma_lch_in)) {
 369                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 370                 return PTR_ERR(dd->dma_lch_in);
 371         }
 372
 373         dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
 374         if (IS_ERR(dd->dma_lch_out)) {
 375                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 376                 err = PTR_ERR(dd->dma_lch_out);
 377                 goto err_dma_out;
 378         }
 379
 380         return 0;
 381
 382 err_dma_out:
 383         dma_release_channel(dd->dma_lch_in);
 384
 385         return err;
 386 }
 387
 388 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 389 {
 390         if (dd->pio_only)
 391                 return;
 392
 393         dma_release_channel(dd->dma_lch_out);
 394         dma_release_channel(dd->dma_lch_in);
 395 }
 396
 397 static void sg_copy_buf(void *buf, struct scatterlist *sg,
 398                               unsigned int start, unsigned int nbytes, int out)
 399 {
 400         struct scatter_walk walk;
 401
 402         if (!nbytes)
 403                 return;
 404
 405         scatterwalk_start(&walk, sg);
 406         scatterwalk_advance(&walk, start);
 407         scatterwalk_copychunks(buf, &walk, nbytes, out);
 408         scatterwalk_done(&walk, out, 0);
 409 }
 410
 411 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 412                 struct scatterlist *in_sg, struct scatterlist *out_sg,
 413                 int in_sg_len, int out_sg_len)
 414 {
 415         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 416         struct omap_aes_dev *dd = ctx->dd;
 417         struct dma_async_tx_descriptor *tx_in, *tx_out;
 418         struct dma_slave_config cfg;
 419         int ret;
 420
 421         if (dd->pio_only) {
 422                 scatterwalk_start(&dd->in_walk, dd->in_sg);
 423                 scatterwalk_start(&dd->out_walk, dd->out_sg);
 424
 425                 /* Enable DATAIN interrupt and let it take
 426                    care of the rest */
 427                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 428                 return 0;
 429         }
 430
 431         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 432
 433         memset(&cfg, 0, sizeof(cfg));
 434
 435         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 436         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 437         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 438         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 439         cfg.src_maxburst = DST_MAXBURST;
 440         cfg.dst_maxburst = DST_MAXBURST;
 441
 442         /* IN */
 443         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 444         if (ret) {
 445                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 446                         ret);
 447                 return ret;
 448         }
 449
 450         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 451                                         DMA_MEM_TO_DEV,
 452                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 453         if (!tx_in) {
 454                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 455                 return -EINVAL;
 456         }
 457
 458         /* No callback necessary */
 459         tx_in->callback_param = dd;
 460
 461         /* OUT */
 462         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 463         if (ret) {
 464                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 465                         ret);
 466                 return ret;
 467         }
 468
 469         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 470                                         DMA_DEV_TO_MEM,
 471                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 472         if (!tx_out) {
 473                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 474                 return -EINVAL;
 475         }
 476
 477         tx_out->callback = omap_aes_dma_out_callback;
 478         tx_out->callback_param = dd;
 479
 480         dmaengine_submit(tx_in);
 481         dmaengine_submit(tx_out);
 482
 483         dma_async_issue_pending(dd->dma_lch_in);
 484         dma_async_issue_pending(dd->dma_lch_out);
 485
 486         /* start DMA */
 487         dd->pdata->trigger(dd, dd->total);
 488
 489         return 0;
 490 }
 491
 492 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 493 {
 494         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 495                                         crypto_ablkcipher_reqtfm(dd->req));
 496         int err;
 497
 498         pr_debug("total: %d\n", dd->total);
 499
 500         if (!dd->pio_only) {
 501                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 502                                  DMA_TO_DEVICE);
 503                 if (!err) {
 504                         dev_err(dd->dev, "dma_map_sg() error\n");
 505                         return -EINVAL;
 506                 }
 507
 508                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 509                                  DMA_FROM_DEVICE);
 510                 if (!err) {
 511                         dev_err(dd->dev, "dma_map_sg() error\n");
 512                         return -EINVAL;
 513                 }
 514         }
 515
 516         err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 517                                  dd->out_sg_len);
 518         if (err && !dd->pio_only) {
 519                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 520                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 521                              DMA_FROM_DEVICE);
 522         }
 523
 524         return err;
 525 }
 526
 527 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 528 {
 529         struct ablkcipher_request *req = dd->req;
 530
 531         pr_debug("err: %d\n", err);
 532
 533         crypto_finalize_cipher_request(dd->engine, req, err);
 534
 535         pm_runtime_mark_last_busy(dd->dev);
 536         pm_runtime_put_autosuspend(dd->dev);
 537 }
 538
 539 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 540 {
 541         pr_debug("total: %d\n", dd->total);
 542
 543         omap_aes_dma_stop(dd);
 544
 545
 546         return 0;
 547 }
 548
 549 static int omap_aes_check_aligned(struct scatterlist *sg, int total)
 550 {
 551         int len = 0;
 552
 553         if (!IS_ALIGNED(total, AES_BLOCK_SIZE))
 554                 return -EINVAL;
 555
 556         while (sg) {
 557                 if (!IS_ALIGNED(sg->offset, 4))
 558                         return -1;
 559                 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
 560                         return -1;
 561
 562                 len += sg->length;
 563                 sg = sg_next(sg);
 564         }
 565
 566         if (len != total)
 567                 return -1;
 568
 569         return 0;
 570 }
 571
 572 static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
 573 {
 574         void *buf_in, *buf_out;
 575         int pages, total;
 576
 577         total = ALIGN(dd->total, AES_BLOCK_SIZE);
 578         pages = get_order(total);
 579
 580         buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
 581         buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
 582
 583         if (!buf_in || !buf_out) {
 584                 pr_err("Couldn't allocated pages for unaligned cases.\n");
 585                 return -1;
 586         }
 587
 588         dd->orig_out = dd->out_sg;
 589
 590         sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
 591
 592         sg_init_table(&dd->in_sgl, 1);
 593         sg_set_buf(&dd->in_sgl, buf_in, total);
 594         dd->in_sg = &dd->in_sgl;
 595         dd->in_sg_len = 1;
 596
 597         sg_init_table(&dd->out_sgl, 1);
 598         sg_set_buf(&dd->out_sgl, buf_out, total);
 599         dd->out_sg = &dd->out_sgl;
 600         dd->out_sg_len = 1;
 601
 602         return 0;
 603 }
 604
 605 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 606                                  struct ablkcipher_request *req)
 607 {
 608         if (req)
 609                 return crypto_transfer_cipher_request_to_engine(dd->engine, req);
 610
 611         return 0;
 612 }
 613
 614 static int omap_aes_prepare_req(struct crypto_engine *engine,
 615                                 struct ablkcipher_request *req)
 616 {
 617         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 618                         crypto_ablkcipher_reqtfm(req));
 619         struct omap_aes_dev *dd = omap_aes_find_dev(ctx);
 620         struct omap_aes_reqctx *rctx;
 621
 622         if (!dd)
 623                 return -ENODEV;
 624
 625         /* assign new request to device */
 626         dd->req = req;
 627         dd->total = req->nbytes;
 628         dd->total_save = req->nbytes;
 629         dd->in_sg = req->src;
 630         dd->out_sg = req->dst;
 631
 632         dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
 633         if (dd->in_sg_len < 0)
 634                 return dd->in_sg_len;
 635
 636         dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
 637         if (dd->out_sg_len < 0)
 638                 return dd->out_sg_len;
 639
 640         if (omap_aes_check_aligned(dd->in_sg, dd->total) ||
 641             omap_aes_check_aligned(dd->out_sg, dd->total)) {
 642                 if (omap_aes_copy_sgs(dd))
 643                         pr_err("Failed to copy SGs for unaligned cases\n");
 644                 dd->sgs_copied = 1;
 645         } else {
 646                 dd->sgs_copied = 0;
 647         }
 648
 649         rctx = ablkcipher_request_ctx(req);
 650         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 651         rctx->mode &= FLAGS_MODE_MASK;
 652         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 653
 654         dd->ctx = ctx;
 655         ctx->dd = dd;
 656
 657         return omap_aes_write_ctrl(dd);
 658 }
 659
 660 static int omap_aes_crypt_req(struct crypto_engine *engine,
 661                               struct ablkcipher_request *req)
 662 {
 663         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 664                         crypto_ablkcipher_reqtfm(req));
 665         struct omap_aes_dev *dd = omap_aes_find_dev(ctx);
 666
 667         if (!dd)
 668                 return -ENODEV;
 669
 670         return omap_aes_crypt_dma_start(dd);
 671 }
 672
 673 static void omap_aes_done_task(unsigned long data)
 674 {
 675         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 676         void *buf_in, *buf_out;
 677         int pages, len;
 678
 679         pr_debug("enter done_task\n");
 680
 681         if (!dd->pio_only) {
 682                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 683                                        DMA_FROM_DEVICE);
 684                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 685                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 686                              DMA_FROM_DEVICE);
 687                 omap_aes_crypt_dma_stop(dd);
 688         }
 689
 690         if (dd->sgs_copied) {
 691                 buf_in = sg_virt(&dd->in_sgl);
 692                 buf_out = sg_virt(&dd->out_sgl);
 693
 694                 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
 695
 696                 len = ALIGN(dd->total_save, AES_BLOCK_SIZE);
 697                 pages = get_order(len);
 698                 free_pages((unsigned long)buf_in, pages);
 699                 free_pages((unsigned long)buf_out, pages);
 700         }
 701
 702         omap_aes_finish_req(dd, 0);
 703
 704         pr_debug("exit\n");
 705 }
 706
 707 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 708 {
 709         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 710                         crypto_ablkcipher_reqtfm(req));
 711         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 712         struct omap_aes_dev *dd;
 713
 714         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 715                   !!(mode & FLAGS_ENCRYPT),
 716                   !!(mode & FLAGS_CBC));
 717
 718         dd = omap_aes_find_dev(ctx);
 719         if (!dd)
 720                 return -ENODEV;
 721
 722         rctx->mode = mode;
 723
 724         return omap_aes_handle_queue(dd, req);
 725 }
 726
 727 /* ********************** ALG API ************************************ */
 728
 729 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 730                            unsigned int keylen)
 731 {
 732         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 733
 734         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 735                    keylen != AES_KEYSIZE_256)
 736                 return -EINVAL;
 737
 738         pr_debug("enter, keylen: %d\n", keylen);
 739
 740         memcpy(ctx->key, key, keylen);
 741         ctx->keylen = keylen;
 742
 743         return 0;
 744 }
 745
 746 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 747 {
 748         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 749 }
 750
 751 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 752 {
 753         return omap_aes_crypt(req, 0);
 754 }
 755
 756 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 757 {
 758         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 759 }
 760
 761 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 762 {
 763         return omap_aes_crypt(req, FLAGS_CBC);
 764 }
 765
 766 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 767 {
 768         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 769 }
 770
 771 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 772 {
 773         return omap_aes_crypt(req, FLAGS_CTR);
 774 }
 775
 776 static int omap_aes_cra_init(struct crypto_tfm *tfm)
 777 {
 778         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 779
 780         return 0;
 781 }
 782
 783 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 784 {
 785 }
 786
 787 /* ********************** ALGS ************************************ */
 788
 789 static struct crypto_alg algs_ecb_cbc[] = {
 790 {
 791         .cra_name               = "ecb(aes)",
 792         .cra_driver_name        = "ecb-aes-omap",
 793         .cra_priority           = 300,
 794         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 795                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 796                                   CRYPTO_ALG_ASYNC,
 797         .cra_blocksize          = AES_BLOCK_SIZE,
 798         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 799         .cra_alignmask          = 0,
 800         .cra_type               = &crypto_ablkcipher_type,
 801         .cra_module             = THIS_MODULE,
 802         .cra_init               = omap_aes_cra_init,
 803         .cra_exit               = omap_aes_cra_exit,
 804         .cra_u.ablkcipher = {
 805                 .min_keysize    = AES_MIN_KEY_SIZE,
 806                 .max_keysize    = AES_MAX_KEY_SIZE,
 807                 .setkey         = omap_aes_setkey,
 808                 .encrypt        = omap_aes_ecb_encrypt,
 809                 .decrypt        = omap_aes_ecb_decrypt,
 810         }
 811 },
 812 {
 813         .cra_name               = "cbc(aes)",
 814         .cra_driver_name        = "cbc-aes-omap",
 815         .cra_priority           = 300,
 816         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 817                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 818                                   CRYPTO_ALG_ASYNC,
 819         .cra_blocksize          = AES_BLOCK_SIZE,
 820         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 821         .cra_alignmask          = 0,
 822         .cra_type               = &crypto_ablkcipher_type,
 823         .cra_module             = THIS_MODULE,
 824         .cra_init               = omap_aes_cra_init,
 825         .cra_exit               = omap_aes_cra_exit,
 826         .cra_u.ablkcipher = {
 827                 .min_keysize    = AES_MIN_KEY_SIZE,
 828                 .max_keysize    = AES_MAX_KEY_SIZE,
 829                 .ivsize         = AES_BLOCK_SIZE,
 830                 .setkey         = omap_aes_setkey,
 831                 .encrypt        = omap_aes_cbc_encrypt,
 832                 .decrypt        = omap_aes_cbc_decrypt,
 833         }
 834 }
 835 };
 836
 837 static struct crypto_alg algs_ctr[] = {
 838 {
 839         .cra_name               = "ctr(aes)",
 840         .cra_driver_name        = "ctr-aes-omap",
 841         .cra_priority           = 300,
 842         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 843                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 844                                   CRYPTO_ALG_ASYNC,
 845         .cra_blocksize          = AES_BLOCK_SIZE,
 846         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 847         .cra_alignmask          = 0,
 848         .cra_type               = &crypto_ablkcipher_type,
 849         .cra_module             = THIS_MODULE,
 850         .cra_init               = omap_aes_cra_init,
 851         .cra_exit               = omap_aes_cra_exit,
 852         .cra_u.ablkcipher = {
 853                 .min_keysize    = AES_MIN_KEY_SIZE,
 854                 .max_keysize    = AES_MAX_KEY_SIZE,
 855                 .geniv          = "eseqiv",
 856                 .ivsize         = AES_BLOCK_SIZE,
 857                 .setkey         = omap_aes_setkey,
 858                 .encrypt        = omap_aes_ctr_encrypt,
 859                 .decrypt        = omap_aes_ctr_decrypt,
 860         }
 861 } ,
 862 };
 863
 864 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 865         {
 866                 .algs_list      = algs_ecb_cbc,
 867                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 868         },
 869 };
 870
 871 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 872         .algs_info      = omap_aes_algs_info_ecb_cbc,
 873         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 874         .trigger        = omap_aes_dma_trigger_omap2,
 875         .key_ofs        = 0x1c,
 876         .iv_ofs         = 0x20,
 877         .ctrl_ofs       = 0x30,
 878         .data_ofs       = 0x34,
 879         .rev_ofs        = 0x44,
 880         .mask_ofs       = 0x48,
 881         .dma_enable_in  = BIT(2),
 882         .dma_enable_out = BIT(3),
 883         .dma_start      = BIT(5),
 884         .major_mask     = 0xf0,
 885         .major_shift    = 4,
 886         .minor_mask     = 0x0f,
 887         .minor_shift    = 0,
 888 };
 889
 890 #ifdef CONFIG_OF
 891 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 892         {
 893                 .algs_list      = algs_ecb_cbc,
 894                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 895         },
 896         {
 897                 .algs_list      = algs_ctr,
 898                 .size           = ARRAY_SIZE(algs_ctr),
 899         },
 900 };
 901
 902 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 903         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 904         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 905         .trigger        = omap_aes_dma_trigger_omap2,
 906         .key_ofs        = 0x1c,
 907         .iv_ofs         = 0x20,
 908         .ctrl_ofs       = 0x30,
 909         .data_ofs       = 0x34,
 910         .rev_ofs        = 0x44,
 911         .mask_ofs       = 0x48,
 912         .dma_enable_in  = BIT(2),
 913         .dma_enable_out = BIT(3),
 914         .dma_start      = BIT(5),
 915         .major_mask     = 0xf0,
 916         .major_shift    = 4,
 917         .minor_mask     = 0x0f,
 918         .minor_shift    = 0,
 919 };
 920
 921 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 922         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 923         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 924         .trigger        = omap_aes_dma_trigger_omap4,
 925         .key_ofs        = 0x3c,
 926         .iv_ofs         = 0x40,
 927         .ctrl_ofs       = 0x50,
 928         .data_ofs       = 0x60,
 929         .rev_ofs        = 0x80,
 930         .mask_ofs       = 0x84,
 931         .irq_status_ofs = 0x8c,
 932         .irq_enable_ofs = 0x90,
 933         .dma_enable_in  = BIT(5),
 934         .dma_enable_out = BIT(6),
 935         .major_mask     = 0x0700,
 936         .major_shift    = 8,
 937         .minor_mask     = 0x003f,
 938         .minor_shift    = 0,
 939 };
 940
 941 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
 942 {
 943         struct omap_aes_dev *dd = dev_id;
 944         u32 status, i;
 945         u32 *src, *dst;
 946
 947         status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
 948         if (status & AES_REG_IRQ_DATA_IN) {
 949                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 950
 951                 BUG_ON(!dd->in_sg);
 952
 953                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
 954
 955                 src = sg_virt(dd->in_sg) + _calc_walked(in);
 956
 957                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 958                         omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
 959
 960                         scatterwalk_advance(&dd->in_walk, 4);
 961                         if (dd->in_sg->length == _calc_walked(in)) {
 962                                 dd->in_sg = sg_next(dd->in_sg);
 963                                 if (dd->in_sg) {
 964                                         scatterwalk_start(&dd->in_walk,
 965                                                           dd->in_sg);
 966                                         src = sg_virt(dd->in_sg) +
 967                                               _calc_walked(in);
 968                                 }
 969                         } else {
 970                                 src++;
 971                         }
 972                 }
 973
 974                 /* Clear IRQ status */
 975                 status &= ~AES_REG_IRQ_DATA_IN;
 976                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
 977
 978                 /* Enable DATA_OUT interrupt */
 979                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
 980
 981         } else if (status & AES_REG_IRQ_DATA_OUT) {
 982                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 983
 984                 BUG_ON(!dd->out_sg);
 985
 986                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
 987
 988                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
 989
 990                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 991                         *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
 992                         scatterwalk_advance(&dd->out_walk, 4);
 993                         if (dd->out_sg->length == _calc_walked(out)) {
 994                                 dd->out_sg = sg_next(dd->out_sg);
 995                                 if (dd->out_sg) {
 996                                         scatterwalk_start(&dd->out_walk,
 997                                                           dd->out_sg);
 998                                         dst = sg_virt(dd->out_sg) +
 999                                               _calc_walked(out);
1000                                 }
1001                         } else {
1002                                 dst++;
1003                         }
1004                 }
1005
1006                 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
1007
1008                 /* Clear IRQ status */
1009                 status &= ~AES_REG_IRQ_DATA_OUT;
1010                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1011
1012                 if (!dd->total)
1013                         /* All bytes read! */
1014                         tasklet_schedule(&dd->done_task);
1015                 else
1016                         /* Enable DATA_IN interrupt for next block */
1017                         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1018         }
1019
1020         return IRQ_HANDLED;
1021 }
1022
1023 static const struct of_device_id omap_aes_of_match[] = {
1024         {
1025                 .compatible     = "ti,omap2-aes",
1026                 .data           = &omap_aes_pdata_omap2,
1027         },
1028         {
1029                 .compatible     = "ti,omap3-aes",
1030                 .data           = &omap_aes_pdata_omap3,
1031         },
1032         {
1033                 .compatible     = "ti,omap4-aes",
1034                 .data           = &omap_aes_pdata_omap4,
1035         },
1036         {},
1037 };
1038 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1039
1040 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1041                 struct device *dev, struct resource *res)
1042 {
1043         struct device_node *node = dev->of_node;
1044         const struct of_device_id *match;
1045         int err = 0;
1046
1047         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1048         if (!match) {
1049                 dev_err(dev, "no compatible OF match\n");
1050                 err = -EINVAL;
1051                 goto err;
1052         }
1053
1054         err = of_address_to_resource(node, 0, res);
1055         if (err < 0) {
1056                 dev_err(dev, "can't translate OF node address\n");
1057                 err = -EINVAL;
1058                 goto err;
1059         }
1060
1061         dd->pdata = match->data;
1062
1063 err:
1064         return err;
1065 }
1066 #else
1067 static const struct of_device_id omap_aes_of_match[] = {
1068         {},
1069 };
1070
1071 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1072                 struct device *dev, struct resource *res)
1073 {
1074         return -EINVAL;
1075 }
1076 #endif
1077
1078 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1079                 struct platform_device *pdev, struct resource *res)
1080 {
1081         struct device *dev = &pdev->dev;
1082         struct resource *r;
1083         int err = 0;
1084
1085         /* Get the base address */
1086         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1087         if (!r) {
1088                 dev_err(dev, "no MEM resource info\n");
1089                 err = -ENODEV;
1090                 goto err;
1091         }
1092         memcpy(res, r, sizeof(*res));
1093
1094         /* Only OMAP2/3 can be non-DT */
1095         dd->pdata = &omap_aes_pdata_omap2;
1096
1097 err:
1098         return err;
1099 }
1100
1101 static int omap_aes_probe(struct platform_device *pdev)
1102 {
1103         struct device *dev = &pdev->dev;
1104         struct omap_aes_dev *dd;
1105         struct crypto_alg *algp;
1106         struct resource res;
1107         int err = -ENOMEM, i, j, irq = -1;
1108         u32 reg;
1109
1110         dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1111         if (dd == NULL) {
1112                 dev_err(dev, "unable to alloc data struct.\n");
1113                 goto err_data;
1114         }
1115         dd->dev = dev;
1116         platform_set_drvdata(pdev, dd);
1117
1118         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1119                                omap_aes_get_res_pdev(dd, pdev, &res);
1120         if (err)
1121                 goto err_res;
1122
1123         dd->io_base = devm_ioremap_resource(dev, &res);
1124         if (IS_ERR(dd->io_base)) {
1125                 err = PTR_ERR(dd->io_base);
1126                 goto err_res;
1127         }
1128         dd->phys_base = res.start;
1129
1130         pm_runtime_use_autosuspend(dev);
1131         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1132
1133         pm_runtime_enable(dev);
1134         err = pm_runtime_get_sync(dev);
1135         if (err < 0) {
1136                 dev_err(dev, "%s: failed to get_sync(%d)\n",
1137                         __func__, err);
1138                 goto err_res;
1139         }
1140
1141         omap_aes_dma_stop(dd);
1142
1143         reg = omap_aes_read(dd, AES_REG_REV(dd));
1144
1145         pm_runtime_put_sync(dev);
1146
1147         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1148                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1149                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1150
1151         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1152
1153         err = omap_aes_dma_init(dd);
1154         if (err == -EPROBE_DEFER) {
1155                 goto err_irq;
1156         } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1157                 dd->pio_only = 1;
1158
1159                 irq = platform_get_irq(pdev, 0);
1160                 if (irq < 0) {
1161                         dev_err(dev, "can't get IRQ resource\n");
1162                         goto err_irq;
1163                 }
1164
1165                 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1166                                 dev_name(dev), dd);
1167                 if (err) {
1168                         dev_err(dev, "Unable to grab omap-aes IRQ\n");
1169                         goto err_irq;
1170                 }
1171         }
1172
1173
1174         INIT_LIST_HEAD(&dd->list);
1175         spin_lock(&list_lock);
1176         list_add_tail(&dd->list, &dev_list);
1177         spin_unlock(&list_lock);
1178
1179         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1180                 if (!dd->pdata->algs_info[i].registered) {
1181                         for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1182                                 algp = &dd->pdata->algs_info[i].algs_list[j];
1183
1184                                 pr_debug("reg alg: %s\n", algp->cra_name);
1185                                 INIT_LIST_HEAD(&algp->cra_list);
1186
1187                                 err = crypto_register_alg(algp);
1188                                 if (err)
1189                                         goto err_algs;
1190
1191                                 dd->pdata->algs_info[i].registered++;
1192                         }
1193                 }
1194         }
1195
1196         /* Initialize crypto engine */
1197         dd->engine = crypto_engine_alloc_init(dev, 1);
1198         if (!dd->engine)
1199                 goto err_algs;
1200
1201         dd->engine->prepare_cipher_request = omap_aes_prepare_req;
1202         dd->engine->cipher_one_request = omap_aes_crypt_req;
1203         err = crypto_engine_start(dd->engine);
1204         if (err)
1205                 goto err_engine;
1206
1207         return 0;
1208 err_engine:
1209         crypto_engine_exit(dd->engine);
1210 err_algs:
1211         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1212                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1213                         crypto_unregister_alg(
1214                                         &dd->pdata->algs_info[i].algs_list[j]);
1215
1216         omap_aes_dma_cleanup(dd);
1217 err_irq:
1218         tasklet_kill(&dd->done_task);
1219         pm_runtime_disable(dev);
1220 err_res:
1221         dd = NULL;
1222 err_data:
1223         dev_err(dev, "initialization failed.\n");
1224         return err;
1225 }
1226
1227 static int omap_aes_remove(struct platform_device *pdev)
1228 {
1229         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1230         int i, j;
1231
1232         if (!dd)
1233                 return -ENODEV;
1234
1235         spin_lock(&list_lock);
1236         list_del(&dd->list);
1237         spin_unlock(&list_lock);
1238
1239         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1240                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1241                         crypto_unregister_alg(
1242                                         &dd->pdata->algs_info[i].algs_list[j]);
1243
1244         crypto_engine_exit(dd->engine);
1245         tasklet_kill(&dd->done_task);
1246         omap_aes_dma_cleanup(dd);
1247         pm_runtime_disable(dd->dev);
1248         dd = NULL;
1249
1250         return 0;
1251 }
1252
1253 #ifdef CONFIG_PM_SLEEP
1254 static int omap_aes_suspend(struct device *dev)
1255 {
1256         pm_runtime_put_sync(dev);
1257         return 0;
1258 }
1259
1260 static int omap_aes_resume(struct device *dev)
1261 {
1262         pm_runtime_get_sync(dev);
1263         return 0;
1264 }
1265 #endif
1266
1267 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1268
1269 static struct platform_driver omap_aes_driver = {
1270         .probe  = omap_aes_probe,
1271         .remove = omap_aes_remove,
1272         .driver = {
1273                 .name   = "omap-aes",
1274                 .pm     = &omap_aes_pm_ops,
1275                 .of_match_table = omap_aes_of_match,
1276         },
1277 };
1278
1279 module_platform_driver(omap_aes_driver);
1280
1281 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1282 MODULE_LICENSE("GPL v2");
1283 MODULE_AUTHOR("Dmitry Kasatkin");
1284