drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40 #include <linux/slab.h>
  41 #include <linux/string.h>
  42
  43 #include <crypto/algapi.h>
  44 #include <crypto/aes.h>
  45 #include <crypto/des.h>
  46 #include <crypto/sha.h>
  47 #include <crypto/md5.h>
  48 #include <crypto/aead.h>
  49 #include <crypto/authenc.h>
  50 #include <crypto/skcipher.h>
  51 #include <crypto/hash.h>
  52 #include <crypto/internal/hash.h>
  53 #include <crypto/scatterwalk.h>
  54
  55 #include "talitos.h"
  56
  57 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
  58 {
  59         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
  60         talitos_ptr->eptr = upper_32_bits(dma_addr);
  61 }
  62
  63 /*
  64  * map virtual single (contiguous) pointer to h/w descriptor pointer
  65  */
  66 static void map_single_talitos_ptr(struct device *dev,
  67                                    struct talitos_ptr *talitos_ptr,
  68                                    unsigned short len, void *data,
  69                                    unsigned char extent,
  70                                    enum dma_data_direction dir)
  71 {
  72         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
  73
  74         talitos_ptr->len = cpu_to_be16(len);
  75         to_talitos_ptr(talitos_ptr, dma_addr);
  76         talitos_ptr->j_extent = extent;
  77 }
  78
  79 /*
  80  * unmap bus single (contiguous) h/w descriptor pointer
  81  */
  82 static void unmap_single_talitos_ptr(struct device *dev,
  83                                      struct talitos_ptr *talitos_ptr,
  84                                      enum dma_data_direction dir)
  85 {
  86         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
  87                          be16_to_cpu(talitos_ptr->len), dir);
  88 }
  89
  90 static int reset_channel(struct device *dev, int ch)
  91 {
  92         struct talitos_private *priv = dev_get_drvdata(dev);
  93         unsigned int timeout = TALITOS_TIMEOUT;
  94
  95         setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
  96
  97         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
  98                && --timeout)
  99                 cpu_relax();
 100
 101         if (timeout == 0) {
 102                 dev_err(dev, "failed to reset channel %d\n", ch);
 103                 return -EIO;
 104         }
 105
 106         /* set 36-bit addressing, done writeback enable and done IRQ enable */
 107         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
 108                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
 109
 110         /* and ICCR writeback, if available */
 111         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 112                 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
 113                           TALITOS_CCCR_LO_IWSE);
 114
 115         return 0;
 116 }
 117
 118 static int reset_device(struct device *dev)
 119 {
 120         struct talitos_private *priv = dev_get_drvdata(dev);
 121         unsigned int timeout = TALITOS_TIMEOUT;
 122         u32 mcr = TALITOS_MCR_SWR;
 123
 124         setbits32(priv->reg + TALITOS_MCR, mcr);
 125
 126         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 127                && --timeout)
 128                 cpu_relax();
 129
 130         if (priv->irq[1]) {
 131                 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
 132                 setbits32(priv->reg + TALITOS_MCR, mcr);
 133         }
 134
 135         if (timeout == 0) {
 136                 dev_err(dev, "failed to reset device\n");
 137                 return -EIO;
 138         }
 139
 140         return 0;
 141 }
 142
 143 /*
 144  * Reset and initialize the device
 145  */
 146 static int init_device(struct device *dev)
 147 {
 148         struct talitos_private *priv = dev_get_drvdata(dev);
 149         int ch, err;
 150
 151         /*
 152          * Master reset
 153          * errata documentation: warning: certain SEC interrupts
 154          * are not fully cleared by writing the MCR:SWR bit,
 155          * set bit twice to completely reset
 156          */
 157         err = reset_device(dev);
 158         if (err)
 159                 return err;
 160
 161         err = reset_device(dev);
 162         if (err)
 163                 return err;
 164
 165         /* reset channels */
 166         for (ch = 0; ch < priv->num_channels; ch++) {
 167                 err = reset_channel(dev, ch);
 168                 if (err)
 169                         return err;
 170         }
 171
 172         /* enable channel done and error interrupts */
 173         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 174         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 175
 176         /* disable integrity check error interrupts (use writeback instead) */
 177         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 178                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 179                           TALITOS_MDEUICR_LO_ICE);
 180
 181         return 0;
 182 }
 183
 184 /**
 185  * talitos_submit - submits a descriptor to the device for processing
 186  * @dev:        the SEC device to be used
 187  * @ch:         the SEC device channel to be used
 188  * @desc:       the descriptor to be processed by the device
 189  * @callback:   whom to call when processing is complete
 190  * @context:    a handle for use by caller (optional)
 191  *
 192  * desc must contain valid dma-mapped (bus physical) address pointers.
 193  * callback must check err and feedback in descriptor header
 194  * for device processing status.
 195  */
 196 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 197                    void (*callback)(struct device *dev,
 198                                     struct talitos_desc *desc,
 199                                     void *context, int error),
 200                    void *context)
 201 {
 202         struct talitos_private *priv = dev_get_drvdata(dev);
 203         struct talitos_request *request;
 204         unsigned long flags;
 205         int head;
 206
 207         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 208
 209         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
 210                 /* h/w fifo is full */
 211                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 212                 return -EAGAIN;
 213         }
 214
 215         head = priv->chan[ch].head;
 216         request = &priv->chan[ch].fifo[head];
 217
 218         /* map descriptor and save caller data */
 219         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 220                                            DMA_BIDIRECTIONAL);
 221         request->callback = callback;
 222         request->context = context;
 223
 224         /* increment fifo head */
 225         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
 226
 227         smp_wmb();
 228         request->desc = desc;
 229
 230         /* GO! */
 231         wmb();
 232         out_be32(priv->chan[ch].reg + TALITOS_FF,
 233                  upper_32_bits(request->dma_desc));
 234         out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
 235                  lower_32_bits(request->dma_desc));
 236
 237         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 238
 239         return -EINPROGRESS;
 240 }
 241 EXPORT_SYMBOL(talitos_submit);
 242
 243 /*
 244  * process what was done, notify callback of error if not
 245  */
 246 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 247 {
 248         struct talitos_private *priv = dev_get_drvdata(dev);
 249         struct talitos_request *request, saved_req;
 250         unsigned long flags;
 251         int tail, status;
 252
 253         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 254
 255         tail = priv->chan[ch].tail;
 256         while (priv->chan[ch].fifo[tail].desc) {
 257                 request = &priv->chan[ch].fifo[tail];
 258
 259                 /* descriptors with their done bits set don't get the error */
 260                 rmb();
 261                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 262                         status = 0;
 263                 else
 264                         if (!error)
 265                                 break;
 266                         else
 267                                 status = error;
 268
 269                 dma_unmap_single(dev, request->dma_desc,
 270                                  sizeof(struct talitos_desc),
 271                                  DMA_BIDIRECTIONAL);
 272
 273                 /* copy entries so we can call callback outside lock */
 274                 saved_req.desc = request->desc;
 275                 saved_req.callback = request->callback;
 276                 saved_req.context = request->context;
 277
 278                 /* release request entry in fifo */
 279                 smp_wmb();
 280                 request->desc = NULL;
 281
 282                 /* increment fifo tail */
 283                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
 284
 285                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 286
 287                 atomic_dec(&priv->chan[ch].submit_count);
 288
 289                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 290                                    status);
 291                 /* channel may resume processing in single desc error case */
 292                 if (error && !reset_ch && status == error)
 293                         return;
 294                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 295                 tail = priv->chan[ch].tail;
 296         }
 297
 298         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 299 }
 300
 301 /*
 302  * process completed requests for channels that have done status
 303  */
 304 #define DEF_TALITOS_DONE(name, ch_done_mask)                            \
 305 static void talitos_done_##name(unsigned long data)                     \
 306 {                                                                       \
 307         struct device *dev = (struct device *)data;                     \
 308         struct talitos_private *priv = dev_get_drvdata(dev);            \
 309         unsigned long flags;                                            \
 310                                                                         \
 311         if (ch_done_mask & 1)                                           \
 312                 flush_channel(dev, 0, 0, 0);                            \
 313         if (priv->num_channels == 1)                                    \
 314                 goto out;                                               \
 315         if (ch_done_mask & (1 << 2))                                    \
 316                 flush_channel(dev, 1, 0, 0);                            \
 317         if (ch_done_mask & (1 << 4))                                    \
 318                 flush_channel(dev, 2, 0, 0);                            \
 319         if (ch_done_mask & (1 << 6))                                    \
 320                 flush_channel(dev, 3, 0, 0);                            \
 321                                                                         \
 322 out:                                                                    \
 323         /* At this point, all completed channels have been processed */ \
 324         /* Unmask done interrupts for channels completed later on. */   \
 325         spin_lock_irqsave(&priv->reg_lock, flags);                      \
 326         setbits32(priv->reg + TALITOS_IMR, ch_done_mask);               \
 327         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);     \
 328         spin_unlock_irqrestore(&priv->reg_lock, flags);                 \
 329 }
 330 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
 331 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
 332 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
 333
 334 /*
 335  * locate current (offending) descriptor
 336  */
 337 static u32 current_desc_hdr(struct device *dev, int ch)
 338 {
 339         struct talitos_private *priv = dev_get_drvdata(dev);
 340         int tail = priv->chan[ch].tail;
 341         dma_addr_t cur_desc;
 342
 343         cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
 344
 345         while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
 346                 tail = (tail + 1) & (priv->fifo_len - 1);
 347                 if (tail == priv->chan[ch].tail) {
 348                         dev_err(dev, "couldn't locate current descriptor\n");
 349                         return 0;
 350                 }
 351         }
 352
 353         return priv->chan[ch].fifo[tail].desc->hdr;
 354 }
 355
 356 /*
 357  * user diagnostics; report root cause of error based on execution unit status
 358  */
 359 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
 360 {
 361         struct talitos_private *priv = dev_get_drvdata(dev);
 362         int i;
 363
 364         if (!desc_hdr)
 365                 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
 366
 367         switch (desc_hdr & DESC_HDR_SEL0_MASK) {
 368         case DESC_HDR_SEL0_AFEU:
 369                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 370                         in_be32(priv->reg + TALITOS_AFEUISR),
 371                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 372                 break;
 373         case DESC_HDR_SEL0_DEU:
 374                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 375                         in_be32(priv->reg + TALITOS_DEUISR),
 376                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 377                 break;
 378         case DESC_HDR_SEL0_MDEUA:
 379         case DESC_HDR_SEL0_MDEUB:
 380                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 381                         in_be32(priv->reg + TALITOS_MDEUISR),
 382                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 383                 break;
 384         case DESC_HDR_SEL0_RNG:
 385                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 386                         in_be32(priv->reg + TALITOS_RNGUISR),
 387                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 388                 break;
 389         case DESC_HDR_SEL0_PKEU:
 390                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 391                         in_be32(priv->reg + TALITOS_PKEUISR),
 392                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 393                 break;
 394         case DESC_HDR_SEL0_AESU:
 395                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 396                         in_be32(priv->reg + TALITOS_AESUISR),
 397                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 398                 break;
 399         case DESC_HDR_SEL0_CRCU:
 400                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 401                         in_be32(priv->reg + TALITOS_CRCUISR),
 402                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 403                 break;
 404         case DESC_HDR_SEL0_KEU:
 405                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 406                         in_be32(priv->reg + TALITOS_KEUISR),
 407                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 408                 break;
 409         }
 410
 411         switch (desc_hdr & DESC_HDR_SEL1_MASK) {
 412         case DESC_HDR_SEL1_MDEUA:
 413         case DESC_HDR_SEL1_MDEUB:
 414                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 415                         in_be32(priv->reg + TALITOS_MDEUISR),
 416                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 417                 break;
 418         case DESC_HDR_SEL1_CRCU:
 419                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 420                         in_be32(priv->reg + TALITOS_CRCUISR),
 421                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 422                 break;
 423         }
 424
 425         for (i = 0; i < 8; i++)
 426                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 427                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
 428                         in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
 429 }
 430
 431 /*
 432  * recover from error interrupts
 433  */
 434 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 435 {
 436         struct talitos_private *priv = dev_get_drvdata(dev);
 437         unsigned int timeout = TALITOS_TIMEOUT;
 438         int ch, error, reset_dev = 0, reset_ch = 0;
 439         u32 v, v_lo;
 440
 441         for (ch = 0; ch < priv->num_channels; ch++) {
 442                 /* skip channels without errors */
 443                 if (!(isr & (1 << (ch * 2 + 1))))
 444                         continue;
 445
 446                 error = -EINVAL;
 447
 448                 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
 449                 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
 450
 451                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 452                         dev_err(dev, "double fetch fifo overflow error\n");
 453                         error = -EAGAIN;
 454                         reset_ch = 1;
 455                 }
 456                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 457                         /* h/w dropped descriptor */
 458                         dev_err(dev, "single fetch fifo overflow error\n");
 459                         error = -EAGAIN;
 460                 }
 461                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 462                         dev_err(dev, "master data transfer error\n");
 463                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 464                         dev_err(dev, "s/g data length zero error\n");
 465                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 466                         dev_err(dev, "fetch pointer zero error\n");
 467                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 468                         dev_err(dev, "illegal descriptor header error\n");
 469                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 470                         dev_err(dev, "invalid execution unit error\n");
 471                 if (v_lo & TALITOS_CCPSR_LO_EU)
 472                         report_eu_error(dev, ch, current_desc_hdr(dev, ch));
 473                 if (v_lo & TALITOS_CCPSR_LO_GB)
 474                         dev_err(dev, "gather boundary error\n");
 475                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 476                         dev_err(dev, "gather return/length error\n");
 477                 if (v_lo & TALITOS_CCPSR_LO_SB)
 478                         dev_err(dev, "scatter boundary error\n");
 479                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 480                         dev_err(dev, "scatter return/length error\n");
 481
 482                 flush_channel(dev, ch, error, reset_ch);
 483
 484                 if (reset_ch) {
 485                         reset_channel(dev, ch);
 486                 } else {
 487                         setbits32(priv->chan[ch].reg + TALITOS_CCCR,
 488                                   TALITOS_CCCR_CONT);
 489                         setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
 490                         while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
 491                                TALITOS_CCCR_CONT) && --timeout)
 492                                 cpu_relax();
 493                         if (timeout == 0) {
 494                                 dev_err(dev, "failed to restart channel %d\n",
 495                                         ch);
 496                                 reset_dev = 1;
 497                         }
 498                 }
 499         }
 500         if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
 501                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 502                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 503
 504                 /* purge request queues */
 505                 for (ch = 0; ch < priv->num_channels; ch++)
 506                         flush_channel(dev, ch, -EIO, 1);
 507
 508                 /* reset and reinitialize the device */
 509                 init_device(dev);
 510         }
 511 }
 512
 513 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)           \
 514 static irqreturn_t talitos_interrupt_##name(int irq, void *data)               \
 515 {                                                                              \
 516         struct device *dev = data;                                             \
 517         struct talitos_private *priv = dev_get_drvdata(dev);                   \
 518         u32 isr, isr_lo;                                                       \
 519         unsigned long flags;                                                   \
 520                                                                                \
 521         spin_lock_irqsave(&priv->reg_lock, flags);                             \
 522         isr = in_be32(priv->reg + TALITOS_ISR);                                \
 523         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);                          \
 524         /* Acknowledge interrupt */                                            \
 525         out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
 526         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);                          \
 527                                                                                \
 528         if (unlikely(isr & ch_err_mask || isr_lo)) {                           \
 529                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 530                 talitos_error(dev, isr & ch_err_mask, isr_lo);                 \
 531         }                                                                      \
 532         else {                                                                 \
 533                 if (likely(isr & ch_done_mask)) {                              \
 534                         /* mask further done interrupts. */                    \
 535                         clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
 536                         /* done_task will unmask done interrupts at exit */    \
 537                         tasklet_schedule(&priv->done_task[tlet]);              \
 538                 }                                                              \
 539                 spin_unlock_irqrestore(&priv->reg_lock, flags);                \
 540         }                                                                      \
 541                                                                                \
 542         return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED :  \
 543                                                                 IRQ_NONE;      \
 544 }
 545 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
 546 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
 547 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
 548
 549 /*
 550  * hwrng
 551  */
 552 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 553 {
 554         struct device *dev = (struct device *)rng->priv;
 555         struct talitos_private *priv = dev_get_drvdata(dev);
 556         u32 ofl;
 557         int i;
 558
 559         for (i = 0; i < 20; i++) {
 560                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 561                       TALITOS_RNGUSR_LO_OFL;
 562                 if (ofl || !wait)
 563                         break;
 564                 udelay(10);
 565         }
 566
 567         return !!ofl;
 568 }
 569
 570 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 571 {
 572         struct device *dev = (struct device *)rng->priv;
 573         struct talitos_private *priv = dev_get_drvdata(dev);
 574
 575         /* rng fifo requires 64-bit accesses */
 576         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 577         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 578
 579         return sizeof(u32);
 580 }
 581
 582 static int talitos_rng_init(struct hwrng *rng)
 583 {
 584         struct device *dev = (struct device *)rng->priv;
 585         struct talitos_private *priv = dev_get_drvdata(dev);
 586         unsigned int timeout = TALITOS_TIMEOUT;
 587
 588         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 589         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 590                && --timeout)
 591                 cpu_relax();
 592         if (timeout == 0) {
 593                 dev_err(dev, "failed to reset rng hw\n");
 594                 return -ENODEV;
 595         }
 596
 597         /* start generating */
 598         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 599
 600         return 0;
 601 }
 602
 603 static int talitos_register_rng(struct device *dev)
 604 {
 605         struct talitos_private *priv = dev_get_drvdata(dev);
 606
 607         priv->rng.name          = dev_driver_string(dev),
 608         priv->rng.init          = talitos_rng_init,
 609         priv->rng.data_present  = talitos_rng_data_present,
 610         priv->rng.data_read     = talitos_rng_data_read,
 611         priv->rng.priv          = (unsigned long)dev;
 612
 613         return hwrng_register(&priv->rng);
 614 }
 615
 616 static void talitos_unregister_rng(struct device *dev)
 617 {
 618         struct talitos_private *priv = dev_get_drvdata(dev);
 619
 620         hwrng_unregister(&priv->rng);
 621 }
 622
 623 /*
 624  * crypto alg
 625  */
 626 #define TALITOS_CRA_PRIORITY            3000
 627 #define TALITOS_MAX_KEY_SIZE            96
 628 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 629
 630 #define MD5_BLOCK_SIZE    64
 631
 632 struct talitos_ctx {
 633         struct device *dev;
 634         int ch;
 635         __be32 desc_hdr_template;
 636         u8 key[TALITOS_MAX_KEY_SIZE];
 637         u8 iv[TALITOS_MAX_IV_LENGTH];
 638         unsigned int keylen;
 639         unsigned int enckeylen;
 640         unsigned int authkeylen;
 641         unsigned int authsize;
 642 };
 643
 644 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
 645 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 646
 647 struct talitos_ahash_req_ctx {
 648         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
 649         unsigned int hw_context_size;
 650         u8 buf[HASH_MAX_BLOCK_SIZE];
 651         u8 bufnext[HASH_MAX_BLOCK_SIZE];
 652         unsigned int swinit;
 653         unsigned int first;
 654         unsigned int last;
 655         unsigned int to_hash_later;
 656         u64 nbuf;
 657         struct scatterlist bufsl[2];
 658         struct scatterlist *psrc;
 659 };
 660
 661 static int aead_setauthsize(struct crypto_aead *authenc,
 662                             unsigned int authsize)
 663 {
 664         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 665
 666         ctx->authsize = authsize;
 667
 668         return 0;
 669 }
 670
 671 static int aead_setkey(struct crypto_aead *authenc,
 672                        const u8 *key, unsigned int keylen)
 673 {
 674         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 675         struct rtattr *rta = (void *)key;
 676         struct crypto_authenc_key_param *param;
 677         unsigned int authkeylen;
 678         unsigned int enckeylen;
 679
 680         if (!RTA_OK(rta, keylen))
 681                 goto badkey;
 682
 683         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
 684                 goto badkey;
 685
 686         if (RTA_PAYLOAD(rta) < sizeof(*param))
 687                 goto badkey;
 688
 689         param = RTA_DATA(rta);
 690         enckeylen = be32_to_cpu(param->enckeylen);
 691
 692         key += RTA_ALIGN(rta->rta_len);
 693         keylen -= RTA_ALIGN(rta->rta_len);
 694
 695         if (keylen < enckeylen)
 696                 goto badkey;
 697
 698         authkeylen = keylen - enckeylen;
 699
 700         if (keylen > TALITOS_MAX_KEY_SIZE)
 701                 goto badkey;
 702
 703         memcpy(&ctx->key, key, keylen);
 704
 705         ctx->keylen = keylen;
 706         ctx->enckeylen = enckeylen;
 707         ctx->authkeylen = authkeylen;
 708
 709         return 0;
 710
 711 badkey:
 712         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 713         return -EINVAL;
 714 }
 715
 716 /*
 717  * talitos_edesc - s/w-extended descriptor
 718  * @assoc_nents: number of segments in associated data scatterlist
 719  * @src_nents: number of segments in input scatterlist
 720  * @dst_nents: number of segments in output scatterlist
 721  * @assoc_chained: whether assoc is chained or not
 722  * @src_chained: whether src is chained or not
 723  * @dst_chained: whether dst is chained or not
 724  * @iv_dma: dma address of iv for checking continuity and link table
 725  * @dma_len: length of dma mapped link_tbl space
 726  * @dma_link_tbl: bus physical address of link_tbl
 727  * @desc: h/w descriptor
 728  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 729  *
 730  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 731  * is greater than 1, an integrity check value is concatenated to the end
 732  * of link_tbl data
 733  */
 734 struct talitos_edesc {
 735         int assoc_nents;
 736         int src_nents;
 737         int dst_nents;
 738         bool assoc_chained;
 739         bool src_chained;
 740         bool dst_chained;
 741         dma_addr_t iv_dma;
 742         int dma_len;
 743         dma_addr_t dma_link_tbl;
 744         struct talitos_desc desc;
 745         struct talitos_ptr link_tbl[0];
 746 };
 747
 748 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 749                           unsigned int nents, enum dma_data_direction dir,
 750                           bool chained)
 751 {
 752         if (unlikely(chained))
 753                 while (sg) {
 754                         dma_map_sg(dev, sg, 1, dir);
 755                         sg = scatterwalk_sg_next(sg);
 756                 }
 757         else
 758                 dma_map_sg(dev, sg, nents, dir);
 759         return nents;
 760 }
 761
 762 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 763                                    enum dma_data_direction dir)
 764 {
 765         while (sg) {
 766                 dma_unmap_sg(dev, sg, 1, dir);
 767                 sg = scatterwalk_sg_next(sg);
 768         }
 769 }
 770
 771 static void talitos_sg_unmap(struct device *dev,
 772                              struct talitos_edesc *edesc,
 773                              struct scatterlist *src,
 774                              struct scatterlist *dst)
 775 {
 776         unsigned int src_nents = edesc->src_nents ? : 1;
 777         unsigned int dst_nents = edesc->dst_nents ? : 1;
 778
 779         if (src != dst) {
 780                 if (edesc->src_chained)
 781                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 782                 else
 783                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 784
 785                 if (dst) {
 786                         if (edesc->dst_chained)
 787                                 talitos_unmap_sg_chain(dev, dst,
 788                                                        DMA_FROM_DEVICE);
 789                         else
 790                                 dma_unmap_sg(dev, dst, dst_nents,
 791                                              DMA_FROM_DEVICE);
 792                 }
 793         } else
 794                 if (edesc->src_chained)
 795                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 796                 else
 797                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 798 }
 799
 800 static void ipsec_esp_unmap(struct device *dev,
 801                             struct talitos_edesc *edesc,
 802                             struct aead_request *areq)
 803 {
 804         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 805         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 806         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 807         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 808
 809         if (edesc->assoc_chained)
 810                 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
 811         else
 812                 /* assoc_nents counts also for IV in non-contiguous cases */
 813                 dma_unmap_sg(dev, areq->assoc,
 814                              edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
 815                              DMA_TO_DEVICE);
 816
 817         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 818
 819         if (edesc->dma_len)
 820                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 821                                  DMA_BIDIRECTIONAL);
 822 }
 823
 824 /*
 825  * ipsec_esp descriptor callbacks
 826  */
 827 static void ipsec_esp_encrypt_done(struct device *dev,
 828                                    struct talitos_desc *desc, void *context,
 829                                    int err)
 830 {
 831         struct aead_request *areq = context;
 832         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 833         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 834         struct talitos_edesc *edesc;
 835         struct scatterlist *sg;
 836         void *icvdata;
 837
 838         edesc = container_of(desc, struct talitos_edesc, desc);
 839
 840         ipsec_esp_unmap(dev, edesc, areq);
 841
 842         /* copy the generated ICV to dst */
 843         if (edesc->dst_nents) {
 844                 icvdata = &edesc->link_tbl[edesc->src_nents +
 845                                            edesc->dst_nents + 2 +
 846                                            edesc->assoc_nents];
 847                 sg = sg_last(areq->dst, edesc->dst_nents);
 848                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 849                        icvdata, ctx->authsize);
 850         }
 851
 852         kfree(edesc);
 853
 854         aead_request_complete(areq, err);
 855 }
 856
 857 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 858                                           struct talitos_desc *desc,
 859                                           void *context, int err)
 860 {
 861         struct aead_request *req = context;
 862         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 863         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 864         struct talitos_edesc *edesc;
 865         struct scatterlist *sg;
 866         void *icvdata;
 867
 868         edesc = container_of(desc, struct talitos_edesc, desc);
 869
 870         ipsec_esp_unmap(dev, edesc, req);
 871
 872         if (!err) {
 873                 /* auth check */
 874                 if (edesc->dma_len)
 875                         icvdata = &edesc->link_tbl[edesc->src_nents +
 876                                                    edesc->dst_nents + 2 +
 877                                                    edesc->assoc_nents];
 878                 else
 879                         icvdata = &edesc->link_tbl[0];
 880
 881                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 882                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 883                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 884         }
 885
 886         kfree(edesc);
 887
 888         aead_request_complete(req, err);
 889 }
 890
 891 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 892                                           struct talitos_desc *desc,
 893                                           void *context, int err)
 894 {
 895         struct aead_request *req = context;
 896         struct talitos_edesc *edesc;
 897
 898         edesc = container_of(desc, struct talitos_edesc, desc);
 899
 900         ipsec_esp_unmap(dev, edesc, req);
 901
 902         /* check ICV auth status */
 903         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 904                      DESC_HDR_LO_ICCR1_PASS))
 905                 err = -EBADMSG;
 906
 907         kfree(edesc);
 908
 909         aead_request_complete(req, err);
 910 }
 911
 912 /*
 913  * convert scatterlist to SEC h/w link table format
 914  * stop at cryptlen bytes
 915  */
 916 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 917                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 918 {
 919         int n_sg = sg_count;
 920
 921         while (n_sg--) {
 922                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
 923                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 924                 link_tbl_ptr->j_extent = 0;
 925                 link_tbl_ptr++;
 926                 cryptlen -= sg_dma_len(sg);
 927                 sg = scatterwalk_sg_next(sg);
 928         }
 929
 930         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 931         link_tbl_ptr--;
 932         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 933                 /* Empty this entry, and move to previous one */
 934                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 935                 link_tbl_ptr->len = 0;
 936                 sg_count--;
 937                 link_tbl_ptr--;
 938         }
 939         be16_add_cpu(&link_tbl_ptr->len, cryptlen);
 940
 941         /* tag end of link table */
 942         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 943
 944         return sg_count;
 945 }
 946
 947 /*
 948  * fill in and submit ipsec_esp descriptor
 949  */
 950 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
 951                      u64 seq, void (*callback) (struct device *dev,
 952                                                 struct talitos_desc *desc,
 953                                                 void *context, int error))
 954 {
 955         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 956         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 957         struct device *dev = ctx->dev;
 958         struct talitos_desc *desc = &edesc->desc;
 959         unsigned int cryptlen = areq->cryptlen;
 960         unsigned int authsize = ctx->authsize;
 961         unsigned int ivsize = crypto_aead_ivsize(aead);
 962         int sg_count, ret;
 963         int sg_link_tbl_len;
 964
 965         /* hmac key */
 966         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 967                                0, DMA_TO_DEVICE);
 968
 969         /* hmac data */
 970         desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
 971         if (edesc->assoc_nents) {
 972                 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
 973                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
 974
 975                 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
 976                                sizeof(struct talitos_ptr));
 977                 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
 978
 979                 /* assoc_nents - 1 entries for assoc, 1 for IV */
 980                 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
 981                                           areq->assoclen, tbl_ptr);
 982
 983                 /* add IV to link table */
 984                 tbl_ptr += sg_count - 1;
 985                 tbl_ptr->j_extent = 0;
 986                 tbl_ptr++;
 987                 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
 988                 tbl_ptr->len = cpu_to_be16(ivsize);
 989                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 990
 991                 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
 992                                            edesc->dma_len, DMA_BIDIRECTIONAL);
 993         } else {
 994                 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc));
 995                 desc->ptr[1].j_extent = 0;
 996         }
 997
 998         /* cipher iv */
 999         to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
1000         desc->ptr[2].len = cpu_to_be16(ivsize);
1001         desc->ptr[2].j_extent = 0;
1002         /* Sync needed for the aead_givencrypt case */
1003         dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
1004
1005         /* cipher key */
1006         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1007                                (char *)&ctx->key + ctx->authkeylen, 0,
1008                                DMA_TO_DEVICE);
1009
1010         /*
1011          * cipher in
1012          * map and adjust cipher len to aead request cryptlen.
1013          * extent is bytes of HMAC postpended to ciphertext,
1014          * typically 12 for ipsec
1015          */
1016         desc->ptr[4].len = cpu_to_be16(cryptlen);
1017         desc->ptr[4].j_extent = authsize;
1018
1019         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1020                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1021                                                            : DMA_TO_DEVICE,
1022                                   edesc->src_chained);
1023
1024         if (sg_count == 1) {
1025                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1026         } else {
1027                 sg_link_tbl_len = cryptlen;
1028
1029                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1030                         sg_link_tbl_len = cryptlen + authsize;
1031
1032                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1033                                           &edesc->link_tbl[0]);
1034                 if (sg_count > 1) {
1035                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1036                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1037                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1038                                                    edesc->dma_len,
1039                                                    DMA_BIDIRECTIONAL);
1040                 } else {
1041                         /* Only one segment now, so no link tbl needed */
1042                         to_talitos_ptr(&desc->ptr[4],
1043                                        sg_dma_address(areq->src));
1044                 }
1045         }
1046
1047         /* cipher out */
1048         desc->ptr[5].len = cpu_to_be16(cryptlen);
1049         desc->ptr[5].j_extent = authsize;
1050
1051         if (areq->src != areq->dst)
1052                 sg_count = talitos_map_sg(dev, areq->dst,
1053                                           edesc->dst_nents ? : 1,
1054                                           DMA_FROM_DEVICE, edesc->dst_chained);
1055
1056         if (sg_count == 1) {
1057                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1058         } else {
1059                 int tbl_off = edesc->src_nents + 1;
1060                 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1061
1062                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1063                                tbl_off * sizeof(struct talitos_ptr));
1064                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1065                                           tbl_ptr);
1066
1067                 /* Add an entry to the link table for ICV data */
1068                 tbl_ptr += sg_count - 1;
1069                 tbl_ptr->j_extent = 0;
1070                 tbl_ptr++;
1071                 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1072                 tbl_ptr->len = cpu_to_be16(authsize);
1073
1074                 /* icv data follows link tables */
1075                 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1076                                (tbl_off + edesc->dst_nents + 1 +
1077                                 edesc->assoc_nents) *
1078                                sizeof(struct talitos_ptr));
1079                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1080                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1081                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1082         }
1083
1084         /* iv out */
1085         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1086                                DMA_FROM_DEVICE);
1087
1088         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1089         if (ret != -EINPROGRESS) {
1090                 ipsec_esp_unmap(dev, edesc, areq);
1091                 kfree(edesc);
1092         }
1093         return ret;
1094 }
1095
1096 /*
1097  * derive number of elements in scatterlist
1098  */
1099 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1100 {
1101         struct scatterlist *sg = sg_list;
1102         int sg_nents = 0;
1103
1104         *chained = false;
1105         while (nbytes > 0) {
1106                 sg_nents++;
1107                 nbytes -= sg->length;
1108                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1109                         *chained = true;
1110                 sg = scatterwalk_sg_next(sg);
1111         }
1112
1113         return sg_nents;
1114 }
1115
1116 /**
1117  * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1118  * @sgl:                 The SG list
1119  * @nents:               Number of SG entries
1120  * @buf:                 Where to copy to
1121  * @buflen:              The number of bytes to copy
1122  * @skip:                The number of bytes to skip before copying.
1123  *                       Note: skip + buflen should equal SG total size.
1124  *
1125  * Returns the number of copied bytes.
1126  *
1127  **/
1128 static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1129                                     void *buf, size_t buflen, unsigned int skip)
1130 {
1131         unsigned int offset = 0;
1132         unsigned int boffset = 0;
1133         struct sg_mapping_iter miter;
1134         unsigned long flags;
1135         unsigned int sg_flags = SG_MITER_ATOMIC;
1136         size_t total_buffer = buflen + skip;
1137
1138         sg_flags |= SG_MITER_FROM_SG;
1139
1140         sg_miter_start(&miter, sgl, nents, sg_flags);
1141
1142         local_irq_save(flags);
1143
1144         while (sg_miter_next(&miter) && offset < total_buffer) {
1145                 unsigned int len;
1146                 unsigned int ignore;
1147
1148                 if ((offset + miter.length) > skip) {
1149                         if (offset < skip) {
1150                                 /* Copy part of this segment */
1151                                 ignore = skip - offset;
1152                                 len = miter.length - ignore;
1153                                 if (boffset + len > buflen)
1154                                         len = buflen - boffset;
1155                                 memcpy(buf + boffset, miter.addr + ignore, len);
1156                         } else {
1157                                 /* Copy all of this segment (up to buflen) */
1158                                 len = miter.length;
1159                                 if (boffset + len > buflen)
1160                                         len = buflen - boffset;
1161                                 memcpy(buf + boffset, miter.addr, len);
1162                         }
1163                         boffset += len;
1164                 }
1165                 offset += miter.length;
1166         }
1167
1168         sg_miter_stop(&miter);
1169
1170         local_irq_restore(flags);
1171         return boffset;
1172 }
1173
1174 /*
1175  * allocate and map the extended descriptor
1176  */
1177 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1178                                                  struct scatterlist *assoc,
1179                                                  struct scatterlist *src,
1180                                                  struct scatterlist *dst,
1181                                                  u8 *iv,
1182                                                  unsigned int assoclen,
1183                                                  unsigned int cryptlen,
1184                                                  unsigned int authsize,
1185                                                  unsigned int ivsize,
1186                                                  int icv_stashing,
1187                                                  u32 cryptoflags)
1188 {
1189         struct talitos_edesc *edesc;
1190         int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1191         bool assoc_chained = false, src_chained = false, dst_chained = false;
1192         dma_addr_t iv_dma = 0;
1193         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1194                       GFP_ATOMIC;
1195
1196         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1197                 dev_err(dev, "length exceeds h/w max limit\n");
1198                 return ERR_PTR(-EINVAL);
1199         }
1200
1201         if (iv)
1202                 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1203
1204         if (assoc) {
1205                 /*
1206                  * Currently it is assumed that iv is provided whenever assoc
1207                  * is.
1208                  */
1209                 BUG_ON(!iv);
1210
1211                 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1212                 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1213                                assoc_chained);
1214                 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1215
1216                 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1217                         assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1218         }
1219
1220         src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1221         src_nents = (src_nents == 1) ? 0 : src_nents;
1222
1223         if (!dst) {
1224                 dst_nents = 0;
1225         } else {
1226                 if (dst == src) {
1227                         dst_nents = src_nents;
1228                 } else {
1229                         dst_nents = sg_count(dst, cryptlen + authsize,
1230                                              &dst_chained);
1231                         dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1232                 }
1233         }
1234
1235         /*
1236          * allocate space for base edesc plus the link tables,
1237          * allowing for two separate entries for ICV and generated ICV (+ 2),
1238          * and the ICV data itself
1239          */
1240         alloc_len = sizeof(struct talitos_edesc);
1241         if (assoc_nents || src_nents || dst_nents) {
1242                 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1243                           sizeof(struct talitos_ptr) + authsize;
1244                 alloc_len += dma_len;
1245         } else {
1246                 dma_len = 0;
1247                 alloc_len += icv_stashing ? authsize : 0;
1248         }
1249
1250         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1251         if (!edesc) {
1252                 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1253                 if (iv_dma)
1254                         dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1255                 dev_err(dev, "could not allocate edescriptor\n");
1256                 return ERR_PTR(-ENOMEM);
1257         }
1258
1259         edesc->assoc_nents = assoc_nents;
1260         edesc->src_nents = src_nents;
1261         edesc->dst_nents = dst_nents;
1262         edesc->assoc_chained = assoc_chained;
1263         edesc->src_chained = src_chained;
1264         edesc->dst_chained = dst_chained;
1265         edesc->iv_dma = iv_dma;
1266         edesc->dma_len = dma_len;
1267         if (dma_len)
1268                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1269                                                      edesc->dma_len,
1270                                                      DMA_BIDIRECTIONAL);
1271
1272         return edesc;
1273 }
1274
1275 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1276                                               int icv_stashing)
1277 {
1278         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1279         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1280         unsigned int ivsize = crypto_aead_ivsize(authenc);
1281
1282         return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1283                                    iv, areq->assoclen, areq->cryptlen,
1284                                    ctx->authsize, ivsize, icv_stashing,
1285                                    areq->base.flags);
1286 }
1287
1288 static int aead_encrypt(struct aead_request *req)
1289 {
1290         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1291         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1292         struct talitos_edesc *edesc;
1293
1294         /* allocate extended descriptor */
1295         edesc = aead_edesc_alloc(req, req->iv, 0);
1296         if (IS_ERR(edesc))
1297                 return PTR_ERR(edesc);
1298
1299         /* set encrypt */
1300         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1301
1302         return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1303 }
1304
1305 static int aead_decrypt(struct aead_request *req)
1306 {
1307         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1308         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1309         unsigned int authsize = ctx->authsize;
1310         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1311         struct talitos_edesc *edesc;
1312         struct scatterlist *sg;
1313         void *icvdata;
1314
1315         req->cryptlen -= authsize;
1316
1317         /* allocate extended descriptor */
1318         edesc = aead_edesc_alloc(req, req->iv, 1);
1319         if (IS_ERR(edesc))
1320                 return PTR_ERR(edesc);
1321
1322         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1323             ((!edesc->src_nents && !edesc->dst_nents) ||
1324              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1325
1326                 /* decrypt and check the ICV */
1327                 edesc->desc.hdr = ctx->desc_hdr_template |
1328                                   DESC_HDR_DIR_INBOUND |
1329                                   DESC_HDR_MODE1_MDEU_CICV;
1330
1331                 /* reset integrity check result bits */
1332                 edesc->desc.hdr_lo = 0;
1333
1334                 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1335         }
1336
1337         /* Have to check the ICV with software */
1338         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1339
1340         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1341         if (edesc->dma_len)
1342                 icvdata = &edesc->link_tbl[edesc->src_nents +
1343                                            edesc->dst_nents + 2 +
1344                                            edesc->assoc_nents];
1345         else
1346                 icvdata = &edesc->link_tbl[0];
1347
1348         sg = sg_last(req->src, edesc->src_nents ? : 1);
1349
1350         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1351                ctx->authsize);
1352
1353         return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1354 }
1355
1356 static int aead_givencrypt(struct aead_givcrypt_request *req)
1357 {
1358         struct aead_request *areq = &req->areq;
1359         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1360         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1361         struct talitos_edesc *edesc;
1362
1363         /* allocate extended descriptor */
1364         edesc = aead_edesc_alloc(areq, req->giv, 0);
1365         if (IS_ERR(edesc))
1366                 return PTR_ERR(edesc);
1367
1368         /* set encrypt */
1369         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1370
1371         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1372         /* avoid consecutive packets going out with same IV */
1373         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1374
1375         return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1376 }
1377
1378 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1379                              const u8 *key, unsigned int keylen)
1380 {
1381         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1382
1383         memcpy(&ctx->key, key, keylen);
1384         ctx->keylen = keylen;
1385
1386         return 0;
1387 }
1388
1389 static void common_nonsnoop_unmap(struct device *dev,
1390                                   struct talitos_edesc *edesc,
1391                                   struct ablkcipher_request *areq)
1392 {
1393         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1394         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1395         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1396
1397         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1398
1399         if (edesc->dma_len)
1400                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1401                                  DMA_BIDIRECTIONAL);
1402 }
1403
1404 static void ablkcipher_done(struct device *dev,
1405                             struct talitos_desc *desc, void *context,
1406                             int err)
1407 {
1408         struct ablkcipher_request *areq = context;
1409         struct talitos_edesc *edesc;
1410
1411         edesc = container_of(desc, struct talitos_edesc, desc);
1412
1413         common_nonsnoop_unmap(dev, edesc, areq);
1414
1415         kfree(edesc);
1416
1417         areq->base.complete(&areq->base, err);
1418 }
1419
1420 static int common_nonsnoop(struct talitos_edesc *edesc,
1421                            struct ablkcipher_request *areq,
1422                            void (*callback) (struct device *dev,
1423                                              struct talitos_desc *desc,
1424                                              void *context, int error))
1425 {
1426         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1427         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1428         struct device *dev = ctx->dev;
1429         struct talitos_desc *desc = &edesc->desc;
1430         unsigned int cryptlen = areq->nbytes;
1431         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1432         int sg_count, ret;
1433
1434         /* first DWORD empty */
1435         desc->ptr[0].len = 0;
1436         to_talitos_ptr(&desc->ptr[0], 0);
1437         desc->ptr[0].j_extent = 0;
1438
1439         /* cipher iv */
1440         to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1441         desc->ptr[1].len = cpu_to_be16(ivsize);
1442         desc->ptr[1].j_extent = 0;
1443
1444         /* cipher key */
1445         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1446                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1447
1448         /*
1449          * cipher in
1450          */
1451         desc->ptr[3].len = cpu_to_be16(cryptlen);
1452         desc->ptr[3].j_extent = 0;
1453
1454         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1455                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1456                                                            : DMA_TO_DEVICE,
1457                                   edesc->src_chained);
1458
1459         if (sg_count == 1) {
1460                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1461         } else {
1462                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1463                                           &edesc->link_tbl[0]);
1464                 if (sg_count > 1) {
1465                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1466                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1467                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1468                                                    edesc->dma_len,
1469                                                    DMA_BIDIRECTIONAL);
1470                 } else {
1471                         /* Only one segment now, so no link tbl needed */
1472                         to_talitos_ptr(&desc->ptr[3],
1473                                        sg_dma_address(areq->src));
1474                 }
1475         }
1476
1477         /* cipher out */
1478         desc->ptr[4].len = cpu_to_be16(cryptlen);
1479         desc->ptr[4].j_extent = 0;
1480
1481         if (areq->src != areq->dst)
1482                 sg_count = talitos_map_sg(dev, areq->dst,
1483                                           edesc->dst_nents ? : 1,
1484                                           DMA_FROM_DEVICE, edesc->dst_chained);
1485
1486         if (sg_count == 1) {
1487                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1488         } else {
1489                 struct talitos_ptr *link_tbl_ptr =
1490                         &edesc->link_tbl[edesc->src_nents + 1];
1491
1492                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1493                                               (edesc->src_nents + 1) *
1494                                               sizeof(struct talitos_ptr));
1495                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1496                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1497                                           link_tbl_ptr);
1498                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1499                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1500         }
1501
1502         /* iv out */
1503         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1504                                DMA_FROM_DEVICE);
1505
1506         /* last DWORD empty */
1507         desc->ptr[6].len = 0;
1508         to_talitos_ptr(&desc->ptr[6], 0);
1509         desc->ptr[6].j_extent = 0;
1510
1511         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1512         if (ret != -EINPROGRESS) {
1513                 common_nonsnoop_unmap(dev, edesc, areq);
1514                 kfree(edesc);
1515         }
1516         return ret;
1517 }
1518
1519 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1520                                                     areq)
1521 {
1522         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1523         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1524         unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1525
1526         return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1527                                    areq->info, 0, areq->nbytes, 0, ivsize, 0,
1528                                    areq->base.flags);
1529 }
1530
1531 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1532 {
1533         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1534         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1535         struct talitos_edesc *edesc;
1536
1537         /* allocate extended descriptor */
1538         edesc = ablkcipher_edesc_alloc(areq);
1539         if (IS_ERR(edesc))
1540                 return PTR_ERR(edesc);
1541
1542         /* set encrypt */
1543         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1544
1545         return common_nonsnoop(edesc, areq, ablkcipher_done);
1546 }
1547
1548 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1549 {
1550         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1551         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1552         struct talitos_edesc *edesc;
1553
1554         /* allocate extended descriptor */
1555         edesc = ablkcipher_edesc_alloc(areq);
1556         if (IS_ERR(edesc))
1557                 return PTR_ERR(edesc);
1558
1559         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1560
1561         return common_nonsnoop(edesc, areq, ablkcipher_done);
1562 }
1563
1564 static void common_nonsnoop_hash_unmap(struct device *dev,
1565                                        struct talitos_edesc *edesc,
1566                                        struct ahash_request *areq)
1567 {
1568         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1569
1570         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1571
1572         /* When using hashctx-in, must unmap it. */
1573         if (edesc->desc.ptr[1].len)
1574                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1575                                          DMA_TO_DEVICE);
1576
1577         if (edesc->desc.ptr[2].len)
1578                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1579                                          DMA_TO_DEVICE);
1580
1581         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1582
1583         if (edesc->dma_len)
1584                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1585                                  DMA_BIDIRECTIONAL);
1586
1587 }
1588
1589 static void ahash_done(struct device *dev,
1590                        struct talitos_desc *desc, void *context,
1591                        int err)
1592 {
1593         struct ahash_request *areq = context;
1594         struct talitos_edesc *edesc =
1595                  container_of(desc, struct talitos_edesc, desc);
1596         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1597
1598         if (!req_ctx->last && req_ctx->to_hash_later) {
1599                 /* Position any partial block for next update/final/finup */
1600                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1601                 req_ctx->nbuf = req_ctx->to_hash_later;
1602         }
1603         common_nonsnoop_hash_unmap(dev, edesc, areq);
1604
1605         kfree(edesc);
1606
1607         areq->base.complete(&areq->base, err);
1608 }
1609
1610 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1611                                 struct ahash_request *areq, unsigned int length,
1612                                 void (*callback) (struct device *dev,
1613                                                   struct talitos_desc *desc,
1614                                                   void *context, int error))
1615 {
1616         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1617         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1618         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1619         struct device *dev = ctx->dev;
1620         struct talitos_desc *desc = &edesc->desc;
1621         int sg_count, ret;
1622
1623         /* first DWORD empty */
1624         desc->ptr[0] = zero_entry;
1625
1626         /* hash context in */
1627         if (!req_ctx->first || req_ctx->swinit) {
1628                 map_single_talitos_ptr(dev, &desc->ptr[1],
1629                                        req_ctx->hw_context_size,
1630                                        (char *)req_ctx->hw_context, 0,
1631                                        DMA_TO_DEVICE);
1632                 req_ctx->swinit = 0;
1633         } else {
1634                 desc->ptr[1] = zero_entry;
1635                 /* Indicate next op is not the first. */
1636                 req_ctx->first = 0;
1637         }
1638
1639         /* HMAC key */
1640         if (ctx->keylen)
1641                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1642                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1643         else
1644                 desc->ptr[2] = zero_entry;
1645
1646         /*
1647          * data in
1648          */
1649         desc->ptr[3].len = cpu_to_be16(length);
1650         desc->ptr[3].j_extent = 0;
1651
1652         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1653                                   edesc->src_nents ? : 1,
1654                                   DMA_TO_DEVICE, edesc->src_chained);
1655
1656         if (sg_count == 1) {
1657                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1658         } else {
1659                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1660                                           &edesc->link_tbl[0]);
1661                 if (sg_count > 1) {
1662                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1663                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1664                         dma_sync_single_for_device(ctx->dev,
1665                                                    edesc->dma_link_tbl,
1666                                                    edesc->dma_len,
1667                                                    DMA_BIDIRECTIONAL);
1668                 } else {
1669                         /* Only one segment now, so no link tbl needed */
1670                         to_talitos_ptr(&desc->ptr[3],
1671                                        sg_dma_address(req_ctx->psrc));
1672                 }
1673         }
1674
1675         /* fifth DWORD empty */
1676         desc->ptr[4] = zero_entry;
1677
1678         /* hash/HMAC out -or- hash context out */
1679         if (req_ctx->last)
1680                 map_single_talitos_ptr(dev, &desc->ptr[5],
1681                                        crypto_ahash_digestsize(tfm),
1682                                        areq->result, 0, DMA_FROM_DEVICE);
1683         else
1684                 map_single_talitos_ptr(dev, &desc->ptr[5],
1685                                        req_ctx->hw_context_size,
1686                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1687
1688         /* last DWORD empty */
1689         desc->ptr[6] = zero_entry;
1690
1691         ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1692         if (ret != -EINPROGRESS) {
1693                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1694                 kfree(edesc);
1695         }
1696         return ret;
1697 }
1698
1699 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1700                                                unsigned int nbytes)
1701 {
1702         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1703         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1704         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1705
1706         return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1707                                    nbytes, 0, 0, 0, areq->base.flags);
1708 }
1709
1710 static int ahash_init(struct ahash_request *areq)
1711 {
1712         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1713         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1714
1715         /* Initialize the context */
1716         req_ctx->nbuf = 0;
1717         req_ctx->first = 1; /* first indicates h/w must init its context */
1718         req_ctx->swinit = 0; /* assume h/w init of context */
1719         req_ctx->hw_context_size =
1720                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1721                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1722                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1723
1724         return 0;
1725 }
1726
1727 /*
1728  * on h/w without explicit sha224 support, we initialize h/w context
1729  * manually with sha224 constants, and tell it to run sha256.
1730  */
1731 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1732 {
1733         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1734
1735         ahash_init(areq);
1736         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1737
1738         req_ctx->hw_context[0] = SHA224_H0;
1739         req_ctx->hw_context[1] = SHA224_H1;
1740         req_ctx->hw_context[2] = SHA224_H2;
1741         req_ctx->hw_context[3] = SHA224_H3;
1742         req_ctx->hw_context[4] = SHA224_H4;
1743         req_ctx->hw_context[5] = SHA224_H5;
1744         req_ctx->hw_context[6] = SHA224_H6;
1745         req_ctx->hw_context[7] = SHA224_H7;
1746
1747         /* init 64-bit count */
1748         req_ctx->hw_context[8] = 0;
1749         req_ctx->hw_context[9] = 0;
1750
1751         return 0;
1752 }
1753
1754 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1755 {
1756         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1757         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1758         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1759         struct talitos_edesc *edesc;
1760         unsigned int blocksize =
1761                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1762         unsigned int nbytes_to_hash;
1763         unsigned int to_hash_later;
1764         unsigned int nsg;
1765         bool chained;
1766
1767         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1768                 /* Buffer up to one whole block */
1769                 sg_copy_to_buffer(areq->src,
1770                                   sg_count(areq->src, nbytes, &chained),
1771                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1772                 req_ctx->nbuf += nbytes;
1773                 return 0;
1774         }
1775
1776         /* At least (blocksize + 1) bytes are available to hash */
1777         nbytes_to_hash = nbytes + req_ctx->nbuf;
1778         to_hash_later = nbytes_to_hash & (blocksize - 1);
1779
1780         if (req_ctx->last)
1781                 to_hash_later = 0;
1782         else if (to_hash_later)
1783                 /* There is a partial block. Hash the full block(s) now */
1784                 nbytes_to_hash -= to_hash_later;
1785         else {
1786                 /* Keep one block buffered */
1787                 nbytes_to_hash -= blocksize;
1788                 to_hash_later = blocksize;
1789         }
1790
1791         /* Chain in any previously buffered data */
1792         if (req_ctx->nbuf) {
1793                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1794                 sg_init_table(req_ctx->bufsl, nsg);
1795                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1796                 if (nsg > 1)
1797                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1798                 req_ctx->psrc = req_ctx->bufsl;
1799         } else
1800                 req_ctx->psrc = areq->src;
1801
1802         if (to_hash_later) {
1803                 int nents = sg_count(areq->src, nbytes, &chained);
1804                 sg_copy_end_to_buffer(areq->src, nents,
1805                                       req_ctx->bufnext,
1806                                       to_hash_later,
1807                                       nbytes - to_hash_later);
1808         }
1809         req_ctx->to_hash_later = to_hash_later;
1810
1811         /* Allocate extended descriptor */
1812         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1813         if (IS_ERR(edesc))
1814                 return PTR_ERR(edesc);
1815
1816         edesc->desc.hdr = ctx->desc_hdr_template;
1817
1818         /* On last one, request SEC to pad; otherwise continue */
1819         if (req_ctx->last)
1820                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1821         else
1822                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1823
1824         /* request SEC to INIT hash. */
1825         if (req_ctx->first && !req_ctx->swinit)
1826                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1827
1828         /* When the tfm context has a keylen, it's an HMAC.
1829          * A first or last (ie. not middle) descriptor must request HMAC.
1830          */
1831         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1832                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1833
1834         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1835                                     ahash_done);
1836 }
1837
1838 static int ahash_update(struct ahash_request *areq)
1839 {
1840         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1841
1842         req_ctx->last = 0;
1843
1844         return ahash_process_req(areq, areq->nbytes);
1845 }
1846
1847 static int ahash_final(struct ahash_request *areq)
1848 {
1849         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1850
1851         req_ctx->last = 1;
1852
1853         return ahash_process_req(areq, 0);
1854 }
1855
1856 static int ahash_finup(struct ahash_request *areq)
1857 {
1858         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1859
1860         req_ctx->last = 1;
1861
1862         return ahash_process_req(areq, areq->nbytes);
1863 }
1864
1865 static int ahash_digest(struct ahash_request *areq)
1866 {
1867         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1868         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1869
1870         ahash->init(areq);
1871         req_ctx->last = 1;
1872
1873         return ahash_process_req(areq, areq->nbytes);
1874 }
1875
1876 struct keyhash_result {
1877         struct completion completion;
1878         int err;
1879 };
1880
1881 static void keyhash_complete(struct crypto_async_request *req, int err)
1882 {
1883         struct keyhash_result *res = req->data;
1884
1885         if (err == -EINPROGRESS)
1886                 return;
1887
1888         res->err = err;
1889         complete(&res->completion);
1890 }
1891
1892 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1893                    u8 *hash)
1894 {
1895         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1896
1897         struct scatterlist sg[1];
1898         struct ahash_request *req;
1899         struct keyhash_result hresult;
1900         int ret;
1901
1902         init_completion(&hresult.completion);
1903
1904         req = ahash_request_alloc(tfm, GFP_KERNEL);
1905         if (!req)
1906                 return -ENOMEM;
1907
1908         /* Keep tfm keylen == 0 during hash of the long key */
1909         ctx->keylen = 0;
1910         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1911                                    keyhash_complete, &hresult);
1912
1913         sg_init_one(&sg[0], key, keylen);
1914
1915         ahash_request_set_crypt(req, sg, hash, keylen);
1916         ret = crypto_ahash_digest(req);
1917         switch (ret) {
1918         case 0:
1919                 break;
1920         case -EINPROGRESS:
1921         case -EBUSY:
1922                 ret = wait_for_completion_interruptible(
1923                         &hresult.completion);
1924                 if (!ret)
1925                         ret = hresult.err;
1926                 break;
1927         default:
1928                 break;
1929         }
1930         ahash_request_free(req);
1931
1932         return ret;
1933 }
1934
1935 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1936                         unsigned int keylen)
1937 {
1938         struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1939         unsigned int blocksize =
1940                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1941         unsigned int digestsize = crypto_ahash_digestsize(tfm);
1942         unsigned int keysize = keylen;
1943         u8 hash[SHA512_DIGEST_SIZE];
1944         int ret;
1945
1946         if (keylen <= blocksize)
1947                 memcpy(ctx->key, key, keysize);
1948         else {
1949                 /* Must get the hash of the long key */
1950                 ret = keyhash(tfm, key, keylen, hash);
1951
1952                 if (ret) {
1953                         crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1954                         return -EINVAL;
1955                 }
1956
1957                 keysize = digestsize;
1958                 memcpy(ctx->key, hash, digestsize);
1959         }
1960
1961         ctx->keylen = keysize;
1962
1963         return 0;
1964 }
1965
1966
1967 struct talitos_alg_template {
1968         u32 type;
1969         union {
1970                 struct crypto_alg crypto;
1971                 struct ahash_alg hash;
1972         } alg;
1973         __be32 desc_hdr_template;
1974 };
1975
1976 static struct talitos_alg_template driver_algs[] = {
1977         /*
1978          * AEAD algorithms. These use a single-pass ipsec_esp descriptor.
1979          * authencesn(*,*) is also registered, although not present
1980          * explicitly here.
1981          */
1982         {       .type = CRYPTO_ALG_TYPE_AEAD,
1983                 .alg.crypto = {
1984                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1985                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1986                         .cra_blocksize = AES_BLOCK_SIZE,
1987                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1988                         .cra_aead = {
1989                                 .ivsize = AES_BLOCK_SIZE,
1990                                 .maxauthsize = SHA1_DIGEST_SIZE,
1991                         }
1992                 },
1993                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1994                                      DESC_HDR_SEL0_AESU |
1995                                      DESC_HDR_MODE0_AESU_CBC |
1996                                      DESC_HDR_SEL1_MDEUA |
1997                                      DESC_HDR_MODE1_MDEU_INIT |
1998                                      DESC_HDR_MODE1_MDEU_PAD |
1999                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2000         },
2001         {       .type = CRYPTO_ALG_TYPE_AEAD,
2002                 .alg.crypto = {
2003                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
2004                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
2005                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2006                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2007                         .cra_aead = {
2008                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2009                                 .maxauthsize = SHA1_DIGEST_SIZE,
2010                         }
2011                 },
2012                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2013                                      DESC_HDR_SEL0_DEU |
2014                                      DESC_HDR_MODE0_DEU_CBC |
2015                                      DESC_HDR_MODE0_DEU_3DES |
2016                                      DESC_HDR_SEL1_MDEUA |
2017                                      DESC_HDR_MODE1_MDEU_INIT |
2018                                      DESC_HDR_MODE1_MDEU_PAD |
2019                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2020         },
2021         {       .type = CRYPTO_ALG_TYPE_AEAD,
2022                 .alg.crypto = {
2023                         .cra_name = "authenc(hmac(sha224),cbc(aes))",
2024                         .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
2025                         .cra_blocksize = AES_BLOCK_SIZE,
2026                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2027                         .cra_aead = {
2028                                 .ivsize = AES_BLOCK_SIZE,
2029                                 .maxauthsize = SHA224_DIGEST_SIZE,
2030                         }
2031                 },
2032                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2033                                      DESC_HDR_SEL0_AESU |
2034                                      DESC_HDR_MODE0_AESU_CBC |
2035                                      DESC_HDR_SEL1_MDEUA |
2036                                      DESC_HDR_MODE1_MDEU_INIT |
2037                                      DESC_HDR_MODE1_MDEU_PAD |
2038                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2039         },
2040         {       .type = CRYPTO_ALG_TYPE_AEAD,
2041                 .alg.crypto = {
2042                         .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
2043                         .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
2044                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2045                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2046                         .cra_aead = {
2047                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2048                                 .maxauthsize = SHA224_DIGEST_SIZE,
2049                         }
2050                 },
2051                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2052                                      DESC_HDR_SEL0_DEU |
2053                                      DESC_HDR_MODE0_DEU_CBC |
2054                                      DESC_HDR_MODE0_DEU_3DES |
2055                                      DESC_HDR_SEL1_MDEUA |
2056                                      DESC_HDR_MODE1_MDEU_INIT |
2057                                      DESC_HDR_MODE1_MDEU_PAD |
2058                                      DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2059         },
2060         {       .type = CRYPTO_ALG_TYPE_AEAD,
2061                 .alg.crypto = {
2062                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
2063                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
2064                         .cra_blocksize = AES_BLOCK_SIZE,
2065                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2066                         .cra_aead = {
2067                                 .ivsize = AES_BLOCK_SIZE,
2068                                 .maxauthsize = SHA256_DIGEST_SIZE,
2069                         }
2070                 },
2071                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2072                                      DESC_HDR_SEL0_AESU |
2073                                      DESC_HDR_MODE0_AESU_CBC |
2074                                      DESC_HDR_SEL1_MDEUA |
2075                                      DESC_HDR_MODE1_MDEU_INIT |
2076                                      DESC_HDR_MODE1_MDEU_PAD |
2077                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2078         },
2079         {       .type = CRYPTO_ALG_TYPE_AEAD,
2080                 .alg.crypto = {
2081                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2082                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2083                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2084                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2085                         .cra_aead = {
2086                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2087                                 .maxauthsize = SHA256_DIGEST_SIZE,
2088                         }
2089                 },
2090                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2091                                      DESC_HDR_SEL0_DEU |
2092                                      DESC_HDR_MODE0_DEU_CBC |
2093                                      DESC_HDR_MODE0_DEU_3DES |
2094                                      DESC_HDR_SEL1_MDEUA |
2095                                      DESC_HDR_MODE1_MDEU_INIT |
2096                                      DESC_HDR_MODE1_MDEU_PAD |
2097                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2098         },
2099         {       .type = CRYPTO_ALG_TYPE_AEAD,
2100                 .alg.crypto = {
2101                         .cra_name = "authenc(hmac(sha384),cbc(aes))",
2102                         .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2103                         .cra_blocksize = AES_BLOCK_SIZE,
2104                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2105                         .cra_aead = {
2106                                 .ivsize = AES_BLOCK_SIZE,
2107                                 .maxauthsize = SHA384_DIGEST_SIZE,
2108                         }
2109                 },
2110                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2111                                      DESC_HDR_SEL0_AESU |
2112                                      DESC_HDR_MODE0_AESU_CBC |
2113                                      DESC_HDR_SEL1_MDEUB |
2114                                      DESC_HDR_MODE1_MDEU_INIT |
2115                                      DESC_HDR_MODE1_MDEU_PAD |
2116                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2117         },
2118         {       .type = CRYPTO_ALG_TYPE_AEAD,
2119                 .alg.crypto = {
2120                         .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2121                         .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2122                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2123                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2124                         .cra_aead = {
2125                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2126                                 .maxauthsize = SHA384_DIGEST_SIZE,
2127                         }
2128                 },
2129                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2130                                      DESC_HDR_SEL0_DEU |
2131                                      DESC_HDR_MODE0_DEU_CBC |
2132                                      DESC_HDR_MODE0_DEU_3DES |
2133                                      DESC_HDR_SEL1_MDEUB |
2134                                      DESC_HDR_MODE1_MDEU_INIT |
2135                                      DESC_HDR_MODE1_MDEU_PAD |
2136                                      DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2137         },
2138         {       .type = CRYPTO_ALG_TYPE_AEAD,
2139                 .alg.crypto = {
2140                         .cra_name = "authenc(hmac(sha512),cbc(aes))",
2141                         .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2142                         .cra_blocksize = AES_BLOCK_SIZE,
2143                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2144                         .cra_aead = {
2145                                 .ivsize = AES_BLOCK_SIZE,
2146                                 .maxauthsize = SHA512_DIGEST_SIZE,
2147                         }
2148                 },
2149                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2150                                      DESC_HDR_SEL0_AESU |
2151                                      DESC_HDR_MODE0_AESU_CBC |
2152                                      DESC_HDR_SEL1_MDEUB |
2153                                      DESC_HDR_MODE1_MDEU_INIT |
2154                                      DESC_HDR_MODE1_MDEU_PAD |
2155                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2156         },
2157         {       .type = CRYPTO_ALG_TYPE_AEAD,
2158                 .alg.crypto = {
2159                         .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2160                         .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2161                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2162                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2163                         .cra_aead = {
2164                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2165                                 .maxauthsize = SHA512_DIGEST_SIZE,
2166                         }
2167                 },
2168                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2169                                      DESC_HDR_SEL0_DEU |
2170                                      DESC_HDR_MODE0_DEU_CBC |
2171                                      DESC_HDR_MODE0_DEU_3DES |
2172                                      DESC_HDR_SEL1_MDEUB |
2173                                      DESC_HDR_MODE1_MDEU_INIT |
2174                                      DESC_HDR_MODE1_MDEU_PAD |
2175                                      DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2176         },
2177         {       .type = CRYPTO_ALG_TYPE_AEAD,
2178                 .alg.crypto = {
2179                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2180                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2181                         .cra_blocksize = AES_BLOCK_SIZE,
2182                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2183                         .cra_aead = {
2184                                 .ivsize = AES_BLOCK_SIZE,
2185                                 .maxauthsize = MD5_DIGEST_SIZE,
2186                         }
2187                 },
2188                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2189                                      DESC_HDR_SEL0_AESU |
2190                                      DESC_HDR_MODE0_AESU_CBC |
2191                                      DESC_HDR_SEL1_MDEUA |
2192                                      DESC_HDR_MODE1_MDEU_INIT |
2193                                      DESC_HDR_MODE1_MDEU_PAD |
2194                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2195         },
2196         {       .type = CRYPTO_ALG_TYPE_AEAD,
2197                 .alg.crypto = {
2198                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2199                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2200                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2201                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2202                         .cra_aead = {
2203                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2204                                 .maxauthsize = MD5_DIGEST_SIZE,
2205                         }
2206                 },
2207                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2208                                      DESC_HDR_SEL0_DEU |
2209                                      DESC_HDR_MODE0_DEU_CBC |
2210                                      DESC_HDR_MODE0_DEU_3DES |
2211                                      DESC_HDR_SEL1_MDEUA |
2212                                      DESC_HDR_MODE1_MDEU_INIT |
2213                                      DESC_HDR_MODE1_MDEU_PAD |
2214                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2215         },
2216         /* ABLKCIPHER algorithms. */
2217         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2218                 .alg.crypto = {
2219                         .cra_name = "cbc(aes)",
2220                         .cra_driver_name = "cbc-aes-talitos",
2221                         .cra_blocksize = AES_BLOCK_SIZE,
2222                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2223                                      CRYPTO_ALG_ASYNC,
2224                         .cra_ablkcipher = {
2225                                 .min_keysize = AES_MIN_KEY_SIZE,
2226                                 .max_keysize = AES_MAX_KEY_SIZE,
2227                                 .ivsize = AES_BLOCK_SIZE,
2228                         }
2229                 },
2230                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2231                                      DESC_HDR_SEL0_AESU |
2232                                      DESC_HDR_MODE0_AESU_CBC,
2233         },
2234         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2235                 .alg.crypto = {
2236                         .cra_name = "cbc(des3_ede)",
2237                         .cra_driver_name = "cbc-3des-talitos",
2238                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2239                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2240                                      CRYPTO_ALG_ASYNC,
2241                         .cra_ablkcipher = {
2242                                 .min_keysize = DES3_EDE_KEY_SIZE,
2243                                 .max_keysize = DES3_EDE_KEY_SIZE,
2244                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2245                         }
2246                 },
2247                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2248                                      DESC_HDR_SEL0_DEU |
2249                                      DESC_HDR_MODE0_DEU_CBC |
2250                                      DESC_HDR_MODE0_DEU_3DES,
2251         },
2252         /* AHASH algorithms. */
2253         {       .type = CRYPTO_ALG_TYPE_AHASH,
2254                 .alg.hash = {
2255                         .halg.digestsize = MD5_DIGEST_SIZE,
2256                         .halg.base = {
2257                                 .cra_name = "md5",
2258                                 .cra_driver_name = "md5-talitos",
2259                                 .cra_blocksize = MD5_BLOCK_SIZE,
2260                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2261                                              CRYPTO_ALG_ASYNC,
2262                         }
2263                 },
2264                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2265                                      DESC_HDR_SEL0_MDEUA |
2266                                      DESC_HDR_MODE0_MDEU_MD5,
2267         },
2268         {       .type = CRYPTO_ALG_TYPE_AHASH,
2269                 .alg.hash = {
2270                         .halg.digestsize = SHA1_DIGEST_SIZE,
2271                         .halg.base = {
2272                                 .cra_name = "sha1",
2273                                 .cra_driver_name = "sha1-talitos",
2274                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2275                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2276                                              CRYPTO_ALG_ASYNC,
2277                         }
2278                 },
2279                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2280                                      DESC_HDR_SEL0_MDEUA |
2281                                      DESC_HDR_MODE0_MDEU_SHA1,
2282         },
2283         {       .type = CRYPTO_ALG_TYPE_AHASH,
2284                 .alg.hash = {
2285                         .halg.digestsize = SHA224_DIGEST_SIZE,
2286                         .halg.base = {
2287                                 .cra_name = "sha224",
2288                                 .cra_driver_name = "sha224-talitos",
2289                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2290                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2291                                              CRYPTO_ALG_ASYNC,
2292                         }
2293                 },
2294                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2295                                      DESC_HDR_SEL0_MDEUA |
2296                                      DESC_HDR_MODE0_MDEU_SHA224,
2297         },
2298         {       .type = CRYPTO_ALG_TYPE_AHASH,
2299                 .alg.hash = {
2300                         .halg.digestsize = SHA256_DIGEST_SIZE,
2301                         .halg.base = {
2302                                 .cra_name = "sha256",
2303                                 .cra_driver_name = "sha256-talitos",
2304                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2305                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2306                                              CRYPTO_ALG_ASYNC,
2307                         }
2308                 },
2309                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2310                                      DESC_HDR_SEL0_MDEUA |
2311                                      DESC_HDR_MODE0_MDEU_SHA256,
2312         },
2313         {       .type = CRYPTO_ALG_TYPE_AHASH,
2314                 .alg.hash = {
2315                         .halg.digestsize = SHA384_DIGEST_SIZE,
2316                         .halg.base = {
2317                                 .cra_name = "sha384",
2318                                 .cra_driver_name = "sha384-talitos",
2319                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2320                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2321                                              CRYPTO_ALG_ASYNC,
2322                         }
2323                 },
2324                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2325                                      DESC_HDR_SEL0_MDEUB |
2326                                      DESC_HDR_MODE0_MDEUB_SHA384,
2327         },
2328         {       .type = CRYPTO_ALG_TYPE_AHASH,
2329                 .alg.hash = {
2330                         .halg.digestsize = SHA512_DIGEST_SIZE,
2331                         .halg.base = {
2332                                 .cra_name = "sha512",
2333                                 .cra_driver_name = "sha512-talitos",
2334                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2335                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2336                                              CRYPTO_ALG_ASYNC,
2337                         }
2338                 },
2339                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2340                                      DESC_HDR_SEL0_MDEUB |
2341                                      DESC_HDR_MODE0_MDEUB_SHA512,
2342         },
2343         {       .type = CRYPTO_ALG_TYPE_AHASH,
2344                 .alg.hash = {
2345                         .halg.digestsize = MD5_DIGEST_SIZE,
2346                         .halg.base = {
2347                                 .cra_name = "hmac(md5)",
2348                                 .cra_driver_name = "hmac-md5-talitos",
2349                                 .cra_blocksize = MD5_BLOCK_SIZE,
2350                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2351                                              CRYPTO_ALG_ASYNC,
2352                         }
2353                 },
2354                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2355                                      DESC_HDR_SEL0_MDEUA |
2356                                      DESC_HDR_MODE0_MDEU_MD5,
2357         },
2358         {       .type = CRYPTO_ALG_TYPE_AHASH,
2359                 .alg.hash = {
2360                         .halg.digestsize = SHA1_DIGEST_SIZE,
2361                         .halg.base = {
2362                                 .cra_name = "hmac(sha1)",
2363                                 .cra_driver_name = "hmac-sha1-talitos",
2364                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2365                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2366                                              CRYPTO_ALG_ASYNC,
2367                         }
2368                 },
2369                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2370                                      DESC_HDR_SEL0_MDEUA |
2371                                      DESC_HDR_MODE0_MDEU_SHA1,
2372         },
2373         {       .type = CRYPTO_ALG_TYPE_AHASH,
2374                 .alg.hash = {
2375                         .halg.digestsize = SHA224_DIGEST_SIZE,
2376                         .halg.base = {
2377                                 .cra_name = "hmac(sha224)",
2378                                 .cra_driver_name = "hmac-sha224-talitos",
2379                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2380                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2381                                              CRYPTO_ALG_ASYNC,
2382                         }
2383                 },
2384                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2385                                      DESC_HDR_SEL0_MDEUA |
2386                                      DESC_HDR_MODE0_MDEU_SHA224,
2387         },
2388         {       .type = CRYPTO_ALG_TYPE_AHASH,
2389                 .alg.hash = {
2390                         .halg.digestsize = SHA256_DIGEST_SIZE,
2391                         .halg.base = {
2392                                 .cra_name = "hmac(sha256)",
2393                                 .cra_driver_name = "hmac-sha256-talitos",
2394                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2395                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2396                                              CRYPTO_ALG_ASYNC,
2397                         }
2398                 },
2399                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2400                                      DESC_HDR_SEL0_MDEUA |
2401                                      DESC_HDR_MODE0_MDEU_SHA256,
2402         },
2403         {       .type = CRYPTO_ALG_TYPE_AHASH,
2404                 .alg.hash = {
2405                         .halg.digestsize = SHA384_DIGEST_SIZE,
2406                         .halg.base = {
2407                                 .cra_name = "hmac(sha384)",
2408                                 .cra_driver_name = "hmac-sha384-talitos",
2409                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2410                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2411                                              CRYPTO_ALG_ASYNC,
2412                         }
2413                 },
2414                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2415                                      DESC_HDR_SEL0_MDEUB |
2416                                      DESC_HDR_MODE0_MDEUB_SHA384,
2417         },
2418         {       .type = CRYPTO_ALG_TYPE_AHASH,
2419                 .alg.hash = {
2420                         .halg.digestsize = SHA512_DIGEST_SIZE,
2421                         .halg.base = {
2422                                 .cra_name = "hmac(sha512)",
2423                                 .cra_driver_name = "hmac-sha512-talitos",
2424                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2425                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2426                                              CRYPTO_ALG_ASYNC,
2427                         }
2428                 },
2429                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2430                                      DESC_HDR_SEL0_MDEUB |
2431                                      DESC_HDR_MODE0_MDEUB_SHA512,
2432         }
2433 };
2434
2435 struct talitos_crypto_alg {
2436         struct list_head entry;
2437         struct device *dev;
2438         struct talitos_alg_template algt;
2439 };
2440
2441 static int talitos_cra_init(struct crypto_tfm *tfm)
2442 {
2443         struct crypto_alg *alg = tfm->__crt_alg;
2444         struct talitos_crypto_alg *talitos_alg;
2445         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2446         struct talitos_private *priv;
2447
2448         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2449                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2450                                            struct talitos_crypto_alg,
2451                                            algt.alg.hash);
2452         else
2453                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2454                                            algt.alg.crypto);
2455
2456         /* update context with ptr to dev */
2457         ctx->dev = talitos_alg->dev;
2458
2459         /* assign SEC channel to tfm in round-robin fashion */
2460         priv = dev_get_drvdata(ctx->dev);
2461         ctx->ch = atomic_inc_return(&priv->last_chan) &
2462                   (priv->num_channels - 1);
2463
2464         /* copy descriptor header template value */
2465         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2466
2467         /* select done notification */
2468         ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2469
2470         return 0;
2471 }
2472
2473 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2474 {
2475         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2476
2477         talitos_cra_init(tfm);
2478
2479         /* random first IV */
2480         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2481
2482         return 0;
2483 }
2484
2485 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2486 {
2487         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2488
2489         talitos_cra_init(tfm);
2490
2491         ctx->keylen = 0;
2492         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2493                                  sizeof(struct talitos_ahash_req_ctx));
2494
2495         return 0;
2496 }
2497
2498 /*
2499  * given the alg's descriptor header template, determine whether descriptor
2500  * type and primary/secondary execution units required match the hw
2501  * capabilities description provided in the device tree node.
2502  */
2503 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2504 {
2505         struct talitos_private *priv = dev_get_drvdata(dev);
2506         int ret;
2507
2508         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2509               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2510
2511         if (SECONDARY_EU(desc_hdr_template))
2512                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2513                               & priv->exec_units);
2514
2515         return ret;
2516 }
2517
2518 static int talitos_remove(struct platform_device *ofdev)
2519 {
2520         struct device *dev = &ofdev->dev;
2521         struct talitos_private *priv = dev_get_drvdata(dev);
2522         struct talitos_crypto_alg *t_alg, *n;
2523         int i;
2524
2525         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2526                 switch (t_alg->algt.type) {
2527                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2528                 case CRYPTO_ALG_TYPE_AEAD:
2529                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2530                         break;
2531                 case CRYPTO_ALG_TYPE_AHASH:
2532                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2533                         break;
2534                 }
2535                 list_del(&t_alg->entry);
2536                 kfree(t_alg);
2537         }
2538
2539         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2540                 talitos_unregister_rng(dev);
2541
2542         for (i = 0; i < priv->num_channels; i++)
2543                 kfree(priv->chan[i].fifo);
2544
2545         kfree(priv->chan);
2546
2547         for (i = 0; i < 2; i++)
2548                 if (priv->irq[i]) {
2549                         free_irq(priv->irq[i], dev);
2550                         irq_dispose_mapping(priv->irq[i]);
2551                 }
2552
2553         tasklet_kill(&priv->done_task[0]);
2554         if (priv->irq[1])
2555                 tasklet_kill(&priv->done_task[1]);
2556
2557         iounmap(priv->reg);
2558
2559         dev_set_drvdata(dev, NULL);
2560
2561         kfree(priv);
2562
2563         return 0;
2564 }
2565
2566 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2567                                                     struct talitos_alg_template
2568                                                            *template)
2569 {
2570         struct talitos_private *priv = dev_get_drvdata(dev);
2571         struct talitos_crypto_alg *t_alg;
2572         struct crypto_alg *alg;
2573
2574         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2575         if (!t_alg)
2576                 return ERR_PTR(-ENOMEM);
2577
2578         t_alg->algt = *template;
2579
2580         switch (t_alg->algt.type) {
2581         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2582                 alg = &t_alg->algt.alg.crypto;
2583                 alg->cra_init = talitos_cra_init;
2584                 alg->cra_type = &crypto_ablkcipher_type;
2585                 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2586                 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2587                 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2588                 alg->cra_ablkcipher.geniv = "eseqiv";
2589                 break;
2590         case CRYPTO_ALG_TYPE_AEAD:
2591                 alg = &t_alg->algt.alg.crypto;
2592                 alg->cra_init = talitos_cra_init_aead;
2593                 alg->cra_type = &crypto_aead_type;
2594                 alg->cra_aead.setkey = aead_setkey;
2595                 alg->cra_aead.setauthsize = aead_setauthsize;
2596                 alg->cra_aead.encrypt = aead_encrypt;
2597                 alg->cra_aead.decrypt = aead_decrypt;
2598                 alg->cra_aead.givencrypt = aead_givencrypt;
2599                 alg->cra_aead.geniv = "<built-in>";
2600                 break;
2601         case CRYPTO_ALG_TYPE_AHASH:
2602                 alg = &t_alg->algt.alg.hash.halg.base;
2603                 alg->cra_init = talitos_cra_init_ahash;
2604                 alg->cra_type = &crypto_ahash_type;
2605                 t_alg->algt.alg.hash.init = ahash_init;
2606                 t_alg->algt.alg.hash.update = ahash_update;
2607                 t_alg->algt.alg.hash.final = ahash_final;
2608                 t_alg->algt.alg.hash.finup = ahash_finup;
2609                 t_alg->algt.alg.hash.digest = ahash_digest;
2610                 t_alg->algt.alg.hash.setkey = ahash_setkey;
2611
2612                 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2613                     !strncmp(alg->cra_name, "hmac", 4)) {
2614                         kfree(t_alg);
2615                         return ERR_PTR(-ENOTSUPP);
2616                 }
2617                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2618                     (!strcmp(alg->cra_name, "sha224") ||
2619                      !strcmp(alg->cra_name, "hmac(sha224)"))) {
2620                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2621                         t_alg->algt.desc_hdr_template =
2622                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2623                                         DESC_HDR_SEL0_MDEUA |
2624                                         DESC_HDR_MODE0_MDEU_SHA256;
2625                 }
2626                 break;
2627         default:
2628                 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2629                 return ERR_PTR(-EINVAL);
2630         }
2631
2632         alg->cra_module = THIS_MODULE;
2633         alg->cra_priority = TALITOS_CRA_PRIORITY;
2634         alg->cra_alignmask = 0;
2635         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2636         alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2637
2638         t_alg->dev = dev;
2639
2640         return t_alg;
2641 }
2642
2643 static int talitos_probe_irq(struct platform_device *ofdev)
2644 {
2645         struct device *dev = &ofdev->dev;
2646         struct device_node *np = ofdev->dev.of_node;
2647         struct talitos_private *priv = dev_get_drvdata(dev);
2648         int err;
2649
2650         priv->irq[0] = irq_of_parse_and_map(np, 0);
2651         if (!priv->irq[0]) {
2652                 dev_err(dev, "failed to map irq\n");
2653                 return -EINVAL;
2654         }
2655
2656         priv->irq[1] = irq_of_parse_and_map(np, 1);
2657
2658         /* get the primary irq line */
2659         if (!priv->irq[1]) {
2660                 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2661                                   dev_driver_string(dev), dev);
2662                 goto primary_out;
2663         }
2664
2665         err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2666                           dev_driver_string(dev), dev);
2667         if (err)
2668                 goto primary_out;
2669
2670         /* get the secondary irq line */
2671         err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2672                           dev_driver_string(dev), dev);
2673         if (err) {
2674                 dev_err(dev, "failed to request secondary irq\n");
2675                 irq_dispose_mapping(priv->irq[1]);
2676                 priv->irq[1] = 0;
2677         }
2678
2679         return err;
2680
2681 primary_out:
2682         if (err) {
2683                 dev_err(dev, "failed to request primary irq\n");
2684                 irq_dispose_mapping(priv->irq[0]);
2685                 priv->irq[0] = 0;
2686         }
2687
2688         return err;
2689 }
2690
2691 static int talitos_probe(struct platform_device *ofdev)
2692 {
2693         struct device *dev = &ofdev->dev;
2694         struct device_node *np = ofdev->dev.of_node;
2695         struct talitos_private *priv;
2696         const unsigned int *prop;
2697         int i, err;
2698
2699         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2700         if (!priv)
2701                 return -ENOMEM;
2702
2703         dev_set_drvdata(dev, priv);
2704
2705         priv->ofdev = ofdev;
2706
2707         spin_lock_init(&priv->reg_lock);
2708
2709         err = talitos_probe_irq(ofdev);
2710         if (err)
2711                 goto err_out;
2712
2713         if (!priv->irq[1]) {
2714                 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2715                              (unsigned long)dev);
2716         } else {
2717                 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2718                              (unsigned long)dev);
2719                 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2720                              (unsigned long)dev);
2721         }
2722
2723         INIT_LIST_HEAD(&priv->alg_list);
2724
2725         priv->reg = of_iomap(np, 0);
2726         if (!priv->reg) {
2727                 dev_err(dev, "failed to of_iomap\n");
2728                 err = -ENOMEM;
2729                 goto err_out;
2730         }
2731
2732         /* get SEC version capabilities from device tree */
2733         prop = of_get_property(np, "fsl,num-channels", NULL);
2734         if (prop)
2735                 priv->num_channels = *prop;
2736
2737         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2738         if (prop)
2739                 priv->chfifo_len = *prop;
2740
2741         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2742         if (prop)
2743                 priv->exec_units = *prop;
2744
2745         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2746         if (prop)
2747                 priv->desc_types = *prop;
2748
2749         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2750             !priv->exec_units || !priv->desc_types) {
2751                 dev_err(dev, "invalid property data in device tree node\n");
2752                 err = -EINVAL;
2753                 goto err_out;
2754         }
2755
2756         if (of_device_is_compatible(np, "fsl,sec3.0"))
2757                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2758
2759         if (of_device_is_compatible(np, "fsl,sec2.1"))
2760                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2761                                   TALITOS_FTR_SHA224_HWINIT |
2762                                   TALITOS_FTR_HMAC_OK;
2763
2764         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2765                              priv->num_channels, GFP_KERNEL);
2766         if (!priv->chan) {
2767                 dev_err(dev, "failed to allocate channel management space\n");
2768                 err = -ENOMEM;
2769                 goto err_out;
2770         }
2771
2772         for (i = 0; i < priv->num_channels; i++) {
2773                 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2774                 if (!priv->irq[1] || !(i & 1))
2775                         priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2776         }
2777
2778         for (i = 0; i < priv->num_channels; i++) {
2779                 spin_lock_init(&priv->chan[i].head_lock);
2780                 spin_lock_init(&priv->chan[i].tail_lock);
2781         }
2782
2783         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2784
2785         for (i = 0; i < priv->num_channels; i++) {
2786                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2787                                              priv->fifo_len, GFP_KERNEL);
2788                 if (!priv->chan[i].fifo) {
2789                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2790                         err = -ENOMEM;
2791                         goto err_out;
2792                 }
2793         }
2794
2795         for (i = 0; i < priv->num_channels; i++)
2796                 atomic_set(&priv->chan[i].submit_count,
2797                            -(priv->chfifo_len - 1));
2798
2799         dma_set_mask(dev, DMA_BIT_MASK(36));
2800
2801         /* reset and initialize the h/w */
2802         err = init_device(dev);
2803         if (err) {
2804                 dev_err(dev, "failed to initialize device\n");
2805                 goto err_out;
2806         }
2807
2808         /* register the RNG, if available */
2809         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2810                 err = talitos_register_rng(dev);
2811                 if (err) {
2812                         dev_err(dev, "failed to register hwrng: %d\n", err);
2813                         goto err_out;
2814                 } else
2815                         dev_info(dev, "hwrng\n");
2816         }
2817
2818         /* register crypto algorithms the device supports */
2819         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2820                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2821                         struct talitos_crypto_alg *t_alg;
2822                         char *name = NULL;
2823                         bool authenc = false;
2824
2825 authencesn:
2826                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2827                         if (IS_ERR(t_alg)) {
2828                                 err = PTR_ERR(t_alg);
2829                                 if (err == -ENOTSUPP)
2830                                         continue;
2831                                 goto err_out;
2832                         }
2833
2834                         switch (t_alg->algt.type) {
2835                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2836                         case CRYPTO_ALG_TYPE_AEAD:
2837                                 err = crypto_register_alg(
2838                                                 &t_alg->algt.alg.crypto);
2839                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2840                                 authenc = authenc ? !authenc :
2841                                           !(bool)memcmp(name, "authenc", 7);
2842                                 break;
2843                         case CRYPTO_ALG_TYPE_AHASH:
2844                                 err = crypto_register_ahash(
2845                                                 &t_alg->algt.alg.hash);
2846                                 name =
2847                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2848                                 break;
2849                         }
2850                         if (err) {
2851                                 dev_err(dev, "%s alg registration failed\n",
2852                                         name);
2853                                 kfree(t_alg);
2854                         } else {
2855                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2856                                 if (authenc) {
2857                                         struct crypto_alg *alg =
2858                                                 &driver_algs[i].alg.crypto;
2859
2860                                         name = alg->cra_name;
2861                                         memmove(name + 10, name + 7,
2862                                                 strlen(name) - 7);
2863                                         memcpy(name + 7, "esn", 3);
2864
2865                                         name = alg->cra_driver_name;
2866                                         memmove(name + 10, name + 7,
2867                                                 strlen(name) - 7);
2868                                         memcpy(name + 7, "esn", 3);
2869
2870                                         goto authencesn;
2871                                 }
2872                         }
2873                 }
2874         }
2875         if (!list_empty(&priv->alg_list))
2876                 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2877                          (char *)of_get_property(np, "compatible", NULL));
2878
2879         return 0;
2880
2881 err_out:
2882         talitos_remove(ofdev);
2883
2884         return err;
2885 }
2886
2887 static const struct of_device_id talitos_match[] = {
2888         {
2889                 .compatible = "fsl,sec2.0",
2890         },
2891         {},
2892 };
2893 MODULE_DEVICE_TABLE(of, talitos_match);
2894
2895 static struct platform_driver talitos_driver = {
2896         .driver = {
2897                 .name = "talitos",
2898                 .owner = THIS_MODULE,
2899                 .of_match_table = talitos_match,
2900         },
2901         .probe = talitos_probe,
2902         .remove = talitos_remove,
2903 };
2904
2905 module_platform_driver(talitos_driver);
2906
2907 MODULE_LICENSE("GPL");
2908 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2909 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");