drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25
  26 #include "../dmaengine.h"
  27 #include "internal.h"
  28
  29 /*
  30  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  31  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  32  * of which use ARM any more).  See the "Databook" from Synopsys for
  33  * information beyond what licensees probably provide.
  34  *
  35  * The driver has been tested with the Atmel AT32AP7000, which does not
  36  * support descriptor writeback.
  37  */
  38
  39 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  40                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  41                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  42                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  43                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  44                         DW_DMA_MSIZE_16;                        \
  45                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  46                         DW_DMA_MSIZE_16;                        \
  47                                                                 \
  48                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  49                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  50                  | DWC_CTLL_LLP_D_EN                            \
  51                  | DWC_CTLL_LLP_S_EN                            \
  52                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  53                  | DWC_CTLL_SMS(_dwc->src_master));             \
  54         })
  55
  56 /*
  57  * Number of descriptors to allocate for each channel. This should be
  58  * made configurable somehow; preferably, the clients (at least the
  59  * ones using slave transfers) should be able to give us a hint.
  60  */
  61 #define NR_DESCS_PER_CHANNEL    64
  62
  63 /*----------------------------------------------------------------------*/
  64
  65 static struct device *chan2dev(struct dma_chan *chan)
  66 {
  67         return &chan->dev->device;
  68 }
  69
  70 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  71 {
  72         return to_dw_desc(dwc->active_list.next);
  73 }
  74
  75 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  76 {
  77         struct dw_desc *desc, *_desc;
  78         struct dw_desc *ret = NULL;
  79         unsigned int i = 0;
  80         unsigned long flags;
  81
  82         spin_lock_irqsave(&dwc->lock, flags);
  83         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  84                 i++;
  85                 if (async_tx_test_ack(&desc->txd)) {
  86                         list_del(&desc->desc_node);
  87                         ret = desc;
  88                         break;
  89                 }
  90                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  91         }
  92         spin_unlock_irqrestore(&dwc->lock, flags);
  93
  94         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
  95
  96         return ret;
  97 }
  98
  99 /*
 100  * Move a descriptor, including any children, to the free list.
 101  * `desc' must not be on any lists.
 102  */
 103 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 104 {
 105         unsigned long flags;
 106
 107         if (desc) {
 108                 struct dw_desc *child;
 109
 110                 spin_lock_irqsave(&dwc->lock, flags);
 111                 list_for_each_entry(child, &desc->tx_list, desc_node)
 112                         dev_vdbg(chan2dev(&dwc->chan),
 113                                         "moving child desc %p to freelist\n",
 114                                         child);
 115                 list_splice_init(&desc->tx_list, &dwc->free_list);
 116                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 117                 list_add(&desc->desc_node, &dwc->free_list);
 118                 spin_unlock_irqrestore(&dwc->lock, flags);
 119         }
 120 }
 121
 122 static void dwc_initialize(struct dw_dma_chan *dwc)
 123 {
 124         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 125         struct dw_dma_slave *dws = dwc->chan.private;
 126         u32 cfghi = DWC_CFGH_FIFO_MODE;
 127         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 128
 129         if (dwc->initialized == true)
 130                 return;
 131
 132         if (dws) {
 133                 /*
 134                  * We need controller-specific data to set up slave
 135                  * transfers.
 136                  */
 137                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 138
 139                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 140                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 141         } else {
 142                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 143                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 144         }
 145
 146         channel_writel(dwc, CFG_LO, cfglo);
 147         channel_writel(dwc, CFG_HI, cfghi);
 148
 149         /* Enable interrupts */
 150         channel_set_bit(dw, MASK.XFER, dwc->mask);
 151         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 152
 153         dwc->initialized = true;
 154 }
 155
 156 /*----------------------------------------------------------------------*/
 157
 158 static inline unsigned int dwc_fast_fls(unsigned long long v)
 159 {
 160         /*
 161          * We can be a lot more clever here, but this should take care
 162          * of the most common optimization.
 163          */
 164         if (!(v & 7))
 165                 return 3;
 166         else if (!(v & 3))
 167                 return 2;
 168         else if (!(v & 1))
 169                 return 1;
 170         return 0;
 171 }
 172
 173 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 174 {
 175         dev_err(chan2dev(&dwc->chan),
 176                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 177                 channel_readl(dwc, SAR),
 178                 channel_readl(dwc, DAR),
 179                 channel_readl(dwc, LLP),
 180                 channel_readl(dwc, CTL_HI),
 181                 channel_readl(dwc, CTL_LO));
 182 }
 183
 184 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 185 {
 186         channel_clear_bit(dw, CH_EN, dwc->mask);
 187         while (dma_readl(dw, CH_EN) & dwc->mask)
 188                 cpu_relax();
 189 }
 190
 191 /*----------------------------------------------------------------------*/
 192
 193 /* Perform single block transfer */
 194 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 195                                        struct dw_desc *desc)
 196 {
 197         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 198         u32             ctllo;
 199
 200         /*
 201          * Software emulation of LLP mode relies on interrupts to continue
 202          * multi block transfer.
 203          */
 204         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 205
 206         channel_writel(dwc, SAR, desc->lli.sar);
 207         channel_writel(dwc, DAR, desc->lli.dar);
 208         channel_writel(dwc, CTL_LO, ctllo);
 209         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 210         channel_set_bit(dw, CH_EN, dwc->mask);
 211
 212         /* Move pointer to next descriptor */
 213         dwc->tx_node_active = dwc->tx_node_active->next;
 214 }
 215
 216 /* Called with dwc->lock held and bh disabled */
 217 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 218 {
 219         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 220         unsigned long   was_soft_llp;
 221
 222         /* ASSERT:  channel is idle */
 223         if (dma_readl(dw, CH_EN) & dwc->mask) {
 224                 dev_err(chan2dev(&dwc->chan),
 225                         "BUG: Attempted to start non-idle channel\n");
 226                 dwc_dump_chan_regs(dwc);
 227
 228                 /* The tasklet will hopefully advance the queue... */
 229                 return;
 230         }
 231
 232         if (dwc->nollp) {
 233                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 234                                                 &dwc->flags);
 235                 if (was_soft_llp) {
 236                         dev_err(chan2dev(&dwc->chan),
 237                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 238                         return;
 239                 }
 240
 241                 dwc_initialize(dwc);
 242
 243                 dwc->residue = first->total_len;
 244                 dwc->tx_node_active = &first->tx_list;
 245
 246                 /* Submit first block */
 247                 dwc_do_single_block(dwc, first);
 248
 249                 return;
 250         }
 251
 252         dwc_initialize(dwc);
 253
 254         channel_writel(dwc, LLP, first->txd.phys);
 255         channel_writel(dwc, CTL_LO,
 256                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 257         channel_writel(dwc, CTL_HI, 0);
 258         channel_set_bit(dw, CH_EN, dwc->mask);
 259 }
 260
 261 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 262 {
 263         struct dw_desc *desc;
 264
 265         if (list_empty(&dwc->queue))
 266                 return;
 267
 268         list_move(dwc->queue.next, &dwc->active_list);
 269         desc = dwc_first_active(dwc);
 270         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 271         dwc_dostart(dwc, desc);
 272 }
 273
 274 /*----------------------------------------------------------------------*/
 275
 276 static void
 277 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 278                 bool callback_required)
 279 {
 280         dma_async_tx_callback           callback = NULL;
 281         void                            *param = NULL;
 282         struct dma_async_tx_descriptor  *txd = &desc->txd;
 283         struct dw_desc                  *child;
 284         unsigned long                   flags;
 285
 286         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 287
 288         spin_lock_irqsave(&dwc->lock, flags);
 289         dma_cookie_complete(txd);
 290         if (callback_required) {
 291                 callback = txd->callback;
 292                 param = txd->callback_param;
 293         }
 294
 295         /* async_tx_ack */
 296         list_for_each_entry(child, &desc->tx_list, desc_node)
 297                 async_tx_ack(&child->txd);
 298         async_tx_ack(&desc->txd);
 299
 300         list_splice_init(&desc->tx_list, &dwc->free_list);
 301         list_move(&desc->desc_node, &dwc->free_list);
 302
 303         dma_descriptor_unmap(txd);
 304         spin_unlock_irqrestore(&dwc->lock, flags);
 305
 306         if (callback)
 307                 callback(param);
 308 }
 309
 310 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 311 {
 312         struct dw_desc *desc, *_desc;
 313         LIST_HEAD(list);
 314         unsigned long flags;
 315
 316         spin_lock_irqsave(&dwc->lock, flags);
 317         if (dma_readl(dw, CH_EN) & dwc->mask) {
 318                 dev_err(chan2dev(&dwc->chan),
 319                         "BUG: XFER bit set, but channel not idle!\n");
 320
 321                 /* Try to continue after resetting the channel... */
 322                 dwc_chan_disable(dw, dwc);
 323         }
 324
 325         /*
 326          * Submit queued descriptors ASAP, i.e. before we go through
 327          * the completed ones.
 328          */
 329         list_splice_init(&dwc->active_list, &list);
 330         dwc_dostart_first_queued(dwc);
 331
 332         spin_unlock_irqrestore(&dwc->lock, flags);
 333
 334         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 335                 dwc_descriptor_complete(dwc, desc, true);
 336 }
 337
 338 /* Returns how many bytes were already received from source */
 339 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 340 {
 341         u32 ctlhi = channel_readl(dwc, CTL_HI);
 342         u32 ctllo = channel_readl(dwc, CTL_LO);
 343
 344         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 345 }
 346
 347 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 348 {
 349         dma_addr_t llp;
 350         struct dw_desc *desc, *_desc;
 351         struct dw_desc *child;
 352         u32 status_xfer;
 353         unsigned long flags;
 354
 355         spin_lock_irqsave(&dwc->lock, flags);
 356         llp = channel_readl(dwc, LLP);
 357         status_xfer = dma_readl(dw, RAW.XFER);
 358
 359         if (status_xfer & dwc->mask) {
 360                 /* Everything we've submitted is done */
 361                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 362
 363                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 364                         struct list_head *head, *active = dwc->tx_node_active;
 365
 366                         /*
 367                          * We are inside first active descriptor.
 368                          * Otherwise something is really wrong.
 369                          */
 370                         desc = dwc_first_active(dwc);
 371
 372                         head = &desc->tx_list;
 373                         if (active != head) {
 374                                 /* Update desc to reflect last sent one */
 375                                 if (active != head->next)
 376                                         desc = to_dw_desc(active->prev);
 377
 378                                 dwc->residue -= desc->len;
 379
 380                                 child = to_dw_desc(active);
 381
 382                                 /* Submit next block */
 383                                 dwc_do_single_block(dwc, child);
 384
 385                                 spin_unlock_irqrestore(&dwc->lock, flags);
 386                                 return;
 387                         }
 388
 389                         /* We are done here */
 390                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 391                 }
 392
 393                 dwc->residue = 0;
 394
 395                 spin_unlock_irqrestore(&dwc->lock, flags);
 396
 397                 dwc_complete_all(dw, dwc);
 398                 return;
 399         }
 400
 401         if (list_empty(&dwc->active_list)) {
 402                 dwc->residue = 0;
 403                 spin_unlock_irqrestore(&dwc->lock, flags);
 404                 return;
 405         }
 406
 407         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 408                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 409                 spin_unlock_irqrestore(&dwc->lock, flags);
 410                 return;
 411         }
 412
 413         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 414
 415         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 416                 /* Initial residue value */
 417                 dwc->residue = desc->total_len;
 418
 419                 /* Check first descriptors addr */
 420                 if (desc->txd.phys == llp) {
 421                         spin_unlock_irqrestore(&dwc->lock, flags);
 422                         return;
 423                 }
 424
 425                 /* Check first descriptors llp */
 426                 if (desc->lli.llp == llp) {
 427                         /* This one is currently in progress */
 428                         dwc->residue -= dwc_get_sent(dwc);
 429                         spin_unlock_irqrestore(&dwc->lock, flags);
 430                         return;
 431                 }
 432
 433                 dwc->residue -= desc->len;
 434                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 435                         if (child->lli.llp == llp) {
 436                                 /* Currently in progress */
 437                                 dwc->residue -= dwc_get_sent(dwc);
 438                                 spin_unlock_irqrestore(&dwc->lock, flags);
 439                                 return;
 440                         }
 441                         dwc->residue -= child->len;
 442                 }
 443
 444                 /*
 445                  * No descriptors so far seem to be in progress, i.e.
 446                  * this one must be done.
 447                  */
 448                 spin_unlock_irqrestore(&dwc->lock, flags);
 449                 dwc_descriptor_complete(dwc, desc, true);
 450                 spin_lock_irqsave(&dwc->lock, flags);
 451         }
 452
 453         dev_err(chan2dev(&dwc->chan),
 454                 "BUG: All descriptors done, but channel not idle!\n");
 455
 456         /* Try to continue after resetting the channel... */
 457         dwc_chan_disable(dw, dwc);
 458
 459         dwc_dostart_first_queued(dwc);
 460         spin_unlock_irqrestore(&dwc->lock, flags);
 461 }
 462
 463 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 464 {
 465         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 466                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 467 }
 468
 469 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 470 {
 471         struct dw_desc *bad_desc;
 472         struct dw_desc *child;
 473         unsigned long flags;
 474
 475         dwc_scan_descriptors(dw, dwc);
 476
 477         spin_lock_irqsave(&dwc->lock, flags);
 478
 479         /*
 480          * The descriptor currently at the head of the active list is
 481          * borked. Since we don't have any way to report errors, we'll
 482          * just have to scream loudly and try to carry on.
 483          */
 484         bad_desc = dwc_first_active(dwc);
 485         list_del_init(&bad_desc->desc_node);
 486         list_move(dwc->queue.next, dwc->active_list.prev);
 487
 488         /* Clear the error flag and try to restart the controller */
 489         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 490         if (!list_empty(&dwc->active_list))
 491                 dwc_dostart(dwc, dwc_first_active(dwc));
 492
 493         /*
 494          * WARN may seem harsh, but since this only happens
 495          * when someone submits a bad physical address in a
 496          * descriptor, we should consider ourselves lucky that the
 497          * controller flagged an error instead of scribbling over
 498          * random memory locations.
 499          */
 500         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 501                                        "  cookie: %d\n", bad_desc->txd.cookie);
 502         dwc_dump_lli(dwc, &bad_desc->lli);
 503         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 504                 dwc_dump_lli(dwc, &child->lli);
 505
 506         spin_unlock_irqrestore(&dwc->lock, flags);
 507
 508         /* Pretend the descriptor completed successfully */
 509         dwc_descriptor_complete(dwc, bad_desc, true);
 510 }
 511
 512 /* --------------------- Cyclic DMA API extensions -------------------- */
 513
 514 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 515 {
 516         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 517         return channel_readl(dwc, SAR);
 518 }
 519 EXPORT_SYMBOL(dw_dma_get_src_addr);
 520
 521 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 522 {
 523         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 524         return channel_readl(dwc, DAR);
 525 }
 526 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 527
 528 /* Called with dwc->lock held and all DMAC interrupts disabled */
 529 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 530                 u32 status_err, u32 status_xfer)
 531 {
 532         unsigned long flags;
 533
 534         if (dwc->mask) {
 535                 void (*callback)(void *param);
 536                 void *callback_param;
 537
 538                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 539                                 channel_readl(dwc, LLP));
 540
 541                 callback = dwc->cdesc->period_callback;
 542                 callback_param = dwc->cdesc->period_callback_param;
 543
 544                 if (callback)
 545                         callback(callback_param);
 546         }
 547
 548         /*
 549          * Error and transfer complete are highly unlikely, and will most
 550          * likely be due to a configuration error by the user.
 551          */
 552         if (unlikely(status_err & dwc->mask) ||
 553                         unlikely(status_xfer & dwc->mask)) {
 554                 int i;
 555
 556                 dev_err(chan2dev(&dwc->chan),
 557                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 558                         status_xfer ? "xfer" : "error");
 559
 560                 spin_lock_irqsave(&dwc->lock, flags);
 561
 562                 dwc_dump_chan_regs(dwc);
 563
 564                 dwc_chan_disable(dw, dwc);
 565
 566                 /* Make sure DMA does not restart by loading a new list */
 567                 channel_writel(dwc, LLP, 0);
 568                 channel_writel(dwc, CTL_LO, 0);
 569                 channel_writel(dwc, CTL_HI, 0);
 570
 571                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 572                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 573
 574                 for (i = 0; i < dwc->cdesc->periods; i++)
 575                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 576
 577                 spin_unlock_irqrestore(&dwc->lock, flags);
 578         }
 579 }
 580
 581 /* ------------------------------------------------------------------------- */
 582
 583 static void dw_dma_tasklet(unsigned long data)
 584 {
 585         struct dw_dma *dw = (struct dw_dma *)data;
 586         struct dw_dma_chan *dwc;
 587         u32 status_xfer;
 588         u32 status_err;
 589         int i;
 590
 591         status_xfer = dma_readl(dw, RAW.XFER);
 592         status_err = dma_readl(dw, RAW.ERROR);
 593
 594         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 595
 596         for (i = 0; i < dw->dma.chancnt; i++) {
 597                 dwc = &dw->chan[i];
 598                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 599                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 600                 else if (status_err & (1 << i))
 601                         dwc_handle_error(dw, dwc);
 602                 else if (status_xfer & (1 << i))
 603                         dwc_scan_descriptors(dw, dwc);
 604         }
 605
 606         /*
 607          * Re-enable interrupts.
 608          */
 609         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 610         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 611 }
 612
 613 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 614 {
 615         struct dw_dma *dw = dev_id;
 616         u32 status = dma_readl(dw, STATUS_INT);
 617
 618         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 619
 620         /* Check if we have any interrupt from the DMAC */
 621         if (!status)
 622                 return IRQ_NONE;
 623
 624         /*
 625          * Just disable the interrupts. We'll turn them back on in the
 626          * softirq handler.
 627          */
 628         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 629         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 630
 631         status = dma_readl(dw, STATUS_INT);
 632         if (status) {
 633                 dev_err(dw->dma.dev,
 634                         "BUG: Unexpected interrupts pending: 0x%x\n",
 635                         status);
 636
 637                 /* Try to recover */
 638                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 639                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 640                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 641                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 642         }
 643
 644         tasklet_schedule(&dw->tasklet);
 645
 646         return IRQ_HANDLED;
 647 }
 648
 649 /*----------------------------------------------------------------------*/
 650
 651 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 652 {
 653         struct dw_desc          *desc = txd_to_dw_desc(tx);
 654         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 655         dma_cookie_t            cookie;
 656         unsigned long           flags;
 657
 658         spin_lock_irqsave(&dwc->lock, flags);
 659         cookie = dma_cookie_assign(tx);
 660
 661         /*
 662          * REVISIT: We should attempt to chain as many descriptors as
 663          * possible, perhaps even appending to those already submitted
 664          * for DMA. But this is hard to do in a race-free manner.
 665          */
 666
 667         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 668         list_add_tail(&desc->desc_node, &dwc->queue);
 669
 670         spin_unlock_irqrestore(&dwc->lock, flags);
 671
 672         return cookie;
 673 }
 674
 675 static struct dma_async_tx_descriptor *
 676 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 677                 size_t len, unsigned long flags)
 678 {
 679         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 680         struct dw_dma           *dw = to_dw_dma(chan->device);
 681         struct dw_desc          *desc;
 682         struct dw_desc          *first;
 683         struct dw_desc          *prev;
 684         size_t                  xfer_count;
 685         size_t                  offset;
 686         unsigned int            src_width;
 687         unsigned int            dst_width;
 688         unsigned int            data_width;
 689         u32                     ctllo;
 690
 691         dev_vdbg(chan2dev(chan),
 692                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 693                         &dest, &src, len, flags);
 694
 695         if (unlikely(!len)) {
 696                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 697                 return NULL;
 698         }
 699
 700         dwc->direction = DMA_MEM_TO_MEM;
 701
 702         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 703                            dw->data_width[dwc->dst_master]);
 704
 705         src_width = dst_width = min_t(unsigned int, data_width,
 706                                       dwc_fast_fls(src | dest | len));
 707
 708         ctllo = DWC_DEFAULT_CTLLO(chan)
 709                         | DWC_CTLL_DST_WIDTH(dst_width)
 710                         | DWC_CTLL_SRC_WIDTH(src_width)
 711                         | DWC_CTLL_DST_INC
 712                         | DWC_CTLL_SRC_INC
 713                         | DWC_CTLL_FC_M2M;
 714         prev = first = NULL;
 715
 716         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 717                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 718                                            dwc->block_size);
 719
 720                 desc = dwc_desc_get(dwc);
 721                 if (!desc)
 722                         goto err_desc_get;
 723
 724                 desc->lli.sar = src + offset;
 725                 desc->lli.dar = dest + offset;
 726                 desc->lli.ctllo = ctllo;
 727                 desc->lli.ctlhi = xfer_count;
 728                 desc->len = xfer_count << src_width;
 729
 730                 if (!first) {
 731                         first = desc;
 732                 } else {
 733                         prev->lli.llp = desc->txd.phys;
 734                         list_add_tail(&desc->desc_node,
 735                                         &first->tx_list);
 736                 }
 737                 prev = desc;
 738         }
 739
 740         if (flags & DMA_PREP_INTERRUPT)
 741                 /* Trigger interrupt after last block */
 742                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 743
 744         prev->lli.llp = 0;
 745         first->txd.flags = flags;
 746         first->total_len = len;
 747
 748         return &first->txd;
 749
 750 err_desc_get:
 751         dwc_desc_put(dwc, first);
 752         return NULL;
 753 }
 754
 755 static struct dma_async_tx_descriptor *
 756 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 757                 unsigned int sg_len, enum dma_transfer_direction direction,
 758                 unsigned long flags, void *context)
 759 {
 760         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 761         struct dw_dma           *dw = to_dw_dma(chan->device);
 762         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 763         struct dw_desc          *prev;
 764         struct dw_desc          *first;
 765         u32                     ctllo;
 766         dma_addr_t              reg;
 767         unsigned int            reg_width;
 768         unsigned int            mem_width;
 769         unsigned int            data_width;
 770         unsigned int            i;
 771         struct scatterlist      *sg;
 772         size_t                  total_len = 0;
 773
 774         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 775
 776         if (unlikely(!is_slave_direction(direction) || !sg_len))
 777                 return NULL;
 778
 779         dwc->direction = direction;
 780
 781         prev = first = NULL;
 782
 783         switch (direction) {
 784         case DMA_MEM_TO_DEV:
 785                 reg_width = __fls(sconfig->dst_addr_width);
 786                 reg = sconfig->dst_addr;
 787                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 788                                 | DWC_CTLL_DST_WIDTH(reg_width)
 789                                 | DWC_CTLL_DST_FIX
 790                                 | DWC_CTLL_SRC_INC);
 791
 792                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 793                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 794
 795                 data_width = dw->data_width[dwc->src_master];
 796
 797                 for_each_sg(sgl, sg, sg_len, i) {
 798                         struct dw_desc  *desc;
 799                         u32             len, dlen, mem;
 800
 801                         mem = sg_dma_address(sg);
 802                         len = sg_dma_len(sg);
 803
 804                         mem_width = min_t(unsigned int,
 805                                           data_width, dwc_fast_fls(mem | len));
 806
 807 slave_sg_todev_fill_desc:
 808                         desc = dwc_desc_get(dwc);
 809                         if (!desc) {
 810                                 dev_err(chan2dev(chan),
 811                                         "not enough descriptors available\n");
 812                                 goto err_desc_get;
 813                         }
 814
 815                         desc->lli.sar = mem;
 816                         desc->lli.dar = reg;
 817                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 818                         if ((len >> mem_width) > dwc->block_size) {
 819                                 dlen = dwc->block_size << mem_width;
 820                                 mem += dlen;
 821                                 len -= dlen;
 822                         } else {
 823                                 dlen = len;
 824                                 len = 0;
 825                         }
 826
 827                         desc->lli.ctlhi = dlen >> mem_width;
 828                         desc->len = dlen;
 829
 830                         if (!first) {
 831                                 first = desc;
 832                         } else {
 833                                 prev->lli.llp = desc->txd.phys;
 834                                 list_add_tail(&desc->desc_node,
 835                                                 &first->tx_list);
 836                         }
 837                         prev = desc;
 838                         total_len += dlen;
 839
 840                         if (len)
 841                                 goto slave_sg_todev_fill_desc;
 842                 }
 843                 break;
 844         case DMA_DEV_TO_MEM:
 845                 reg_width = __fls(sconfig->src_addr_width);
 846                 reg = sconfig->src_addr;
 847                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 848                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 849                                 | DWC_CTLL_DST_INC
 850                                 | DWC_CTLL_SRC_FIX);
 851
 852                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 853                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 854
 855                 data_width = dw->data_width[dwc->dst_master];
 856
 857                 for_each_sg(sgl, sg, sg_len, i) {
 858                         struct dw_desc  *desc;
 859                         u32             len, dlen, mem;
 860
 861                         mem = sg_dma_address(sg);
 862                         len = sg_dma_len(sg);
 863
 864                         mem_width = min_t(unsigned int,
 865                                           data_width, dwc_fast_fls(mem | len));
 866
 867 slave_sg_fromdev_fill_desc:
 868                         desc = dwc_desc_get(dwc);
 869                         if (!desc) {
 870                                 dev_err(chan2dev(chan),
 871                                                 "not enough descriptors available\n");
 872                                 goto err_desc_get;
 873                         }
 874
 875                         desc->lli.sar = reg;
 876                         desc->lli.dar = mem;
 877                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 878                         if ((len >> reg_width) > dwc->block_size) {
 879                                 dlen = dwc->block_size << reg_width;
 880                                 mem += dlen;
 881                                 len -= dlen;
 882                         } else {
 883                                 dlen = len;
 884                                 len = 0;
 885                         }
 886                         desc->lli.ctlhi = dlen >> reg_width;
 887                         desc->len = dlen;
 888
 889                         if (!first) {
 890                                 first = desc;
 891                         } else {
 892                                 prev->lli.llp = desc->txd.phys;
 893                                 list_add_tail(&desc->desc_node,
 894                                                 &first->tx_list);
 895                         }
 896                         prev = desc;
 897                         total_len += dlen;
 898
 899                         if (len)
 900                                 goto slave_sg_fromdev_fill_desc;
 901                 }
 902                 break;
 903         default:
 904                 return NULL;
 905         }
 906
 907         if (flags & DMA_PREP_INTERRUPT)
 908                 /* Trigger interrupt after last block */
 909                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 910
 911         prev->lli.llp = 0;
 912         first->total_len = total_len;
 913
 914         return &first->txd;
 915
 916 err_desc_get:
 917         dwc_desc_put(dwc, first);
 918         return NULL;
 919 }
 920
 921 bool dw_dma_filter(struct dma_chan *chan, void *param)
 922 {
 923         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 924         struct dw_dma_slave *dws = param;
 925
 926         if (!dws || dws->dma_dev != chan->device->dev)
 927                 return false;
 928
 929         /* We have to copy data since dws can be temporary storage */
 930
 931         dwc->src_id = dws->src_id;
 932         dwc->dst_id = dws->dst_id;
 933
 934         dwc->src_master = dws->src_master;
 935         dwc->dst_master = dws->dst_master;
 936
 937         return true;
 938 }
 939 EXPORT_SYMBOL_GPL(dw_dma_filter);
 940
 941 /*
 942  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 943  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 944  *
 945  * NOTE: burst size 2 is not supported by controller.
 946  *
 947  * This can be done by finding least significant bit set: n & (n - 1)
 948  */
 949 static inline void convert_burst(u32 *maxburst)
 950 {
 951         if (*maxburst > 1)
 952                 *maxburst = fls(*maxburst) - 2;
 953         else
 954                 *maxburst = 0;
 955 }
 956
 957 static int
 958 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 959 {
 960         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 961
 962         /* Check if chan will be configured for slave transfers */
 963         if (!is_slave_direction(sconfig->direction))
 964                 return -EINVAL;
 965
 966         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 967         dwc->direction = sconfig->direction;
 968
 969         convert_burst(&dwc->dma_sconfig.src_maxburst);
 970         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 971
 972         return 0;
 973 }
 974
 975 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 976 {
 977         u32 cfglo = channel_readl(dwc, CFG_LO);
 978         unsigned int count = 20;        /* timeout iterations */
 979
 980         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 981         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 982                 udelay(2);
 983
 984         dwc->paused = true;
 985 }
 986
 987 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 988 {
 989         u32 cfglo = channel_readl(dwc, CFG_LO);
 990
 991         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 992
 993         dwc->paused = false;
 994 }
 995
 996 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 997                        unsigned long arg)
 998 {
 999         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1000         struct dw_dma           *dw = to_dw_dma(chan->device);
1001         struct dw_desc          *desc, *_desc;
1002         unsigned long           flags;
1003         LIST_HEAD(list);
1004
1005         if (cmd == DMA_PAUSE) {
1006                 spin_lock_irqsave(&dwc->lock, flags);
1007
1008                 dwc_chan_pause(dwc);
1009
1010                 spin_unlock_irqrestore(&dwc->lock, flags);
1011         } else if (cmd == DMA_RESUME) {
1012                 if (!dwc->paused)
1013                         return 0;
1014
1015                 spin_lock_irqsave(&dwc->lock, flags);
1016
1017                 dwc_chan_resume(dwc);
1018
1019                 spin_unlock_irqrestore(&dwc->lock, flags);
1020         } else if (cmd == DMA_TERMINATE_ALL) {
1021                 spin_lock_irqsave(&dwc->lock, flags);
1022
1023                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1024
1025                 dwc_chan_disable(dw, dwc);
1026
1027                 dwc_chan_resume(dwc);
1028
1029                 /* active_list entries will end up before queued entries */
1030                 list_splice_init(&dwc->queue, &list);
1031                 list_splice_init(&dwc->active_list, &list);
1032
1033                 spin_unlock_irqrestore(&dwc->lock, flags);
1034
1035                 /* Flush all pending and queued descriptors */
1036                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1037                         dwc_descriptor_complete(dwc, desc, false);
1038         } else if (cmd == DMA_SLAVE_CONFIG) {
1039                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1040         } else {
1041                 return -ENXIO;
1042         }
1043
1044         return 0;
1045 }
1046
1047 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1048 {
1049         unsigned long flags;
1050         u32 residue;
1051
1052         spin_lock_irqsave(&dwc->lock, flags);
1053
1054         residue = dwc->residue;
1055         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1056                 residue -= dwc_get_sent(dwc);
1057
1058         spin_unlock_irqrestore(&dwc->lock, flags);
1059         return residue;
1060 }
1061
1062 static enum dma_status
1063 dwc_tx_status(struct dma_chan *chan,
1064               dma_cookie_t cookie,
1065               struct dma_tx_state *txstate)
1066 {
1067         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1068         enum dma_status         ret;
1069
1070         ret = dma_cookie_status(chan, cookie, txstate);
1071         if (ret == DMA_COMPLETE)
1072                 return ret;
1073
1074         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1075
1076         ret = dma_cookie_status(chan, cookie, txstate);
1077         if (ret != DMA_COMPLETE)
1078                 dma_set_residue(txstate, dwc_get_residue(dwc));
1079
1080         if (dwc->paused && ret == DMA_IN_PROGRESS)
1081                 return DMA_PAUSED;
1082
1083         return ret;
1084 }
1085
1086 static void dwc_issue_pending(struct dma_chan *chan)
1087 {
1088         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1089         unsigned long           flags;
1090
1091         spin_lock_irqsave(&dwc->lock, flags);
1092         if (list_empty(&dwc->active_list))
1093                 dwc_dostart_first_queued(dwc);
1094         spin_unlock_irqrestore(&dwc->lock, flags);
1095 }
1096
1097 /*----------------------------------------------------------------------*/
1098
1099 static void dw_dma_off(struct dw_dma *dw)
1100 {
1101         int i;
1102
1103         dma_writel(dw, CFG, 0);
1104
1105         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1106         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1107         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1108         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1109
1110         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1111                 cpu_relax();
1112
1113         for (i = 0; i < dw->dma.chancnt; i++)
1114                 dw->chan[i].initialized = false;
1115 }
1116
1117 static void dw_dma_on(struct dw_dma *dw)
1118 {
1119         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1120 }
1121
1122 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1123 {
1124         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1125         struct dw_dma           *dw = to_dw_dma(chan->device);
1126         struct dw_desc          *desc;
1127         int                     i;
1128         unsigned long           flags;
1129
1130         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1131
1132         /* ASSERT:  channel is idle */
1133         if (dma_readl(dw, CH_EN) & dwc->mask) {
1134                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1135                 return -EIO;
1136         }
1137
1138         dma_cookie_init(chan);
1139
1140         /*
1141          * NOTE: some controllers may have additional features that we
1142          * need to initialize here, like "scatter-gather" (which
1143          * doesn't mean what you think it means), and status writeback.
1144          */
1145
1146         /* Enable controller here if needed */
1147         if (!dw->in_use)
1148                 dw_dma_on(dw);
1149         dw->in_use |= dwc->mask;
1150
1151         spin_lock_irqsave(&dwc->lock, flags);
1152         i = dwc->descs_allocated;
1153         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1154                 dma_addr_t phys;
1155
1156                 spin_unlock_irqrestore(&dwc->lock, flags);
1157
1158                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1159                 if (!desc)
1160                         goto err_desc_alloc;
1161
1162                 memset(desc, 0, sizeof(struct dw_desc));
1163
1164                 INIT_LIST_HEAD(&desc->tx_list);
1165                 dma_async_tx_descriptor_init(&desc->txd, chan);
1166                 desc->txd.tx_submit = dwc_tx_submit;
1167                 desc->txd.flags = DMA_CTRL_ACK;
1168                 desc->txd.phys = phys;
1169
1170                 dwc_desc_put(dwc, desc);
1171
1172                 spin_lock_irqsave(&dwc->lock, flags);
1173                 i = ++dwc->descs_allocated;
1174         }
1175
1176         spin_unlock_irqrestore(&dwc->lock, flags);
1177
1178         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1179
1180         return i;
1181
1182 err_desc_alloc:
1183         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1184
1185         return i;
1186 }
1187
1188 static void dwc_free_chan_resources(struct dma_chan *chan)
1189 {
1190         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1191         struct dw_dma           *dw = to_dw_dma(chan->device);
1192         struct dw_desc          *desc, *_desc;
1193         unsigned long           flags;
1194         LIST_HEAD(list);
1195
1196         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1197                         dwc->descs_allocated);
1198
1199         /* ASSERT:  channel is idle */
1200         BUG_ON(!list_empty(&dwc->active_list));
1201         BUG_ON(!list_empty(&dwc->queue));
1202         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1203
1204         spin_lock_irqsave(&dwc->lock, flags);
1205         list_splice_init(&dwc->free_list, &list);
1206         dwc->descs_allocated = 0;
1207         dwc->initialized = false;
1208
1209         /* Disable interrupts */
1210         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1211         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1212
1213         spin_unlock_irqrestore(&dwc->lock, flags);
1214
1215         /* Disable controller in case it was a last user */
1216         dw->in_use &= ~dwc->mask;
1217         if (!dw->in_use)
1218                 dw_dma_off(dw);
1219
1220         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1221                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1222                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1223         }
1224
1225         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1226 }
1227
1228 /* --------------------- Cyclic DMA API extensions -------------------- */
1229
1230 /**
1231  * dw_dma_cyclic_start - start the cyclic DMA transfer
1232  * @chan: the DMA channel to start
1233  *
1234  * Must be called with soft interrupts disabled. Returns zero on success or
1235  * -errno on failure.
1236  */
1237 int dw_dma_cyclic_start(struct dma_chan *chan)
1238 {
1239         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1240         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1241         unsigned long           flags;
1242
1243         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1244                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1245                 return -ENODEV;
1246         }
1247
1248         spin_lock_irqsave(&dwc->lock, flags);
1249
1250         /* Assert channel is idle */
1251         if (dma_readl(dw, CH_EN) & dwc->mask) {
1252                 dev_err(chan2dev(&dwc->chan),
1253                         "BUG: Attempted to start non-idle channel\n");
1254                 dwc_dump_chan_regs(dwc);
1255                 spin_unlock_irqrestore(&dwc->lock, flags);
1256                 return -EBUSY;
1257         }
1258
1259         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1260         dma_writel(dw, CLEAR.XFER, dwc->mask);
1261
1262         /* Setup DMAC channel registers */
1263         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1264         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1265         channel_writel(dwc, CTL_HI, 0);
1266
1267         channel_set_bit(dw, CH_EN, dwc->mask);
1268
1269         spin_unlock_irqrestore(&dwc->lock, flags);
1270
1271         return 0;
1272 }
1273 EXPORT_SYMBOL(dw_dma_cyclic_start);
1274
1275 /**
1276  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1277  * @chan: the DMA channel to stop
1278  *
1279  * Must be called with soft interrupts disabled.
1280  */
1281 void dw_dma_cyclic_stop(struct dma_chan *chan)
1282 {
1283         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1284         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1285         unsigned long           flags;
1286
1287         spin_lock_irqsave(&dwc->lock, flags);
1288
1289         dwc_chan_disable(dw, dwc);
1290
1291         spin_unlock_irqrestore(&dwc->lock, flags);
1292 }
1293 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1294
1295 /**
1296  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1297  * @chan: the DMA channel to prepare
1298  * @buf_addr: physical DMA address where the buffer starts
1299  * @buf_len: total number of bytes for the entire buffer
1300  * @period_len: number of bytes for each period
1301  * @direction: transfer direction, to or from device
1302  *
1303  * Must be called before trying to start the transfer. Returns a valid struct
1304  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1305  */
1306 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1307                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1308                 enum dma_transfer_direction direction)
1309 {
1310         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1311         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1312         struct dw_cyclic_desc           *cdesc;
1313         struct dw_cyclic_desc           *retval = NULL;
1314         struct dw_desc                  *desc;
1315         struct dw_desc                  *last = NULL;
1316         unsigned long                   was_cyclic;
1317         unsigned int                    reg_width;
1318         unsigned int                    periods;
1319         unsigned int                    i;
1320         unsigned long                   flags;
1321
1322         spin_lock_irqsave(&dwc->lock, flags);
1323         if (dwc->nollp) {
1324                 spin_unlock_irqrestore(&dwc->lock, flags);
1325                 dev_dbg(chan2dev(&dwc->chan),
1326                                 "channel doesn't support LLP transfers\n");
1327                 return ERR_PTR(-EINVAL);
1328         }
1329
1330         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1331                 spin_unlock_irqrestore(&dwc->lock, flags);
1332                 dev_dbg(chan2dev(&dwc->chan),
1333                                 "queue and/or active list are not empty\n");
1334                 return ERR_PTR(-EBUSY);
1335         }
1336
1337         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1338         spin_unlock_irqrestore(&dwc->lock, flags);
1339         if (was_cyclic) {
1340                 dev_dbg(chan2dev(&dwc->chan),
1341                                 "channel already prepared for cyclic DMA\n");
1342                 return ERR_PTR(-EBUSY);
1343         }
1344
1345         retval = ERR_PTR(-EINVAL);
1346
1347         if (unlikely(!is_slave_direction(direction)))
1348                 goto out_err;
1349
1350         dwc->direction = direction;
1351
1352         if (direction == DMA_MEM_TO_DEV)
1353                 reg_width = __ffs(sconfig->dst_addr_width);
1354         else
1355                 reg_width = __ffs(sconfig->src_addr_width);
1356
1357         periods = buf_len / period_len;
1358
1359         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1360         if (period_len > (dwc->block_size << reg_width))
1361                 goto out_err;
1362         if (unlikely(period_len & ((1 << reg_width) - 1)))
1363                 goto out_err;
1364         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1365                 goto out_err;
1366
1367         retval = ERR_PTR(-ENOMEM);
1368
1369         if (periods > NR_DESCS_PER_CHANNEL)
1370                 goto out_err;
1371
1372         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1373         if (!cdesc)
1374                 goto out_err;
1375
1376         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1377         if (!cdesc->desc)
1378                 goto out_err_alloc;
1379
1380         for (i = 0; i < periods; i++) {
1381                 desc = dwc_desc_get(dwc);
1382                 if (!desc)
1383                         goto out_err_desc_get;
1384
1385                 switch (direction) {
1386                 case DMA_MEM_TO_DEV:
1387                         desc->lli.dar = sconfig->dst_addr;
1388                         desc->lli.sar = buf_addr + (period_len * i);
1389                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1390                                         | DWC_CTLL_DST_WIDTH(reg_width)
1391                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1392                                         | DWC_CTLL_DST_FIX
1393                                         | DWC_CTLL_SRC_INC
1394                                         | DWC_CTLL_INT_EN);
1395
1396                         desc->lli.ctllo |= sconfig->device_fc ?
1397                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1398                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1399
1400                         break;
1401                 case DMA_DEV_TO_MEM:
1402                         desc->lli.dar = buf_addr + (period_len * i);
1403                         desc->lli.sar = sconfig->src_addr;
1404                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1405                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1406                                         | DWC_CTLL_DST_WIDTH(reg_width)
1407                                         | DWC_CTLL_DST_INC
1408                                         | DWC_CTLL_SRC_FIX
1409                                         | DWC_CTLL_INT_EN);
1410
1411                         desc->lli.ctllo |= sconfig->device_fc ?
1412                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1413                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1414
1415                         break;
1416                 default:
1417                         break;
1418                 }
1419
1420                 desc->lli.ctlhi = (period_len >> reg_width);
1421                 cdesc->desc[i] = desc;
1422
1423                 if (last)
1424                         last->lli.llp = desc->txd.phys;
1425
1426                 last = desc;
1427         }
1428
1429         /* Let's make a cyclic list */
1430         last->lli.llp = cdesc->desc[0]->txd.phys;
1431
1432         dev_dbg(chan2dev(&dwc->chan),
1433                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1434                         &buf_addr, buf_len, period_len, periods);
1435
1436         cdesc->periods = periods;
1437         dwc->cdesc = cdesc;
1438
1439         return cdesc;
1440
1441 out_err_desc_get:
1442         while (i--)
1443                 dwc_desc_put(dwc, cdesc->desc[i]);
1444 out_err_alloc:
1445         kfree(cdesc);
1446 out_err:
1447         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1448         return (struct dw_cyclic_desc *)retval;
1449 }
1450 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1451
1452 /**
1453  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1454  * @chan: the DMA channel to free
1455  */
1456 void dw_dma_cyclic_free(struct dma_chan *chan)
1457 {
1458         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1459         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1460         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1461         int                     i;
1462         unsigned long           flags;
1463
1464         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1465
1466         if (!cdesc)
1467                 return;
1468
1469         spin_lock_irqsave(&dwc->lock, flags);
1470
1471         dwc_chan_disable(dw, dwc);
1472
1473         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1474         dma_writel(dw, CLEAR.XFER, dwc->mask);
1475
1476         spin_unlock_irqrestore(&dwc->lock, flags);
1477
1478         for (i = 0; i < cdesc->periods; i++)
1479                 dwc_desc_put(dwc, cdesc->desc[i]);
1480
1481         kfree(cdesc->desc);
1482         kfree(cdesc);
1483
1484         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1485 }
1486 EXPORT_SYMBOL(dw_dma_cyclic_free);
1487
1488 /*----------------------------------------------------------------------*/
1489
1490 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1491 {
1492         struct dw_dma           *dw;
1493         bool                    autocfg;
1494         unsigned int            dw_params;
1495         unsigned int            nr_channels;
1496         unsigned int            max_blk_size = 0;
1497         int                     err;
1498         int                     i;
1499
1500         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1501         if (!dw)
1502                 return -ENOMEM;
1503
1504         dw->regs = chip->regs;
1505         chip->dw = dw;
1506
1507         dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1508         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1509
1510         dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1511
1512         if (!pdata && autocfg) {
1513                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1514                 if (!pdata) {
1515                         err = -ENOMEM;
1516                         goto err_pdata;
1517                 }
1518
1519                 /* Fill platform data with the default values */
1520                 pdata->is_private = true;
1521                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1522                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1523         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1524                 err = -EINVAL;
1525                 goto err_pdata;
1526         }
1527
1528         if (autocfg)
1529                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1530         else
1531                 nr_channels = pdata->nr_channels;
1532
1533         dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
1534                                 GFP_KERNEL);
1535         if (!dw->chan) {
1536                 err = -ENOMEM;
1537                 goto err_pdata;
1538         }
1539
1540         /* Get hardware configuration parameters */
1541         if (autocfg) {
1542                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1543
1544                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1545                 for (i = 0; i < dw->nr_masters; i++) {
1546                         dw->data_width[i] =
1547                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1548                 }
1549         } else {
1550                 dw->nr_masters = pdata->nr_masters;
1551                 memcpy(dw->data_width, pdata->data_width, 4);
1552         }
1553
1554         /* Calculate all channel mask before DMA setup */
1555         dw->all_chan_mask = (1 << nr_channels) - 1;
1556
1557         /* Force dma off, just in case */
1558         dw_dma_off(dw);
1559
1560         /* Disable BLOCK interrupts as well */
1561         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1562
1563         /* Create a pool of consistent memory blocks for hardware descriptors */
1564         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1565                                          sizeof(struct dw_desc), 4, 0);
1566         if (!dw->desc_pool) {
1567                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1568                 err = -ENOMEM;
1569                 goto err_pdata;
1570         }
1571
1572         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1573
1574         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1575                           "dw_dmac", dw);
1576         if (err)
1577                 goto err_pdata;
1578
1579         INIT_LIST_HEAD(&dw->dma.channels);
1580         for (i = 0; i < nr_channels; i++) {
1581                 struct dw_dma_chan      *dwc = &dw->chan[i];
1582                 int                     r = nr_channels - i - 1;
1583
1584                 dwc->chan.device = &dw->dma;
1585                 dma_cookie_init(&dwc->chan);
1586                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1587                         list_add_tail(&dwc->chan.device_node,
1588                                         &dw->dma.channels);
1589                 else
1590                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1591
1592                 /* 7 is highest priority & 0 is lowest. */
1593                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1594                         dwc->priority = r;
1595                 else
1596                         dwc->priority = i;
1597
1598                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1599                 spin_lock_init(&dwc->lock);
1600                 dwc->mask = 1 << i;
1601
1602                 INIT_LIST_HEAD(&dwc->active_list);
1603                 INIT_LIST_HEAD(&dwc->queue);
1604                 INIT_LIST_HEAD(&dwc->free_list);
1605
1606                 channel_clear_bit(dw, CH_EN, dwc->mask);
1607
1608                 dwc->direction = DMA_TRANS_NONE;
1609
1610                 /* Hardware configuration */
1611                 if (autocfg) {
1612                         unsigned int dwc_params;
1613                         void __iomem *addr = chip->regs + r * sizeof(u32);
1614
1615                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1616
1617                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1618                                            dwc_params);
1619
1620                         /*
1621                          * Decode maximum block size for given channel. The
1622                          * stored 4 bit value represents blocks from 0x00 for 3
1623                          * up to 0x0a for 4095.
1624                          */
1625                         dwc->block_size =
1626                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1627                         dwc->nollp =
1628                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1629                 } else {
1630                         dwc->block_size = pdata->block_size;
1631
1632                         /* Check if channel supports multi block transfer */
1633                         channel_writel(dwc, LLP, 0xfffffffc);
1634                         dwc->nollp =
1635                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1636                         channel_writel(dwc, LLP, 0);
1637                 }
1638         }
1639
1640         /* Clear all interrupts on all channels. */
1641         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1642         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1643         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1644         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1645         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1646
1647         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1648         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1649         if (pdata->is_private)
1650                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1651         dw->dma.dev = chip->dev;
1652         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1653         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1654
1655         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1656
1657         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1658         dw->dma.device_control = dwc_control;
1659
1660         dw->dma.device_tx_status = dwc_tx_status;
1661         dw->dma.device_issue_pending = dwc_issue_pending;
1662
1663         err = dma_async_device_register(&dw->dma);
1664         if (err)
1665                 goto err_dma_register;
1666
1667         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1668                  nr_channels);
1669
1670         return 0;
1671
1672 err_dma_register:
1673         free_irq(chip->irq, dw);
1674 err_pdata:
1675         return err;
1676 }
1677 EXPORT_SYMBOL_GPL(dw_dma_probe);
1678
1679 int dw_dma_remove(struct dw_dma_chip *chip)
1680 {
1681         struct dw_dma           *dw = chip->dw;
1682         struct dw_dma_chan      *dwc, *_dwc;
1683
1684         dw_dma_off(dw);
1685         dma_async_device_unregister(&dw->dma);
1686
1687         free_irq(chip->irq, dw);
1688         tasklet_kill(&dw->tasklet);
1689
1690         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1691                         chan.device_node) {
1692                 list_del(&dwc->chan.device_node);
1693                 channel_clear_bit(dw, CH_EN, dwc->mask);
1694         }
1695
1696         return 0;
1697 }
1698 EXPORT_SYMBOL_GPL(dw_dma_remove);
1699
1700 int dw_dma_disable(struct dw_dma_chip *chip)
1701 {
1702         struct dw_dma *dw = chip->dw;
1703
1704         dw_dma_off(dw);
1705         return 0;
1706 }
1707 EXPORT_SYMBOL_GPL(dw_dma_disable);
1708
1709 int dw_dma_enable(struct dw_dma_chip *chip)
1710 {
1711         struct dw_dma *dw = chip->dw;
1712
1713         dw_dma_on(dw);
1714         return 0;
1715 }
1716 EXPORT_SYMBOL_GPL(dw_dma_enable);
1717
1718 MODULE_LICENSE("GPL v2");
1719 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1720 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1721 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");