drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                                                                 \
  49                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  50                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  51                  | DWC_CTLL_LLP_D_EN                            \
  52                  | DWC_CTLL_LLP_S_EN                            \
  53                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  54                  | DWC_CTLL_SMS(_dwc->src_master));             \
  55         })
  56
  57 /*
  58  * Number of descriptors to allocate for each channel. This should be
  59  * made configurable somehow; preferably, the clients (at least the
  60  * ones using slave transfers) should be able to give us a hint.
  61  */
  62 #define NR_DESCS_PER_CHANNEL    64
  63
  64 /* The set of bus widths supported by the DMA controller */
  65 #define DW_DMA_BUSWIDTHS                          \
  66         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
  67         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)          | \
  68         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)         | \
  69         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  70
  71 /*----------------------------------------------------------------------*/
  72
  73 static struct device *chan2dev(struct dma_chan *chan)
  74 {
  75         return &chan->dev->device;
  76 }
  77
  78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  79 {
  80         return to_dw_desc(dwc->active_list.next);
  81 }
  82
  83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  84 {
  85         struct dw_desc *desc, *_desc;
  86         struct dw_desc *ret = NULL;
  87         unsigned int i = 0;
  88         unsigned long flags;
  89
  90         spin_lock_irqsave(&dwc->lock, flags);
  91         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  92                 i++;
  93                 if (async_tx_test_ack(&desc->txd)) {
  94                         list_del(&desc->desc_node);
  95                         ret = desc;
  96                         break;
  97                 }
  98                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  99         }
 100         spin_unlock_irqrestore(&dwc->lock, flags);
 101
 102         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 103
 104         return ret;
 105 }
 106
 107 /*
 108  * Move a descriptor, including any children, to the free list.
 109  * `desc' must not be on any lists.
 110  */
 111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 112 {
 113         unsigned long flags;
 114
 115         if (desc) {
 116                 struct dw_desc *child;
 117
 118                 spin_lock_irqsave(&dwc->lock, flags);
 119                 list_for_each_entry(child, &desc->tx_list, desc_node)
 120                         dev_vdbg(chan2dev(&dwc->chan),
 121                                         "moving child desc %p to freelist\n",
 122                                         child);
 123                 list_splice_init(&desc->tx_list, &dwc->free_list);
 124                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 125                 list_add(&desc->desc_node, &dwc->free_list);
 126                 spin_unlock_irqrestore(&dwc->lock, flags);
 127         }
 128 }
 129
 130 static void dwc_initialize(struct dw_dma_chan *dwc)
 131 {
 132         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 133         struct dw_dma_slave *dws = dwc->chan.private;
 134         u32 cfghi = DWC_CFGH_FIFO_MODE;
 135         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 136
 137         if (dwc->initialized == true)
 138                 return;
 139
 140         if (dws) {
 141                 /*
 142                  * We need controller-specific data to set up slave
 143                  * transfers.
 144                  */
 145                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 146
 147                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 148                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 149         } else {
 150                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 151                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 152         }
 153
 154         channel_writel(dwc, CFG_LO, cfglo);
 155         channel_writel(dwc, CFG_HI, cfghi);
 156
 157         /* Enable interrupts */
 158         channel_set_bit(dw, MASK.XFER, dwc->mask);
 159         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 160
 161         dwc->initialized = true;
 162 }
 163
 164 /*----------------------------------------------------------------------*/
 165
 166 static inline unsigned int dwc_fast_ffs(unsigned long long v)
 167 {
 168         /*
 169          * We can be a lot more clever here, but this should take care
 170          * of the most common optimization.
 171          */
 172         if (!(v & 7))
 173                 return 3;
 174         else if (!(v & 3))
 175                 return 2;
 176         else if (!(v & 1))
 177                 return 1;
 178         return 0;
 179 }
 180
 181 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 182 {
 183         dev_err(chan2dev(&dwc->chan),
 184                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 185                 channel_readl(dwc, SAR),
 186                 channel_readl(dwc, DAR),
 187                 channel_readl(dwc, LLP),
 188                 channel_readl(dwc, CTL_HI),
 189                 channel_readl(dwc, CTL_LO));
 190 }
 191
 192 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 193 {
 194         channel_clear_bit(dw, CH_EN, dwc->mask);
 195         while (dma_readl(dw, CH_EN) & dwc->mask)
 196                 cpu_relax();
 197 }
 198
 199 /*----------------------------------------------------------------------*/
 200
 201 /* Perform single block transfer */
 202 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 203                                        struct dw_desc *desc)
 204 {
 205         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 206         u32             ctllo;
 207
 208         /*
 209          * Software emulation of LLP mode relies on interrupts to continue
 210          * multi block transfer.
 211          */
 212         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 213
 214         channel_writel(dwc, SAR, desc->lli.sar);
 215         channel_writel(dwc, DAR, desc->lli.dar);
 216         channel_writel(dwc, CTL_LO, ctllo);
 217         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 218         channel_set_bit(dw, CH_EN, dwc->mask);
 219
 220         /* Move pointer to next descriptor */
 221         dwc->tx_node_active = dwc->tx_node_active->next;
 222 }
 223
 224 /* Called with dwc->lock held and bh disabled */
 225 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 226 {
 227         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 228         unsigned long   was_soft_llp;
 229
 230         /* ASSERT:  channel is idle */
 231         if (dma_readl(dw, CH_EN) & dwc->mask) {
 232                 dev_err(chan2dev(&dwc->chan),
 233                         "%s: BUG: Attempted to start non-idle channel\n",
 234                         __func__);
 235                 dwc_dump_chan_regs(dwc);
 236
 237                 /* The tasklet will hopefully advance the queue... */
 238                 return;
 239         }
 240
 241         if (dwc->nollp) {
 242                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 243                                                 &dwc->flags);
 244                 if (was_soft_llp) {
 245                         dev_err(chan2dev(&dwc->chan),
 246                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 247                         return;
 248                 }
 249
 250                 dwc_initialize(dwc);
 251
 252                 dwc->residue = first->total_len;
 253                 dwc->tx_node_active = &first->tx_list;
 254
 255                 /* Submit first block */
 256                 dwc_do_single_block(dwc, first);
 257
 258                 return;
 259         }
 260
 261         dwc_initialize(dwc);
 262
 263         channel_writel(dwc, LLP, first->txd.phys);
 264         channel_writel(dwc, CTL_LO,
 265                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 266         channel_writel(dwc, CTL_HI, 0);
 267         channel_set_bit(dw, CH_EN, dwc->mask);
 268 }
 269
 270 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 271 {
 272         struct dw_desc *desc;
 273
 274         if (list_empty(&dwc->queue))
 275                 return;
 276
 277         list_move(dwc->queue.next, &dwc->active_list);
 278         desc = dwc_first_active(dwc);
 279         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 280         dwc_dostart(dwc, desc);
 281 }
 282
 283 /*----------------------------------------------------------------------*/
 284
 285 static void
 286 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 287                 bool callback_required)
 288 {
 289         dma_async_tx_callback           callback = NULL;
 290         void                            *param = NULL;
 291         struct dma_async_tx_descriptor  *txd = &desc->txd;
 292         struct dw_desc                  *child;
 293         unsigned long                   flags;
 294
 295         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 296
 297         spin_lock_irqsave(&dwc->lock, flags);
 298         dma_cookie_complete(txd);
 299         if (callback_required) {
 300                 callback = txd->callback;
 301                 param = txd->callback_param;
 302         }
 303
 304         /* async_tx_ack */
 305         list_for_each_entry(child, &desc->tx_list, desc_node)
 306                 async_tx_ack(&child->txd);
 307         async_tx_ack(&desc->txd);
 308
 309         list_splice_init(&desc->tx_list, &dwc->free_list);
 310         list_move(&desc->desc_node, &dwc->free_list);
 311
 312         dma_descriptor_unmap(txd);
 313         spin_unlock_irqrestore(&dwc->lock, flags);
 314
 315         if (callback)
 316                 callback(param);
 317 }
 318
 319 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 320 {
 321         struct dw_desc *desc, *_desc;
 322         LIST_HEAD(list);
 323         unsigned long flags;
 324
 325         spin_lock_irqsave(&dwc->lock, flags);
 326         if (dma_readl(dw, CH_EN) & dwc->mask) {
 327                 dev_err(chan2dev(&dwc->chan),
 328                         "BUG: XFER bit set, but channel not idle!\n");
 329
 330                 /* Try to continue after resetting the channel... */
 331                 dwc_chan_disable(dw, dwc);
 332         }
 333
 334         /*
 335          * Submit queued descriptors ASAP, i.e. before we go through
 336          * the completed ones.
 337          */
 338         list_splice_init(&dwc->active_list, &list);
 339         dwc_dostart_first_queued(dwc);
 340
 341         spin_unlock_irqrestore(&dwc->lock, flags);
 342
 343         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 344                 dwc_descriptor_complete(dwc, desc, true);
 345 }
 346
 347 /* Returns how many bytes were already received from source */
 348 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 349 {
 350         u32 ctlhi = channel_readl(dwc, CTL_HI);
 351         u32 ctllo = channel_readl(dwc, CTL_LO);
 352
 353         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 354 }
 355
 356 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 357 {
 358         dma_addr_t llp;
 359         struct dw_desc *desc, *_desc;
 360         struct dw_desc *child;
 361         u32 status_xfer;
 362         unsigned long flags;
 363
 364         spin_lock_irqsave(&dwc->lock, flags);
 365         llp = channel_readl(dwc, LLP);
 366         status_xfer = dma_readl(dw, RAW.XFER);
 367
 368         if (status_xfer & dwc->mask) {
 369                 /* Everything we've submitted is done */
 370                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 371
 372                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 373                         struct list_head *head, *active = dwc->tx_node_active;
 374
 375                         /*
 376                          * We are inside first active descriptor.
 377                          * Otherwise something is really wrong.
 378                          */
 379                         desc = dwc_first_active(dwc);
 380
 381                         head = &desc->tx_list;
 382                         if (active != head) {
 383                                 /* Update desc to reflect last sent one */
 384                                 if (active != head->next)
 385                                         desc = to_dw_desc(active->prev);
 386
 387                                 dwc->residue -= desc->len;
 388
 389                                 child = to_dw_desc(active);
 390
 391                                 /* Submit next block */
 392                                 dwc_do_single_block(dwc, child);
 393
 394                                 spin_unlock_irqrestore(&dwc->lock, flags);
 395                                 return;
 396                         }
 397
 398                         /* We are done here */
 399                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 400                 }
 401
 402                 dwc->residue = 0;
 403
 404                 spin_unlock_irqrestore(&dwc->lock, flags);
 405
 406                 dwc_complete_all(dw, dwc);
 407                 return;
 408         }
 409
 410         if (list_empty(&dwc->active_list)) {
 411                 dwc->residue = 0;
 412                 spin_unlock_irqrestore(&dwc->lock, flags);
 413                 return;
 414         }
 415
 416         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 417                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 418                 spin_unlock_irqrestore(&dwc->lock, flags);
 419                 return;
 420         }
 421
 422         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 423
 424         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 425                 /* Initial residue value */
 426                 dwc->residue = desc->total_len;
 427
 428                 /* Check first descriptors addr */
 429                 if (desc->txd.phys == llp) {
 430                         spin_unlock_irqrestore(&dwc->lock, flags);
 431                         return;
 432                 }
 433
 434                 /* Check first descriptors llp */
 435                 if (desc->lli.llp == llp) {
 436                         /* This one is currently in progress */
 437                         dwc->residue -= dwc_get_sent(dwc);
 438                         spin_unlock_irqrestore(&dwc->lock, flags);
 439                         return;
 440                 }
 441
 442                 dwc->residue -= desc->len;
 443                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 444                         if (child->lli.llp == llp) {
 445                                 /* Currently in progress */
 446                                 dwc->residue -= dwc_get_sent(dwc);
 447                                 spin_unlock_irqrestore(&dwc->lock, flags);
 448                                 return;
 449                         }
 450                         dwc->residue -= child->len;
 451                 }
 452
 453                 /*
 454                  * No descriptors so far seem to be in progress, i.e.
 455                  * this one must be done.
 456                  */
 457                 spin_unlock_irqrestore(&dwc->lock, flags);
 458                 dwc_descriptor_complete(dwc, desc, true);
 459                 spin_lock_irqsave(&dwc->lock, flags);
 460         }
 461
 462         dev_err(chan2dev(&dwc->chan),
 463                 "BUG: All descriptors done, but channel not idle!\n");
 464
 465         /* Try to continue after resetting the channel... */
 466         dwc_chan_disable(dw, dwc);
 467
 468         dwc_dostart_first_queued(dwc);
 469         spin_unlock_irqrestore(&dwc->lock, flags);
 470 }
 471
 472 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 473 {
 474         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 475                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 476 }
 477
 478 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 479 {
 480         struct dw_desc *bad_desc;
 481         struct dw_desc *child;
 482         unsigned long flags;
 483
 484         dwc_scan_descriptors(dw, dwc);
 485
 486         spin_lock_irqsave(&dwc->lock, flags);
 487
 488         /*
 489          * The descriptor currently at the head of the active list is
 490          * borked. Since we don't have any way to report errors, we'll
 491          * just have to scream loudly and try to carry on.
 492          */
 493         bad_desc = dwc_first_active(dwc);
 494         list_del_init(&bad_desc->desc_node);
 495         list_move(dwc->queue.next, dwc->active_list.prev);
 496
 497         /* Clear the error flag and try to restart the controller */
 498         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 499         if (!list_empty(&dwc->active_list))
 500                 dwc_dostart(dwc, dwc_first_active(dwc));
 501
 502         /*
 503          * WARN may seem harsh, but since this only happens
 504          * when someone submits a bad physical address in a
 505          * descriptor, we should consider ourselves lucky that the
 506          * controller flagged an error instead of scribbling over
 507          * random memory locations.
 508          */
 509         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 510                                        "  cookie: %d\n", bad_desc->txd.cookie);
 511         dwc_dump_lli(dwc, &bad_desc->lli);
 512         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 513                 dwc_dump_lli(dwc, &child->lli);
 514
 515         spin_unlock_irqrestore(&dwc->lock, flags);
 516
 517         /* Pretend the descriptor completed successfully */
 518         dwc_descriptor_complete(dwc, bad_desc, true);
 519 }
 520
 521 /* --------------------- Cyclic DMA API extensions -------------------- */
 522
 523 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 524 {
 525         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 526         return channel_readl(dwc, SAR);
 527 }
 528 EXPORT_SYMBOL(dw_dma_get_src_addr);
 529
 530 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 531 {
 532         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 533         return channel_readl(dwc, DAR);
 534 }
 535 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 536
 537 /* Called with dwc->lock held and all DMAC interrupts disabled */
 538 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 539                 u32 status_block, u32 status_err, u32 status_xfer)
 540 {
 541         unsigned long flags;
 542
 543         if (status_block & dwc->mask) {
 544                 void (*callback)(void *param);
 545                 void *callback_param;
 546
 547                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 548                                 channel_readl(dwc, LLP));
 549                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 550
 551                 callback = dwc->cdesc->period_callback;
 552                 callback_param = dwc->cdesc->period_callback_param;
 553
 554                 if (callback)
 555                         callback(callback_param);
 556         }
 557
 558         /*
 559          * Error and transfer complete are highly unlikely, and will most
 560          * likely be due to a configuration error by the user.
 561          */
 562         if (unlikely(status_err & dwc->mask) ||
 563                         unlikely(status_xfer & dwc->mask)) {
 564                 int i;
 565
 566                 dev_err(chan2dev(&dwc->chan),
 567                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 568                         status_xfer ? "xfer" : "error");
 569
 570                 spin_lock_irqsave(&dwc->lock, flags);
 571
 572                 dwc_dump_chan_regs(dwc);
 573
 574                 dwc_chan_disable(dw, dwc);
 575
 576                 /* Make sure DMA does not restart by loading a new list */
 577                 channel_writel(dwc, LLP, 0);
 578                 channel_writel(dwc, CTL_LO, 0);
 579                 channel_writel(dwc, CTL_HI, 0);
 580
 581                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 582                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 583                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 584
 585                 for (i = 0; i < dwc->cdesc->periods; i++)
 586                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 587
 588                 spin_unlock_irqrestore(&dwc->lock, flags);
 589         }
 590
 591         /* Re-enable interrupts */
 592         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 593 }
 594
 595 /* ------------------------------------------------------------------------- */
 596
 597 static void dw_dma_tasklet(unsigned long data)
 598 {
 599         struct dw_dma *dw = (struct dw_dma *)data;
 600         struct dw_dma_chan *dwc;
 601         u32 status_block;
 602         u32 status_xfer;
 603         u32 status_err;
 604         int i;
 605
 606         status_block = dma_readl(dw, RAW.BLOCK);
 607         status_xfer = dma_readl(dw, RAW.XFER);
 608         status_err = dma_readl(dw, RAW.ERROR);
 609
 610         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 611
 612         for (i = 0; i < dw->dma.chancnt; i++) {
 613                 dwc = &dw->chan[i];
 614                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 615                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 616                                         status_xfer);
 617                 else if (status_err & (1 << i))
 618                         dwc_handle_error(dw, dwc);
 619                 else if (status_xfer & (1 << i))
 620                         dwc_scan_descriptors(dw, dwc);
 621         }
 622
 623         /* Re-enable interrupts */
 624         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 625         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 626 }
 627
 628 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 629 {
 630         struct dw_dma *dw = dev_id;
 631         u32 status;
 632
 633         /* Check if we have any interrupt from the DMAC which is not in use */
 634         if (!dw->in_use)
 635                 return IRQ_NONE;
 636
 637         status = dma_readl(dw, STATUS_INT);
 638         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 639
 640         /* Check if we have any interrupt from the DMAC */
 641         if (!status)
 642                 return IRQ_NONE;
 643
 644         /*
 645          * Just disable the interrupts. We'll turn them back on in the
 646          * softirq handler.
 647          */
 648         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 649         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 650         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 651
 652         status = dma_readl(dw, STATUS_INT);
 653         if (status) {
 654                 dev_err(dw->dma.dev,
 655                         "BUG: Unexpected interrupts pending: 0x%x\n",
 656                         status);
 657
 658                 /* Try to recover */
 659                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 660                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 661                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 662                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 663                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 664         }
 665
 666         tasklet_schedule(&dw->tasklet);
 667
 668         return IRQ_HANDLED;
 669 }
 670
 671 /*----------------------------------------------------------------------*/
 672
 673 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 674 {
 675         struct dw_desc          *desc = txd_to_dw_desc(tx);
 676         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 677         dma_cookie_t            cookie;
 678         unsigned long           flags;
 679
 680         spin_lock_irqsave(&dwc->lock, flags);
 681         cookie = dma_cookie_assign(tx);
 682
 683         /*
 684          * REVISIT: We should attempt to chain as many descriptors as
 685          * possible, perhaps even appending to those already submitted
 686          * for DMA. But this is hard to do in a race-free manner.
 687          */
 688
 689         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 690         list_add_tail(&desc->desc_node, &dwc->queue);
 691
 692         spin_unlock_irqrestore(&dwc->lock, flags);
 693
 694         return cookie;
 695 }
 696
 697 static struct dma_async_tx_descriptor *
 698 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 699                 size_t len, unsigned long flags)
 700 {
 701         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 702         struct dw_dma           *dw = to_dw_dma(chan->device);
 703         struct dw_desc          *desc;
 704         struct dw_desc          *first;
 705         struct dw_desc          *prev;
 706         size_t                  xfer_count;
 707         size_t                  offset;
 708         unsigned int            src_width;
 709         unsigned int            dst_width;
 710         unsigned int            data_width;
 711         u32                     ctllo;
 712
 713         dev_vdbg(chan2dev(chan),
 714                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 715                         &dest, &src, len, flags);
 716
 717         if (unlikely(!len)) {
 718                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 719                 return NULL;
 720         }
 721
 722         dwc->direction = DMA_MEM_TO_MEM;
 723
 724         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 725                            dw->data_width[dwc->dst_master]);
 726
 727         src_width = dst_width = min_t(unsigned int, data_width,
 728                                       dwc_fast_ffs(src | dest | len));
 729
 730         ctllo = DWC_DEFAULT_CTLLO(chan)
 731                         | DWC_CTLL_DST_WIDTH(dst_width)
 732                         | DWC_CTLL_SRC_WIDTH(src_width)
 733                         | DWC_CTLL_DST_INC
 734                         | DWC_CTLL_SRC_INC
 735                         | DWC_CTLL_FC_M2M;
 736         prev = first = NULL;
 737
 738         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 739                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 740                                            dwc->block_size);
 741
 742                 desc = dwc_desc_get(dwc);
 743                 if (!desc)
 744                         goto err_desc_get;
 745
 746                 desc->lli.sar = src + offset;
 747                 desc->lli.dar = dest + offset;
 748                 desc->lli.ctllo = ctllo;
 749                 desc->lli.ctlhi = xfer_count;
 750                 desc->len = xfer_count << src_width;
 751
 752                 if (!first) {
 753                         first = desc;
 754                 } else {
 755                         prev->lli.llp = desc->txd.phys;
 756                         list_add_tail(&desc->desc_node,
 757                                         &first->tx_list);
 758                 }
 759                 prev = desc;
 760         }
 761
 762         if (flags & DMA_PREP_INTERRUPT)
 763                 /* Trigger interrupt after last block */
 764                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 765
 766         prev->lli.llp = 0;
 767         first->txd.flags = flags;
 768         first->total_len = len;
 769
 770         return &first->txd;
 771
 772 err_desc_get:
 773         dwc_desc_put(dwc, first);
 774         return NULL;
 775 }
 776
 777 static struct dma_async_tx_descriptor *
 778 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 779                 unsigned int sg_len, enum dma_transfer_direction direction,
 780                 unsigned long flags, void *context)
 781 {
 782         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 783         struct dw_dma           *dw = to_dw_dma(chan->device);
 784         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 785         struct dw_desc          *prev;
 786         struct dw_desc          *first;
 787         u32                     ctllo;
 788         dma_addr_t              reg;
 789         unsigned int            reg_width;
 790         unsigned int            mem_width;
 791         unsigned int            data_width;
 792         unsigned int            i;
 793         struct scatterlist      *sg;
 794         size_t                  total_len = 0;
 795
 796         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 797
 798         if (unlikely(!is_slave_direction(direction) || !sg_len))
 799                 return NULL;
 800
 801         dwc->direction = direction;
 802
 803         prev = first = NULL;
 804
 805         switch (direction) {
 806         case DMA_MEM_TO_DEV:
 807                 reg_width = __ffs(sconfig->dst_addr_width);
 808                 reg = sconfig->dst_addr;
 809                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 810                                 | DWC_CTLL_DST_WIDTH(reg_width)
 811                                 | DWC_CTLL_DST_FIX
 812                                 | DWC_CTLL_SRC_INC);
 813
 814                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 815                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 816
 817                 data_width = dw->data_width[dwc->src_master];
 818
 819                 for_each_sg(sgl, sg, sg_len, i) {
 820                         struct dw_desc  *desc;
 821                         u32             len, dlen, mem;
 822
 823                         mem = sg_dma_address(sg);
 824                         len = sg_dma_len(sg);
 825
 826                         mem_width = min_t(unsigned int,
 827                                           data_width, dwc_fast_ffs(mem | len));
 828
 829 slave_sg_todev_fill_desc:
 830                         desc = dwc_desc_get(dwc);
 831                         if (!desc)
 832                                 goto err_desc_get;
 833
 834                         desc->lli.sar = mem;
 835                         desc->lli.dar = reg;
 836                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 837                         if ((len >> mem_width) > dwc->block_size) {
 838                                 dlen = dwc->block_size << mem_width;
 839                                 mem += dlen;
 840                                 len -= dlen;
 841                         } else {
 842                                 dlen = len;
 843                                 len = 0;
 844                         }
 845
 846                         desc->lli.ctlhi = dlen >> mem_width;
 847                         desc->len = dlen;
 848
 849                         if (!first) {
 850                                 first = desc;
 851                         } else {
 852                                 prev->lli.llp = desc->txd.phys;
 853                                 list_add_tail(&desc->desc_node,
 854                                                 &first->tx_list);
 855                         }
 856                         prev = desc;
 857                         total_len += dlen;
 858
 859                         if (len)
 860                                 goto slave_sg_todev_fill_desc;
 861                 }
 862                 break;
 863         case DMA_DEV_TO_MEM:
 864                 reg_width = __ffs(sconfig->src_addr_width);
 865                 reg = sconfig->src_addr;
 866                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 867                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 868                                 | DWC_CTLL_DST_INC
 869                                 | DWC_CTLL_SRC_FIX);
 870
 871                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 872                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 873
 874                 data_width = dw->data_width[dwc->dst_master];
 875
 876                 for_each_sg(sgl, sg, sg_len, i) {
 877                         struct dw_desc  *desc;
 878                         u32             len, dlen, mem;
 879
 880                         mem = sg_dma_address(sg);
 881                         len = sg_dma_len(sg);
 882
 883                         mem_width = min_t(unsigned int,
 884                                           data_width, dwc_fast_ffs(mem | len));
 885
 886 slave_sg_fromdev_fill_desc:
 887                         desc = dwc_desc_get(dwc);
 888                         if (!desc)
 889                                 goto err_desc_get;
 890
 891                         desc->lli.sar = reg;
 892                         desc->lli.dar = mem;
 893                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 894                         if ((len >> reg_width) > dwc->block_size) {
 895                                 dlen = dwc->block_size << reg_width;
 896                                 mem += dlen;
 897                                 len -= dlen;
 898                         } else {
 899                                 dlen = len;
 900                                 len = 0;
 901                         }
 902                         desc->lli.ctlhi = dlen >> reg_width;
 903                         desc->len = dlen;
 904
 905                         if (!first) {
 906                                 first = desc;
 907                         } else {
 908                                 prev->lli.llp = desc->txd.phys;
 909                                 list_add_tail(&desc->desc_node,
 910                                                 &first->tx_list);
 911                         }
 912                         prev = desc;
 913                         total_len += dlen;
 914
 915                         if (len)
 916                                 goto slave_sg_fromdev_fill_desc;
 917                 }
 918                 break;
 919         default:
 920                 return NULL;
 921         }
 922
 923         if (flags & DMA_PREP_INTERRUPT)
 924                 /* Trigger interrupt after last block */
 925                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 926
 927         prev->lli.llp = 0;
 928         first->total_len = total_len;
 929
 930         return &first->txd;
 931
 932 err_desc_get:
 933         dev_err(chan2dev(chan),
 934                 "not enough descriptors available. Direction %d\n", direction);
 935         dwc_desc_put(dwc, first);
 936         return NULL;
 937 }
 938
 939 bool dw_dma_filter(struct dma_chan *chan, void *param)
 940 {
 941         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 942         struct dw_dma_slave *dws = param;
 943
 944         if (!dws || dws->dma_dev != chan->device->dev)
 945                 return false;
 946
 947         /* We have to copy data since dws can be temporary storage */
 948
 949         dwc->src_id = dws->src_id;
 950         dwc->dst_id = dws->dst_id;
 951
 952         dwc->src_master = dws->src_master;
 953         dwc->dst_master = dws->dst_master;
 954
 955         return true;
 956 }
 957 EXPORT_SYMBOL_GPL(dw_dma_filter);
 958
 959 /*
 960  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 961  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 962  *
 963  * NOTE: burst size 2 is not supported by controller.
 964  *
 965  * This can be done by finding least significant bit set: n & (n - 1)
 966  */
 967 static inline void convert_burst(u32 *maxburst)
 968 {
 969         if (*maxburst > 1)
 970                 *maxburst = fls(*maxburst) - 2;
 971         else
 972                 *maxburst = 0;
 973 }
 974
 975 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 976 {
 977         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 978
 979         /* Check if chan will be configured for slave transfers */
 980         if (!is_slave_direction(sconfig->direction))
 981                 return -EINVAL;
 982
 983         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 984         dwc->direction = sconfig->direction;
 985
 986         convert_burst(&dwc->dma_sconfig.src_maxburst);
 987         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 988
 989         return 0;
 990 }
 991
 992 static int dwc_pause(struct dma_chan *chan)
 993 {
 994         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 995         unsigned long           flags;
 996         unsigned int            count = 20;     /* timeout iterations */
 997         u32                     cfglo;
 998
 999         spin_lock_irqsave(&dwc->lock, flags);
1000
1001         cfglo = channel_readl(dwc, CFG_LO);
1002         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
1003         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
1004                 udelay(2);
1005
1006         dwc->paused = true;
1007
1008         spin_unlock_irqrestore(&dwc->lock, flags);
1009
1010         return 0;
1011 }
1012
1013 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1014 {
1015         u32 cfglo = channel_readl(dwc, CFG_LO);
1016
1017         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1018
1019         dwc->paused = false;
1020 }
1021
1022 static int dwc_resume(struct dma_chan *chan)
1023 {
1024         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1025         unsigned long           flags;
1026
1027         if (!dwc->paused)
1028                 return 0;
1029
1030         spin_lock_irqsave(&dwc->lock, flags);
1031
1032         dwc_chan_resume(dwc);
1033
1034         spin_unlock_irqrestore(&dwc->lock, flags);
1035
1036         return 0;
1037 }
1038
1039 static int dwc_terminate_all(struct dma_chan *chan)
1040 {
1041         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1042         struct dw_dma           *dw = to_dw_dma(chan->device);
1043         struct dw_desc          *desc, *_desc;
1044         unsigned long           flags;
1045         LIST_HEAD(list);
1046
1047         spin_lock_irqsave(&dwc->lock, flags);
1048
1049         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1050
1051         dwc_chan_disable(dw, dwc);
1052
1053         dwc_chan_resume(dwc);
1054
1055         /* active_list entries will end up before queued entries */
1056         list_splice_init(&dwc->queue, &list);
1057         list_splice_init(&dwc->active_list, &list);
1058
1059         spin_unlock_irqrestore(&dwc->lock, flags);
1060
1061         /* Flush all pending and queued descriptors */
1062         list_for_each_entry_safe(desc, _desc, &list, desc_node)
1063                 dwc_descriptor_complete(dwc, desc, false);
1064
1065         return 0;
1066 }
1067
1068 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1069 {
1070         unsigned long flags;
1071         u32 residue;
1072
1073         spin_lock_irqsave(&dwc->lock, flags);
1074
1075         residue = dwc->residue;
1076         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1077                 residue -= dwc_get_sent(dwc);
1078
1079         spin_unlock_irqrestore(&dwc->lock, flags);
1080         return residue;
1081 }
1082
1083 static enum dma_status
1084 dwc_tx_status(struct dma_chan *chan,
1085               dma_cookie_t cookie,
1086               struct dma_tx_state *txstate)
1087 {
1088         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1089         enum dma_status         ret;
1090
1091         ret = dma_cookie_status(chan, cookie, txstate);
1092         if (ret == DMA_COMPLETE)
1093                 return ret;
1094
1095         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1096
1097         ret = dma_cookie_status(chan, cookie, txstate);
1098         if (ret != DMA_COMPLETE)
1099                 dma_set_residue(txstate, dwc_get_residue(dwc));
1100
1101         if (dwc->paused && ret == DMA_IN_PROGRESS)
1102                 return DMA_PAUSED;
1103
1104         return ret;
1105 }
1106
1107 static void dwc_issue_pending(struct dma_chan *chan)
1108 {
1109         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1110         unsigned long           flags;
1111
1112         spin_lock_irqsave(&dwc->lock, flags);
1113         if (list_empty(&dwc->active_list))
1114                 dwc_dostart_first_queued(dwc);
1115         spin_unlock_irqrestore(&dwc->lock, flags);
1116 }
1117
1118 /*----------------------------------------------------------------------*/
1119
1120 static void dw_dma_off(struct dw_dma *dw)
1121 {
1122         int i;
1123
1124         dma_writel(dw, CFG, 0);
1125
1126         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1127         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1128         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1129         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1130         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1131
1132         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1133                 cpu_relax();
1134
1135         for (i = 0; i < dw->dma.chancnt; i++)
1136                 dw->chan[i].initialized = false;
1137 }
1138
1139 static void dw_dma_on(struct dw_dma *dw)
1140 {
1141         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1142 }
1143
1144 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1145 {
1146         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1147         struct dw_dma           *dw = to_dw_dma(chan->device);
1148         struct dw_desc          *desc;
1149         int                     i;
1150         unsigned long           flags;
1151
1152         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1153
1154         /* ASSERT:  channel is idle */
1155         if (dma_readl(dw, CH_EN) & dwc->mask) {
1156                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1157                 return -EIO;
1158         }
1159
1160         dma_cookie_init(chan);
1161
1162         /*
1163          * NOTE: some controllers may have additional features that we
1164          * need to initialize here, like "scatter-gather" (which
1165          * doesn't mean what you think it means), and status writeback.
1166          */
1167
1168         /* Enable controller here if needed */
1169         if (!dw->in_use)
1170                 dw_dma_on(dw);
1171         dw->in_use |= dwc->mask;
1172
1173         spin_lock_irqsave(&dwc->lock, flags);
1174         i = dwc->descs_allocated;
1175         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1176                 dma_addr_t phys;
1177
1178                 spin_unlock_irqrestore(&dwc->lock, flags);
1179
1180                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1181                 if (!desc)
1182                         goto err_desc_alloc;
1183
1184                 memset(desc, 0, sizeof(struct dw_desc));
1185
1186                 INIT_LIST_HEAD(&desc->tx_list);
1187                 dma_async_tx_descriptor_init(&desc->txd, chan);
1188                 desc->txd.tx_submit = dwc_tx_submit;
1189                 desc->txd.flags = DMA_CTRL_ACK;
1190                 desc->txd.phys = phys;
1191
1192                 dwc_desc_put(dwc, desc);
1193
1194                 spin_lock_irqsave(&dwc->lock, flags);
1195                 i = ++dwc->descs_allocated;
1196         }
1197
1198         spin_unlock_irqrestore(&dwc->lock, flags);
1199
1200         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1201
1202         return i;
1203
1204 err_desc_alloc:
1205         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1206
1207         return i;
1208 }
1209
1210 static void dwc_free_chan_resources(struct dma_chan *chan)
1211 {
1212         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1213         struct dw_dma           *dw = to_dw_dma(chan->device);
1214         struct dw_desc          *desc, *_desc;
1215         unsigned long           flags;
1216         LIST_HEAD(list);
1217
1218         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1219                         dwc->descs_allocated);
1220
1221         /* ASSERT:  channel is idle */
1222         BUG_ON(!list_empty(&dwc->active_list));
1223         BUG_ON(!list_empty(&dwc->queue));
1224         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1225
1226         spin_lock_irqsave(&dwc->lock, flags);
1227         list_splice_init(&dwc->free_list, &list);
1228         dwc->descs_allocated = 0;
1229         dwc->initialized = false;
1230
1231         /* Disable interrupts */
1232         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1233         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1234         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1235
1236         spin_unlock_irqrestore(&dwc->lock, flags);
1237
1238         /* Disable controller in case it was a last user */
1239         dw->in_use &= ~dwc->mask;
1240         if (!dw->in_use)
1241                 dw_dma_off(dw);
1242
1243         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1244                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1245                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1246         }
1247
1248         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1249 }
1250
1251 /* --------------------- Cyclic DMA API extensions -------------------- */
1252
1253 /**
1254  * dw_dma_cyclic_start - start the cyclic DMA transfer
1255  * @chan: the DMA channel to start
1256  *
1257  * Must be called with soft interrupts disabled. Returns zero on success or
1258  * -errno on failure.
1259  */
1260 int dw_dma_cyclic_start(struct dma_chan *chan)
1261 {
1262         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1263         struct dw_dma           *dw = to_dw_dma(chan->device);
1264         unsigned long           flags;
1265
1266         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1267                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1268                 return -ENODEV;
1269         }
1270
1271         spin_lock_irqsave(&dwc->lock, flags);
1272
1273         /* Enable interrupts to perform cyclic transfer */
1274         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1275
1276         dwc_dostart(dwc, dwc->cdesc->desc[0]);
1277
1278         spin_unlock_irqrestore(&dwc->lock, flags);
1279
1280         return 0;
1281 }
1282 EXPORT_SYMBOL(dw_dma_cyclic_start);
1283
1284 /**
1285  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1286  * @chan: the DMA channel to stop
1287  *
1288  * Must be called with soft interrupts disabled.
1289  */
1290 void dw_dma_cyclic_stop(struct dma_chan *chan)
1291 {
1292         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1293         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1294         unsigned long           flags;
1295
1296         spin_lock_irqsave(&dwc->lock, flags);
1297
1298         dwc_chan_disable(dw, dwc);
1299
1300         spin_unlock_irqrestore(&dwc->lock, flags);
1301 }
1302 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1303
1304 /**
1305  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1306  * @chan: the DMA channel to prepare
1307  * @buf_addr: physical DMA address where the buffer starts
1308  * @buf_len: total number of bytes for the entire buffer
1309  * @period_len: number of bytes for each period
1310  * @direction: transfer direction, to or from device
1311  *
1312  * Must be called before trying to start the transfer. Returns a valid struct
1313  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1314  */
1315 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1316                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1317                 enum dma_transfer_direction direction)
1318 {
1319         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1320         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1321         struct dw_cyclic_desc           *cdesc;
1322         struct dw_cyclic_desc           *retval = NULL;
1323         struct dw_desc                  *desc;
1324         struct dw_desc                  *last = NULL;
1325         unsigned long                   was_cyclic;
1326         unsigned int                    reg_width;
1327         unsigned int                    periods;
1328         unsigned int                    i;
1329         unsigned long                   flags;
1330
1331         spin_lock_irqsave(&dwc->lock, flags);
1332         if (dwc->nollp) {
1333                 spin_unlock_irqrestore(&dwc->lock, flags);
1334                 dev_dbg(chan2dev(&dwc->chan),
1335                                 "channel doesn't support LLP transfers\n");
1336                 return ERR_PTR(-EINVAL);
1337         }
1338
1339         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1340                 spin_unlock_irqrestore(&dwc->lock, flags);
1341                 dev_dbg(chan2dev(&dwc->chan),
1342                                 "queue and/or active list are not empty\n");
1343                 return ERR_PTR(-EBUSY);
1344         }
1345
1346         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1347         spin_unlock_irqrestore(&dwc->lock, flags);
1348         if (was_cyclic) {
1349                 dev_dbg(chan2dev(&dwc->chan),
1350                                 "channel already prepared for cyclic DMA\n");
1351                 return ERR_PTR(-EBUSY);
1352         }
1353
1354         retval = ERR_PTR(-EINVAL);
1355
1356         if (unlikely(!is_slave_direction(direction)))
1357                 goto out_err;
1358
1359         dwc->direction = direction;
1360
1361         if (direction == DMA_MEM_TO_DEV)
1362                 reg_width = __ffs(sconfig->dst_addr_width);
1363         else
1364                 reg_width = __ffs(sconfig->src_addr_width);
1365
1366         periods = buf_len / period_len;
1367
1368         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1369         if (period_len > (dwc->block_size << reg_width))
1370                 goto out_err;
1371         if (unlikely(period_len & ((1 << reg_width) - 1)))
1372                 goto out_err;
1373         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1374                 goto out_err;
1375
1376         retval = ERR_PTR(-ENOMEM);
1377
1378         if (periods > NR_DESCS_PER_CHANNEL)
1379                 goto out_err;
1380
1381         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1382         if (!cdesc)
1383                 goto out_err;
1384
1385         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1386         if (!cdesc->desc)
1387                 goto out_err_alloc;
1388
1389         for (i = 0; i < periods; i++) {
1390                 desc = dwc_desc_get(dwc);
1391                 if (!desc)
1392                         goto out_err_desc_get;
1393
1394                 switch (direction) {
1395                 case DMA_MEM_TO_DEV:
1396                         desc->lli.dar = sconfig->dst_addr;
1397                         desc->lli.sar = buf_addr + (period_len * i);
1398                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1399                                         | DWC_CTLL_DST_WIDTH(reg_width)
1400                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1401                                         | DWC_CTLL_DST_FIX
1402                                         | DWC_CTLL_SRC_INC
1403                                         | DWC_CTLL_INT_EN);
1404
1405                         desc->lli.ctllo |= sconfig->device_fc ?
1406                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1407                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1408
1409                         break;
1410                 case DMA_DEV_TO_MEM:
1411                         desc->lli.dar = buf_addr + (period_len * i);
1412                         desc->lli.sar = sconfig->src_addr;
1413                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1414                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1415                                         | DWC_CTLL_DST_WIDTH(reg_width)
1416                                         | DWC_CTLL_DST_INC
1417                                         | DWC_CTLL_SRC_FIX
1418                                         | DWC_CTLL_INT_EN);
1419
1420                         desc->lli.ctllo |= sconfig->device_fc ?
1421                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1422                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1423
1424                         break;
1425                 default:
1426                         break;
1427                 }
1428
1429                 desc->lli.ctlhi = (period_len >> reg_width);
1430                 cdesc->desc[i] = desc;
1431
1432                 if (last)
1433                         last->lli.llp = desc->txd.phys;
1434
1435                 last = desc;
1436         }
1437
1438         /* Let's make a cyclic list */
1439         last->lli.llp = cdesc->desc[0]->txd.phys;
1440
1441         dev_dbg(chan2dev(&dwc->chan),
1442                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1443                         &buf_addr, buf_len, period_len, periods);
1444
1445         cdesc->periods = periods;
1446         dwc->cdesc = cdesc;
1447
1448         return cdesc;
1449
1450 out_err_desc_get:
1451         while (i--)
1452                 dwc_desc_put(dwc, cdesc->desc[i]);
1453 out_err_alloc:
1454         kfree(cdesc);
1455 out_err:
1456         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1457         return (struct dw_cyclic_desc *)retval;
1458 }
1459 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1460
1461 /**
1462  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1463  * @chan: the DMA channel to free
1464  */
1465 void dw_dma_cyclic_free(struct dma_chan *chan)
1466 {
1467         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1468         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1469         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1470         int                     i;
1471         unsigned long           flags;
1472
1473         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1474
1475         if (!cdesc)
1476                 return;
1477
1478         spin_lock_irqsave(&dwc->lock, flags);
1479
1480         dwc_chan_disable(dw, dwc);
1481
1482         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1483         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1484         dma_writel(dw, CLEAR.XFER, dwc->mask);
1485
1486         spin_unlock_irqrestore(&dwc->lock, flags);
1487
1488         for (i = 0; i < cdesc->periods; i++)
1489                 dwc_desc_put(dwc, cdesc->desc[i]);
1490
1491         kfree(cdesc->desc);
1492         kfree(cdesc);
1493
1494         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1495 }
1496 EXPORT_SYMBOL(dw_dma_cyclic_free);
1497
1498 /*----------------------------------------------------------------------*/
1499
1500 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1501 {
1502         struct dw_dma           *dw;
1503         bool                    autocfg = false;
1504         unsigned int            dw_params;
1505         unsigned int            max_blk_size = 0;
1506         int                     err;
1507         int                     i;
1508
1509         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1510         if (!dw)
1511                 return -ENOMEM;
1512
1513         dw->regs = chip->regs;
1514         chip->dw = dw;
1515
1516         pm_runtime_get_sync(chip->dev);
1517
1518         if (!pdata) {
1519                 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1520                 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1521
1522                 autocfg = dw_params >> DW_PARAMS_EN & 1;
1523                 if (!autocfg) {
1524                         err = -EINVAL;
1525                         goto err_pdata;
1526                 }
1527
1528                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1529                 if (!pdata) {
1530                         err = -ENOMEM;
1531                         goto err_pdata;
1532                 }
1533
1534                 /* Get hardware configuration parameters */
1535                 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1536                 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1537                 for (i = 0; i < pdata->nr_masters; i++) {
1538                         pdata->data_width[i] =
1539                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1540                 }
1541                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1542
1543                 /* Fill platform data with the default values */
1544                 pdata->is_private = true;
1545                 pdata->is_memcpy = true;
1546                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1547                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1548         } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1549                 err = -EINVAL;
1550                 goto err_pdata;
1551         }
1552
1553         dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1554                                 GFP_KERNEL);
1555         if (!dw->chan) {
1556                 err = -ENOMEM;
1557                 goto err_pdata;
1558         }
1559
1560         /* Get hardware configuration parameters */
1561         dw->nr_masters = pdata->nr_masters;
1562         for (i = 0; i < dw->nr_masters; i++)
1563                 dw->data_width[i] = pdata->data_width[i];
1564
1565         /* Calculate all channel mask before DMA setup */
1566         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1567
1568         /* Force dma off, just in case */
1569         dw_dma_off(dw);
1570
1571         /* Create a pool of consistent memory blocks for hardware descriptors */
1572         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1573                                          sizeof(struct dw_desc), 4, 0);
1574         if (!dw->desc_pool) {
1575                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1576                 err = -ENOMEM;
1577                 goto err_pdata;
1578         }
1579
1580         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1581
1582         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1583                           "dw_dmac", dw);
1584         if (err)
1585                 goto err_pdata;
1586
1587         INIT_LIST_HEAD(&dw->dma.channels);
1588         for (i = 0; i < pdata->nr_channels; i++) {
1589                 struct dw_dma_chan      *dwc = &dw->chan[i];
1590
1591                 dwc->chan.device = &dw->dma;
1592                 dma_cookie_init(&dwc->chan);
1593                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1594                         list_add_tail(&dwc->chan.device_node,
1595                                         &dw->dma.channels);
1596                 else
1597                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1598
1599                 /* 7 is highest priority & 0 is lowest. */
1600                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1601                         dwc->priority = pdata->nr_channels - i - 1;
1602                 else
1603                         dwc->priority = i;
1604
1605                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1606                 spin_lock_init(&dwc->lock);
1607                 dwc->mask = 1 << i;
1608
1609                 INIT_LIST_HEAD(&dwc->active_list);
1610                 INIT_LIST_HEAD(&dwc->queue);
1611                 INIT_LIST_HEAD(&dwc->free_list);
1612
1613                 channel_clear_bit(dw, CH_EN, dwc->mask);
1614
1615                 dwc->direction = DMA_TRANS_NONE;
1616
1617                 /* Hardware configuration */
1618                 if (autocfg) {
1619                         unsigned int dwc_params;
1620                         unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1621                         void __iomem *addr = chip->regs + r * sizeof(u32);
1622
1623                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1624
1625                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1626                                            dwc_params);
1627
1628                         /*
1629                          * Decode maximum block size for given channel. The
1630                          * stored 4 bit value represents blocks from 0x00 for 3
1631                          * up to 0x0a for 4095.
1632                          */
1633                         dwc->block_size =
1634                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1635                         dwc->nollp =
1636                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1637                 } else {
1638                         dwc->block_size = pdata->block_size;
1639
1640                         /* Check if channel supports multi block transfer */
1641                         channel_writel(dwc, LLP, 0xfffffffc);
1642                         dwc->nollp =
1643                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1644                         channel_writel(dwc, LLP, 0);
1645                 }
1646         }
1647
1648         /* Clear all interrupts on all channels. */
1649         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1650         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1651         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1652         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1653         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1654
1655         /* Set capabilities */
1656         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1657         if (pdata->is_private)
1658                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1659         if (pdata->is_memcpy)
1660                 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1661
1662         dw->dma.dev = chip->dev;
1663         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1664         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1665
1666         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1667         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1668
1669         dw->dma.device_config = dwc_config;
1670         dw->dma.device_pause = dwc_pause;
1671         dw->dma.device_resume = dwc_resume;
1672         dw->dma.device_terminate_all = dwc_terminate_all;
1673
1674         dw->dma.device_tx_status = dwc_tx_status;
1675         dw->dma.device_issue_pending = dwc_issue_pending;
1676
1677         /* DMA capabilities */
1678         dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1679         dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1680         dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1681                              BIT(DMA_MEM_TO_MEM);
1682         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1683
1684         err = dma_async_device_register(&dw->dma);
1685         if (err)
1686                 goto err_dma_register;
1687
1688         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1689                  pdata->nr_channels);
1690
1691         pm_runtime_put_sync_suspend(chip->dev);
1692
1693         return 0;
1694
1695 err_dma_register:
1696         free_irq(chip->irq, dw);
1697 err_pdata:
1698         pm_runtime_put_sync_suspend(chip->dev);
1699         return err;
1700 }
1701 EXPORT_SYMBOL_GPL(dw_dma_probe);
1702
1703 int dw_dma_remove(struct dw_dma_chip *chip)
1704 {
1705         struct dw_dma           *dw = chip->dw;
1706         struct dw_dma_chan      *dwc, *_dwc;
1707
1708         pm_runtime_get_sync(chip->dev);
1709
1710         dw_dma_off(dw);
1711         dma_async_device_unregister(&dw->dma);
1712
1713         free_irq(chip->irq, dw);
1714         tasklet_kill(&dw->tasklet);
1715
1716         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1717                         chan.device_node) {
1718                 list_del(&dwc->chan.device_node);
1719                 channel_clear_bit(dw, CH_EN, dwc->mask);
1720         }
1721
1722         pm_runtime_put_sync_suspend(chip->dev);
1723         return 0;
1724 }
1725 EXPORT_SYMBOL_GPL(dw_dma_remove);
1726
1727 int dw_dma_disable(struct dw_dma_chip *chip)
1728 {
1729         struct dw_dma *dw = chip->dw;
1730
1731         dw_dma_off(dw);
1732         return 0;
1733 }
1734 EXPORT_SYMBOL_GPL(dw_dma_disable);
1735
1736 int dw_dma_enable(struct dw_dma_chip *chip)
1737 {
1738         struct dw_dma *dw = chip->dw;
1739
1740         dw_dma_on(dw);
1741         return 0;
1742 }
1743 EXPORT_SYMBOL_GPL(dw_dma_enable);
1744
1745 MODULE_LICENSE("GPL v2");
1746 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1747 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1748 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");