drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/module.h>
  23 #include <linux/types.h>
  24 #include <linux/bitops.h>
  25 #include <linux/mm.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 #include <linux/sched.h>
  30 #include <linux/semaphore.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/device.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/firmware.h>
  35 #include <linux/slab.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/of.h>
  39 #include <linux/of_address.h>
  40 #include <linux/of_device.h>
  41 #include <linux/of_dma.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/dma-imx-sdma.h>
  45 #include <linux/platform_data/dma-imx.h>
  46 #include <linux/regmap.h>
  47 #include <linux/mfd/syscon.h>
  48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  49
  50 #include "dmaengine.h"
  51
  52 /* SDMA registers */
  53 #define SDMA_H_C0PTR            0x000
  54 #define SDMA_H_INTR             0x004
  55 #define SDMA_H_STATSTOP         0x008
  56 #define SDMA_H_START            0x00c
  57 #define SDMA_H_EVTOVR           0x010
  58 #define SDMA_H_DSPOVR           0x014
  59 #define SDMA_H_HOSTOVR          0x018
  60 #define SDMA_H_EVTPEND          0x01c
  61 #define SDMA_H_DSPENBL          0x020
  62 #define SDMA_H_RESET            0x024
  63 #define SDMA_H_EVTERR           0x028
  64 #define SDMA_H_INTRMSK          0x02c
  65 #define SDMA_H_PSW              0x030
  66 #define SDMA_H_EVTERRDBG        0x034
  67 #define SDMA_H_CONFIG           0x038
  68 #define SDMA_ONCE_ENB           0x040
  69 #define SDMA_ONCE_DATA          0x044
  70 #define SDMA_ONCE_INSTR         0x048
  71 #define SDMA_ONCE_STAT          0x04c
  72 #define SDMA_ONCE_CMD           0x050
  73 #define SDMA_EVT_MIRROR         0x054
  74 #define SDMA_ILLINSTADDR        0x058
  75 #define SDMA_CHN0ADDR           0x05c
  76 #define SDMA_ONCE_RTB           0x060
  77 #define SDMA_XTRIG_CONF1        0x070
  78 #define SDMA_XTRIG_CONF2        0x074
  79 #define SDMA_CHNENBL0_IMX35     0x200
  80 #define SDMA_CHNENBL0_IMX31     0x080
  81 #define SDMA_CHNPRI_0           0x100
  82
  83 /*
  84  * Buffer descriptor status values.
  85  */
  86 #define BD_DONE  0x01
  87 #define BD_WRAP  0x02
  88 #define BD_CONT  0x04
  89 #define BD_INTR  0x08
  90 #define BD_RROR  0x10
  91 #define BD_LAST  0x20
  92 #define BD_EXTD  0x80
  93
  94 /*
  95  * Data Node descriptor status values.
  96  */
  97 #define DND_END_OF_FRAME  0x80
  98 #define DND_END_OF_XFER   0x40
  99 #define DND_DONE          0x20
 100 #define DND_UNUSED        0x01
 101
 102 /*
 103  * IPCV2 descriptor status values.
 104  */
 105 #define BD_IPCV2_END_OF_FRAME  0x40
 106
 107 #define IPCV2_MAX_NODES        50
 108 /*
 109  * Error bit set in the CCB status field by the SDMA,
 110  * in setbd routine, in case of a transfer error
 111  */
 112 #define DATA_ERROR  0x10000000
 113
 114 /*
 115  * Buffer descriptor commands.
 116  */
 117 #define C0_ADDR             0x01
 118 #define C0_LOAD             0x02
 119 #define C0_DUMP             0x03
 120 #define C0_SETCTX           0x07
 121 #define C0_GETCTX           0x03
 122 #define C0_SETDM            0x01
 123 #define C0_SETPM            0x04
 124 #define C0_GETDM            0x02
 125 #define C0_GETPM            0x08
 126 /*
 127  * Change endianness indicator in the BD command field
 128  */
 129 #define CHANGE_ENDIANNESS   0x80
 130
 131 /*
 132  *  p_2_p watermark_level description
 133  *      Bits            Name                    Description
 134  *      0-7             Lower WML               Lower watermark level
 135  *      8               PS                      1: Pad Swallowing
 136  *                                              0: No Pad Swallowing
 137  *      9               PA                      1: Pad Adding
 138  *                                              0: No Pad Adding
 139  *      10              SPDIF                   If this bit is set both source
 140  *                                              and destination are on SPBA
 141  *      11              Source Bit(SP)          1: Source on SPBA
 142  *                                              0: Source on AIPS
 143  *      12              Destination Bit(DP)     1: Destination on SPBA
 144  *                                              0: Destination on AIPS
 145  *      13-15           ---------               MUST BE 0
 146  *      16-23           Higher WML              HWML
 147  *      24-27           N                       Total number of samples after
 148  *                                              which Pad adding/Swallowing
 149  *                                              must be done. It must be odd.
 150  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 151  *                                              LWML event mask
 152  *                                              0: LWE in EVENTS register
 153  *                                              1: LWE in EVENTS2 register
 154  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 155  *                                              HWML event mask
 156  *                                              0: HWE in EVENTS register
 157  *                                              1: HWE in EVENTS2 register
 158  *      30              ---------               MUST BE 0
 159  *      31              CONT                    1: Amount of samples to be
 160  *                                              transferred is unknown and
 161  *                                              script will keep on
 162  *                                              transferring samples as long as
 163  *                                              both events are detected and
 164  *                                              script must be manually stopped
 165  *                                              by the application
 166  *                                              0: The amount of samples to be
 167  *                                              transferred is equal to the
 168  *                                              count field of mode word
 169  */
 170 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 171 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 172 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 173 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 174 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 175 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 176 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 177 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 178 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 179 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 180
 181 /*
 182  * Mode/Count of data node descriptors - IPCv2
 183  */
 184 struct sdma_mode_count {
 185         u32 count   : 16; /* size of the buffer pointed by this BD */
 186         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 187         u32 command :  8; /* command mostly used for channel 0 */
 188 };
 189
 190 /*
 191  * Buffer descriptor
 192  */
 193 struct sdma_buffer_descriptor {
 194         struct sdma_mode_count  mode;
 195         u32 buffer_addr;        /* address of the buffer described */
 196         u32 ext_buffer_addr;    /* extended buffer address */
 197 } __attribute__ ((packed));
 198
 199 /**
 200  * struct sdma_channel_control - Channel control Block
 201  *
 202  * @current_bd_ptr      current buffer descriptor processed
 203  * @base_bd_ptr         first element of buffer descriptor array
 204  * @unused              padding. The SDMA engine expects an array of 128 byte
 205  *                      control blocks
 206  */
 207 struct sdma_channel_control {
 208         u32 current_bd_ptr;
 209         u32 base_bd_ptr;
 210         u32 unused[2];
 211 } __attribute__ ((packed));
 212
 213 /**
 214  * struct sdma_state_registers - SDMA context for a channel
 215  *
 216  * @pc:         program counter
 217  * @t:          test bit: status of arithmetic & test instruction
 218  * @rpc:        return program counter
 219  * @sf:         source fault while loading data
 220  * @spc:        loop start program counter
 221  * @df:         destination fault while storing data
 222  * @epc:        loop end program counter
 223  * @lm:         loop mode
 224  */
 225 struct sdma_state_registers {
 226         u32 pc     :14;
 227         u32 unused1: 1;
 228         u32 t      : 1;
 229         u32 rpc    :14;
 230         u32 unused0: 1;
 231         u32 sf     : 1;
 232         u32 spc    :14;
 233         u32 unused2: 1;
 234         u32 df     : 1;
 235         u32 epc    :14;
 236         u32 lm     : 2;
 237 } __attribute__ ((packed));
 238
 239 /**
 240  * struct sdma_context_data - sdma context specific to a channel
 241  *
 242  * @channel_state:      channel state bits
 243  * @gReg:               general registers
 244  * @mda:                burst dma destination address register
 245  * @msa:                burst dma source address register
 246  * @ms:                 burst dma status register
 247  * @md:                 burst dma data register
 248  * @pda:                peripheral dma destination address register
 249  * @psa:                peripheral dma source address register
 250  * @ps:                 peripheral dma status register
 251  * @pd:                 peripheral dma data register
 252  * @ca:                 CRC polynomial register
 253  * @cs:                 CRC accumulator register
 254  * @dda:                dedicated core destination address register
 255  * @dsa:                dedicated core source address register
 256  * @ds:                 dedicated core status register
 257  * @dd:                 dedicated core data register
 258  */
 259 struct sdma_context_data {
 260         struct sdma_state_registers  channel_state;
 261         u32  gReg[8];
 262         u32  mda;
 263         u32  msa;
 264         u32  ms;
 265         u32  md;
 266         u32  pda;
 267         u32  psa;
 268         u32  ps;
 269         u32  pd;
 270         u32  ca;
 271         u32  cs;
 272         u32  dda;
 273         u32  dsa;
 274         u32  ds;
 275         u32  dd;
 276         u32  scratch0;
 277         u32  scratch1;
 278         u32  scratch2;
 279         u32  scratch3;
 280         u32  scratch4;
 281         u32  scratch5;
 282         u32  scratch6;
 283         u32  scratch7;
 284 } __attribute__ ((packed));
 285
 286 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 287
 288 struct sdma_engine;
 289
 290 /**
 291  * struct sdma_channel - housekeeping for a SDMA channel
 292  *
 293  * @sdma                pointer to the SDMA engine for this channel
 294  * @channel             the channel number, matches dmaengine chan_id + 1
 295  * @direction           transfer type. Needed for setting SDMA script
 296  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 297  * @event_id0           aka dma request line
 298  * @event_id1           for channels that use 2 events
 299  * @word_size           peripheral access size
 300  * @buf_tail            ID of the buffer that was processed
 301  * @num_bd              max NUM_BD. number of descriptors currently handling
 302  */
 303 struct sdma_channel {
 304         struct sdma_engine              *sdma;
 305         unsigned int                    channel;
 306         enum dma_transfer_direction             direction;
 307         enum sdma_peripheral_type       peripheral_type;
 308         unsigned int                    event_id0;
 309         unsigned int                    event_id1;
 310         enum dma_slave_buswidth         word_size;
 311         unsigned int                    buf_tail;
 312         unsigned int                    num_bd;
 313         unsigned int                    period_len;
 314         struct sdma_buffer_descriptor   *bd;
 315         dma_addr_t                      bd_phys;
 316         unsigned int                    pc_from_device, pc_to_device;
 317         unsigned int                    device_to_device;
 318         unsigned long                   flags;
 319         dma_addr_t                      per_address, per_address2;
 320         unsigned long                   event_mask[2];
 321         unsigned long                   watermark_level;
 322         u32                             shp_addr, per_addr;
 323         struct dma_chan                 chan;
 324         spinlock_t                      lock;
 325         struct dma_async_tx_descriptor  desc;
 326         enum dma_status                 status;
 327         unsigned int                    chn_count;
 328         unsigned int                    chn_real_count;
 329         struct tasklet_struct           tasklet;
 330         struct imx_dma_data             data;
 331 };
 332
 333 #define IMX_DMA_SG_LOOP         BIT(0)
 334
 335 #define MAX_DMA_CHANNELS 32
 336 #define MXC_SDMA_DEFAULT_PRIORITY 1
 337 #define MXC_SDMA_MIN_PRIORITY 1
 338 #define MXC_SDMA_MAX_PRIORITY 7
 339
 340 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 341
 342 /**
 343  * struct sdma_firmware_header - Layout of the firmware image
 344  *
 345  * @magic               "SDMA"
 346  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 347  *                      changes.
 348  * @version_minor       firmware minor version (for binary compatible changes)
 349  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 350  * @num_script_addrs    Number of script addresses in this image
 351  * @ram_code_start      offset of SDMA ram image in this firmware image
 352  * @ram_code_size       size of SDMA ram image
 353  * @script_addrs        Stores the start address of the SDMA scripts
 354  *                      (in SDMA memory space)
 355  */
 356 struct sdma_firmware_header {
 357         u32     magic;
 358         u32     version_major;
 359         u32     version_minor;
 360         u32     script_addrs_start;
 361         u32     num_script_addrs;
 362         u32     ram_code_start;
 363         u32     ram_code_size;
 364 };
 365
 366 struct sdma_driver_data {
 367         int chnenbl0;
 368         int num_events;
 369         struct sdma_script_start_addrs  *script_addrs;
 370 };
 371
 372 struct sdma_engine {
 373         struct device                   *dev;
 374         struct device_dma_parameters    dma_parms;
 375         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 376         struct sdma_channel_control     *channel_control;
 377         void __iomem                    *regs;
 378         struct sdma_context_data        *context;
 379         dma_addr_t                      context_phys;
 380         struct dma_device               dma_device;
 381         struct clk                      *clk_ipg;
 382         struct clk                      *clk_ahb;
 383         spinlock_t                      channel_0_lock;
 384         u32                             script_number;
 385         struct sdma_script_start_addrs  *script_addrs;
 386         const struct sdma_driver_data   *drvdata;
 387         u32                             spba_start_addr;
 388         u32                             spba_end_addr;
 389         unsigned int                    irq;
 390 };
 391
 392 static struct sdma_driver_data sdma_imx31 = {
 393         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 394         .num_events = 32,
 395 };
 396
 397 static struct sdma_script_start_addrs sdma_script_imx25 = {
 398         .ap_2_ap_addr = 729,
 399         .uart_2_mcu_addr = 904,
 400         .per_2_app_addr = 1255,
 401         .mcu_2_app_addr = 834,
 402         .uartsh_2_mcu_addr = 1120,
 403         .per_2_shp_addr = 1329,
 404         .mcu_2_shp_addr = 1048,
 405         .ata_2_mcu_addr = 1560,
 406         .mcu_2_ata_addr = 1479,
 407         .app_2_per_addr = 1189,
 408         .app_2_mcu_addr = 770,
 409         .shp_2_per_addr = 1407,
 410         .shp_2_mcu_addr = 979,
 411 };
 412
 413 static struct sdma_driver_data sdma_imx25 = {
 414         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 415         .num_events = 48,
 416         .script_addrs = &sdma_script_imx25,
 417 };
 418
 419 static struct sdma_driver_data sdma_imx35 = {
 420         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 421         .num_events = 48,
 422 };
 423
 424 static struct sdma_script_start_addrs sdma_script_imx51 = {
 425         .ap_2_ap_addr = 642,
 426         .uart_2_mcu_addr = 817,
 427         .mcu_2_app_addr = 747,
 428         .mcu_2_shp_addr = 961,
 429         .ata_2_mcu_addr = 1473,
 430         .mcu_2_ata_addr = 1392,
 431         .app_2_per_addr = 1033,
 432         .app_2_mcu_addr = 683,
 433         .shp_2_per_addr = 1251,
 434         .shp_2_mcu_addr = 892,
 435 };
 436
 437 static struct sdma_driver_data sdma_imx51 = {
 438         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 439         .num_events = 48,
 440         .script_addrs = &sdma_script_imx51,
 441 };
 442
 443 static struct sdma_script_start_addrs sdma_script_imx53 = {
 444         .ap_2_ap_addr = 642,
 445         .app_2_mcu_addr = 683,
 446         .mcu_2_app_addr = 747,
 447         .uart_2_mcu_addr = 817,
 448         .shp_2_mcu_addr = 891,
 449         .mcu_2_shp_addr = 960,
 450         .uartsh_2_mcu_addr = 1032,
 451         .spdif_2_mcu_addr = 1100,
 452         .mcu_2_spdif_addr = 1134,
 453         .firi_2_mcu_addr = 1193,
 454         .mcu_2_firi_addr = 1290,
 455 };
 456
 457 static struct sdma_driver_data sdma_imx53 = {
 458         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 459         .num_events = 48,
 460         .script_addrs = &sdma_script_imx53,
 461 };
 462
 463 static struct sdma_script_start_addrs sdma_script_imx6q = {
 464         .ap_2_ap_addr = 642,
 465         .uart_2_mcu_addr = 817,
 466         .mcu_2_app_addr = 747,
 467         .per_2_per_addr = 6331,
 468         .uartsh_2_mcu_addr = 1032,
 469         .mcu_2_shp_addr = 960,
 470         .app_2_mcu_addr = 683,
 471         .shp_2_mcu_addr = 891,
 472         .spdif_2_mcu_addr = 1100,
 473         .mcu_2_spdif_addr = 1134,
 474 };
 475
 476 static struct sdma_driver_data sdma_imx6q = {
 477         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 478         .num_events = 48,
 479         .script_addrs = &sdma_script_imx6q,
 480 };
 481
 482 static struct sdma_script_start_addrs sdma_script_imx7d = {
 483         .ap_2_ap_addr = 644,
 484         .uart_2_mcu_addr = 819,
 485         .mcu_2_app_addr = 749,
 486         .uartsh_2_mcu_addr = 1034,
 487         .mcu_2_shp_addr = 962,
 488         .app_2_mcu_addr = 685,
 489         .shp_2_mcu_addr = 893,
 490         .spdif_2_mcu_addr = 1102,
 491         .mcu_2_spdif_addr = 1136,
 492 };
 493
 494 static struct sdma_driver_data sdma_imx7d = {
 495         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 496         .num_events = 48,
 497         .script_addrs = &sdma_script_imx7d,
 498 };
 499
 500 static const struct platform_device_id sdma_devtypes[] = {
 501         {
 502                 .name = "imx25-sdma",
 503                 .driver_data = (unsigned long)&sdma_imx25,
 504         }, {
 505                 .name = "imx31-sdma",
 506                 .driver_data = (unsigned long)&sdma_imx31,
 507         }, {
 508                 .name = "imx35-sdma",
 509                 .driver_data = (unsigned long)&sdma_imx35,
 510         }, {
 511                 .name = "imx51-sdma",
 512                 .driver_data = (unsigned long)&sdma_imx51,
 513         }, {
 514                 .name = "imx53-sdma",
 515                 .driver_data = (unsigned long)&sdma_imx53,
 516         }, {
 517                 .name = "imx6q-sdma",
 518                 .driver_data = (unsigned long)&sdma_imx6q,
 519         }, {
 520                 .name = "imx7d-sdma",
 521                 .driver_data = (unsigned long)&sdma_imx7d,
 522         }, {
 523                 /* sentinel */
 524         }
 525 };
 526 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 527
 528 static const struct of_device_id sdma_dt_ids[] = {
 529         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 530         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 531         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 532         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 533         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 534         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 535         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 536         { /* sentinel */ }
 537 };
 538 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 539
 540 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 541 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 542 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 543 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 544
 545 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 546 {
 547         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 548         return chnenbl0 + event * 4;
 549 }
 550
 551 static int sdma_config_ownership(struct sdma_channel *sdmac,
 552                 bool event_override, bool mcu_override, bool dsp_override)
 553 {
 554         struct sdma_engine *sdma = sdmac->sdma;
 555         int channel = sdmac->channel;
 556         unsigned long evt, mcu, dsp;
 557
 558         if (event_override && mcu_override && dsp_override)
 559                 return -EINVAL;
 560
 561         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 562         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 563         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 564
 565         if (dsp_override)
 566                 __clear_bit(channel, &dsp);
 567         else
 568                 __set_bit(channel, &dsp);
 569
 570         if (event_override)
 571                 __clear_bit(channel, &evt);
 572         else
 573                 __set_bit(channel, &evt);
 574
 575         if (mcu_override)
 576                 __clear_bit(channel, &mcu);
 577         else
 578                 __set_bit(channel, &mcu);
 579
 580         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 581         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 582         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 583
 584         return 0;
 585 }
 586
 587 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 588 {
 589         writel(BIT(channel), sdma->regs + SDMA_H_START);
 590 }
 591
 592 /*
 593  * sdma_run_channel0 - run a channel and wait till it's done
 594  */
 595 static int sdma_run_channel0(struct sdma_engine *sdma)
 596 {
 597         int ret;
 598         u32 reg;
 599
 600         sdma_enable_channel(sdma, 0);
 601
 602         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 603                                                 reg, !(reg & 1), 1, 500);
 604         if (ret)
 605                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 606
 607         /* Set bits of CONFIG register with dynamic context switching */
 608         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 609                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 610
 611         return ret;
 612 }
 613
 614 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 615                 u32 address)
 616 {
 617         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 618         void *buf_virt;
 619         dma_addr_t buf_phys;
 620         int ret;
 621         unsigned long flags;
 622
 623         buf_virt = dma_alloc_coherent(NULL,
 624                         size,
 625                         &buf_phys, GFP_KERNEL);
 626         if (!buf_virt) {
 627                 return -ENOMEM;
 628         }
 629
 630         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 631
 632         bd0->mode.command = C0_SETPM;
 633         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 634         bd0->mode.count = size / 2;
 635         bd0->buffer_addr = buf_phys;
 636         bd0->ext_buffer_addr = address;
 637
 638         memcpy(buf_virt, buf, size);
 639
 640         ret = sdma_run_channel0(sdma);
 641
 642         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 643
 644         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 645
 646         return ret;
 647 }
 648
 649 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 650 {
 651         struct sdma_engine *sdma = sdmac->sdma;
 652         int channel = sdmac->channel;
 653         unsigned long val;
 654         u32 chnenbl = chnenbl_ofs(sdma, event);
 655
 656         val = readl_relaxed(sdma->regs + chnenbl);
 657         __set_bit(channel, &val);
 658         writel_relaxed(val, sdma->regs + chnenbl);
 659 }
 660
 661 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 662 {
 663         struct sdma_engine *sdma = sdmac->sdma;
 664         int channel = sdmac->channel;
 665         u32 chnenbl = chnenbl_ofs(sdma, event);
 666         unsigned long val;
 667
 668         val = readl_relaxed(sdma->regs + chnenbl);
 669         __clear_bit(channel, &val);
 670         writel_relaxed(val, sdma->regs + chnenbl);
 671 }
 672
 673 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 674 {
 675         dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
 676 }
 677
 678 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 679 {
 680         struct sdma_buffer_descriptor *bd;
 681
 682         /*
 683          * loop mode. Iterate over descriptors, re-setup them and
 684          * call callback function.
 685          */
 686         while (1) {
 687                 bd = &sdmac->bd[sdmac->buf_tail];
 688
 689                 if (bd->mode.status & BD_DONE)
 690                         break;
 691
 692                 if (bd->mode.status & BD_RROR)
 693                         sdmac->status = DMA_ERROR;
 694
 695                 bd->mode.status |= BD_DONE;
 696                 sdmac->buf_tail++;
 697                 sdmac->buf_tail %= sdmac->num_bd;
 698         }
 699 }
 700
 701 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 702 {
 703         struct sdma_buffer_descriptor *bd;
 704         int i, error = 0;
 705
 706         sdmac->chn_real_count = 0;
 707         /*
 708          * non loop mode. Iterate over all descriptors, collect
 709          * errors and call callback function
 710          */
 711         for (i = 0; i < sdmac->num_bd; i++) {
 712                 bd = &sdmac->bd[i];
 713
 714                  if (bd->mode.status & (BD_DONE | BD_RROR))
 715                         error = -EIO;
 716                  sdmac->chn_real_count += bd->mode.count;
 717         }
 718
 719         if (error)
 720                 sdmac->status = DMA_ERROR;
 721         else
 722                 sdmac->status = DMA_COMPLETE;
 723
 724         dma_cookie_complete(&sdmac->desc);
 725
 726         dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
 727 }
 728
 729 static void sdma_tasklet(unsigned long data)
 730 {
 731         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 732
 733         if (sdmac->flags & IMX_DMA_SG_LOOP)
 734                 sdma_handle_channel_loop(sdmac);
 735         else
 736                 mxc_sdma_handle_channel_normal(sdmac);
 737 }
 738
 739 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 740 {
 741         struct sdma_engine *sdma = dev_id;
 742         unsigned long stat;
 743
 744         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 745         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 746         /* channel 0 is special and not handled here, see run_channel0() */
 747         stat &= ~1;
 748
 749         while (stat) {
 750                 int channel = fls(stat) - 1;
 751                 struct sdma_channel *sdmac = &sdma->channel[channel];
 752
 753                 if (sdmac->flags & IMX_DMA_SG_LOOP)
 754                         sdma_update_channel_loop(sdmac);
 755
 756                 tasklet_schedule(&sdmac->tasklet);
 757
 758                 __clear_bit(channel, &stat);
 759         }
 760
 761         return IRQ_HANDLED;
 762 }
 763
 764 /*
 765  * sets the pc of SDMA script according to the peripheral type
 766  */
 767 static void sdma_get_pc(struct sdma_channel *sdmac,
 768                 enum sdma_peripheral_type peripheral_type)
 769 {
 770         struct sdma_engine *sdma = sdmac->sdma;
 771         int per_2_emi = 0, emi_2_per = 0;
 772         /*
 773          * These are needed once we start to support transfers between
 774          * two peripherals or memory-to-memory transfers
 775          */
 776         int per_2_per = 0;
 777
 778         sdmac->pc_from_device = 0;
 779         sdmac->pc_to_device = 0;
 780         sdmac->device_to_device = 0;
 781
 782         switch (peripheral_type) {
 783         case IMX_DMATYPE_MEMORY:
 784                 break;
 785         case IMX_DMATYPE_DSP:
 786                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 787                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 788                 break;
 789         case IMX_DMATYPE_FIRI:
 790                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 791                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 792                 break;
 793         case IMX_DMATYPE_UART:
 794                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 795                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 796                 break;
 797         case IMX_DMATYPE_UART_SP:
 798                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 799                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 800                 break;
 801         case IMX_DMATYPE_ATA:
 802                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 803                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 804                 break;
 805         case IMX_DMATYPE_CSPI:
 806         case IMX_DMATYPE_EXT:
 807         case IMX_DMATYPE_SSI:
 808         case IMX_DMATYPE_SAI:
 809                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 810                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 811                 break;
 812         case IMX_DMATYPE_SSI_DUAL:
 813                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 814                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 815                 break;
 816         case IMX_DMATYPE_SSI_SP:
 817         case IMX_DMATYPE_MMC:
 818         case IMX_DMATYPE_SDHC:
 819         case IMX_DMATYPE_CSPI_SP:
 820         case IMX_DMATYPE_ESAI:
 821         case IMX_DMATYPE_MSHC_SP:
 822                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 823                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 824                 break;
 825         case IMX_DMATYPE_ASRC:
 826                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 827                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 828                 per_2_per = sdma->script_addrs->per_2_per_addr;
 829                 break;
 830         case IMX_DMATYPE_ASRC_SP:
 831                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 832                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 833                 per_2_per = sdma->script_addrs->per_2_per_addr;
 834                 break;
 835         case IMX_DMATYPE_MSHC:
 836                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 837                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 838                 break;
 839         case IMX_DMATYPE_CCM:
 840                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 841                 break;
 842         case IMX_DMATYPE_SPDIF:
 843                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 844                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 845                 break;
 846         case IMX_DMATYPE_IPU_MEMORY:
 847                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 848                 break;
 849         default:
 850                 break;
 851         }
 852
 853         sdmac->pc_from_device = per_2_emi;
 854         sdmac->pc_to_device = emi_2_per;
 855         sdmac->device_to_device = per_2_per;
 856 }
 857
 858 static int sdma_load_context(struct sdma_channel *sdmac)
 859 {
 860         struct sdma_engine *sdma = sdmac->sdma;
 861         int channel = sdmac->channel;
 862         int load_address;
 863         struct sdma_context_data *context = sdma->context;
 864         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 865         int ret;
 866         unsigned long flags;
 867
 868         if (sdmac->direction == DMA_DEV_TO_MEM)
 869                 load_address = sdmac->pc_from_device;
 870         else if (sdmac->direction == DMA_DEV_TO_DEV)
 871                 load_address = sdmac->device_to_device;
 872         else
 873                 load_address = sdmac->pc_to_device;
 874
 875         if (load_address < 0)
 876                 return load_address;
 877
 878         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 879         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 880         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 881         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 882         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 883         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 884
 885         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 886
 887         memset(context, 0, sizeof(*context));
 888         context->channel_state.pc = load_address;
 889
 890         /* Send by context the event mask,base address for peripheral
 891          * and watermark level
 892          */
 893         context->gReg[0] = sdmac->event_mask[1];
 894         context->gReg[1] = sdmac->event_mask[0];
 895         context->gReg[2] = sdmac->per_addr;
 896         context->gReg[6] = sdmac->shp_addr;
 897         context->gReg[7] = sdmac->watermark_level;
 898
 899         bd0->mode.command = C0_SETDM;
 900         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 901         bd0->mode.count = sizeof(*context) / 4;
 902         bd0->buffer_addr = sdma->context_phys;
 903         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 904         ret = sdma_run_channel0(sdma);
 905
 906         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 907
 908         return ret;
 909 }
 910
 911 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 912 {
 913         return container_of(chan, struct sdma_channel, chan);
 914 }
 915
 916 static int sdma_disable_channel(struct dma_chan *chan)
 917 {
 918         struct sdma_channel *sdmac = to_sdma_chan(chan);
 919         struct sdma_engine *sdma = sdmac->sdma;
 920         int channel = sdmac->channel;
 921
 922         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 923         sdmac->status = DMA_ERROR;
 924
 925         return 0;
 926 }
 927
 928 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 929 {
 930         struct sdma_engine *sdma = sdmac->sdma;
 931
 932         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
 933         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
 934
 935         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
 936         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
 937
 938         if (sdmac->event_id0 > 31)
 939                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
 940
 941         if (sdmac->event_id1 > 31)
 942                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
 943
 944         /*
 945          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
 946          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
 947          * r0(event_mask[1]) and r1(event_mask[0]).
 948          */
 949         if (lwml > hwml) {
 950                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
 951                                                 SDMA_WATERMARK_LEVEL_HWML);
 952                 sdmac->watermark_level |= hwml;
 953                 sdmac->watermark_level |= lwml << 16;
 954                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
 955         }
 956
 957         if (sdmac->per_address2 >= sdma->spba_start_addr &&
 958                         sdmac->per_address2 <= sdma->spba_end_addr)
 959                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
 960
 961         if (sdmac->per_address >= sdma->spba_start_addr &&
 962                         sdmac->per_address <= sdma->spba_end_addr)
 963                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
 964
 965         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
 966 }
 967
 968 static int sdma_config_channel(struct dma_chan *chan)
 969 {
 970         struct sdma_channel *sdmac = to_sdma_chan(chan);
 971         int ret;
 972
 973         sdma_disable_channel(chan);
 974
 975         sdmac->event_mask[0] = 0;
 976         sdmac->event_mask[1] = 0;
 977         sdmac->shp_addr = 0;
 978         sdmac->per_addr = 0;
 979
 980         if (sdmac->event_id0) {
 981                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 982                         return -EINVAL;
 983                 sdma_event_enable(sdmac, sdmac->event_id0);
 984         }
 985
 986         if (sdmac->event_id1) {
 987                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
 988                         return -EINVAL;
 989                 sdma_event_enable(sdmac, sdmac->event_id1);
 990         }
 991
 992         switch (sdmac->peripheral_type) {
 993         case IMX_DMATYPE_DSP:
 994                 sdma_config_ownership(sdmac, false, true, true);
 995                 break;
 996         case IMX_DMATYPE_MEMORY:
 997                 sdma_config_ownership(sdmac, false, true, false);
 998                 break;
 999         default:
1000                 sdma_config_ownership(sdmac, true, true, false);
1001                 break;
1002         }
1003
1004         sdma_get_pc(sdmac, sdmac->peripheral_type);
1005
1006         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1007                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1008                 /* Handle multiple event channels differently */
1009                 if (sdmac->event_id1) {
1010                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1011                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1012                                 sdma_set_watermarklevel_for_p2p(sdmac);
1013                 } else
1014                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1015
1016                 /* Address */
1017                 sdmac->shp_addr = sdmac->per_address;
1018                 sdmac->per_addr = sdmac->per_address2;
1019         } else {
1020                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1021         }
1022
1023         ret = sdma_load_context(sdmac);
1024
1025         return ret;
1026 }
1027
1028 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1029                 unsigned int priority)
1030 {
1031         struct sdma_engine *sdma = sdmac->sdma;
1032         int channel = sdmac->channel;
1033
1034         if (priority < MXC_SDMA_MIN_PRIORITY
1035             || priority > MXC_SDMA_MAX_PRIORITY) {
1036                 return -EINVAL;
1037         }
1038
1039         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1040
1041         return 0;
1042 }
1043
1044 static int sdma_request_channel(struct sdma_channel *sdmac)
1045 {
1046         struct sdma_engine *sdma = sdmac->sdma;
1047         int channel = sdmac->channel;
1048         int ret = -EBUSY;
1049
1050         sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1051                                         GFP_KERNEL);
1052         if (!sdmac->bd) {
1053                 ret = -ENOMEM;
1054                 goto out;
1055         }
1056
1057         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1058         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1059
1060         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1061         return 0;
1062 out:
1063
1064         return ret;
1065 }
1066
1067 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1068 {
1069         unsigned long flags;
1070         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1071         dma_cookie_t cookie;
1072
1073         spin_lock_irqsave(&sdmac->lock, flags);
1074
1075         cookie = dma_cookie_assign(tx);
1076
1077         spin_unlock_irqrestore(&sdmac->lock, flags);
1078
1079         return cookie;
1080 }
1081
1082 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1083 {
1084         struct sdma_channel *sdmac = to_sdma_chan(chan);
1085         struct imx_dma_data *data = chan->private;
1086         int prio, ret;
1087
1088         if (!data)
1089                 return -EINVAL;
1090
1091         switch (data->priority) {
1092         case DMA_PRIO_HIGH:
1093                 prio = 3;
1094                 break;
1095         case DMA_PRIO_MEDIUM:
1096                 prio = 2;
1097                 break;
1098         case DMA_PRIO_LOW:
1099         default:
1100                 prio = 1;
1101                 break;
1102         }
1103
1104         sdmac->peripheral_type = data->peripheral_type;
1105         sdmac->event_id0 = data->dma_request;
1106         sdmac->event_id1 = data->dma_request2;
1107
1108         ret = clk_enable(sdmac->sdma->clk_ipg);
1109         if (ret)
1110                 return ret;
1111         ret = clk_enable(sdmac->sdma->clk_ahb);
1112         if (ret)
1113                 goto disable_clk_ipg;
1114
1115         ret = sdma_request_channel(sdmac);
1116         if (ret)
1117                 goto disable_clk_ahb;
1118
1119         ret = sdma_set_channel_priority(sdmac, prio);
1120         if (ret)
1121                 goto disable_clk_ahb;
1122
1123         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1124         sdmac->desc.tx_submit = sdma_tx_submit;
1125         /* txd.flags will be overwritten in prep funcs */
1126         sdmac->desc.flags = DMA_CTRL_ACK;
1127
1128         return 0;
1129
1130 disable_clk_ahb:
1131         clk_disable(sdmac->sdma->clk_ahb);
1132 disable_clk_ipg:
1133         clk_disable(sdmac->sdma->clk_ipg);
1134         return ret;
1135 }
1136
1137 static void sdma_free_chan_resources(struct dma_chan *chan)
1138 {
1139         struct sdma_channel *sdmac = to_sdma_chan(chan);
1140         struct sdma_engine *sdma = sdmac->sdma;
1141
1142         sdma_disable_channel(chan);
1143
1144         if (sdmac->event_id0)
1145                 sdma_event_disable(sdmac, sdmac->event_id0);
1146         if (sdmac->event_id1)
1147                 sdma_event_disable(sdmac, sdmac->event_id1);
1148
1149         sdmac->event_id0 = 0;
1150         sdmac->event_id1 = 0;
1151
1152         sdma_set_channel_priority(sdmac, 0);
1153
1154         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1155
1156         clk_disable(sdma->clk_ipg);
1157         clk_disable(sdma->clk_ahb);
1158 }
1159
1160 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1161                 struct dma_chan *chan, struct scatterlist *sgl,
1162                 unsigned int sg_len, enum dma_transfer_direction direction,
1163                 unsigned long flags, void *context)
1164 {
1165         struct sdma_channel *sdmac = to_sdma_chan(chan);
1166         struct sdma_engine *sdma = sdmac->sdma;
1167         int ret, i, count;
1168         int channel = sdmac->channel;
1169         struct scatterlist *sg;
1170
1171         if (sdmac->status == DMA_IN_PROGRESS)
1172                 return NULL;
1173         sdmac->status = DMA_IN_PROGRESS;
1174
1175         sdmac->flags = 0;
1176
1177         sdmac->buf_tail = 0;
1178
1179         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1180                         sg_len, channel);
1181
1182         sdmac->direction = direction;
1183         ret = sdma_load_context(sdmac);
1184         if (ret)
1185                 goto err_out;
1186
1187         if (sg_len > NUM_BD) {
1188                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1189                                 channel, sg_len, NUM_BD);
1190                 ret = -EINVAL;
1191                 goto err_out;
1192         }
1193
1194         sdmac->chn_count = 0;
1195         for_each_sg(sgl, sg, sg_len, i) {
1196                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1197                 int param;
1198
1199                 bd->buffer_addr = sg->dma_address;
1200
1201                 count = sg_dma_len(sg);
1202
1203                 if (count > 0xffff) {
1204                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1205                                         channel, count, 0xffff);
1206                         ret = -EINVAL;
1207                         goto err_out;
1208                 }
1209
1210                 bd->mode.count = count;
1211                 sdmac->chn_count += count;
1212
1213                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1214                         ret =  -EINVAL;
1215                         goto err_out;
1216                 }
1217
1218                 switch (sdmac->word_size) {
1219                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1220                         bd->mode.command = 0;
1221                         if (count & 3 || sg->dma_address & 3)
1222                                 return NULL;
1223                         break;
1224                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1225                         bd->mode.command = 2;
1226                         if (count & 1 || sg->dma_address & 1)
1227                                 return NULL;
1228                         break;
1229                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1230                         bd->mode.command = 1;
1231                         break;
1232                 default:
1233                         return NULL;
1234                 }
1235
1236                 param = BD_DONE | BD_EXTD | BD_CONT;
1237
1238                 if (i + 1 == sg_len) {
1239                         param |= BD_INTR;
1240                         param |= BD_LAST;
1241                         param &= ~BD_CONT;
1242                 }
1243
1244                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1245                                 i, count, (u64)sg->dma_address,
1246                                 param & BD_WRAP ? "wrap" : "",
1247                                 param & BD_INTR ? " intr" : "");
1248
1249                 bd->mode.status = param;
1250         }
1251
1252         sdmac->num_bd = sg_len;
1253         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1254
1255         return &sdmac->desc;
1256 err_out:
1257         sdmac->status = DMA_ERROR;
1258         return NULL;
1259 }
1260
1261 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1262                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1263                 size_t period_len, enum dma_transfer_direction direction,
1264                 unsigned long flags)
1265 {
1266         struct sdma_channel *sdmac = to_sdma_chan(chan);
1267         struct sdma_engine *sdma = sdmac->sdma;
1268         int num_periods = buf_len / period_len;
1269         int channel = sdmac->channel;
1270         int ret, i = 0, buf = 0;
1271
1272         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1273
1274         if (sdmac->status == DMA_IN_PROGRESS)
1275                 return NULL;
1276
1277         sdmac->status = DMA_IN_PROGRESS;
1278
1279         sdmac->buf_tail = 0;
1280         sdmac->period_len = period_len;
1281
1282         sdmac->flags |= IMX_DMA_SG_LOOP;
1283         sdmac->direction = direction;
1284         ret = sdma_load_context(sdmac);
1285         if (ret)
1286                 goto err_out;
1287
1288         if (num_periods > NUM_BD) {
1289                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1290                                 channel, num_periods, NUM_BD);
1291                 goto err_out;
1292         }
1293
1294         if (period_len > 0xffff) {
1295                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1296                                 channel, period_len, 0xffff);
1297                 goto err_out;
1298         }
1299
1300         while (buf < buf_len) {
1301                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1302                 int param;
1303
1304                 bd->buffer_addr = dma_addr;
1305
1306                 bd->mode.count = period_len;
1307
1308                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1309                         goto err_out;
1310                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1311                         bd->mode.command = 0;
1312                 else
1313                         bd->mode.command = sdmac->word_size;
1314
1315                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1316                 if (i + 1 == num_periods)
1317                         param |= BD_WRAP;
1318
1319                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1320                                 i, period_len, (u64)dma_addr,
1321                                 param & BD_WRAP ? "wrap" : "",
1322                                 param & BD_INTR ? " intr" : "");
1323
1324                 bd->mode.status = param;
1325
1326                 dma_addr += period_len;
1327                 buf += period_len;
1328
1329                 i++;
1330         }
1331
1332         sdmac->num_bd = num_periods;
1333         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1334
1335         return &sdmac->desc;
1336 err_out:
1337         sdmac->status = DMA_ERROR;
1338         return NULL;
1339 }
1340
1341 static int sdma_config(struct dma_chan *chan,
1342                        struct dma_slave_config *dmaengine_cfg)
1343 {
1344         struct sdma_channel *sdmac = to_sdma_chan(chan);
1345
1346         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1347                 sdmac->per_address = dmaengine_cfg->src_addr;
1348                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1349                         dmaengine_cfg->src_addr_width;
1350                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1351         } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1352                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1353                 sdmac->per_address = dmaengine_cfg->dst_addr;
1354                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1355                         SDMA_WATERMARK_LEVEL_LWML;
1356                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1357                         SDMA_WATERMARK_LEVEL_HWML;
1358                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1359         } else {
1360                 sdmac->per_address = dmaengine_cfg->dst_addr;
1361                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1362                         dmaengine_cfg->dst_addr_width;
1363                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1364         }
1365         sdmac->direction = dmaengine_cfg->direction;
1366         return sdma_config_channel(chan);
1367 }
1368
1369 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1370                                       dma_cookie_t cookie,
1371                                       struct dma_tx_state *txstate)
1372 {
1373         struct sdma_channel *sdmac = to_sdma_chan(chan);
1374         u32 residue;
1375
1376         if (sdmac->flags & IMX_DMA_SG_LOOP)
1377                 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1378         else
1379                 residue = sdmac->chn_count - sdmac->chn_real_count;
1380
1381         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1382                          residue);
1383
1384         return sdmac->status;
1385 }
1386
1387 static void sdma_issue_pending(struct dma_chan *chan)
1388 {
1389         struct sdma_channel *sdmac = to_sdma_chan(chan);
1390         struct sdma_engine *sdma = sdmac->sdma;
1391
1392         if (sdmac->status == DMA_IN_PROGRESS)
1393                 sdma_enable_channel(sdma, sdmac->channel);
1394 }
1395
1396 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1397 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1398 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1399 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1400
1401 static void sdma_add_scripts(struct sdma_engine *sdma,
1402                 const struct sdma_script_start_addrs *addr)
1403 {
1404         s32 *addr_arr = (u32 *)addr;
1405         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1406         int i;
1407
1408         /* use the default firmware in ROM if missing external firmware */
1409         if (!sdma->script_number)
1410                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1411
1412         for (i = 0; i < sdma->script_number; i++)
1413                 if (addr_arr[i] > 0)
1414                         saddr_arr[i] = addr_arr[i];
1415 }
1416
1417 static void sdma_load_firmware(const struct firmware *fw, void *context)
1418 {
1419         struct sdma_engine *sdma = context;
1420         const struct sdma_firmware_header *header;
1421         const struct sdma_script_start_addrs *addr;
1422         unsigned short *ram_code;
1423
1424         if (!fw) {
1425                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1426                 /* In this case we just use the ROM firmware. */
1427                 return;
1428         }
1429
1430         if (fw->size < sizeof(*header))
1431                 goto err_firmware;
1432
1433         header = (struct sdma_firmware_header *)fw->data;
1434
1435         if (header->magic != SDMA_FIRMWARE_MAGIC)
1436                 goto err_firmware;
1437         if (header->ram_code_start + header->ram_code_size > fw->size)
1438                 goto err_firmware;
1439         switch (header->version_major) {
1440         case 1:
1441                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1442                 break;
1443         case 2:
1444                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1445                 break;
1446         case 3:
1447                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1448                 break;
1449         case 4:
1450                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1451                 break;
1452         default:
1453                 dev_err(sdma->dev, "unknown firmware version\n");
1454                 goto err_firmware;
1455         }
1456
1457         addr = (void *)header + header->script_addrs_start;
1458         ram_code = (void *)header + header->ram_code_start;
1459
1460         clk_enable(sdma->clk_ipg);
1461         clk_enable(sdma->clk_ahb);
1462         /* download the RAM image for SDMA */
1463         sdma_load_script(sdma, ram_code,
1464                         header->ram_code_size,
1465                         addr->ram_code_start_addr);
1466         clk_disable(sdma->clk_ipg);
1467         clk_disable(sdma->clk_ahb);
1468
1469         sdma_add_scripts(sdma, addr);
1470
1471         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1472                         header->version_major,
1473                         header->version_minor);
1474
1475 err_firmware:
1476         release_firmware(fw);
1477 }
1478
1479 #define EVENT_REMAP_CELLS 3
1480
1481 static int sdma_event_remap(struct sdma_engine *sdma)
1482 {
1483         struct device_node *np = sdma->dev->of_node;
1484         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1485         struct property *event_remap;
1486         struct regmap *gpr;
1487         char propname[] = "fsl,sdma-event-remap";
1488         u32 reg, val, shift, num_map, i;
1489         int ret = 0;
1490
1491         if (IS_ERR(np) || IS_ERR(gpr_np))
1492                 goto out;
1493
1494         event_remap = of_find_property(np, propname, NULL);
1495         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1496         if (!num_map) {
1497                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1498                 goto out;
1499         } else if (num_map % EVENT_REMAP_CELLS) {
1500                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1501                                 propname, EVENT_REMAP_CELLS);
1502                 ret = -EINVAL;
1503                 goto out;
1504         }
1505
1506         gpr = syscon_node_to_regmap(gpr_np);
1507         if (IS_ERR(gpr)) {
1508                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1509                 ret = PTR_ERR(gpr);
1510                 goto out;
1511         }
1512
1513         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1514                 ret = of_property_read_u32_index(np, propname, i, &reg);
1515                 if (ret) {
1516                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1517                                         propname, i);
1518                         goto out;
1519                 }
1520
1521                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1522                 if (ret) {
1523                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1524                                         propname, i + 1);
1525                         goto out;
1526                 }
1527
1528                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1529                 if (ret) {
1530                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1531                                         propname, i + 2);
1532                         goto out;
1533                 }
1534
1535                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1536         }
1537
1538 out:
1539         if (!IS_ERR(gpr_np))
1540                 of_node_put(gpr_np);
1541
1542         return ret;
1543 }
1544
1545 static int sdma_get_firmware(struct sdma_engine *sdma,
1546                 const char *fw_name)
1547 {
1548         int ret;
1549
1550         ret = request_firmware_nowait(THIS_MODULE,
1551                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1552                         GFP_KERNEL, sdma, sdma_load_firmware);
1553
1554         return ret;
1555 }
1556
1557 static int sdma_init(struct sdma_engine *sdma)
1558 {
1559         int i, ret;
1560         dma_addr_t ccb_phys;
1561
1562         ret = clk_enable(sdma->clk_ipg);
1563         if (ret)
1564                 return ret;
1565         ret = clk_enable(sdma->clk_ahb);
1566         if (ret)
1567                 goto disable_clk_ipg;
1568
1569         /* Be sure SDMA has not started yet */
1570         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1571
1572         sdma->channel_control = dma_alloc_coherent(NULL,
1573                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1574                         sizeof(struct sdma_context_data),
1575                         &ccb_phys, GFP_KERNEL);
1576
1577         if (!sdma->channel_control) {
1578                 ret = -ENOMEM;
1579                 goto err_dma_alloc;
1580         }
1581
1582         sdma->context = (void *)sdma->channel_control +
1583                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1584         sdma->context_phys = ccb_phys +
1585                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1586
1587         /* Zero-out the CCB structures array just allocated */
1588         memset(sdma->channel_control, 0,
1589                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1590
1591         /* disable all channels */
1592         for (i = 0; i < sdma->drvdata->num_events; i++)
1593                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1594
1595         /* All channels have priority 0 */
1596         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1597                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1598
1599         ret = sdma_request_channel(&sdma->channel[0]);
1600         if (ret)
1601                 goto err_dma_alloc;
1602
1603         sdma_config_ownership(&sdma->channel[0], false, true, false);
1604
1605         /* Set Command Channel (Channel Zero) */
1606         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1607
1608         /* Set bits of CONFIG register but with static context switching */
1609         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1610         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1611
1612         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1613
1614         /* Initializes channel's priorities */
1615         sdma_set_channel_priority(&sdma->channel[0], 7);
1616
1617         clk_disable(sdma->clk_ipg);
1618         clk_disable(sdma->clk_ahb);
1619
1620         return 0;
1621
1622 err_dma_alloc:
1623         clk_disable(sdma->clk_ahb);
1624 disable_clk_ipg:
1625         clk_disable(sdma->clk_ipg);
1626         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1627         return ret;
1628 }
1629
1630 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1631 {
1632         struct sdma_channel *sdmac = to_sdma_chan(chan);
1633         struct imx_dma_data *data = fn_param;
1634
1635         if (!imx_dma_is_general_purpose(chan))
1636                 return false;
1637
1638         sdmac->data = *data;
1639         chan->private = &sdmac->data;
1640
1641         return true;
1642 }
1643
1644 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1645                                    struct of_dma *ofdma)
1646 {
1647         struct sdma_engine *sdma = ofdma->of_dma_data;
1648         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1649         struct imx_dma_data data;
1650
1651         if (dma_spec->args_count != 3)
1652                 return NULL;
1653
1654         data.dma_request = dma_spec->args[0];
1655         data.peripheral_type = dma_spec->args[1];
1656         data.priority = dma_spec->args[2];
1657         /*
1658          * init dma_request2 to zero, which is not used by the dts.
1659          * For P2P, dma_request2 is init from dma_request_channel(),
1660          * chan->private will point to the imx_dma_data, and in
1661          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1662          * be set to sdmac->event_id1.
1663          */
1664         data.dma_request2 = 0;
1665
1666         return dma_request_channel(mask, sdma_filter_fn, &data);
1667 }
1668
1669 static int sdma_probe(struct platform_device *pdev)
1670 {
1671         const struct of_device_id *of_id =
1672                         of_match_device(sdma_dt_ids, &pdev->dev);
1673         struct device_node *np = pdev->dev.of_node;
1674         struct device_node *spba_bus;
1675         const char *fw_name;
1676         int ret;
1677         int irq;
1678         struct resource *iores;
1679         struct resource spba_res;
1680         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1681         int i;
1682         struct sdma_engine *sdma;
1683         s32 *saddr_arr;
1684         const struct sdma_driver_data *drvdata = NULL;
1685
1686         if (of_id)
1687                 drvdata = of_id->data;
1688         else if (pdev->id_entry)
1689                 drvdata = (void *)pdev->id_entry->driver_data;
1690
1691         if (!drvdata) {
1692                 dev_err(&pdev->dev, "unable to find driver data\n");
1693                 return -EINVAL;
1694         }
1695
1696         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1697         if (ret)
1698                 return ret;
1699
1700         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1701         if (!sdma)
1702                 return -ENOMEM;
1703
1704         spin_lock_init(&sdma->channel_0_lock);
1705
1706         sdma->dev = &pdev->dev;
1707         sdma->drvdata = drvdata;
1708
1709         irq = platform_get_irq(pdev, 0);
1710         if (irq < 0)
1711                 return irq;
1712
1713         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1714         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1715         if (IS_ERR(sdma->regs))
1716                 return PTR_ERR(sdma->regs);
1717
1718         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1719         if (IS_ERR(sdma->clk_ipg))
1720                 return PTR_ERR(sdma->clk_ipg);
1721
1722         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1723         if (IS_ERR(sdma->clk_ahb))
1724                 return PTR_ERR(sdma->clk_ahb);
1725
1726         clk_prepare(sdma->clk_ipg);
1727         clk_prepare(sdma->clk_ahb);
1728
1729         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1730                                sdma);
1731         if (ret)
1732                 return ret;
1733
1734         sdma->irq = irq;
1735
1736         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1737         if (!sdma->script_addrs)
1738                 return -ENOMEM;
1739
1740         /* initially no scripts available */
1741         saddr_arr = (s32 *)sdma->script_addrs;
1742         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1743                 saddr_arr[i] = -EINVAL;
1744
1745         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1746         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1747
1748         INIT_LIST_HEAD(&sdma->dma_device.channels);
1749         /* Initialize channel parameters */
1750         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1751                 struct sdma_channel *sdmac = &sdma->channel[i];
1752
1753                 sdmac->sdma = sdma;
1754                 spin_lock_init(&sdmac->lock);
1755
1756                 sdmac->chan.device = &sdma->dma_device;
1757                 dma_cookie_init(&sdmac->chan);
1758                 sdmac->channel = i;
1759
1760                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1761                              (unsigned long) sdmac);
1762                 /*
1763                  * Add the channel to the DMAC list. Do not add channel 0 though
1764                  * because we need it internally in the SDMA driver. This also means
1765                  * that channel 0 in dmaengine counting matches sdma channel 1.
1766                  */
1767                 if (i)
1768                         list_add_tail(&sdmac->chan.device_node,
1769                                         &sdma->dma_device.channels);
1770         }
1771
1772         ret = sdma_init(sdma);
1773         if (ret)
1774                 goto err_init;
1775
1776         ret = sdma_event_remap(sdma);
1777         if (ret)
1778                 goto err_init;
1779
1780         if (sdma->drvdata->script_addrs)
1781                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1782         if (pdata && pdata->script_addrs)
1783                 sdma_add_scripts(sdma, pdata->script_addrs);
1784
1785         if (pdata) {
1786                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1787                 if (ret)
1788                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1789         } else {
1790                 /*
1791                  * Because that device tree does not encode ROM script address,
1792                  * the RAM script in firmware is mandatory for device tree
1793                  * probe, otherwise it fails.
1794                  */
1795                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1796                                               &fw_name);
1797                 if (ret)
1798                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1799                 else {
1800                         ret = sdma_get_firmware(sdma, fw_name);
1801                         if (ret)
1802                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1803                 }
1804         }
1805
1806         sdma->dma_device.dev = &pdev->dev;
1807
1808         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1809         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1810         sdma->dma_device.device_tx_status = sdma_tx_status;
1811         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1812         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1813         sdma->dma_device.device_config = sdma_config;
1814         sdma->dma_device.device_terminate_all = sdma_disable_channel;
1815         sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1816         sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1817         sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1818         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1819         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1820         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1821         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1822
1823         platform_set_drvdata(pdev, sdma);
1824
1825         ret = dma_async_device_register(&sdma->dma_device);
1826         if (ret) {
1827                 dev_err(&pdev->dev, "unable to register\n");
1828                 goto err_init;
1829         }
1830
1831         if (np) {
1832                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1833                 if (ret) {
1834                         dev_err(&pdev->dev, "failed to register controller\n");
1835                         goto err_register;
1836                 }
1837
1838                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1839                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1840                 if (!ret) {
1841                         sdma->spba_start_addr = spba_res.start;
1842                         sdma->spba_end_addr = spba_res.end;
1843                 }
1844                 of_node_put(spba_bus);
1845         }
1846
1847         return 0;
1848
1849 err_register:
1850         dma_async_device_unregister(&sdma->dma_device);
1851 err_init:
1852         kfree(sdma->script_addrs);
1853         return ret;
1854 }
1855
1856 static int sdma_remove(struct platform_device *pdev)
1857 {
1858         struct sdma_engine *sdma = platform_get_drvdata(pdev);
1859         int i;
1860
1861         devm_free_irq(&pdev->dev, sdma->irq, sdma);
1862         dma_async_device_unregister(&sdma->dma_device);
1863         kfree(sdma->script_addrs);
1864         /* Kill the tasklet */
1865         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1866                 struct sdma_channel *sdmac = &sdma->channel[i];
1867
1868                 tasklet_kill(&sdmac->tasklet);
1869         }
1870
1871         platform_set_drvdata(pdev, NULL);
1872         return 0;
1873 }
1874
1875 static struct platform_driver sdma_driver = {
1876         .driver         = {
1877                 .name   = "imx-sdma",
1878                 .of_match_table = sdma_dt_ids,
1879         },
1880         .id_table       = sdma_devtypes,
1881         .remove         = sdma_remove,
1882         .probe          = sdma_probe,
1883 };
1884
1885 module_platform_driver(sdma_driver);
1886
1887 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1888 MODULE_DESCRIPTION("i.MX SDMA driver");
1889 MODULE_LICENSE("GPL");