drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/module.h>
  23 #include <linux/types.h>
  24 #include <linux/bitops.h>
  25 #include <linux/mm.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 #include <linux/sched.h>
  30 #include <linux/semaphore.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/device.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/firmware.h>
  35 #include <linux/slab.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/of.h>
  39 #include <linux/of_address.h>
  40 #include <linux/of_device.h>
  41 #include <linux/of_dma.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/dma-imx-sdma.h>
  45 #include <linux/platform_data/dma-imx.h>
  46 #include <linux/regmap.h>
  47 #include <linux/mfd/syscon.h>
  48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  49
  50 #include "dmaengine.h"
  51
  52 /* SDMA registers */
  53 #define SDMA_H_C0PTR            0x000
  54 #define SDMA_H_INTR             0x004
  55 #define SDMA_H_STATSTOP         0x008
  56 #define SDMA_H_START            0x00c
  57 #define SDMA_H_EVTOVR           0x010
  58 #define SDMA_H_DSPOVR           0x014
  59 #define SDMA_H_HOSTOVR          0x018
  60 #define SDMA_H_EVTPEND          0x01c
  61 #define SDMA_H_DSPENBL          0x020
  62 #define SDMA_H_RESET            0x024
  63 #define SDMA_H_EVTERR           0x028
  64 #define SDMA_H_INTRMSK          0x02c
  65 #define SDMA_H_PSW              0x030
  66 #define SDMA_H_EVTERRDBG        0x034
  67 #define SDMA_H_CONFIG           0x038
  68 #define SDMA_ONCE_ENB           0x040
  69 #define SDMA_ONCE_DATA          0x044
  70 #define SDMA_ONCE_INSTR         0x048
  71 #define SDMA_ONCE_STAT          0x04c
  72 #define SDMA_ONCE_CMD           0x050
  73 #define SDMA_EVT_MIRROR         0x054
  74 #define SDMA_ILLINSTADDR        0x058
  75 #define SDMA_CHN0ADDR           0x05c
  76 #define SDMA_ONCE_RTB           0x060
  77 #define SDMA_XTRIG_CONF1        0x070
  78 #define SDMA_XTRIG_CONF2        0x074
  79 #define SDMA_CHNENBL0_IMX35     0x200
  80 #define SDMA_CHNENBL0_IMX31     0x080
  81 #define SDMA_CHNPRI_0           0x100
  82
  83 /*
  84  * Buffer descriptor status values.
  85  */
  86 #define BD_DONE  0x01
  87 #define BD_WRAP  0x02
  88 #define BD_CONT  0x04
  89 #define BD_INTR  0x08
  90 #define BD_RROR  0x10
  91 #define BD_LAST  0x20
  92 #define BD_EXTD  0x80
  93
  94 /*
  95  * Data Node descriptor status values.
  96  */
  97 #define DND_END_OF_FRAME  0x80
  98 #define DND_END_OF_XFER   0x40
  99 #define DND_DONE          0x20
 100 #define DND_UNUSED        0x01
 101
 102 /*
 103  * IPCV2 descriptor status values.
 104  */
 105 #define BD_IPCV2_END_OF_FRAME  0x40
 106
 107 #define IPCV2_MAX_NODES        50
 108 /*
 109  * Error bit set in the CCB status field by the SDMA,
 110  * in setbd routine, in case of a transfer error
 111  */
 112 #define DATA_ERROR  0x10000000
 113
 114 /*
 115  * Buffer descriptor commands.
 116  */
 117 #define C0_ADDR             0x01
 118 #define C0_LOAD             0x02
 119 #define C0_DUMP             0x03
 120 #define C0_SETCTX           0x07
 121 #define C0_GETCTX           0x03
 122 #define C0_SETDM            0x01
 123 #define C0_SETPM            0x04
 124 #define C0_GETDM            0x02
 125 #define C0_GETPM            0x08
 126 /*
 127  * Change endianness indicator in the BD command field
 128  */
 129 #define CHANGE_ENDIANNESS   0x80
 130
 131 /*
 132  *  p_2_p watermark_level description
 133  *      Bits            Name                    Description
 134  *      0-7             Lower WML               Lower watermark level
 135  *      8               PS                      1: Pad Swallowing
 136  *                                              0: No Pad Swallowing
 137  *      9               PA                      1: Pad Adding
 138  *                                              0: No Pad Adding
 139  *      10              SPDIF                   If this bit is set both source
 140  *                                              and destination are on SPBA
 141  *      11              Source Bit(SP)          1: Source on SPBA
 142  *                                              0: Source on AIPS
 143  *      12              Destination Bit(DP)     1: Destination on SPBA
 144  *                                              0: Destination on AIPS
 145  *      13-15           ---------               MUST BE 0
 146  *      16-23           Higher WML              HWML
 147  *      24-27           N                       Total number of samples after
 148  *                                              which Pad adding/Swallowing
 149  *                                              must be done. It must be odd.
 150  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 151  *                                              LWML event mask
 152  *                                              0: LWE in EVENTS register
 153  *                                              1: LWE in EVENTS2 register
 154  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 155  *                                              HWML event mask
 156  *                                              0: HWE in EVENTS register
 157  *                                              1: HWE in EVENTS2 register
 158  *      30              ---------               MUST BE 0
 159  *      31              CONT                    1: Amount of samples to be
 160  *                                              transferred is unknown and
 161  *                                              script will keep on
 162  *                                              transferring samples as long as
 163  *                                              both events are detected and
 164  *                                              script must be manually stopped
 165  *                                              by the application
 166  *                                              0: The amount of samples to be
 167  *                                              transferred is equal to the
 168  *                                              count field of mode word
 169  */
 170 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 171 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 172 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 173 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 174 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 175 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 176 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 177 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 178 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 179 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 180
 181 /*
 182  * Mode/Count of data node descriptors - IPCv2
 183  */
 184 struct sdma_mode_count {
 185         u32 count   : 16; /* size of the buffer pointed by this BD */
 186         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 187         u32 command :  8; /* command mostlky used for channel 0 */
 188 };
 189
 190 /*
 191  * Buffer descriptor
 192  */
 193 struct sdma_buffer_descriptor {
 194         struct sdma_mode_count  mode;
 195         u32 buffer_addr;        /* address of the buffer described */
 196         u32 ext_buffer_addr;    /* extended buffer address */
 197 } __attribute__ ((packed));
 198
 199 /**
 200  * struct sdma_channel_control - Channel control Block
 201  *
 202  * @current_bd_ptr      current buffer descriptor processed
 203  * @base_bd_ptr         first element of buffer descriptor array
 204  * @unused              padding. The SDMA engine expects an array of 128 byte
 205  *                      control blocks
 206  */
 207 struct sdma_channel_control {
 208         u32 current_bd_ptr;
 209         u32 base_bd_ptr;
 210         u32 unused[2];
 211 } __attribute__ ((packed));
 212
 213 /**
 214  * struct sdma_state_registers - SDMA context for a channel
 215  *
 216  * @pc:         program counter
 217  * @t:          test bit: status of arithmetic & test instruction
 218  * @rpc:        return program counter
 219  * @sf:         source fault while loading data
 220  * @spc:        loop start program counter
 221  * @df:         destination fault while storing data
 222  * @epc:        loop end program counter
 223  * @lm:         loop mode
 224  */
 225 struct sdma_state_registers {
 226         u32 pc     :14;
 227         u32 unused1: 1;
 228         u32 t      : 1;
 229         u32 rpc    :14;
 230         u32 unused0: 1;
 231         u32 sf     : 1;
 232         u32 spc    :14;
 233         u32 unused2: 1;
 234         u32 df     : 1;
 235         u32 epc    :14;
 236         u32 lm     : 2;
 237 } __attribute__ ((packed));
 238
 239 /**
 240  * struct sdma_context_data - sdma context specific to a channel
 241  *
 242  * @channel_state:      channel state bits
 243  * @gReg:               general registers
 244  * @mda:                burst dma destination address register
 245  * @msa:                burst dma source address register
 246  * @ms:                 burst dma status register
 247  * @md:                 burst dma data register
 248  * @pda:                peripheral dma destination address register
 249  * @psa:                peripheral dma source address register
 250  * @ps:                 peripheral dma status register
 251  * @pd:                 peripheral dma data register
 252  * @ca:                 CRC polynomial register
 253  * @cs:                 CRC accumulator register
 254  * @dda:                dedicated core destination address register
 255  * @dsa:                dedicated core source address register
 256  * @ds:                 dedicated core status register
 257  * @dd:                 dedicated core data register
 258  */
 259 struct sdma_context_data {
 260         struct sdma_state_registers  channel_state;
 261         u32  gReg[8];
 262         u32  mda;
 263         u32  msa;
 264         u32  ms;
 265         u32  md;
 266         u32  pda;
 267         u32  psa;
 268         u32  ps;
 269         u32  pd;
 270         u32  ca;
 271         u32  cs;
 272         u32  dda;
 273         u32  dsa;
 274         u32  ds;
 275         u32  dd;
 276         u32  scratch0;
 277         u32  scratch1;
 278         u32  scratch2;
 279         u32  scratch3;
 280         u32  scratch4;
 281         u32  scratch5;
 282         u32  scratch6;
 283         u32  scratch7;
 284 } __attribute__ ((packed));
 285
 286 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 287
 288 struct sdma_engine;
 289
 290 /**
 291  * struct sdma_channel - housekeeping for a SDMA channel
 292  *
 293  * @sdma                pointer to the SDMA engine for this channel
 294  * @channel             the channel number, matches dmaengine chan_id + 1
 295  * @direction           transfer type. Needed for setting SDMA script
 296  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 297  * @event_id0           aka dma request line
 298  * @event_id1           for channels that use 2 events
 299  * @word_size           peripheral access size
 300  * @buf_tail            ID of the buffer that was processed
 301  * @num_bd              max NUM_BD. number of descriptors currently handling
 302  */
 303 struct sdma_channel {
 304         struct sdma_engine              *sdma;
 305         unsigned int                    channel;
 306         enum dma_transfer_direction             direction;
 307         enum sdma_peripheral_type       peripheral_type;
 308         unsigned int                    event_id0;
 309         unsigned int                    event_id1;
 310         enum dma_slave_buswidth         word_size;
 311         unsigned int                    buf_tail;
 312         unsigned int                    num_bd;
 313         unsigned int                    period_len;
 314         struct sdma_buffer_descriptor   *bd;
 315         dma_addr_t                      bd_phys;
 316         unsigned int                    pc_from_device, pc_to_device;
 317         unsigned int                    device_to_device;
 318         unsigned long                   flags;
 319         dma_addr_t                      per_address, per_address2;
 320         unsigned long                   event_mask[2];
 321         unsigned long                   watermark_level;
 322         u32                             shp_addr, per_addr;
 323         struct dma_chan                 chan;
 324         spinlock_t                      lock;
 325         struct dma_async_tx_descriptor  desc;
 326         enum dma_status                 status;
 327         unsigned int                    chn_count;
 328         unsigned int                    chn_real_count;
 329         struct tasklet_struct           tasklet;
 330         struct imx_dma_data             data;
 331 };
 332
 333 #define IMX_DMA_SG_LOOP         BIT(0)
 334
 335 #define MAX_DMA_CHANNELS 32
 336 #define MXC_SDMA_DEFAULT_PRIORITY 1
 337 #define MXC_SDMA_MIN_PRIORITY 1
 338 #define MXC_SDMA_MAX_PRIORITY 7
 339
 340 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 341
 342 /**
 343  * struct sdma_firmware_header - Layout of the firmware image
 344  *
 345  * @magic               "SDMA"
 346  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 347  *                      changes.
 348  * @version_minor       firmware minor version (for binary compatible changes)
 349  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 350  * @num_script_addrs    Number of script addresses in this image
 351  * @ram_code_start      offset of SDMA ram image in this firmware image
 352  * @ram_code_size       size of SDMA ram image
 353  * @script_addrs        Stores the start address of the SDMA scripts
 354  *                      (in SDMA memory space)
 355  */
 356 struct sdma_firmware_header {
 357         u32     magic;
 358         u32     version_major;
 359         u32     version_minor;
 360         u32     script_addrs_start;
 361         u32     num_script_addrs;
 362         u32     ram_code_start;
 363         u32     ram_code_size;
 364 };
 365
 366 struct sdma_driver_data {
 367         int chnenbl0;
 368         int num_events;
 369         struct sdma_script_start_addrs  *script_addrs;
 370 };
 371
 372 struct sdma_engine {
 373         struct device                   *dev;
 374         struct device_dma_parameters    dma_parms;
 375         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 376         struct sdma_channel_control     *channel_control;
 377         void __iomem                    *regs;
 378         struct sdma_context_data        *context;
 379         dma_addr_t                      context_phys;
 380         struct dma_device               dma_device;
 381         struct clk                      *clk_ipg;
 382         struct clk                      *clk_ahb;
 383         spinlock_t                      channel_0_lock;
 384         u32                             script_number;
 385         struct sdma_script_start_addrs  *script_addrs;
 386         const struct sdma_driver_data   *drvdata;
 387         u32                             spba_start_addr;
 388         u32                             spba_end_addr;
 389 };
 390
 391 static struct sdma_driver_data sdma_imx31 = {
 392         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 393         .num_events = 32,
 394 };
 395
 396 static struct sdma_script_start_addrs sdma_script_imx25 = {
 397         .ap_2_ap_addr = 729,
 398         .uart_2_mcu_addr = 904,
 399         .per_2_app_addr = 1255,
 400         .mcu_2_app_addr = 834,
 401         .uartsh_2_mcu_addr = 1120,
 402         .per_2_shp_addr = 1329,
 403         .mcu_2_shp_addr = 1048,
 404         .ata_2_mcu_addr = 1560,
 405         .mcu_2_ata_addr = 1479,
 406         .app_2_per_addr = 1189,
 407         .app_2_mcu_addr = 770,
 408         .shp_2_per_addr = 1407,
 409         .shp_2_mcu_addr = 979,
 410 };
 411
 412 static struct sdma_driver_data sdma_imx25 = {
 413         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 414         .num_events = 48,
 415         .script_addrs = &sdma_script_imx25,
 416 };
 417
 418 static struct sdma_driver_data sdma_imx35 = {
 419         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 420         .num_events = 48,
 421 };
 422
 423 static struct sdma_script_start_addrs sdma_script_imx51 = {
 424         .ap_2_ap_addr = 642,
 425         .uart_2_mcu_addr = 817,
 426         .mcu_2_app_addr = 747,
 427         .mcu_2_shp_addr = 961,
 428         .ata_2_mcu_addr = 1473,
 429         .mcu_2_ata_addr = 1392,
 430         .app_2_per_addr = 1033,
 431         .app_2_mcu_addr = 683,
 432         .shp_2_per_addr = 1251,
 433         .shp_2_mcu_addr = 892,
 434 };
 435
 436 static struct sdma_driver_data sdma_imx51 = {
 437         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 438         .num_events = 48,
 439         .script_addrs = &sdma_script_imx51,
 440 };
 441
 442 static struct sdma_script_start_addrs sdma_script_imx53 = {
 443         .ap_2_ap_addr = 642,
 444         .app_2_mcu_addr = 683,
 445         .mcu_2_app_addr = 747,
 446         .uart_2_mcu_addr = 817,
 447         .shp_2_mcu_addr = 891,
 448         .mcu_2_shp_addr = 960,
 449         .uartsh_2_mcu_addr = 1032,
 450         .spdif_2_mcu_addr = 1100,
 451         .mcu_2_spdif_addr = 1134,
 452         .firi_2_mcu_addr = 1193,
 453         .mcu_2_firi_addr = 1290,
 454 };
 455
 456 static struct sdma_driver_data sdma_imx53 = {
 457         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 458         .num_events = 48,
 459         .script_addrs = &sdma_script_imx53,
 460 };
 461
 462 static struct sdma_script_start_addrs sdma_script_imx6q = {
 463         .ap_2_ap_addr = 642,
 464         .uart_2_mcu_addr = 817,
 465         .mcu_2_app_addr = 747,
 466         .per_2_per_addr = 6331,
 467         .uartsh_2_mcu_addr = 1032,
 468         .mcu_2_shp_addr = 960,
 469         .app_2_mcu_addr = 683,
 470         .shp_2_mcu_addr = 891,
 471         .spdif_2_mcu_addr = 1100,
 472         .mcu_2_spdif_addr = 1134,
 473 };
 474
 475 static struct sdma_driver_data sdma_imx6q = {
 476         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 477         .num_events = 48,
 478         .script_addrs = &sdma_script_imx6q,
 479 };
 480
 481 static const struct platform_device_id sdma_devtypes[] = {
 482         {
 483                 .name = "imx25-sdma",
 484                 .driver_data = (unsigned long)&sdma_imx25,
 485         }, {
 486                 .name = "imx31-sdma",
 487                 .driver_data = (unsigned long)&sdma_imx31,
 488         }, {
 489                 .name = "imx35-sdma",
 490                 .driver_data = (unsigned long)&sdma_imx35,
 491         }, {
 492                 .name = "imx51-sdma",
 493                 .driver_data = (unsigned long)&sdma_imx51,
 494         }, {
 495                 .name = "imx53-sdma",
 496                 .driver_data = (unsigned long)&sdma_imx53,
 497         }, {
 498                 .name = "imx6q-sdma",
 499                 .driver_data = (unsigned long)&sdma_imx6q,
 500         }, {
 501                 /* sentinel */
 502         }
 503 };
 504 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 505
 506 static const struct of_device_id sdma_dt_ids[] = {
 507         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 508         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 509         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 510         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 511         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 512         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 513         { /* sentinel */ }
 514 };
 515 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 516
 517 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 518 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 519 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 520 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 521
 522 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 523 {
 524         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 525         return chnenbl0 + event * 4;
 526 }
 527
 528 static int sdma_config_ownership(struct sdma_channel *sdmac,
 529                 bool event_override, bool mcu_override, bool dsp_override)
 530 {
 531         struct sdma_engine *sdma = sdmac->sdma;
 532         int channel = sdmac->channel;
 533         unsigned long evt, mcu, dsp;
 534
 535         if (event_override && mcu_override && dsp_override)
 536                 return -EINVAL;
 537
 538         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 539         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 540         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 541
 542         if (dsp_override)
 543                 __clear_bit(channel, &dsp);
 544         else
 545                 __set_bit(channel, &dsp);
 546
 547         if (event_override)
 548                 __clear_bit(channel, &evt);
 549         else
 550                 __set_bit(channel, &evt);
 551
 552         if (mcu_override)
 553                 __clear_bit(channel, &mcu);
 554         else
 555                 __set_bit(channel, &mcu);
 556
 557         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 558         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 559         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 560
 561         return 0;
 562 }
 563
 564 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 565 {
 566         writel(BIT(channel), sdma->regs + SDMA_H_START);
 567 }
 568
 569 /*
 570  * sdma_run_channel0 - run a channel and wait till it's done
 571  */
 572 static int sdma_run_channel0(struct sdma_engine *sdma)
 573 {
 574         int ret;
 575         u32 reg;
 576
 577         sdma_enable_channel(sdma, 0);
 578
 579         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 580                                                 reg, !(reg & 1), 1, 500);
 581         if (ret)
 582                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 583
 584         /* Set bits of CONFIG register with dynamic context switching */
 585         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 586                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 587
 588         return ret;
 589 }
 590
 591 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 592                 u32 address)
 593 {
 594         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 595         void *buf_virt;
 596         dma_addr_t buf_phys;
 597         int ret;
 598         unsigned long flags;
 599
 600         buf_virt = dma_alloc_coherent(NULL,
 601                         size,
 602                         &buf_phys, GFP_KERNEL);
 603         if (!buf_virt) {
 604                 return -ENOMEM;
 605         }
 606
 607         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 608
 609         bd0->mode.command = C0_SETPM;
 610         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 611         bd0->mode.count = size / 2;
 612         bd0->buffer_addr = buf_phys;
 613         bd0->ext_buffer_addr = address;
 614
 615         memcpy(buf_virt, buf, size);
 616
 617         ret = sdma_run_channel0(sdma);
 618
 619         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 620
 621         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 622
 623         return ret;
 624 }
 625
 626 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 627 {
 628         struct sdma_engine *sdma = sdmac->sdma;
 629         int channel = sdmac->channel;
 630         unsigned long val;
 631         u32 chnenbl = chnenbl_ofs(sdma, event);
 632
 633         val = readl_relaxed(sdma->regs + chnenbl);
 634         __set_bit(channel, &val);
 635         writel_relaxed(val, sdma->regs + chnenbl);
 636 }
 637
 638 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 639 {
 640         struct sdma_engine *sdma = sdmac->sdma;
 641         int channel = sdmac->channel;
 642         u32 chnenbl = chnenbl_ofs(sdma, event);
 643         unsigned long val;
 644
 645         val = readl_relaxed(sdma->regs + chnenbl);
 646         __clear_bit(channel, &val);
 647         writel_relaxed(val, sdma->regs + chnenbl);
 648 }
 649
 650 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 651 {
 652         if (sdmac->desc.callback)
 653                 sdmac->desc.callback(sdmac->desc.callback_param);
 654 }
 655
 656 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 657 {
 658         struct sdma_buffer_descriptor *bd;
 659
 660         /*
 661          * loop mode. Iterate over descriptors, re-setup them and
 662          * call callback function.
 663          */
 664         while (1) {
 665                 bd = &sdmac->bd[sdmac->buf_tail];
 666
 667                 if (bd->mode.status & BD_DONE)
 668                         break;
 669
 670                 if (bd->mode.status & BD_RROR)
 671                         sdmac->status = DMA_ERROR;
 672
 673                 bd->mode.status |= BD_DONE;
 674                 sdmac->buf_tail++;
 675                 sdmac->buf_tail %= sdmac->num_bd;
 676         }
 677 }
 678
 679 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 680 {
 681         struct sdma_buffer_descriptor *bd;
 682         int i, error = 0;
 683
 684         sdmac->chn_real_count = 0;
 685         /*
 686          * non loop mode. Iterate over all descriptors, collect
 687          * errors and call callback function
 688          */
 689         for (i = 0; i < sdmac->num_bd; i++) {
 690                 bd = &sdmac->bd[i];
 691
 692                  if (bd->mode.status & (BD_DONE | BD_RROR))
 693                         error = -EIO;
 694                  sdmac->chn_real_count += bd->mode.count;
 695         }
 696
 697         if (error)
 698                 sdmac->status = DMA_ERROR;
 699         else
 700                 sdmac->status = DMA_COMPLETE;
 701
 702         dma_cookie_complete(&sdmac->desc);
 703         if (sdmac->desc.callback)
 704                 sdmac->desc.callback(sdmac->desc.callback_param);
 705 }
 706
 707 static void sdma_tasklet(unsigned long data)
 708 {
 709         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 710
 711         if (sdmac->flags & IMX_DMA_SG_LOOP)
 712                 sdma_handle_channel_loop(sdmac);
 713         else
 714                 mxc_sdma_handle_channel_normal(sdmac);
 715 }
 716
 717 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 718 {
 719         struct sdma_engine *sdma = dev_id;
 720         unsigned long stat;
 721
 722         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 723         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 724         /* channel 0 is special and not handled here, see run_channel0() */
 725         stat &= ~1;
 726
 727         while (stat) {
 728                 int channel = fls(stat) - 1;
 729                 struct sdma_channel *sdmac = &sdma->channel[channel];
 730
 731                 if (sdmac->flags & IMX_DMA_SG_LOOP)
 732                         sdma_update_channel_loop(sdmac);
 733
 734                 tasklet_schedule(&sdmac->tasklet);
 735
 736                 __clear_bit(channel, &stat);
 737         }
 738
 739         return IRQ_HANDLED;
 740 }
 741
 742 /*
 743  * sets the pc of SDMA script according to the peripheral type
 744  */
 745 static void sdma_get_pc(struct sdma_channel *sdmac,
 746                 enum sdma_peripheral_type peripheral_type)
 747 {
 748         struct sdma_engine *sdma = sdmac->sdma;
 749         int per_2_emi = 0, emi_2_per = 0;
 750         /*
 751          * These are needed once we start to support transfers between
 752          * two peripherals or memory-to-memory transfers
 753          */
 754         int per_2_per = 0, emi_2_emi = 0;
 755
 756         sdmac->pc_from_device = 0;
 757         sdmac->pc_to_device = 0;
 758         sdmac->device_to_device = 0;
 759
 760         switch (peripheral_type) {
 761         case IMX_DMATYPE_MEMORY:
 762                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 763                 break;
 764         case IMX_DMATYPE_DSP:
 765                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 766                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 767                 break;
 768         case IMX_DMATYPE_FIRI:
 769                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 770                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 771                 break;
 772         case IMX_DMATYPE_UART:
 773                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 774                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 775                 break;
 776         case IMX_DMATYPE_UART_SP:
 777                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 778                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 779                 break;
 780         case IMX_DMATYPE_ATA:
 781                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 782                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 783                 break;
 784         case IMX_DMATYPE_CSPI:
 785         case IMX_DMATYPE_EXT:
 786         case IMX_DMATYPE_SSI:
 787         case IMX_DMATYPE_SAI:
 788                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 789                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 790                 break;
 791         case IMX_DMATYPE_SSI_DUAL:
 792                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 793                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 794                 break;
 795         case IMX_DMATYPE_SSI_SP:
 796         case IMX_DMATYPE_MMC:
 797         case IMX_DMATYPE_SDHC:
 798         case IMX_DMATYPE_CSPI_SP:
 799         case IMX_DMATYPE_ESAI:
 800         case IMX_DMATYPE_MSHC_SP:
 801                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 802                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 803                 break;
 804         case IMX_DMATYPE_ASRC:
 805                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 806                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 807                 per_2_per = sdma->script_addrs->per_2_per_addr;
 808                 break;
 809         case IMX_DMATYPE_ASRC_SP:
 810                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 811                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 812                 per_2_per = sdma->script_addrs->per_2_per_addr;
 813                 break;
 814         case IMX_DMATYPE_MSHC:
 815                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 816                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 817                 break;
 818         case IMX_DMATYPE_CCM:
 819                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 820                 break;
 821         case IMX_DMATYPE_SPDIF:
 822                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 823                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 824                 break;
 825         case IMX_DMATYPE_IPU_MEMORY:
 826                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 827                 break;
 828         default:
 829                 break;
 830         }
 831
 832         sdmac->pc_from_device = per_2_emi;
 833         sdmac->pc_to_device = emi_2_per;
 834         sdmac->device_to_device = per_2_per;
 835 }
 836
 837 static int sdma_load_context(struct sdma_channel *sdmac)
 838 {
 839         struct sdma_engine *sdma = sdmac->sdma;
 840         int channel = sdmac->channel;
 841         int load_address;
 842         struct sdma_context_data *context = sdma->context;
 843         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 844         int ret;
 845         unsigned long flags;
 846
 847         if (sdmac->direction == DMA_DEV_TO_MEM)
 848                 load_address = sdmac->pc_from_device;
 849         else if (sdmac->direction == DMA_DEV_TO_DEV)
 850                 load_address = sdmac->device_to_device;
 851         else
 852                 load_address = sdmac->pc_to_device;
 853
 854         if (load_address < 0)
 855                 return load_address;
 856
 857         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 858         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 859         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 860         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 861         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 862         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 863
 864         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 865
 866         memset(context, 0, sizeof(*context));
 867         context->channel_state.pc = load_address;
 868
 869         /* Send by context the event mask,base address for peripheral
 870          * and watermark level
 871          */
 872         context->gReg[0] = sdmac->event_mask[1];
 873         context->gReg[1] = sdmac->event_mask[0];
 874         context->gReg[2] = sdmac->per_addr;
 875         context->gReg[6] = sdmac->shp_addr;
 876         context->gReg[7] = sdmac->watermark_level;
 877
 878         bd0->mode.command = C0_SETDM;
 879         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 880         bd0->mode.count = sizeof(*context) / 4;
 881         bd0->buffer_addr = sdma->context_phys;
 882         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 883         ret = sdma_run_channel0(sdma);
 884
 885         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 886
 887         return ret;
 888 }
 889
 890 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 891 {
 892         return container_of(chan, struct sdma_channel, chan);
 893 }
 894
 895 static int sdma_disable_channel(struct dma_chan *chan)
 896 {
 897         struct sdma_channel *sdmac = to_sdma_chan(chan);
 898         struct sdma_engine *sdma = sdmac->sdma;
 899         int channel = sdmac->channel;
 900
 901         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 902         sdmac->status = DMA_ERROR;
 903
 904         return 0;
 905 }
 906
 907 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
 908 {
 909         struct sdma_engine *sdma = sdmac->sdma;
 910
 911         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
 912         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
 913
 914         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
 915         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
 916
 917         if (sdmac->event_id0 > 31)
 918                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
 919
 920         if (sdmac->event_id1 > 31)
 921                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
 922
 923         /*
 924          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
 925          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
 926          * r0(event_mask[1]) and r1(event_mask[0]).
 927          */
 928         if (lwml > hwml) {
 929                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
 930                                                 SDMA_WATERMARK_LEVEL_HWML);
 931                 sdmac->watermark_level |= hwml;
 932                 sdmac->watermark_level |= lwml << 16;
 933                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
 934         }
 935
 936         if (sdmac->per_address2 >= sdma->spba_start_addr &&
 937                         sdmac->per_address2 <= sdma->spba_end_addr)
 938                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
 939
 940         if (sdmac->per_address >= sdma->spba_start_addr &&
 941                         sdmac->per_address <= sdma->spba_end_addr)
 942                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
 943
 944         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
 945 }
 946
 947 static int sdma_config_channel(struct dma_chan *chan)
 948 {
 949         struct sdma_channel *sdmac = to_sdma_chan(chan);
 950         int ret;
 951
 952         sdma_disable_channel(chan);
 953
 954         sdmac->event_mask[0] = 0;
 955         sdmac->event_mask[1] = 0;
 956         sdmac->shp_addr = 0;
 957         sdmac->per_addr = 0;
 958
 959         if (sdmac->event_id0) {
 960                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 961                         return -EINVAL;
 962                 sdma_event_enable(sdmac, sdmac->event_id0);
 963         }
 964
 965         if (sdmac->event_id1) {
 966                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
 967                         return -EINVAL;
 968                 sdma_event_enable(sdmac, sdmac->event_id1);
 969         }
 970
 971         switch (sdmac->peripheral_type) {
 972         case IMX_DMATYPE_DSP:
 973                 sdma_config_ownership(sdmac, false, true, true);
 974                 break;
 975         case IMX_DMATYPE_MEMORY:
 976                 sdma_config_ownership(sdmac, false, true, false);
 977                 break;
 978         default:
 979                 sdma_config_ownership(sdmac, true, true, false);
 980                 break;
 981         }
 982
 983         sdma_get_pc(sdmac, sdmac->peripheral_type);
 984
 985         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 986                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 987                 /* Handle multiple event channels differently */
 988                 if (sdmac->event_id1) {
 989                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
 990                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
 991                                 sdma_set_watermarklevel_for_p2p(sdmac);
 992                 } else
 993                         __set_bit(sdmac->event_id0, sdmac->event_mask);
 994
 995                 /* Watermark Level */
 996                 sdmac->watermark_level |= sdmac->watermark_level;
 997                 /* Address */
 998                 sdmac->shp_addr = sdmac->per_address;
 999                 sdmac->per_addr = sdmac->per_address2;
1000         } else {
1001                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1002         }
1003
1004         ret = sdma_load_context(sdmac);
1005
1006         return ret;
1007 }
1008
1009 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1010                 unsigned int priority)
1011 {
1012         struct sdma_engine *sdma = sdmac->sdma;
1013         int channel = sdmac->channel;
1014
1015         if (priority < MXC_SDMA_MIN_PRIORITY
1016             || priority > MXC_SDMA_MAX_PRIORITY) {
1017                 return -EINVAL;
1018         }
1019
1020         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1021
1022         return 0;
1023 }
1024
1025 static int sdma_request_channel(struct sdma_channel *sdmac)
1026 {
1027         struct sdma_engine *sdma = sdmac->sdma;
1028         int channel = sdmac->channel;
1029         int ret = -EBUSY;
1030
1031         sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1032                                         GFP_KERNEL);
1033         if (!sdmac->bd) {
1034                 ret = -ENOMEM;
1035                 goto out;
1036         }
1037
1038         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1039         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1040
1041         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1042         return 0;
1043 out:
1044
1045         return ret;
1046 }
1047
1048 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1049 {
1050         unsigned long flags;
1051         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1052         dma_cookie_t cookie;
1053
1054         spin_lock_irqsave(&sdmac->lock, flags);
1055
1056         cookie = dma_cookie_assign(tx);
1057
1058         spin_unlock_irqrestore(&sdmac->lock, flags);
1059
1060         return cookie;
1061 }
1062
1063 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1064 {
1065         struct sdma_channel *sdmac = to_sdma_chan(chan);
1066         struct imx_dma_data *data = chan->private;
1067         int prio, ret;
1068
1069         if (!data)
1070                 return -EINVAL;
1071
1072         switch (data->priority) {
1073         case DMA_PRIO_HIGH:
1074                 prio = 3;
1075                 break;
1076         case DMA_PRIO_MEDIUM:
1077                 prio = 2;
1078                 break;
1079         case DMA_PRIO_LOW:
1080         default:
1081                 prio = 1;
1082                 break;
1083         }
1084
1085         sdmac->peripheral_type = data->peripheral_type;
1086         sdmac->event_id0 = data->dma_request;
1087         sdmac->event_id1 = data->dma_request2;
1088
1089         ret = clk_enable(sdmac->sdma->clk_ipg);
1090         if (ret)
1091                 return ret;
1092         ret = clk_enable(sdmac->sdma->clk_ahb);
1093         if (ret)
1094                 goto disable_clk_ipg;
1095
1096         ret = sdma_request_channel(sdmac);
1097         if (ret)
1098                 goto disable_clk_ahb;
1099
1100         ret = sdma_set_channel_priority(sdmac, prio);
1101         if (ret)
1102                 goto disable_clk_ahb;
1103
1104         dma_async_tx_descriptor_init(&sdmac->desc, chan);
1105         sdmac->desc.tx_submit = sdma_tx_submit;
1106         /* txd.flags will be overwritten in prep funcs */
1107         sdmac->desc.flags = DMA_CTRL_ACK;
1108
1109         return 0;
1110
1111 disable_clk_ahb:
1112         clk_disable(sdmac->sdma->clk_ahb);
1113 disable_clk_ipg:
1114         clk_disable(sdmac->sdma->clk_ipg);
1115         return ret;
1116 }
1117
1118 static void sdma_free_chan_resources(struct dma_chan *chan)
1119 {
1120         struct sdma_channel *sdmac = to_sdma_chan(chan);
1121         struct sdma_engine *sdma = sdmac->sdma;
1122
1123         sdma_disable_channel(chan);
1124
1125         if (sdmac->event_id0)
1126                 sdma_event_disable(sdmac, sdmac->event_id0);
1127         if (sdmac->event_id1)
1128                 sdma_event_disable(sdmac, sdmac->event_id1);
1129
1130         sdmac->event_id0 = 0;
1131         sdmac->event_id1 = 0;
1132
1133         sdma_set_channel_priority(sdmac, 0);
1134
1135         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1136
1137         clk_disable(sdma->clk_ipg);
1138         clk_disable(sdma->clk_ahb);
1139 }
1140
1141 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1142                 struct dma_chan *chan, struct scatterlist *sgl,
1143                 unsigned int sg_len, enum dma_transfer_direction direction,
1144                 unsigned long flags, void *context)
1145 {
1146         struct sdma_channel *sdmac = to_sdma_chan(chan);
1147         struct sdma_engine *sdma = sdmac->sdma;
1148         int ret, i, count;
1149         int channel = sdmac->channel;
1150         struct scatterlist *sg;
1151
1152         if (sdmac->status == DMA_IN_PROGRESS)
1153                 return NULL;
1154         sdmac->status = DMA_IN_PROGRESS;
1155
1156         sdmac->flags = 0;
1157
1158         sdmac->buf_tail = 0;
1159
1160         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1161                         sg_len, channel);
1162
1163         sdmac->direction = direction;
1164         ret = sdma_load_context(sdmac);
1165         if (ret)
1166                 goto err_out;
1167
1168         if (sg_len > NUM_BD) {
1169                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1170                                 channel, sg_len, NUM_BD);
1171                 ret = -EINVAL;
1172                 goto err_out;
1173         }
1174
1175         sdmac->chn_count = 0;
1176         for_each_sg(sgl, sg, sg_len, i) {
1177                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1178                 int param;
1179
1180                 bd->buffer_addr = sg->dma_address;
1181
1182                 count = sg_dma_len(sg);
1183
1184                 if (count > 0xffff) {
1185                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1186                                         channel, count, 0xffff);
1187                         ret = -EINVAL;
1188                         goto err_out;
1189                 }
1190
1191                 bd->mode.count = count;
1192                 sdmac->chn_count += count;
1193
1194                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1195                         ret =  -EINVAL;
1196                         goto err_out;
1197                 }
1198
1199                 switch (sdmac->word_size) {
1200                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1201                         bd->mode.command = 0;
1202                         if (count & 3 || sg->dma_address & 3)
1203                                 return NULL;
1204                         break;
1205                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1206                         bd->mode.command = 2;
1207                         if (count & 1 || sg->dma_address & 1)
1208                                 return NULL;
1209                         break;
1210                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1211                         bd->mode.command = 1;
1212                         break;
1213                 default:
1214                         return NULL;
1215                 }
1216
1217                 param = BD_DONE | BD_EXTD | BD_CONT;
1218
1219                 if (i + 1 == sg_len) {
1220                         param |= BD_INTR;
1221                         param |= BD_LAST;
1222                         param &= ~BD_CONT;
1223                 }
1224
1225                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1226                                 i, count, (u64)sg->dma_address,
1227                                 param & BD_WRAP ? "wrap" : "",
1228                                 param & BD_INTR ? " intr" : "");
1229
1230                 bd->mode.status = param;
1231         }
1232
1233         sdmac->num_bd = sg_len;
1234         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1235
1236         return &sdmac->desc;
1237 err_out:
1238         sdmac->status = DMA_ERROR;
1239         return NULL;
1240 }
1241
1242 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1243                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1244                 size_t period_len, enum dma_transfer_direction direction,
1245                 unsigned long flags)
1246 {
1247         struct sdma_channel *sdmac = to_sdma_chan(chan);
1248         struct sdma_engine *sdma = sdmac->sdma;
1249         int num_periods = buf_len / period_len;
1250         int channel = sdmac->channel;
1251         int ret, i = 0, buf = 0;
1252
1253         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1254
1255         if (sdmac->status == DMA_IN_PROGRESS)
1256                 return NULL;
1257
1258         sdmac->status = DMA_IN_PROGRESS;
1259
1260         sdmac->buf_tail = 0;
1261         sdmac->period_len = period_len;
1262
1263         sdmac->flags |= IMX_DMA_SG_LOOP;
1264         sdmac->direction = direction;
1265         ret = sdma_load_context(sdmac);
1266         if (ret)
1267                 goto err_out;
1268
1269         if (num_periods > NUM_BD) {
1270                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1271                                 channel, num_periods, NUM_BD);
1272                 goto err_out;
1273         }
1274
1275         if (period_len > 0xffff) {
1276                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1277                                 channel, period_len, 0xffff);
1278                 goto err_out;
1279         }
1280
1281         while (buf < buf_len) {
1282                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1283                 int param;
1284
1285                 bd->buffer_addr = dma_addr;
1286
1287                 bd->mode.count = period_len;
1288
1289                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1290                         goto err_out;
1291                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1292                         bd->mode.command = 0;
1293                 else
1294                         bd->mode.command = sdmac->word_size;
1295
1296                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1297                 if (i + 1 == num_periods)
1298                         param |= BD_WRAP;
1299
1300                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1301                                 i, period_len, (u64)dma_addr,
1302                                 param & BD_WRAP ? "wrap" : "",
1303                                 param & BD_INTR ? " intr" : "");
1304
1305                 bd->mode.status = param;
1306
1307                 dma_addr += period_len;
1308                 buf += period_len;
1309
1310                 i++;
1311         }
1312
1313         sdmac->num_bd = num_periods;
1314         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1315
1316         return &sdmac->desc;
1317 err_out:
1318         sdmac->status = DMA_ERROR;
1319         return NULL;
1320 }
1321
1322 static int sdma_config(struct dma_chan *chan,
1323                        struct dma_slave_config *dmaengine_cfg)
1324 {
1325         struct sdma_channel *sdmac = to_sdma_chan(chan);
1326
1327         if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1328                 sdmac->per_address = dmaengine_cfg->src_addr;
1329                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1330                         dmaengine_cfg->src_addr_width;
1331                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1332         } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1333                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1334                 sdmac->per_address = dmaengine_cfg->dst_addr;
1335                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1336                         SDMA_WATERMARK_LEVEL_LWML;
1337                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1338                         SDMA_WATERMARK_LEVEL_HWML;
1339                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1340         } else {
1341                 sdmac->per_address = dmaengine_cfg->dst_addr;
1342                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1343                         dmaengine_cfg->dst_addr_width;
1344                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1345         }
1346         sdmac->direction = dmaengine_cfg->direction;
1347         return sdma_config_channel(chan);
1348 }
1349
1350 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1351                                       dma_cookie_t cookie,
1352                                       struct dma_tx_state *txstate)
1353 {
1354         struct sdma_channel *sdmac = to_sdma_chan(chan);
1355         u32 residue;
1356
1357         if (sdmac->flags & IMX_DMA_SG_LOOP)
1358                 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1359         else
1360                 residue = sdmac->chn_count - sdmac->chn_real_count;
1361
1362         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1363                          residue);
1364
1365         return sdmac->status;
1366 }
1367
1368 static void sdma_issue_pending(struct dma_chan *chan)
1369 {
1370         struct sdma_channel *sdmac = to_sdma_chan(chan);
1371         struct sdma_engine *sdma = sdmac->sdma;
1372
1373         if (sdmac->status == DMA_IN_PROGRESS)
1374                 sdma_enable_channel(sdma, sdmac->channel);
1375 }
1376
1377 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1378 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1379 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1380
1381 static void sdma_add_scripts(struct sdma_engine *sdma,
1382                 const struct sdma_script_start_addrs *addr)
1383 {
1384         s32 *addr_arr = (u32 *)addr;
1385         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1386         int i;
1387
1388         /* use the default firmware in ROM if missing external firmware */
1389         if (!sdma->script_number)
1390                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1391
1392         for (i = 0; i < sdma->script_number; i++)
1393                 if (addr_arr[i] > 0)
1394                         saddr_arr[i] = addr_arr[i];
1395 }
1396
1397 static void sdma_load_firmware(const struct firmware *fw, void *context)
1398 {
1399         struct sdma_engine *sdma = context;
1400         const struct sdma_firmware_header *header;
1401         const struct sdma_script_start_addrs *addr;
1402         unsigned short *ram_code;
1403
1404         if (!fw) {
1405                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1406                 /* In this case we just use the ROM firmware. */
1407                 return;
1408         }
1409
1410         if (fw->size < sizeof(*header))
1411                 goto err_firmware;
1412
1413         header = (struct sdma_firmware_header *)fw->data;
1414
1415         if (header->magic != SDMA_FIRMWARE_MAGIC)
1416                 goto err_firmware;
1417         if (header->ram_code_start + header->ram_code_size > fw->size)
1418                 goto err_firmware;
1419         switch (header->version_major) {
1420         case 1:
1421                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1422                 break;
1423         case 2:
1424                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1425                 break;
1426         case 3:
1427                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1428                 break;
1429         default:
1430                 dev_err(sdma->dev, "unknown firmware version\n");
1431                 goto err_firmware;
1432         }
1433
1434         addr = (void *)header + header->script_addrs_start;
1435         ram_code = (void *)header + header->ram_code_start;
1436
1437         clk_enable(sdma->clk_ipg);
1438         clk_enable(sdma->clk_ahb);
1439         /* download the RAM image for SDMA */
1440         sdma_load_script(sdma, ram_code,
1441                         header->ram_code_size,
1442                         addr->ram_code_start_addr);
1443         clk_disable(sdma->clk_ipg);
1444         clk_disable(sdma->clk_ahb);
1445
1446         sdma_add_scripts(sdma, addr);
1447
1448         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1449                         header->version_major,
1450                         header->version_minor);
1451
1452 err_firmware:
1453         release_firmware(fw);
1454 }
1455
1456 #define EVENT_REMAP_CELLS 3
1457
1458 static int sdma_event_remap(struct sdma_engine *sdma)
1459 {
1460         struct device_node *np = sdma->dev->of_node;
1461         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1462         struct property *event_remap;
1463         struct regmap *gpr;
1464         char propname[] = "fsl,sdma-event-remap";
1465         u32 reg, val, shift, num_map, i;
1466         int ret = 0;
1467
1468         if (IS_ERR(np) || IS_ERR(gpr_np))
1469                 goto out;
1470
1471         event_remap = of_find_property(np, propname, NULL);
1472         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1473         if (!num_map) {
1474                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1475                 goto out;
1476         } else if (num_map % EVENT_REMAP_CELLS) {
1477                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1478                                 propname, EVENT_REMAP_CELLS);
1479                 ret = -EINVAL;
1480                 goto out;
1481         }
1482
1483         gpr = syscon_node_to_regmap(gpr_np);
1484         if (IS_ERR(gpr)) {
1485                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1486                 ret = PTR_ERR(gpr);
1487                 goto out;
1488         }
1489
1490         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1491                 ret = of_property_read_u32_index(np, propname, i, &reg);
1492                 if (ret) {
1493                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1494                                         propname, i);
1495                         goto out;
1496                 }
1497
1498                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1499                 if (ret) {
1500                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1501                                         propname, i + 1);
1502                         goto out;
1503                 }
1504
1505                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1506                 if (ret) {
1507                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1508                                         propname, i + 2);
1509                         goto out;
1510                 }
1511
1512                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1513         }
1514
1515 out:
1516         if (!IS_ERR(gpr_np))
1517                 of_node_put(gpr_np);
1518
1519         return ret;
1520 }
1521
1522 static int sdma_get_firmware(struct sdma_engine *sdma,
1523                 const char *fw_name)
1524 {
1525         int ret;
1526
1527         ret = request_firmware_nowait(THIS_MODULE,
1528                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1529                         GFP_KERNEL, sdma, sdma_load_firmware);
1530
1531         return ret;
1532 }
1533
1534 static int sdma_init(struct sdma_engine *sdma)
1535 {
1536         int i, ret;
1537         dma_addr_t ccb_phys;
1538
1539         ret = clk_enable(sdma->clk_ipg);
1540         if (ret)
1541                 return ret;
1542         ret = clk_enable(sdma->clk_ahb);
1543         if (ret)
1544                 goto disable_clk_ipg;
1545
1546         /* Be sure SDMA has not started yet */
1547         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1548
1549         sdma->channel_control = dma_alloc_coherent(NULL,
1550                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1551                         sizeof(struct sdma_context_data),
1552                         &ccb_phys, GFP_KERNEL);
1553
1554         if (!sdma->channel_control) {
1555                 ret = -ENOMEM;
1556                 goto err_dma_alloc;
1557         }
1558
1559         sdma->context = (void *)sdma->channel_control +
1560                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1561         sdma->context_phys = ccb_phys +
1562                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1563
1564         /* Zero-out the CCB structures array just allocated */
1565         memset(sdma->channel_control, 0,
1566                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1567
1568         /* disable all channels */
1569         for (i = 0; i < sdma->drvdata->num_events; i++)
1570                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1571
1572         /* All channels have priority 0 */
1573         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1574                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1575
1576         ret = sdma_request_channel(&sdma->channel[0]);
1577         if (ret)
1578                 goto err_dma_alloc;
1579
1580         sdma_config_ownership(&sdma->channel[0], false, true, false);
1581
1582         /* Set Command Channel (Channel Zero) */
1583         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1584
1585         /* Set bits of CONFIG register but with static context switching */
1586         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1587         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1588
1589         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1590
1591         /* Initializes channel's priorities */
1592         sdma_set_channel_priority(&sdma->channel[0], 7);
1593
1594         clk_disable(sdma->clk_ipg);
1595         clk_disable(sdma->clk_ahb);
1596
1597         return 0;
1598
1599 err_dma_alloc:
1600         clk_disable(sdma->clk_ahb);
1601 disable_clk_ipg:
1602         clk_disable(sdma->clk_ipg);
1603         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1604         return ret;
1605 }
1606
1607 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1608 {
1609         struct sdma_channel *sdmac = to_sdma_chan(chan);
1610         struct imx_dma_data *data = fn_param;
1611
1612         if (!imx_dma_is_general_purpose(chan))
1613                 return false;
1614
1615         sdmac->data = *data;
1616         chan->private = &sdmac->data;
1617
1618         return true;
1619 }
1620
1621 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1622                                    struct of_dma *ofdma)
1623 {
1624         struct sdma_engine *sdma = ofdma->of_dma_data;
1625         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1626         struct imx_dma_data data;
1627
1628         if (dma_spec->args_count != 3)
1629                 return NULL;
1630
1631         data.dma_request = dma_spec->args[0];
1632         data.peripheral_type = dma_spec->args[1];
1633         data.priority = dma_spec->args[2];
1634         /*
1635          * init dma_request2 to zero, which is not used by the dts.
1636          * For P2P, dma_request2 is init from dma_request_channel(),
1637          * chan->private will point to the imx_dma_data, and in
1638          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1639          * be set to sdmac->event_id1.
1640          */
1641         data.dma_request2 = 0;
1642
1643         return dma_request_channel(mask, sdma_filter_fn, &data);
1644 }
1645
1646 static int sdma_probe(struct platform_device *pdev)
1647 {
1648         const struct of_device_id *of_id =
1649                         of_match_device(sdma_dt_ids, &pdev->dev);
1650         struct device_node *np = pdev->dev.of_node;
1651         struct device_node *spba_bus;
1652         const char *fw_name;
1653         int ret;
1654         int irq;
1655         struct resource *iores;
1656         struct resource spba_res;
1657         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1658         int i;
1659         struct sdma_engine *sdma;
1660         s32 *saddr_arr;
1661         const struct sdma_driver_data *drvdata = NULL;
1662
1663         if (of_id)
1664                 drvdata = of_id->data;
1665         else if (pdev->id_entry)
1666                 drvdata = (void *)pdev->id_entry->driver_data;
1667
1668         if (!drvdata) {
1669                 dev_err(&pdev->dev, "unable to find driver data\n");
1670                 return -EINVAL;
1671         }
1672
1673         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1674         if (ret)
1675                 return ret;
1676
1677         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1678         if (!sdma)
1679                 return -ENOMEM;
1680
1681         spin_lock_init(&sdma->channel_0_lock);
1682
1683         sdma->dev = &pdev->dev;
1684         sdma->drvdata = drvdata;
1685
1686         irq = platform_get_irq(pdev, 0);
1687         if (irq < 0)
1688                 return irq;
1689
1690         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1691         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1692         if (IS_ERR(sdma->regs))
1693                 return PTR_ERR(sdma->regs);
1694
1695         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1696         if (IS_ERR(sdma->clk_ipg))
1697                 return PTR_ERR(sdma->clk_ipg);
1698
1699         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1700         if (IS_ERR(sdma->clk_ahb))
1701                 return PTR_ERR(sdma->clk_ahb);
1702
1703         clk_prepare(sdma->clk_ipg);
1704         clk_prepare(sdma->clk_ahb);
1705
1706         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1707                                sdma);
1708         if (ret)
1709                 return ret;
1710
1711         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1712         if (!sdma->script_addrs)
1713                 return -ENOMEM;
1714
1715         /* initially no scripts available */
1716         saddr_arr = (s32 *)sdma->script_addrs;
1717         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1718                 saddr_arr[i] = -EINVAL;
1719
1720         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1721         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1722
1723         INIT_LIST_HEAD(&sdma->dma_device.channels);
1724         /* Initialize channel parameters */
1725         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1726                 struct sdma_channel *sdmac = &sdma->channel[i];
1727
1728                 sdmac->sdma = sdma;
1729                 spin_lock_init(&sdmac->lock);
1730
1731                 sdmac->chan.device = &sdma->dma_device;
1732                 dma_cookie_init(&sdmac->chan);
1733                 sdmac->channel = i;
1734
1735                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1736                              (unsigned long) sdmac);
1737                 /*
1738                  * Add the channel to the DMAC list. Do not add channel 0 though
1739                  * because we need it internally in the SDMA driver. This also means
1740                  * that channel 0 in dmaengine counting matches sdma channel 1.
1741                  */
1742                 if (i)
1743                         list_add_tail(&sdmac->chan.device_node,
1744                                         &sdma->dma_device.channels);
1745         }
1746
1747         ret = sdma_init(sdma);
1748         if (ret)
1749                 goto err_init;
1750
1751         ret = sdma_event_remap(sdma);
1752         if (ret)
1753                 goto err_init;
1754
1755         if (sdma->drvdata->script_addrs)
1756                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1757         if (pdata && pdata->script_addrs)
1758                 sdma_add_scripts(sdma, pdata->script_addrs);
1759
1760         if (pdata) {
1761                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1762                 if (ret)
1763                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1764         } else {
1765                 /*
1766                  * Because that device tree does not encode ROM script address,
1767                  * the RAM script in firmware is mandatory for device tree
1768                  * probe, otherwise it fails.
1769                  */
1770                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1771                                               &fw_name);
1772                 if (ret)
1773                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1774                 else {
1775                         ret = sdma_get_firmware(sdma, fw_name);
1776                         if (ret)
1777                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1778                 }
1779         }
1780
1781         sdma->dma_device.dev = &pdev->dev;
1782
1783         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1784         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1785         sdma->dma_device.device_tx_status = sdma_tx_status;
1786         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1787         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1788         sdma->dma_device.device_config = sdma_config;
1789         sdma->dma_device.device_terminate_all = sdma_disable_channel;
1790         sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1791         sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1792         sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1793         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1794         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1795         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1796         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1797
1798         platform_set_drvdata(pdev, sdma);
1799
1800         ret = dma_async_device_register(&sdma->dma_device);
1801         if (ret) {
1802                 dev_err(&pdev->dev, "unable to register\n");
1803                 goto err_init;
1804         }
1805
1806         if (np) {
1807                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1808                 if (ret) {
1809                         dev_err(&pdev->dev, "failed to register controller\n");
1810                         goto err_register;
1811                 }
1812
1813                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1814                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1815                 if (!ret) {
1816                         sdma->spba_start_addr = spba_res.start;
1817                         sdma->spba_end_addr = spba_res.end;
1818                 }
1819                 of_node_put(spba_bus);
1820         }
1821
1822         return 0;
1823
1824 err_register:
1825         dma_async_device_unregister(&sdma->dma_device);
1826 err_init:
1827         kfree(sdma->script_addrs);
1828         return ret;
1829 }
1830
1831 static int sdma_remove(struct platform_device *pdev)
1832 {
1833         struct sdma_engine *sdma = platform_get_drvdata(pdev);
1834         int i;
1835
1836         dma_async_device_unregister(&sdma->dma_device);
1837         kfree(sdma->script_addrs);
1838         /* Kill the tasklet */
1839         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1840                 struct sdma_channel *sdmac = &sdma->channel[i];
1841
1842                 tasklet_kill(&sdmac->tasklet);
1843         }
1844
1845         platform_set_drvdata(pdev, NULL);
1846         return 0;
1847 }
1848
1849 static struct platform_driver sdma_driver = {
1850         .driver         = {
1851                 .name   = "imx-sdma",
1852                 .of_match_table = sdma_dt_ids,
1853         },
1854         .id_table       = sdma_devtypes,
1855         .remove         = sdma_remove,
1856         .probe          = sdma_probe,
1857 };
1858
1859 module_platform_driver(sdma_driver);
1860
1861 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1862 MODULE_DESCRIPTION("i.MX SDMA driver");
1863 MODULE_LICENSE("GPL");