drivers/dma/qcom_bam_dma.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14 /*
  15  * QCOM BAM DMA engine driver
  16  *
  17  * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
  18  * peripherals on the MSM 8x74.  The configuration of the channels are dependent
  19  * on the way they are hard wired to that specific peripheral.  The peripheral
  20  * device tree entries specify the configuration of each channel.
  21  *
  22  * The DMA controller requires the use of external memory for storage of the
  23  * hardware descriptors for each channel.  The descriptor FIFO is accessed as a
  24  * circular buffer and operations are managed according to the offset within the
  25  * FIFO.  After pipe/channel reset, all of the pipe registers and internal state
  26  * are back to defaults.
  27  *
  28  * During DMA operations, we write descriptors to the FIFO, being careful to
  29  * handle wrapping and then write the last FIFO offset to that channel's
  30  * P_EVNT_REG register to kick off the transaction.  The P_SW_OFSTS register
  31  * indicates the current FIFO offset that is being processed, so there is some
  32  * indication of where the hardware is currently working.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/io.h>
  37 #include <linux/init.h>
  38 #include <linux/slab.h>
  39 #include <linux/module.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/scatterlist.h>
  43 #include <linux/device.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/of.h>
  46 #include <linux/of_address.h>
  47 #include <linux/of_irq.h>
  48 #include <linux/of_dma.h>
  49 #include <linux/clk.h>
  50 #include <linux/dmaengine.h>
  51
  52 #include "dmaengine.h"
  53 #include "virt-dma.h"
  54
  55 struct bam_desc_hw {
  56         u32 addr;               /* Buffer physical address */
  57         u16 size;               /* Buffer size in bytes */
  58         u16 flags;
  59 };
  60
  61 #define DESC_FLAG_INT BIT(15)
  62 #define DESC_FLAG_EOT BIT(14)
  63 #define DESC_FLAG_EOB BIT(13)
  64 #define DESC_FLAG_NWD BIT(12)
  65
  66 struct bam_async_desc {
  67         struct virt_dma_desc vd;
  68
  69         u32 num_desc;
  70         u32 xfer_len;
  71
  72         /* transaction flags, EOT|EOB|NWD */
  73         u16 flags;
  74
  75         struct bam_desc_hw *curr_desc;
  76
  77         enum dma_transfer_direction dir;
  78         size_t length;
  79         struct bam_desc_hw desc[0];
  80 };
  81
  82 enum bam_reg {
  83         BAM_CTRL,
  84         BAM_REVISION,
  85         BAM_NUM_PIPES,
  86         BAM_DESC_CNT_TRSHLD,
  87         BAM_IRQ_SRCS,
  88         BAM_IRQ_SRCS_MSK,
  89         BAM_IRQ_SRCS_UNMASKED,
  90         BAM_IRQ_STTS,
  91         BAM_IRQ_CLR,
  92         BAM_IRQ_EN,
  93         BAM_CNFG_BITS,
  94         BAM_IRQ_SRCS_EE,
  95         BAM_IRQ_SRCS_MSK_EE,
  96         BAM_P_CTRL,
  97         BAM_P_RST,
  98         BAM_P_HALT,
  99         BAM_P_IRQ_STTS,
 100         BAM_P_IRQ_CLR,
 101         BAM_P_IRQ_EN,
 102         BAM_P_EVNT_DEST_ADDR,
 103         BAM_P_EVNT_REG,
 104         BAM_P_SW_OFSTS,
 105         BAM_P_DATA_FIFO_ADDR,
 106         BAM_P_DESC_FIFO_ADDR,
 107         BAM_P_EVNT_GEN_TRSHLD,
 108         BAM_P_FIFO_SIZES,
 109 };
 110
 111 struct reg_offset_data {
 112         u32 base_offset;
 113         unsigned int pipe_mult, evnt_mult, ee_mult;
 114 };
 115
 116 static const struct reg_offset_data bam_v1_3_reg_info[] = {
 117         [BAM_CTRL]              = { 0x0F80, 0x00, 0x00, 0x00 },
 118         [BAM_REVISION]          = { 0x0F84, 0x00, 0x00, 0x00 },
 119         [BAM_NUM_PIPES]         = { 0x0FBC, 0x00, 0x00, 0x00 },
 120         [BAM_DESC_CNT_TRSHLD]   = { 0x0F88, 0x00, 0x00, 0x00 },
 121         [BAM_IRQ_SRCS]          = { 0x0F8C, 0x00, 0x00, 0x00 },
 122         [BAM_IRQ_SRCS_MSK]      = { 0x0F90, 0x00, 0x00, 0x00 },
 123         [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 },
 124         [BAM_IRQ_STTS]          = { 0x0F94, 0x00, 0x00, 0x00 },
 125         [BAM_IRQ_CLR]           = { 0x0F98, 0x00, 0x00, 0x00 },
 126         [BAM_IRQ_EN]            = { 0x0F9C, 0x00, 0x00, 0x00 },
 127         [BAM_CNFG_BITS]         = { 0x0FFC, 0x00, 0x00, 0x00 },
 128         [BAM_IRQ_SRCS_EE]       = { 0x1800, 0x00, 0x00, 0x80 },
 129         [BAM_IRQ_SRCS_MSK_EE]   = { 0x1804, 0x00, 0x00, 0x80 },
 130         [BAM_P_CTRL]            = { 0x0000, 0x80, 0x00, 0x00 },
 131         [BAM_P_RST]             = { 0x0004, 0x80, 0x00, 0x00 },
 132         [BAM_P_HALT]            = { 0x0008, 0x80, 0x00, 0x00 },
 133         [BAM_P_IRQ_STTS]        = { 0x0010, 0x80, 0x00, 0x00 },
 134         [BAM_P_IRQ_CLR]         = { 0x0014, 0x80, 0x00, 0x00 },
 135         [BAM_P_IRQ_EN]          = { 0x0018, 0x80, 0x00, 0x00 },
 136         [BAM_P_EVNT_DEST_ADDR]  = { 0x102C, 0x00, 0x40, 0x00 },
 137         [BAM_P_EVNT_REG]        = { 0x1018, 0x00, 0x40, 0x00 },
 138         [BAM_P_SW_OFSTS]        = { 0x1000, 0x00, 0x40, 0x00 },
 139         [BAM_P_DATA_FIFO_ADDR]  = { 0x1024, 0x00, 0x40, 0x00 },
 140         [BAM_P_DESC_FIFO_ADDR]  = { 0x101C, 0x00, 0x40, 0x00 },
 141         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 },
 142         [BAM_P_FIFO_SIZES]      = { 0x1020, 0x00, 0x40, 0x00 },
 143 };
 144
 145 static const struct reg_offset_data bam_v1_4_reg_info[] = {
 146         [BAM_CTRL]              = { 0x0000, 0x00, 0x00, 0x00 },
 147         [BAM_REVISION]          = { 0x0004, 0x00, 0x00, 0x00 },
 148         [BAM_NUM_PIPES]         = { 0x003C, 0x00, 0x00, 0x00 },
 149         [BAM_DESC_CNT_TRSHLD]   = { 0x0008, 0x00, 0x00, 0x00 },
 150         [BAM_IRQ_SRCS]          = { 0x000C, 0x00, 0x00, 0x00 },
 151         [BAM_IRQ_SRCS_MSK]      = { 0x0010, 0x00, 0x00, 0x00 },
 152         [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 },
 153         [BAM_IRQ_STTS]          = { 0x0014, 0x00, 0x00, 0x00 },
 154         [BAM_IRQ_CLR]           = { 0x0018, 0x00, 0x00, 0x00 },
 155         [BAM_IRQ_EN]            = { 0x001C, 0x00, 0x00, 0x00 },
 156         [BAM_CNFG_BITS]         = { 0x007C, 0x00, 0x00, 0x00 },
 157         [BAM_IRQ_SRCS_EE]       = { 0x0800, 0x00, 0x00, 0x80 },
 158         [BAM_IRQ_SRCS_MSK_EE]   = { 0x0804, 0x00, 0x00, 0x80 },
 159         [BAM_P_CTRL]            = { 0x1000, 0x1000, 0x00, 0x00 },
 160         [BAM_P_RST]             = { 0x1004, 0x1000, 0x00, 0x00 },
 161         [BAM_P_HALT]            = { 0x1008, 0x1000, 0x00, 0x00 },
 162         [BAM_P_IRQ_STTS]        = { 0x1010, 0x1000, 0x00, 0x00 },
 163         [BAM_P_IRQ_CLR]         = { 0x1014, 0x1000, 0x00, 0x00 },
 164         [BAM_P_IRQ_EN]          = { 0x1018, 0x1000, 0x00, 0x00 },
 165         [BAM_P_EVNT_DEST_ADDR]  = { 0x102C, 0x00, 0x1000, 0x00 },
 166         [BAM_P_EVNT_REG]        = { 0x1018, 0x00, 0x1000, 0x00 },
 167         [BAM_P_SW_OFSTS]        = { 0x1000, 0x00, 0x1000, 0x00 },
 168         [BAM_P_DATA_FIFO_ADDR]  = { 0x1824, 0x00, 0x1000, 0x00 },
 169         [BAM_P_DESC_FIFO_ADDR]  = { 0x181C, 0x00, 0x1000, 0x00 },
 170         [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 },
 171         [BAM_P_FIFO_SIZES]      = { 0x1820, 0x00, 0x1000, 0x00 },
 172 };
 173
 174 /* BAM CTRL */
 175 #define BAM_SW_RST                      BIT(0)
 176 #define BAM_EN                          BIT(1)
 177 #define BAM_EN_ACCUM                    BIT(4)
 178 #define BAM_TESTBUS_SEL_SHIFT           5
 179 #define BAM_TESTBUS_SEL_MASK            0x3F
 180 #define BAM_DESC_CACHE_SEL_SHIFT        13
 181 #define BAM_DESC_CACHE_SEL_MASK         0x3
 182 #define BAM_CACHED_DESC_STORE           BIT(15)
 183 #define IBC_DISABLE                     BIT(16)
 184
 185 /* BAM REVISION */
 186 #define REVISION_SHIFT          0
 187 #define REVISION_MASK           0xFF
 188 #define NUM_EES_SHIFT           8
 189 #define NUM_EES_MASK            0xF
 190 #define CE_BUFFER_SIZE          BIT(13)
 191 #define AXI_ACTIVE              BIT(14)
 192 #define USE_VMIDMT              BIT(15)
 193 #define SECURED                 BIT(16)
 194 #define BAM_HAS_NO_BYPASS       BIT(17)
 195 #define HIGH_FREQUENCY_BAM      BIT(18)
 196 #define INACTIV_TMRS_EXST       BIT(19)
 197 #define NUM_INACTIV_TMRS        BIT(20)
 198 #define DESC_CACHE_DEPTH_SHIFT  21
 199 #define DESC_CACHE_DEPTH_1      (0 << DESC_CACHE_DEPTH_SHIFT)
 200 #define DESC_CACHE_DEPTH_2      (1 << DESC_CACHE_DEPTH_SHIFT)
 201 #define DESC_CACHE_DEPTH_3      (2 << DESC_CACHE_DEPTH_SHIFT)
 202 #define DESC_CACHE_DEPTH_4      (3 << DESC_CACHE_DEPTH_SHIFT)
 203 #define CMD_DESC_EN             BIT(23)
 204 #define INACTIV_TMR_BASE_SHIFT  24
 205 #define INACTIV_TMR_BASE_MASK   0xFF
 206
 207 /* BAM NUM PIPES */
 208 #define BAM_NUM_PIPES_SHIFT             0
 209 #define BAM_NUM_PIPES_MASK              0xFF
 210 #define PERIPH_NON_PIPE_GRP_SHIFT       16
 211 #define PERIPH_NON_PIP_GRP_MASK         0xFF
 212 #define BAM_NON_PIPE_GRP_SHIFT          24
 213 #define BAM_NON_PIPE_GRP_MASK           0xFF
 214
 215 /* BAM CNFG BITS */
 216 #define BAM_PIPE_CNFG           BIT(2)
 217 #define BAM_FULL_PIPE           BIT(11)
 218 #define BAM_NO_EXT_P_RST        BIT(12)
 219 #define BAM_IBC_DISABLE         BIT(13)
 220 #define BAM_SB_CLK_REQ          BIT(14)
 221 #define BAM_PSM_CSW_REQ         BIT(15)
 222 #define BAM_PSM_P_RES           BIT(16)
 223 #define BAM_AU_P_RES            BIT(17)
 224 #define BAM_SI_P_RES            BIT(18)
 225 #define BAM_WB_P_RES            BIT(19)
 226 #define BAM_WB_BLK_CSW          BIT(20)
 227 #define BAM_WB_CSW_ACK_IDL      BIT(21)
 228 #define BAM_WB_RETR_SVPNT       BIT(22)
 229 #define BAM_WB_DSC_AVL_P_RST    BIT(23)
 230 #define BAM_REG_P_EN            BIT(24)
 231 #define BAM_PSM_P_HD_DATA       BIT(25)
 232 #define BAM_AU_ACCUMED          BIT(26)
 233 #define BAM_CMD_ENABLE          BIT(27)
 234
 235 #define BAM_CNFG_BITS_DEFAULT   (BAM_PIPE_CNFG |        \
 236                                  BAM_NO_EXT_P_RST |     \
 237                                  BAM_IBC_DISABLE |      \
 238                                  BAM_SB_CLK_REQ |       \
 239                                  BAM_PSM_CSW_REQ |      \
 240                                  BAM_PSM_P_RES |        \
 241                                  BAM_AU_P_RES |         \
 242                                  BAM_SI_P_RES |         \
 243                                  BAM_WB_P_RES |         \
 244                                  BAM_WB_BLK_CSW |       \
 245                                  BAM_WB_CSW_ACK_IDL |   \
 246                                  BAM_WB_RETR_SVPNT |    \
 247                                  BAM_WB_DSC_AVL_P_RST | \
 248                                  BAM_REG_P_EN |         \
 249                                  BAM_PSM_P_HD_DATA |    \
 250                                  BAM_AU_ACCUMED |       \
 251                                  BAM_CMD_ENABLE)
 252
 253 /* PIPE CTRL */
 254 #define P_EN                    BIT(1)
 255 #define P_DIRECTION             BIT(3)
 256 #define P_SYS_STRM              BIT(4)
 257 #define P_SYS_MODE              BIT(5)
 258 #define P_AUTO_EOB              BIT(6)
 259 #define P_AUTO_EOB_SEL_SHIFT    7
 260 #define P_AUTO_EOB_SEL_512      (0 << P_AUTO_EOB_SEL_SHIFT)
 261 #define P_AUTO_EOB_SEL_256      (1 << P_AUTO_EOB_SEL_SHIFT)
 262 #define P_AUTO_EOB_SEL_128      (2 << P_AUTO_EOB_SEL_SHIFT)
 263 #define P_AUTO_EOB_SEL_64       (3 << P_AUTO_EOB_SEL_SHIFT)
 264 #define P_PREFETCH_LIMIT_SHIFT  9
 265 #define P_PREFETCH_LIMIT_32     (0 << P_PREFETCH_LIMIT_SHIFT)
 266 #define P_PREFETCH_LIMIT_16     (1 << P_PREFETCH_LIMIT_SHIFT)
 267 #define P_PREFETCH_LIMIT_4      (2 << P_PREFETCH_LIMIT_SHIFT)
 268 #define P_WRITE_NWD             BIT(11)
 269 #define P_LOCK_GROUP_SHIFT      16
 270 #define P_LOCK_GROUP_MASK       0x1F
 271
 272 /* BAM_DESC_CNT_TRSHLD */
 273 #define CNT_TRSHLD              0xffff
 274 #define DEFAULT_CNT_THRSHLD     0x4
 275
 276 /* BAM_IRQ_SRCS */
 277 #define BAM_IRQ                 BIT(31)
 278 #define P_IRQ                   0x7fffffff
 279
 280 /* BAM_IRQ_SRCS_MSK */
 281 #define BAM_IRQ_MSK             BAM_IRQ
 282 #define P_IRQ_MSK               P_IRQ
 283
 284 /* BAM_IRQ_STTS */
 285 #define BAM_TIMER_IRQ           BIT(4)
 286 #define BAM_EMPTY_IRQ           BIT(3)
 287 #define BAM_ERROR_IRQ           BIT(2)
 288 #define BAM_HRESP_ERR_IRQ       BIT(1)
 289
 290 /* BAM_IRQ_CLR */
 291 #define BAM_TIMER_CLR           BIT(4)
 292 #define BAM_EMPTY_CLR           BIT(3)
 293 #define BAM_ERROR_CLR           BIT(2)
 294 #define BAM_HRESP_ERR_CLR       BIT(1)
 295
 296 /* BAM_IRQ_EN */
 297 #define BAM_TIMER_EN            BIT(4)
 298 #define BAM_EMPTY_EN            BIT(3)
 299 #define BAM_ERROR_EN            BIT(2)
 300 #define BAM_HRESP_ERR_EN        BIT(1)
 301
 302 /* BAM_P_IRQ_EN */
 303 #define P_PRCSD_DESC_EN         BIT(0)
 304 #define P_TIMER_EN              BIT(1)
 305 #define P_WAKE_EN               BIT(2)
 306 #define P_OUT_OF_DESC_EN        BIT(3)
 307 #define P_ERR_EN                BIT(4)
 308 #define P_TRNSFR_END_EN         BIT(5)
 309 #define P_DEFAULT_IRQS_EN       (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
 310
 311 /* BAM_P_SW_OFSTS */
 312 #define P_SW_OFSTS_MASK         0xffff
 313
 314 #define BAM_DESC_FIFO_SIZE      SZ_32K
 315 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
 316 #define BAM_MAX_DATA_SIZE       (SZ_32K - 8)
 317
 318 struct bam_chan {
 319         struct virt_dma_chan vc;
 320
 321         struct bam_device *bdev;
 322
 323         /* configuration from device tree */
 324         u32 id;
 325
 326         struct bam_async_desc *curr_txd;        /* current running dma */
 327
 328         /* runtime configuration */
 329         struct dma_slave_config slave;
 330
 331         /* fifo storage */
 332         struct bam_desc_hw *fifo_virt;
 333         dma_addr_t fifo_phys;
 334
 335         /* fifo markers */
 336         unsigned short head;            /* start of active descriptor entries */
 337         unsigned short tail;            /* end of active descriptor entries */
 338
 339         unsigned int initialized;       /* is the channel hw initialized? */
 340         unsigned int paused;            /* is the channel paused? */
 341         unsigned int reconfigure;       /* new slave config? */
 342
 343         struct list_head node;
 344 };
 345
 346 static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
 347 {
 348         return container_of(common, struct bam_chan, vc.chan);
 349 }
 350
 351 struct bam_device {
 352         void __iomem *regs;
 353         struct device *dev;
 354         struct dma_device common;
 355         struct device_dma_parameters dma_parms;
 356         struct bam_chan *channels;
 357         u32 num_channels;
 358
 359         /* execution environment ID, from DT */
 360         u32 ee;
 361
 362         const struct reg_offset_data *layout;
 363
 364         struct clk *bamclk;
 365         int irq;
 366
 367         /* dma start transaction tasklet */
 368         struct tasklet_struct task;
 369 };
 370
 371 /**
 372  * bam_addr - returns BAM register address
 373  * @bdev: bam device
 374  * @pipe: pipe instance (ignored when register doesn't have multiple instances)
 375  * @reg:  register enum
 376  */
 377 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
 378                 enum bam_reg reg)
 379 {
 380         const struct reg_offset_data r = bdev->layout[reg];
 381
 382         return bdev->regs + r.base_offset +
 383                 r.pipe_mult * pipe +
 384                 r.evnt_mult * pipe +
 385                 r.ee_mult * bdev->ee;
 386 }
 387
 388 /**
 389  * bam_reset_channel - Reset individual BAM DMA channel
 390  * @bchan: bam channel
 391  *
 392  * This function resets a specific BAM channel
 393  */
 394 static void bam_reset_channel(struct bam_chan *bchan)
 395 {
 396         struct bam_device *bdev = bchan->bdev;
 397
 398         lockdep_assert_held(&bchan->vc.lock);
 399
 400         /* reset channel */
 401         writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
 402         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
 403
 404         /* don't allow cpu to reorder BAM register accesses done after this */
 405         wmb();
 406
 407         /* make sure hw is initialized when channel is used the first time  */
 408         bchan->initialized = 0;
 409 }
 410
 411 /**
 412  * bam_chan_init_hw - Initialize channel hardware
 413  * @bchan: bam channel
 414  *
 415  * This function resets and initializes the BAM channel
 416  */
 417 static void bam_chan_init_hw(struct bam_chan *bchan,
 418         enum dma_transfer_direction dir)
 419 {
 420         struct bam_device *bdev = bchan->bdev;
 421         u32 val;
 422
 423         /* Reset the channel to clear internal state of the FIFO */
 424         bam_reset_channel(bchan);
 425
 426         /*
 427          * write out 8 byte aligned address.  We have enough space for this
 428          * because we allocated 1 more descriptor (8 bytes) than we can use
 429          */
 430         writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
 431                         bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR));
 432         writel_relaxed(BAM_DESC_FIFO_SIZE,
 433                         bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES));
 434
 435         /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
 436         writel_relaxed(P_DEFAULT_IRQS_EN,
 437                         bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 438
 439         /* unmask the specific pipe and EE combo */
 440         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 441         val |= BIT(bchan->id);
 442         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 443
 444         /* don't allow cpu to reorder the channel enable done below */
 445         wmb();
 446
 447         /* set fixed direction and mode, then enable channel */
 448         val = P_EN | P_SYS_MODE;
 449         if (dir == DMA_DEV_TO_MEM)
 450                 val |= P_DIRECTION;
 451
 452         writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL));
 453
 454         bchan->initialized = 1;
 455
 456         /* init FIFO pointers */
 457         bchan->head = 0;
 458         bchan->tail = 0;
 459 }
 460
 461 /**
 462  * bam_alloc_chan - Allocate channel resources for DMA channel.
 463  * @chan: specified channel
 464  *
 465  * This function allocates the FIFO descriptor memory
 466  */
 467 static int bam_alloc_chan(struct dma_chan *chan)
 468 {
 469         struct bam_chan *bchan = to_bam_chan(chan);
 470         struct bam_device *bdev = bchan->bdev;
 471
 472         if (bchan->fifo_virt)
 473                 return 0;
 474
 475         /* allocate FIFO descriptor space, but only if necessary */
 476         bchan->fifo_virt = dma_alloc_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE,
 477                                 &bchan->fifo_phys, GFP_KERNEL);
 478
 479         if (!bchan->fifo_virt) {
 480                 dev_err(bdev->dev, "Failed to allocate desc fifo\n");
 481                 return -ENOMEM;
 482         }
 483
 484         return 0;
 485 }
 486
 487 /**
 488  * bam_free_chan - Frees dma resources associated with specific channel
 489  * @chan: specified channel
 490  *
 491  * Free the allocated fifo descriptor memory and channel resources
 492  *
 493  */
 494 static void bam_free_chan(struct dma_chan *chan)
 495 {
 496         struct bam_chan *bchan = to_bam_chan(chan);
 497         struct bam_device *bdev = bchan->bdev;
 498         u32 val;
 499         unsigned long flags;
 500
 501         vchan_free_chan_resources(to_virt_chan(chan));
 502
 503         if (bchan->curr_txd) {
 504                 dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
 505                 return;
 506         }
 507
 508         spin_lock_irqsave(&bchan->vc.lock, flags);
 509         bam_reset_channel(bchan);
 510         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 511
 512         dma_free_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
 513                                 bchan->fifo_phys);
 514         bchan->fifo_virt = NULL;
 515
 516         /* mask irq for pipe/channel */
 517         val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 518         val &= ~BIT(bchan->id);
 519         writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
 520
 521         /* disable irq */
 522         writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN));
 523 }
 524
 525 /**
 526  * bam_slave_config - set slave configuration for channel
 527  * @chan: dma channel
 528  * @cfg: slave configuration
 529  *
 530  * Sets slave configuration for channel
 531  *
 532  */
 533 static void bam_slave_config(struct bam_chan *bchan,
 534                 struct dma_slave_config *cfg)
 535 {
 536         memcpy(&bchan->slave, cfg, sizeof(*cfg));
 537         bchan->reconfigure = 1;
 538 }
 539
 540 /**
 541  * bam_prep_slave_sg - Prep slave sg transaction
 542  *
 543  * @chan: dma channel
 544  * @sgl: scatter gather list
 545  * @sg_len: length of sg
 546  * @direction: DMA transfer direction
 547  * @flags: DMA flags
 548  * @context: transfer context (unused)
 549  */
 550 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
 551         struct scatterlist *sgl, unsigned int sg_len,
 552         enum dma_transfer_direction direction, unsigned long flags,
 553         void *context)
 554 {
 555         struct bam_chan *bchan = to_bam_chan(chan);
 556         struct bam_device *bdev = bchan->bdev;
 557         struct bam_async_desc *async_desc;
 558         struct scatterlist *sg;
 559         u32 i;
 560         struct bam_desc_hw *desc;
 561         unsigned int num_alloc = 0;
 562
 563
 564         if (!is_slave_direction(direction)) {
 565                 dev_err(bdev->dev, "invalid dma direction\n");
 566                 return NULL;
 567         }
 568
 569         /* calculate number of required entries */
 570         for_each_sg(sgl, sg, sg_len, i)
 571                 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_MAX_DATA_SIZE);
 572
 573         /* allocate enough room to accomodate the number of entries */
 574         async_desc = kzalloc(sizeof(*async_desc) +
 575                         (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
 576
 577         if (!async_desc)
 578                 goto err_out;
 579
 580         if (flags & DMA_PREP_FENCE)
 581                 async_desc->flags |= DESC_FLAG_NWD;
 582
 583         if (flags & DMA_PREP_INTERRUPT)
 584                 async_desc->flags |= DESC_FLAG_EOT;
 585         else
 586                 async_desc->flags |= DESC_FLAG_INT;
 587
 588         async_desc->num_desc = num_alloc;
 589         async_desc->curr_desc = async_desc->desc;
 590         async_desc->dir = direction;
 591
 592         /* fill in temporary descriptors */
 593         desc = async_desc->desc;
 594         for_each_sg(sgl, sg, sg_len, i) {
 595                 unsigned int remainder = sg_dma_len(sg);
 596                 unsigned int curr_offset = 0;
 597
 598                 do {
 599                         desc->addr = sg_dma_address(sg) + curr_offset;
 600
 601                         if (remainder > BAM_MAX_DATA_SIZE) {
 602                                 desc->size = BAM_MAX_DATA_SIZE;
 603                                 remainder -= BAM_MAX_DATA_SIZE;
 604                                 curr_offset += BAM_MAX_DATA_SIZE;
 605                         } else {
 606                                 desc->size = remainder;
 607                                 remainder = 0;
 608                         }
 609
 610                         async_desc->length += desc->size;
 611                         desc++;
 612                 } while (remainder > 0);
 613         }
 614
 615         return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
 616
 617 err_out:
 618         kfree(async_desc);
 619         return NULL;
 620 }
 621
 622 /**
 623  * bam_dma_terminate_all - terminate all transactions on a channel
 624  * @bchan: bam dma channel
 625  *
 626  * Dequeues and frees all transactions
 627  * No callbacks are done
 628  *
 629  */
 630 static void bam_dma_terminate_all(struct bam_chan *bchan)
 631 {
 632         unsigned long flag;
 633         LIST_HEAD(head);
 634
 635         /* remove all transactions, including active transaction */
 636         spin_lock_irqsave(&bchan->vc.lock, flag);
 637         if (bchan->curr_txd) {
 638                 list_add(&bchan->curr_txd->vd.node, &bchan->vc.desc_issued);
 639                 bchan->curr_txd = NULL;
 640         }
 641
 642         vchan_get_all_descriptors(&bchan->vc, &head);
 643         spin_unlock_irqrestore(&bchan->vc.lock, flag);
 644
 645         vchan_dma_desc_free_list(&bchan->vc, &head);
 646 }
 647
 648 /**
 649  * bam_control - DMA device control
 650  * @chan: dma channel
 651  * @cmd: control cmd
 652  * @arg: cmd argument
 653  *
 654  * Perform DMA control command
 655  *
 656  */
 657 static int bam_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 658         unsigned long arg)
 659 {
 660         struct bam_chan *bchan = to_bam_chan(chan);
 661         struct bam_device *bdev = bchan->bdev;
 662         int ret = 0;
 663         unsigned long flag;
 664
 665         switch (cmd) {
 666         case DMA_PAUSE:
 667                 spin_lock_irqsave(&bchan->vc.lock, flag);
 668                 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT));
 669                 bchan->paused = 1;
 670                 spin_unlock_irqrestore(&bchan->vc.lock, flag);
 671                 break;
 672
 673         case DMA_RESUME:
 674                 spin_lock_irqsave(&bchan->vc.lock, flag);
 675                 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT));
 676                 bchan->paused = 0;
 677                 spin_unlock_irqrestore(&bchan->vc.lock, flag);
 678                 break;
 679
 680         case DMA_TERMINATE_ALL:
 681                 bam_dma_terminate_all(bchan);
 682                 break;
 683
 684         case DMA_SLAVE_CONFIG:
 685                 spin_lock_irqsave(&bchan->vc.lock, flag);
 686                 bam_slave_config(bchan, (struct dma_slave_config *)arg);
 687                 spin_unlock_irqrestore(&bchan->vc.lock, flag);
 688                 break;
 689
 690         default:
 691                 ret = -ENXIO;
 692                 break;
 693         }
 694
 695         return ret;
 696 }
 697
 698 /**
 699  * process_channel_irqs - processes the channel interrupts
 700  * @bdev: bam controller
 701  *
 702  * This function processes the channel interrupts
 703  *
 704  */
 705 static u32 process_channel_irqs(struct bam_device *bdev)
 706 {
 707         u32 i, srcs, pipe_stts;
 708         unsigned long flags;
 709         struct bam_async_desc *async_desc;
 710
 711         srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE));
 712
 713         /* return early if no pipe/channel interrupts are present */
 714         if (!(srcs & P_IRQ))
 715                 return srcs;
 716
 717         for (i = 0; i < bdev->num_channels; i++) {
 718                 struct bam_chan *bchan = &bdev->channels[i];
 719
 720                 if (!(srcs & BIT(i)))
 721                         continue;
 722
 723                 /* clear pipe irq */
 724                 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS));
 725
 726                 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR));
 727
 728                 spin_lock_irqsave(&bchan->vc.lock, flags);
 729                 async_desc = bchan->curr_txd;
 730
 731                 if (async_desc) {
 732                         async_desc->num_desc -= async_desc->xfer_len;
 733                         async_desc->curr_desc += async_desc->xfer_len;
 734                         bchan->curr_txd = NULL;
 735
 736                         /* manage FIFO */
 737                         bchan->head += async_desc->xfer_len;
 738                         bchan->head %= MAX_DESCRIPTORS;
 739
 740                         /*
 741                          * if complete, process cookie.  Otherwise
 742                          * push back to front of desc_issued so that
 743                          * it gets restarted by the tasklet
 744                          */
 745                         if (!async_desc->num_desc)
 746                                 vchan_cookie_complete(&async_desc->vd);
 747                         else
 748                                 list_add(&async_desc->vd.node,
 749                                         &bchan->vc.desc_issued);
 750                 }
 751
 752                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
 753         }
 754
 755         return srcs;
 756 }
 757
 758 /**
 759  * bam_dma_irq - irq handler for bam controller
 760  * @irq: IRQ of interrupt
 761  * @data: callback data
 762  *
 763  * IRQ handler for the bam controller
 764  */
 765 static irqreturn_t bam_dma_irq(int irq, void *data)
 766 {
 767         struct bam_device *bdev = data;
 768         u32 clr_mask = 0, srcs = 0;
 769
 770         srcs |= process_channel_irqs(bdev);
 771
 772         /* kick off tasklet to start next dma transfer */
 773         if (srcs & P_IRQ)
 774                 tasklet_schedule(&bdev->task);
 775
 776         if (srcs & BAM_IRQ)
 777                 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS));
 778
 779         /* don't allow reorder of the various accesses to the BAM registers */
 780         mb();
 781
 782         writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR));
 783
 784         return IRQ_HANDLED;
 785 }
 786
 787 /**
 788  * bam_tx_status - returns status of transaction
 789  * @chan: dma channel
 790  * @cookie: transaction cookie
 791  * @txstate: DMA transaction state
 792  *
 793  * Return status of dma transaction
 794  */
 795 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 796                 struct dma_tx_state *txstate)
 797 {
 798         struct bam_chan *bchan = to_bam_chan(chan);
 799         struct virt_dma_desc *vd;
 800         int ret;
 801         size_t residue = 0;
 802         unsigned int i;
 803         unsigned long flags;
 804
 805         ret = dma_cookie_status(chan, cookie, txstate);
 806         if (ret == DMA_COMPLETE)
 807                 return ret;
 808
 809         if (!txstate)
 810                 return bchan->paused ? DMA_PAUSED : ret;
 811
 812         spin_lock_irqsave(&bchan->vc.lock, flags);
 813         vd = vchan_find_desc(&bchan->vc, cookie);
 814         if (vd)
 815                 residue = container_of(vd, struct bam_async_desc, vd)->length;
 816         else if (bchan->curr_txd && bchan->curr_txd->vd.tx.cookie == cookie)
 817                 for (i = 0; i < bchan->curr_txd->num_desc; i++)
 818                         residue += bchan->curr_txd->curr_desc[i].size;
 819
 820         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 821
 822         dma_set_residue(txstate, residue);
 823
 824         if (ret == DMA_IN_PROGRESS && bchan->paused)
 825                 ret = DMA_PAUSED;
 826
 827         return ret;
 828 }
 829
 830 /**
 831  * bam_apply_new_config
 832  * @bchan: bam dma channel
 833  * @dir: DMA direction
 834  */
 835 static void bam_apply_new_config(struct bam_chan *bchan,
 836         enum dma_transfer_direction dir)
 837 {
 838         struct bam_device *bdev = bchan->bdev;
 839         u32 maxburst;
 840
 841         if (dir == DMA_DEV_TO_MEM)
 842                 maxburst = bchan->slave.src_maxburst;
 843         else
 844                 maxburst = bchan->slave.dst_maxburst;
 845
 846         writel_relaxed(maxburst, bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
 847
 848         bchan->reconfigure = 0;
 849 }
 850
 851 /**
 852  * bam_start_dma - start next transaction
 853  * @bchan - bam dma channel
 854  */
 855 static void bam_start_dma(struct bam_chan *bchan)
 856 {
 857         struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
 858         struct bam_device *bdev = bchan->bdev;
 859         struct bam_async_desc *async_desc;
 860         struct bam_desc_hw *desc;
 861         struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
 862                                         sizeof(struct bam_desc_hw));
 863
 864         lockdep_assert_held(&bchan->vc.lock);
 865
 866         if (!vd)
 867                 return;
 868
 869         list_del(&vd->node);
 870
 871         async_desc = container_of(vd, struct bam_async_desc, vd);
 872         bchan->curr_txd = async_desc;
 873
 874         /* on first use, initialize the channel hardware */
 875         if (!bchan->initialized)
 876                 bam_chan_init_hw(bchan, async_desc->dir);
 877
 878         /* apply new slave config changes, if necessary */
 879         if (bchan->reconfigure)
 880                 bam_apply_new_config(bchan, async_desc->dir);
 881
 882         desc = bchan->curr_txd->curr_desc;
 883
 884         if (async_desc->num_desc > MAX_DESCRIPTORS)
 885                 async_desc->xfer_len = MAX_DESCRIPTORS;
 886         else
 887                 async_desc->xfer_len = async_desc->num_desc;
 888
 889         /* set any special flags on the last descriptor */
 890         if (async_desc->num_desc == async_desc->xfer_len)
 891                 desc[async_desc->xfer_len - 1].flags = async_desc->flags;
 892         else
 893                 desc[async_desc->xfer_len - 1].flags |= DESC_FLAG_INT;
 894
 895         if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
 896                 u32 partial = MAX_DESCRIPTORS - bchan->tail;
 897
 898                 memcpy(&fifo[bchan->tail], desc,
 899                                 partial * sizeof(struct bam_desc_hw));
 900                 memcpy(fifo, &desc[partial], (async_desc->xfer_len - partial) *
 901                                 sizeof(struct bam_desc_hw));
 902         } else {
 903                 memcpy(&fifo[bchan->tail], desc,
 904                         async_desc->xfer_len * sizeof(struct bam_desc_hw));
 905         }
 906
 907         bchan->tail += async_desc->xfer_len;
 908         bchan->tail %= MAX_DESCRIPTORS;
 909
 910         /* ensure descriptor writes and dma start not reordered */
 911         wmb();
 912         writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
 913                         bam_addr(bdev, bchan->id, BAM_P_EVNT_REG));
 914 }
 915
 916 /**
 917  * dma_tasklet - DMA IRQ tasklet
 918  * @data: tasklet argument (bam controller structure)
 919  *
 920  * Sets up next DMA operation and then processes all completed transactions
 921  */
 922 static void dma_tasklet(unsigned long data)
 923 {
 924         struct bam_device *bdev = (struct bam_device *)data;
 925         struct bam_chan *bchan;
 926         unsigned long flags;
 927         unsigned int i;
 928
 929         /* go through the channels and kick off transactions */
 930         for (i = 0; i < bdev->num_channels; i++) {
 931                 bchan = &bdev->channels[i];
 932                 spin_lock_irqsave(&bchan->vc.lock, flags);
 933
 934                 if (!list_empty(&bchan->vc.desc_issued) && !bchan->curr_txd)
 935                         bam_start_dma(bchan);
 936                 spin_unlock_irqrestore(&bchan->vc.lock, flags);
 937         }
 938 }
 939
 940 /**
 941  * bam_issue_pending - starts pending transactions
 942  * @chan: dma channel
 943  *
 944  * Calls tasklet directly which in turn starts any pending transactions
 945  */
 946 static void bam_issue_pending(struct dma_chan *chan)
 947 {
 948         struct bam_chan *bchan = to_bam_chan(chan);
 949         unsigned long flags;
 950
 951         spin_lock_irqsave(&bchan->vc.lock, flags);
 952
 953         /* if work pending and idle, start a transaction */
 954         if (vchan_issue_pending(&bchan->vc) && !bchan->curr_txd)
 955                 bam_start_dma(bchan);
 956
 957         spin_unlock_irqrestore(&bchan->vc.lock, flags);
 958 }
 959
 960 /**
 961  * bam_dma_free_desc - free descriptor memory
 962  * @vd: virtual descriptor
 963  *
 964  */
 965 static void bam_dma_free_desc(struct virt_dma_desc *vd)
 966 {
 967         struct bam_async_desc *async_desc = container_of(vd,
 968                         struct bam_async_desc, vd);
 969
 970         kfree(async_desc);
 971 }
 972
 973 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
 974                 struct of_dma *of)
 975 {
 976         struct bam_device *bdev = container_of(of->of_dma_data,
 977                                         struct bam_device, common);
 978         unsigned int request;
 979
 980         if (dma_spec->args_count != 1)
 981                 return NULL;
 982
 983         request = dma_spec->args[0];
 984         if (request >= bdev->num_channels)
 985                 return NULL;
 986
 987         return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
 988 }
 989
 990 /**
 991  * bam_init
 992  * @bdev: bam device
 993  *
 994  * Initialization helper for global bam registers
 995  */
 996 static int bam_init(struct bam_device *bdev)
 997 {
 998         u32 val;
 999
1000         /* read revision and configuration information */
1001         val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)) >> NUM_EES_SHIFT;
1002         val &= NUM_EES_MASK;
1003
1004         /* check that configured EE is within range */
1005         if (bdev->ee >= val)
1006                 return -EINVAL;
1007
1008         val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES));
1009         bdev->num_channels = val & BAM_NUM_PIPES_MASK;
1010
1011         /* s/w reset bam */
1012         /* after reset all pipes are disabled and idle */
1013         val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL));
1014         val |= BAM_SW_RST;
1015         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1016         val &= ~BAM_SW_RST;
1017         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1018
1019         /* make sure previous stores are visible before enabling BAM */
1020         wmb();
1021
1022         /* enable bam */
1023         val |= BAM_EN;
1024         writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
1025
1026         /* set descriptor threshhold, start with 4 bytes */
1027         writel_relaxed(DEFAULT_CNT_THRSHLD,
1028                         bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
1029
1030         /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
1031         writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
1032
1033         /* enable irqs for errors */
1034         writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
1035                         bam_addr(bdev, 0, BAM_IRQ_EN));
1036
1037         /* unmask global bam interrupt */
1038         writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
1039
1040         return 0;
1041 }
1042
1043 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1044         u32 index)
1045 {
1046         bchan->id = index;
1047         bchan->bdev = bdev;
1048
1049         vchan_init(&bchan->vc, &bdev->common);
1050         bchan->vc.desc_free = bam_dma_free_desc;
1051 }
1052
1053 static const struct of_device_id bam_of_match[] = {
1054         { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
1055         { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
1056         {}
1057 };
1058
1059 MODULE_DEVICE_TABLE(of, bam_of_match);
1060
1061 static int bam_dma_probe(struct platform_device *pdev)
1062 {
1063         struct bam_device *bdev;
1064         const struct of_device_id *match;
1065         struct resource *iores;
1066         int ret, i;
1067
1068         bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
1069         if (!bdev)
1070                 return -ENOMEM;
1071
1072         bdev->dev = &pdev->dev;
1073
1074         match = of_match_node(bam_of_match, pdev->dev.of_node);
1075         if (!match) {
1076                 dev_err(&pdev->dev, "Unsupported BAM module\n");
1077                 return -ENODEV;
1078         }
1079
1080         bdev->layout = match->data;
1081
1082         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1083         bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1084         if (IS_ERR(bdev->regs))
1085                 return PTR_ERR(bdev->regs);
1086
1087         bdev->irq = platform_get_irq(pdev, 0);
1088         if (bdev->irq < 0)
1089                 return bdev->irq;
1090
1091         ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
1092         if (ret) {
1093                 dev_err(bdev->dev, "Execution environment unspecified\n");
1094                 return ret;
1095         }
1096
1097         bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
1098         if (IS_ERR(bdev->bamclk))
1099                 return PTR_ERR(bdev->bamclk);
1100
1101         ret = clk_prepare_enable(bdev->bamclk);
1102         if (ret) {
1103                 dev_err(bdev->dev, "failed to prepare/enable clock\n");
1104                 return ret;
1105         }
1106
1107         ret = bam_init(bdev);
1108         if (ret)
1109                 goto err_disable_clk;
1110
1111         tasklet_init(&bdev->task, dma_tasklet, (unsigned long)bdev);
1112
1113         bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
1114                                 sizeof(*bdev->channels), GFP_KERNEL);
1115
1116         if (!bdev->channels) {
1117                 ret = -ENOMEM;
1118                 goto err_disable_clk;
1119         }
1120
1121         /* allocate and initialize channels */
1122         INIT_LIST_HEAD(&bdev->common.channels);
1123
1124         for (i = 0; i < bdev->num_channels; i++)
1125                 bam_channel_init(bdev, &bdev->channels[i], i);
1126
1127         ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
1128                         IRQF_TRIGGER_HIGH, "bam_dma", bdev);
1129         if (ret)
1130                 goto err_disable_clk;
1131
1132         /* set max dma segment size */
1133         bdev->common.dev = bdev->dev;
1134         bdev->common.dev->dma_parms = &bdev->dma_parms;
1135         ret = dma_set_max_seg_size(bdev->common.dev, BAM_MAX_DATA_SIZE);
1136         if (ret) {
1137                 dev_err(bdev->dev, "cannot set maximum segment size\n");
1138                 goto err_disable_clk;
1139         }
1140
1141         platform_set_drvdata(pdev, bdev);
1142
1143         /* set capabilities */
1144         dma_cap_zero(bdev->common.cap_mask);
1145         dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
1146
1147         /* initialize dmaengine apis */
1148         bdev->common.device_alloc_chan_resources = bam_alloc_chan;
1149         bdev->common.device_free_chan_resources = bam_free_chan;
1150         bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
1151         bdev->common.device_control = bam_control;
1152         bdev->common.device_issue_pending = bam_issue_pending;
1153         bdev->common.device_tx_status = bam_tx_status;
1154         bdev->common.dev = bdev->dev;
1155
1156         ret = dma_async_device_register(&bdev->common);
1157         if (ret) {
1158                 dev_err(bdev->dev, "failed to register dma async device\n");
1159                 goto err_disable_clk;
1160         }
1161
1162         ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
1163                                         &bdev->common);
1164         if (ret)
1165                 goto err_unregister_dma;
1166
1167         return 0;
1168
1169 err_unregister_dma:
1170         dma_async_device_unregister(&bdev->common);
1171 err_disable_clk:
1172         clk_disable_unprepare(bdev->bamclk);
1173         return ret;
1174 }
1175
1176 static int bam_dma_remove(struct platform_device *pdev)
1177 {
1178         struct bam_device *bdev = platform_get_drvdata(pdev);
1179         u32 i;
1180
1181         of_dma_controller_free(pdev->dev.of_node);
1182         dma_async_device_unregister(&bdev->common);
1183
1184         /* mask all interrupts for this execution environment */
1185         writel_relaxed(0, bam_addr(bdev, 0,  BAM_IRQ_SRCS_MSK_EE));
1186
1187         devm_free_irq(bdev->dev, bdev->irq, bdev);
1188
1189         for (i = 0; i < bdev->num_channels; i++) {
1190                 bam_dma_terminate_all(&bdev->channels[i]);
1191                 tasklet_kill(&bdev->channels[i].vc.task);
1192
1193                 dma_free_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE,
1194                         bdev->channels[i].fifo_virt,
1195                         bdev->channels[i].fifo_phys);
1196         }
1197
1198         tasklet_kill(&bdev->task);
1199
1200         clk_disable_unprepare(bdev->bamclk);
1201
1202         return 0;
1203 }
1204
1205 static struct platform_driver bam_dma_driver = {
1206         .probe = bam_dma_probe,
1207         .remove = bam_dma_remove,
1208         .driver = {
1209                 .name = "bam-dma-engine",
1210                 .of_match_table = bam_of_match,
1211         },
1212 };
1213
1214 module_platform_driver(bam_dma_driver);
1215
1216 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
1217 MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
1218 MODULE_LICENSE("GPL v2");