drivers/dma/sun6i-dma.c

   1 /*
   2  * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
   3  * Author: Sugar <shuge@allwinnertech.com>
   4  *
   5  * Copyright (C) 2014 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/reset.h>
  23 #include <linux/slab.h>
  24 #include <linux/types.h>
  25
  26 #include "virt-dma.h"
  27
  28 /*
  29  * There's 16 physical channels that can work in parallel.
  30  *
  31  * However we have 30 different endpoints for our requests.
  32  *
  33  * Since the channels are able to handle only an unidirectional
  34  * transfer, we need to allocate more virtual channels so that
  35  * everyone can grab one channel.
  36  *
  37  * Some devices can't work in both direction (mostly because it
  38  * wouldn't make sense), so we have a bit fewer virtual channels than
  39  * 2 channels per endpoints.
  40  */
  41
  42 #define NR_MAX_CHANNELS         16
  43 #define NR_MAX_REQUESTS         30
  44 #define NR_MAX_VCHANS           53
  45
  46 /*
  47  * Common registers
  48  */
  49 #define DMA_IRQ_EN(x)           ((x) * 0x04)
  50 #define DMA_IRQ_HALF                    BIT(0)
  51 #define DMA_IRQ_PKG                     BIT(1)
  52 #define DMA_IRQ_QUEUE                   BIT(2)
  53
  54 #define DMA_IRQ_CHAN_NR                 8
  55 #define DMA_IRQ_CHAN_WIDTH              4
  56
  57
  58 #define DMA_IRQ_STAT(x)         ((x) * 0x04 + 0x10)
  59
  60 #define DMA_STAT                0x30
  61
  62 /*
  63  * Channels specific registers
  64  */
  65 #define DMA_CHAN_ENABLE         0x00
  66 #define DMA_CHAN_ENABLE_START           BIT(0)
  67 #define DMA_CHAN_ENABLE_STOP            0
  68
  69 #define DMA_CHAN_PAUSE          0x04
  70 #define DMA_CHAN_PAUSE_PAUSE            BIT(1)
  71 #define DMA_CHAN_PAUSE_RESUME           0
  72
  73 #define DMA_CHAN_LLI_ADDR       0x08
  74
  75 #define DMA_CHAN_CUR_CFG        0x0c
  76 #define DMA_CHAN_CFG_SRC_DRQ(x)         ((x) & 0x1f)
  77 #define DMA_CHAN_CFG_SRC_IO_MODE        BIT(5)
  78 #define DMA_CHAN_CFG_SRC_LINEAR_MODE    (0 << 5)
  79 #define DMA_CHAN_CFG_SRC_BURST(x)       (((x) & 0x3) << 7)
  80 #define DMA_CHAN_CFG_SRC_WIDTH(x)       (((x) & 0x3) << 9)
  81
  82 #define DMA_CHAN_CFG_DST_DRQ(x)         (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
  83 #define DMA_CHAN_CFG_DST_IO_MODE        (DMA_CHAN_CFG_SRC_IO_MODE << 16)
  84 #define DMA_CHAN_CFG_DST_LINEAR_MODE    (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
  85 #define DMA_CHAN_CFG_DST_BURST(x)       (DMA_CHAN_CFG_SRC_BURST(x) << 16)
  86 #define DMA_CHAN_CFG_DST_WIDTH(x)       (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
  87
  88 #define DMA_CHAN_CUR_SRC        0x10
  89
  90 #define DMA_CHAN_CUR_DST        0x14
  91
  92 #define DMA_CHAN_CUR_CNT        0x18
  93
  94 #define DMA_CHAN_CUR_PARA       0x1c
  95
  96
  97 /*
  98  * Various hardware related defines
  99  */
 100 #define LLI_LAST_ITEM   0xfffff800
 101 #define NORMAL_WAIT     8
 102 #define DRQ_SDRAM       1
 103
 104 /*
 105  * Hardware representation of the LLI
 106  *
 107  * The hardware will be fed the physical address of this structure,
 108  * and read its content in order to start the transfer.
 109  */
 110 struct sun6i_dma_lli {
 111         u32                     cfg;
 112         u32                     src;
 113         u32                     dst;
 114         u32                     len;
 115         u32                     para;
 116         u32                     p_lli_next;
 117
 118         /*
 119          * This field is not used by the DMA controller, but will be
 120          * used by the CPU to go through the list (mostly for dumping
 121          * or freeing it).
 122          */
 123         struct sun6i_dma_lli    *v_lli_next;
 124 };
 125
 126
 127 struct sun6i_desc {
 128         struct virt_dma_desc    vd;
 129         dma_addr_t              p_lli;
 130         struct sun6i_dma_lli    *v_lli;
 131 };
 132
 133 struct sun6i_pchan {
 134         u32                     idx;
 135         void __iomem            *base;
 136         struct sun6i_vchan      *vchan;
 137         struct sun6i_desc       *desc;
 138         struct sun6i_desc       *done;
 139 };
 140
 141 struct sun6i_vchan {
 142         struct virt_dma_chan    vc;
 143         struct list_head        node;
 144         struct dma_slave_config cfg;
 145         struct sun6i_pchan      *phy;
 146         u8                      port;
 147 };
 148
 149 struct sun6i_dma_dev {
 150         struct dma_device       slave;
 151         void __iomem            *base;
 152         struct clk              *clk;
 153         int                     irq;
 154         spinlock_t              lock;
 155         struct reset_control    *rstc;
 156         struct tasklet_struct   task;
 157         atomic_t                tasklet_shutdown;
 158         struct list_head        pending;
 159         struct dma_pool         *pool;
 160         struct sun6i_pchan      *pchans;
 161         struct sun6i_vchan      *vchans;
 162 };
 163
 164 static struct device *chan2dev(struct dma_chan *chan)
 165 {
 166         return &chan->dev->device;
 167 }
 168
 169 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
 170 {
 171         return container_of(d, struct sun6i_dma_dev, slave);
 172 }
 173
 174 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
 175 {
 176         return container_of(chan, struct sun6i_vchan, vc.chan);
 177 }
 178
 179 static inline struct sun6i_desc *
 180 to_sun6i_desc(struct dma_async_tx_descriptor *tx)
 181 {
 182         return container_of(tx, struct sun6i_desc, vd.tx);
 183 }
 184
 185 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
 186 {
 187         dev_dbg(sdev->slave.dev, "Common register:\n"
 188                 "\tmask0(%04x): 0x%08x\n"
 189                 "\tmask1(%04x): 0x%08x\n"
 190                 "\tpend0(%04x): 0x%08x\n"
 191                 "\tpend1(%04x): 0x%08x\n"
 192                 "\tstats(%04x): 0x%08x\n",
 193                 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
 194                 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
 195                 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
 196                 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
 197                 DMA_STAT, readl(sdev->base + DMA_STAT));
 198 }
 199
 200 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
 201                                             struct sun6i_pchan *pchan)
 202 {
 203         phys_addr_t reg = virt_to_phys(pchan->base);
 204
 205         dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n"
 206                 "\t___en(%04x): \t0x%08x\n"
 207                 "\tpause(%04x): \t0x%08x\n"
 208                 "\tstart(%04x): \t0x%08x\n"
 209                 "\t__cfg(%04x): \t0x%08x\n"
 210                 "\t__src(%04x): \t0x%08x\n"
 211                 "\t__dst(%04x): \t0x%08x\n"
 212                 "\tcount(%04x): \t0x%08x\n"
 213                 "\t_para(%04x): \t0x%08x\n\n",
 214                 pchan->idx, &reg,
 215                 DMA_CHAN_ENABLE,
 216                 readl(pchan->base + DMA_CHAN_ENABLE),
 217                 DMA_CHAN_PAUSE,
 218                 readl(pchan->base + DMA_CHAN_PAUSE),
 219                 DMA_CHAN_LLI_ADDR,
 220                 readl(pchan->base + DMA_CHAN_LLI_ADDR),
 221                 DMA_CHAN_CUR_CFG,
 222                 readl(pchan->base + DMA_CHAN_CUR_CFG),
 223                 DMA_CHAN_CUR_SRC,
 224                 readl(pchan->base + DMA_CHAN_CUR_SRC),
 225                 DMA_CHAN_CUR_DST,
 226                 readl(pchan->base + DMA_CHAN_CUR_DST),
 227                 DMA_CHAN_CUR_CNT,
 228                 readl(pchan->base + DMA_CHAN_CUR_CNT),
 229                 DMA_CHAN_CUR_PARA,
 230                 readl(pchan->base + DMA_CHAN_CUR_PARA));
 231 }
 232
 233 static inline s8 convert_burst(u32 maxburst)
 234 {
 235         switch (maxburst) {
 236         case 1:
 237                 return 0;
 238         case 8:
 239                 return 2;
 240         default:
 241                 return -EINVAL;
 242         }
 243 }
 244
 245 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
 246 {
 247         if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
 248             (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
 249                 return -EINVAL;
 250
 251         return addr_width >> 1;
 252 }
 253
 254 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
 255                                struct sun6i_dma_lli *next,
 256                                dma_addr_t next_phy,
 257                                struct sun6i_desc *txd)
 258 {
 259         if ((!prev && !txd) || !next)
 260                 return NULL;
 261
 262         if (!prev) {
 263                 txd->p_lli = next_phy;
 264                 txd->v_lli = next;
 265         } else {
 266                 prev->p_lli_next = next_phy;
 267                 prev->v_lli_next = next;
 268         }
 269
 270         next->p_lli_next = LLI_LAST_ITEM;
 271         next->v_lli_next = NULL;
 272
 273         return next;
 274 }
 275
 276 static inline int sun6i_dma_cfg_lli(struct sun6i_dma_lli *lli,
 277                                     dma_addr_t src,
 278                                     dma_addr_t dst, u32 len,
 279                                     struct dma_slave_config *config)
 280 {
 281         u8 src_width, dst_width, src_burst, dst_burst;
 282
 283         if (!config)
 284                 return -EINVAL;
 285
 286         src_burst = convert_burst(config->src_maxburst);
 287         if (src_burst)
 288                 return src_burst;
 289
 290         dst_burst = convert_burst(config->dst_maxburst);
 291         if (dst_burst)
 292                 return dst_burst;
 293
 294         src_width = convert_buswidth(config->src_addr_width);
 295         if (src_width)
 296                 return src_width;
 297
 298         dst_width = convert_buswidth(config->dst_addr_width);
 299         if (dst_width)
 300                 return dst_width;
 301
 302         lli->cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
 303                 DMA_CHAN_CFG_SRC_WIDTH(src_width) |
 304                 DMA_CHAN_CFG_DST_BURST(dst_burst) |
 305                 DMA_CHAN_CFG_DST_WIDTH(dst_width);
 306
 307         lli->src = src;
 308         lli->dst = dst;
 309         lli->len = len;
 310         lli->para = NORMAL_WAIT;
 311
 312         return 0;
 313 }
 314
 315 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
 316                                       struct sun6i_dma_lli *lli)
 317 {
 318         phys_addr_t p_lli = virt_to_phys(lli);
 319
 320         dev_dbg(chan2dev(&vchan->vc.chan),
 321                 "\n\tdesc:   p - %pa v - 0x%p\n"
 322                 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
 323                 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
 324                 &p_lli, lli,
 325                 lli->cfg, lli->src, lli->dst,
 326                 lli->len, lli->para, lli->p_lli_next);
 327 }
 328
 329 static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
 330 {
 331         struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
 332         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
 333         struct sun6i_dma_lli *v_lli, *v_next;
 334         dma_addr_t p_lli, p_next;
 335
 336         if (unlikely(!txd))
 337                 return;
 338
 339         p_lli = txd->p_lli;
 340         v_lli = txd->v_lli;
 341
 342         while (v_lli) {
 343                 v_next = v_lli->v_lli_next;
 344                 p_next = v_lli->p_lli_next;
 345
 346                 dma_pool_free(sdev->pool, v_lli, p_lli);
 347
 348                 v_lli = v_next;
 349                 p_lli = p_next;
 350         }
 351
 352         kfree(txd);
 353 }
 354
 355 static int sun6i_dma_terminate_all(struct sun6i_vchan *vchan)
 356 {
 357         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
 358         struct sun6i_pchan *pchan = vchan->phy;
 359         unsigned long flags;
 360         LIST_HEAD(head);
 361
 362         spin_lock(&sdev->lock);
 363         list_del_init(&vchan->node);
 364         spin_unlock(&sdev->lock);
 365
 366         spin_lock_irqsave(&vchan->vc.lock, flags);
 367
 368         vchan_get_all_descriptors(&vchan->vc, &head);
 369
 370         if (pchan) {
 371                 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
 372                 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
 373
 374                 vchan->phy = NULL;
 375                 pchan->vchan = NULL;
 376                 pchan->desc = NULL;
 377                 pchan->done = NULL;
 378         }
 379
 380         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 381
 382         vchan_dma_desc_free_list(&vchan->vc, &head);
 383
 384         return 0;
 385 }
 386
 387 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
 388 {
 389         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
 390         struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
 391         struct sun6i_pchan *pchan = vchan->phy;
 392         u32 irq_val, irq_reg, irq_offset;
 393
 394         if (!pchan)
 395                 return -EAGAIN;
 396
 397         if (!desc) {
 398                 pchan->desc = NULL;
 399                 pchan->done = NULL;
 400                 return -EAGAIN;
 401         }
 402
 403         list_del(&desc->node);
 404
 405         pchan->desc = to_sun6i_desc(&desc->tx);
 406         pchan->done = NULL;
 407
 408         sun6i_dma_dump_lli(vchan, pchan->desc->v_lli);
 409
 410         irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
 411         irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
 412
 413         irq_val = readl(sdev->base + DMA_IRQ_EN(irq_offset));
 414         irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH);
 415         writel(irq_val, sdev->base + DMA_IRQ_EN(irq_offset));
 416
 417         writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
 418         writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
 419
 420         sun6i_dma_dump_com_regs(sdev);
 421         sun6i_dma_dump_chan_regs(sdev, pchan);
 422
 423         return 0;
 424 }
 425
 426 static void sun6i_dma_tasklet(unsigned long data)
 427 {
 428         struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data;
 429         struct sun6i_vchan *vchan;
 430         struct sun6i_pchan *pchan;
 431         unsigned int pchan_alloc = 0;
 432         unsigned int pchan_idx;
 433
 434         list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
 435                 spin_lock_irq(&vchan->vc.lock);
 436
 437                 pchan = vchan->phy;
 438
 439                 if (pchan && pchan->done) {
 440                         if (sun6i_dma_start_desc(vchan)) {
 441                                 /*
 442                                  * No current txd associated with this channel
 443                                  */
 444                                 dev_dbg(sdev->slave.dev, "pchan %u: free\n",
 445                                         pchan->idx);
 446
 447                                 /* Mark this channel free */
 448                                 vchan->phy = NULL;
 449                                 pchan->vchan = NULL;
 450                         }
 451                 }
 452                 spin_unlock_irq(&vchan->vc.lock);
 453         }
 454
 455         spin_lock_irq(&sdev->lock);
 456         for (pchan_idx = 0; pchan_idx < NR_MAX_CHANNELS; pchan_idx++) {
 457                 pchan = &sdev->pchans[pchan_idx];
 458
 459                 if (pchan->vchan || list_empty(&sdev->pending))
 460                         continue;
 461
 462                 vchan = list_first_entry(&sdev->pending,
 463                                          struct sun6i_vchan, node);
 464
 465                 /* Remove from pending channels */
 466                 list_del_init(&vchan->node);
 467                 pchan_alloc |= BIT(pchan_idx);
 468
 469                 /* Mark this channel allocated */
 470                 pchan->vchan = vchan;
 471                 vchan->phy = pchan;
 472                 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
 473                         pchan->idx, &vchan->vc);
 474         }
 475         spin_unlock_irq(&sdev->lock);
 476
 477         for (pchan_idx = 0; pchan_idx < NR_MAX_CHANNELS; pchan_idx++) {
 478                 if (!(pchan_alloc & BIT(pchan_idx)))
 479                         continue;
 480
 481                 pchan = sdev->pchans + pchan_idx;
 482                 vchan = pchan->vchan;
 483                 if (vchan) {
 484                         spin_lock_irq(&vchan->vc.lock);
 485                         sun6i_dma_start_desc(vchan);
 486                         spin_unlock_irq(&vchan->vc.lock);
 487                 }
 488         }
 489 }
 490
 491 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
 492 {
 493         struct sun6i_dma_dev *sdev = dev_id;
 494         struct sun6i_vchan *vchan;
 495         struct sun6i_pchan *pchan;
 496         int i, j, ret = IRQ_NONE;
 497         u32 status;
 498
 499         for (i = 0; i < 2; i++) {
 500                 status = readl(sdev->base + DMA_IRQ_STAT(i));
 501                 if (!status)
 502                         continue;
 503
 504                 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
 505                         i ? "high" : "low", status);
 506
 507                 writel(status, sdev->base + DMA_IRQ_STAT(i));
 508
 509                 for (j = 0; (j < 8) && status; j++) {
 510                         if (status & DMA_IRQ_QUEUE) {
 511                                 pchan = sdev->pchans + j;
 512                                 vchan = pchan->vchan;
 513
 514                                 if (vchan) {
 515                                         spin_lock(&vchan->vc.lock);
 516                                         vchan_cookie_complete(&pchan->desc->vd);
 517                                         pchan->done = pchan->desc;
 518                                         spin_unlock(&vchan->vc.lock);
 519                                 }
 520                         }
 521
 522                         status = status >> 4;
 523                 }
 524
 525                 if (!atomic_read(&sdev->tasklet_shutdown))
 526                         tasklet_schedule(&sdev->task);
 527                 ret = IRQ_HANDLED;
 528         }
 529
 530         return ret;
 531 }
 532
 533 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
 534                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 535                 size_t len, unsigned long flags)
 536 {
 537         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 538         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 539         struct sun6i_dma_lli *v_lli;
 540         struct sun6i_desc *txd;
 541         dma_addr_t p_lli;
 542         s8 burst, width;
 543
 544         dev_dbg(chan2dev(chan),
 545                 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
 546                 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
 547
 548         if (!len)
 549                 return NULL;
 550
 551         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 552         if (!txd)
 553                 return NULL;
 554
 555         v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 556         if (!v_lli) {
 557                 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
 558                 goto err_txd_free;
 559         }
 560
 561         v_lli->src = src;
 562         v_lli->dst = dest;
 563         v_lli->len = len;
 564         v_lli->para = NORMAL_WAIT;
 565
 566         burst = convert_burst(8);
 567         width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
 568         v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 569                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 570                 DMA_CHAN_CFG_DST_LINEAR_MODE |
 571                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 572                 DMA_CHAN_CFG_SRC_BURST(burst) |
 573                 DMA_CHAN_CFG_SRC_WIDTH(width) |
 574                 DMA_CHAN_CFG_DST_BURST(burst) |
 575                 DMA_CHAN_CFG_DST_WIDTH(width);
 576
 577         sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
 578
 579         sun6i_dma_dump_lli(vchan, v_lli);
 580
 581         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 582
 583 err_txd_free:
 584         kfree(txd);
 585         return NULL;
 586 }
 587
 588 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
 589                 struct dma_chan *chan, struct scatterlist *sgl,
 590                 unsigned int sg_len, enum dma_transfer_direction dir,
 591                 unsigned long flags, void *context)
 592 {
 593         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 594         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 595         struct dma_slave_config *sconfig = &vchan->cfg;
 596         struct sun6i_dma_lli *v_lli, *prev = NULL;
 597         struct sun6i_desc *txd;
 598         struct scatterlist *sg;
 599         dma_addr_t p_lli;
 600         int i, ret;
 601
 602         if (!sgl)
 603                 return NULL;
 604
 605         if (!is_slave_direction(dir)) {
 606                 dev_err(chan2dev(chan), "Invalid DMA direction\n");
 607                 return NULL;
 608         }
 609
 610         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 611         if (!txd)
 612                 return NULL;
 613
 614         for_each_sg(sgl, sg, sg_len, i) {
 615                 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 616                 if (!v_lli)
 617                         goto err_lli_free;
 618
 619                 if (dir == DMA_MEM_TO_DEV) {
 620                         ret = sun6i_dma_cfg_lli(v_lli, sg_dma_address(sg),
 621                                                 sconfig->dst_addr, sg_dma_len(sg),
 622                                                 sconfig);
 623                         if (ret)
 624                                 goto err_cur_lli_free;
 625
 626                         v_lli->cfg |= DMA_CHAN_CFG_DST_IO_MODE |
 627                                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 628                                 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 629                                 DMA_CHAN_CFG_DST_DRQ(vchan->port);
 630
 631                         dev_dbg(chan2dev(chan),
 632                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
 633                                 __func__, vchan->vc.chan.chan_id,
 634                                 &sconfig->dst_addr, &sg_dma_address(sg),
 635                                 sg_dma_len(sg), flags);
 636
 637                 } else {
 638                         ret = sun6i_dma_cfg_lli(v_lli, sconfig->src_addr,
 639                                                 sg_dma_address(sg), sg_dma_len(sg),
 640                                                 sconfig);
 641                         if (ret)
 642                                 goto err_cur_lli_free;
 643
 644                         v_lli->cfg |= DMA_CHAN_CFG_DST_LINEAR_MODE |
 645                                 DMA_CHAN_CFG_SRC_IO_MODE |
 646                                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 647                                 DMA_CHAN_CFG_SRC_DRQ(vchan->port);
 648
 649                         dev_dbg(chan2dev(chan),
 650                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
 651                                 __func__, vchan->vc.chan.chan_id,
 652                                 &sg_dma_address(sg), &sconfig->src_addr,
 653                                 sg_dma_len(sg), flags);
 654                 }
 655
 656                 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
 657         }
 658
 659         dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
 660         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 661                 sun6i_dma_dump_lli(vchan, prev);
 662
 663         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 664
 665 err_cur_lli_free:
 666         dma_pool_free(sdev->pool, v_lli, p_lli);
 667 err_lli_free:
 668         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 669                 dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
 670         kfree(txd);
 671         return NULL;
 672 }
 673
 674 static int sun6i_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 675                        unsigned long arg)
 676 {
 677         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 678         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 679         struct sun6i_pchan *pchan = vchan->phy;
 680         unsigned long flags;
 681         int ret = 0;
 682
 683         switch (cmd) {
 684         case DMA_RESUME:
 685                 dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
 686
 687                 spin_lock_irqsave(&vchan->vc.lock, flags);
 688
 689                 if (pchan) {
 690                         writel(DMA_CHAN_PAUSE_RESUME,
 691                                pchan->base + DMA_CHAN_PAUSE);
 692                 } else if (!list_empty(&vchan->vc.desc_issued)) {
 693                         spin_lock(&sdev->lock);
 694                         list_add_tail(&vchan->node, &sdev->pending);
 695                         spin_unlock(&sdev->lock);
 696                 }
 697
 698                 spin_unlock_irqrestore(&vchan->vc.lock, flags);
 699                 break;
 700
 701         case DMA_PAUSE:
 702                 dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
 703
 704                 if (pchan) {
 705                         writel(DMA_CHAN_PAUSE_PAUSE,
 706                                pchan->base + DMA_CHAN_PAUSE);
 707                 } else {
 708                         spin_lock(&sdev->lock);
 709                         list_del_init(&vchan->node);
 710                         spin_unlock(&sdev->lock);
 711                 }
 712                 break;
 713
 714         case DMA_TERMINATE_ALL:
 715                 ret = sun6i_dma_terminate_all(vchan);
 716                 break;
 717         case DMA_SLAVE_CONFIG:
 718                 memcpy(&vchan->cfg, (void *)arg, sizeof(struct dma_slave_config));
 719                 break;
 720         default:
 721                 ret = -ENXIO;
 722                 break;
 723         }
 724         return ret;
 725 }
 726
 727 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
 728                                            dma_cookie_t cookie,
 729                                            struct dma_tx_state *state)
 730 {
 731         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 732         struct sun6i_pchan *pchan = vchan->phy;
 733         struct sun6i_dma_lli *lli;
 734         struct virt_dma_desc *vd;
 735         struct sun6i_desc *txd;
 736         enum dma_status ret;
 737         unsigned long flags;
 738         size_t bytes = 0;
 739
 740         ret = dma_cookie_status(chan, cookie, state);
 741         if (ret == DMA_COMPLETE)
 742                 return ret;
 743
 744         spin_lock_irqsave(&vchan->vc.lock, flags);
 745
 746         vd = vchan_find_desc(&vchan->vc, cookie);
 747         txd = to_sun6i_desc(&vd->tx);
 748
 749         if (vd) {
 750                 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
 751                         bytes += lli->len;
 752         } else if (!pchan || !pchan->desc) {
 753                 bytes = 0;
 754         } else {
 755                 bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
 756         }
 757
 758         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 759
 760         dma_set_residue(state, bytes);
 761
 762         return ret;
 763 }
 764
 765 static void sun6i_dma_issue_pending(struct dma_chan *chan)
 766 {
 767         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 768         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 769         unsigned long flags;
 770
 771         spin_lock_irqsave(&vchan->vc.lock, flags);
 772
 773         if (vchan_issue_pending(&vchan->vc)) {
 774                 spin_lock(&sdev->lock);
 775
 776                 if (!vchan->phy && list_empty(&vchan->node)) {
 777                         list_add_tail(&vchan->node, &sdev->pending);
 778                         tasklet_schedule(&sdev->task);
 779                         dev_dbg(chan2dev(chan), "vchan %p: issued\n",
 780                                 &vchan->vc);
 781                 }
 782
 783                 spin_unlock(&sdev->lock);
 784         } else {
 785                 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
 786                         &vchan->vc);
 787         }
 788
 789         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 790 }
 791
 792 static int sun6i_dma_alloc_chan_resources(struct dma_chan *chan)
 793 {
 794         return 0;
 795 }
 796
 797 static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
 798 {
 799         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 800         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 801         unsigned long flags;
 802
 803         spin_lock_irqsave(&sdev->lock, flags);
 804         list_del_init(&vchan->node);
 805         spin_unlock_irqrestore(&sdev->lock, flags);
 806
 807         vchan_free_chan_resources(&vchan->vc);
 808 }
 809
 810 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
 811                                            struct of_dma *ofdma)
 812 {
 813         struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
 814         struct sun6i_vchan *vchan;
 815         struct dma_chan *chan;
 816         u8 port = dma_spec->args[0];
 817
 818         if (port > NR_MAX_REQUESTS)
 819                 return NULL;
 820
 821         chan = dma_get_any_slave_channel(&sdev->slave);
 822         if (!chan)
 823                 return NULL;
 824
 825         vchan = to_sun6i_vchan(chan);
 826         vchan->port = port;
 827
 828         return chan;
 829 }
 830
 831 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
 832 {
 833         /* Disable all interrupts from DMA */
 834         writel(0, sdev->base + DMA_IRQ_EN(0));
 835         writel(0, sdev->base + DMA_IRQ_EN(1));
 836
 837         /* Prevent spurious interrupts from scheduling the tasklet */
 838         atomic_inc(&sdev->tasklet_shutdown);
 839
 840         /* Make sure we won't have any further interrupts */
 841         devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
 842
 843         /* Actually prevent the tasklet from being scheduled */
 844         tasklet_kill(&sdev->task);
 845 }
 846
 847 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
 848 {
 849         int i;
 850
 851         for (i = 0; i < NR_MAX_VCHANS; i++) {
 852                 struct sun6i_vchan *vchan = &sdev->vchans[i];
 853
 854                 list_del(&vchan->vc.chan.device_node);
 855                 tasklet_kill(&vchan->vc.task);
 856         }
 857 }
 858
 859 static int sun6i_dma_probe(struct platform_device *pdev)
 860 {
 861         struct sun6i_dma_dev *sdc;
 862         struct resource *res;
 863         int ret, i;
 864
 865         sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
 866         if (!sdc)
 867                 return -ENOMEM;
 868
 869         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 870         sdc->base = devm_ioremap_resource(&pdev->dev, res);
 871         if (IS_ERR(sdc->base))
 872                 return PTR_ERR(sdc->base);
 873
 874         sdc->irq = platform_get_irq(pdev, 0);
 875         if (sdc->irq < 0) {
 876                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 877                 return sdc->irq;
 878         }
 879
 880         sdc->clk = devm_clk_get(&pdev->dev, NULL);
 881         if (IS_ERR(sdc->clk)) {
 882                 dev_err(&pdev->dev, "No clock specified\n");
 883                 return PTR_ERR(sdc->clk);
 884         }
 885
 886         sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
 887         if (IS_ERR(sdc->rstc)) {
 888                 dev_err(&pdev->dev, "No reset controller specified\n");
 889                 return PTR_ERR(sdc->rstc);
 890         }
 891
 892         sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
 893                                      sizeof(struct sun6i_dma_lli), 4, 0);
 894         if (!sdc->pool) {
 895                 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
 896                 return -ENOMEM;
 897         }
 898
 899         platform_set_drvdata(pdev, sdc);
 900         INIT_LIST_HEAD(&sdc->pending);
 901         spin_lock_init(&sdc->lock);
 902
 903         dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
 904         dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
 905         dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
 906
 907         INIT_LIST_HEAD(&sdc->slave.channels);
 908         sdc->slave.device_alloc_chan_resources  = sun6i_dma_alloc_chan_resources;
 909         sdc->slave.device_free_chan_resources   = sun6i_dma_free_chan_resources;
 910         sdc->slave.device_tx_status             = sun6i_dma_tx_status;
 911         sdc->slave.device_issue_pending         = sun6i_dma_issue_pending;
 912         sdc->slave.device_prep_slave_sg         = sun6i_dma_prep_slave_sg;
 913         sdc->slave.device_prep_dma_memcpy       = sun6i_dma_prep_dma_memcpy;
 914         sdc->slave.device_control               = sun6i_dma_control;
 915         sdc->slave.chancnt                      = NR_MAX_VCHANS;
 916         sdc->slave.copy_align                   = 4;
 917
 918         sdc->slave.dev = &pdev->dev;
 919
 920         sdc->pchans = devm_kcalloc(&pdev->dev, NR_MAX_CHANNELS,
 921                                    sizeof(struct sun6i_pchan), GFP_KERNEL);
 922         if (!sdc->pchans)
 923                 return -ENOMEM;
 924
 925         sdc->vchans = devm_kcalloc(&pdev->dev, NR_MAX_VCHANS,
 926                                    sizeof(struct sun6i_vchan), GFP_KERNEL);
 927         if (!sdc->vchans)
 928                 return -ENOMEM;
 929
 930         tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc);
 931
 932         for (i = 0; i < NR_MAX_CHANNELS; i++) {
 933                 struct sun6i_pchan *pchan = &sdc->pchans[i];
 934
 935                 pchan->idx = i;
 936                 pchan->base = sdc->base + 0x100 + i * 0x40;
 937         }
 938
 939         for (i = 0; i < NR_MAX_VCHANS; i++) {
 940                 struct sun6i_vchan *vchan = &sdc->vchans[i];
 941
 942                 INIT_LIST_HEAD(&vchan->node);
 943                 vchan->vc.desc_free = sun6i_dma_free_desc;
 944                 vchan_init(&vchan->vc, &sdc->slave);
 945         }
 946
 947         ret = reset_control_deassert(sdc->rstc);
 948         if (ret) {
 949                 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
 950                 goto err_chan_free;
 951         }
 952
 953         ret = clk_prepare_enable(sdc->clk);
 954         if (ret) {
 955                 dev_err(&pdev->dev, "Couldn't enable the clock\n");
 956                 goto err_reset_assert;
 957         }
 958
 959         ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
 960                                dev_name(&pdev->dev), sdc);
 961         if (ret) {
 962                 dev_err(&pdev->dev, "Cannot request IRQ\n");
 963                 goto err_clk_disable;
 964         }
 965
 966         ret = dma_async_device_register(&sdc->slave);
 967         if (ret) {
 968                 dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
 969                 goto err_irq_disable;
 970         }
 971
 972         ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
 973                                          sdc);
 974         if (ret) {
 975                 dev_err(&pdev->dev, "of_dma_controller_register failed\n");
 976                 goto err_dma_unregister;
 977         }
 978
 979         return 0;
 980
 981 err_dma_unregister:
 982         dma_async_device_unregister(&sdc->slave);
 983 err_irq_disable:
 984         sun6i_kill_tasklet(sdc);
 985 err_clk_disable:
 986         clk_disable_unprepare(sdc->clk);
 987 err_reset_assert:
 988         reset_control_assert(sdc->rstc);
 989 err_chan_free:
 990         sun6i_dma_free(sdc);
 991         return ret;
 992 }
 993
 994 static int sun6i_dma_remove(struct platform_device *pdev)
 995 {
 996         struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
 997
 998         of_dma_controller_free(pdev->dev.of_node);
 999         dma_async_device_unregister(&sdc->slave);
1000
1001         sun6i_kill_tasklet(sdc);
1002
1003         clk_disable_unprepare(sdc->clk);
1004         reset_control_assert(sdc->rstc);
1005
1006         sun6i_dma_free(sdc);
1007
1008         return 0;
1009 }
1010
1011 static struct of_device_id sun6i_dma_match[] = {
1012         { .compatible = "allwinner,sun6i-a31-dma" },
1013         { /* sentinel */ }
1014 };
1015
1016 static struct platform_driver sun6i_dma_driver = {
1017         .probe          = sun6i_dma_probe,
1018         .remove         = sun6i_dma_remove,
1019         .driver = {
1020                 .name           = "sun6i-dma",
1021                 .of_match_table = sun6i_dma_match,
1022         },
1023 };
1024 module_platform_driver(sun6i_dma_driver);
1025
1026 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
1027 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
1028 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1029 MODULE_LICENSE("GPL");