drivers/dma/txx9dmac.c

   1 /*
   2  * Driver for the TXx9 SoC DMA Controller
   3  *
   4  * Copyright (C) 2009 Atsushi Nemoto
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/dma-mapping.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/slab.h>
  17 #include <linux/scatterlist.h>
  18
  19 #include "dmaengine.h"
  20 #include "txx9dmac.h"
  21
  22 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
  23 {
  24         return container_of(chan, struct txx9dmac_chan, chan);
  25 }
  26
  27 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
  28 {
  29         return dc->ch_regs;
  30 }
  31
  32 static struct txx9dmac_cregs32 __iomem *__dma_regs32(
  33         const struct txx9dmac_chan *dc)
  34 {
  35         return dc->ch_regs;
  36 }
  37
  38 #define channel64_readq(dc, name) \
  39         __raw_readq(&(__dma_regs(dc)->name))
  40 #define channel64_writeq(dc, name, val) \
  41         __raw_writeq((val), &(__dma_regs(dc)->name))
  42 #define channel64_readl(dc, name) \
  43         __raw_readl(&(__dma_regs(dc)->name))
  44 #define channel64_writel(dc, name, val) \
  45         __raw_writel((val), &(__dma_regs(dc)->name))
  46
  47 #define channel32_readl(dc, name) \
  48         __raw_readl(&(__dma_regs32(dc)->name))
  49 #define channel32_writel(dc, name, val) \
  50         __raw_writel((val), &(__dma_regs32(dc)->name))
  51
  52 #define channel_readq(dc, name) channel64_readq(dc, name)
  53 #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
  54 #define channel_readl(dc, name) \
  55         (is_dmac64(dc) ? \
  56          channel64_readl(dc, name) : channel32_readl(dc, name))
  57 #define channel_writel(dc, name, val) \
  58         (is_dmac64(dc) ? \
  59          channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
  60
  61 static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
  62 {
  63         if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
  64                 return channel64_readq(dc, CHAR);
  65         else
  66                 return channel64_readl(dc, CHAR);
  67 }
  68
  69 static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
  70 {
  71         if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
  72                 channel64_writeq(dc, CHAR, val);
  73         else
  74                 channel64_writel(dc, CHAR, val);
  75 }
  76
  77 static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
  78 {
  79 #if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
  80         channel64_writel(dc, CHAR, 0);
  81         channel64_writel(dc, __pad_CHAR, 0);
  82 #else
  83         channel64_writeq(dc, CHAR, 0);
  84 #endif
  85 }
  86
  87 static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
  88 {
  89         if (is_dmac64(dc))
  90                 return channel64_read_CHAR(dc);
  91         else
  92                 return channel32_readl(dc, CHAR);
  93 }
  94
  95 static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
  96 {
  97         if (is_dmac64(dc))
  98                 channel64_write_CHAR(dc, val);
  99         else
 100                 channel32_writel(dc, CHAR, val);
 101 }
 102
 103 static struct txx9dmac_regs __iomem *__txx9dmac_regs(
 104         const struct txx9dmac_dev *ddev)
 105 {
 106         return ddev->regs;
 107 }
 108
 109 static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
 110         const struct txx9dmac_dev *ddev)
 111 {
 112         return ddev->regs;
 113 }
 114
 115 #define dma64_readl(ddev, name) \
 116         __raw_readl(&(__txx9dmac_regs(ddev)->name))
 117 #define dma64_writel(ddev, name, val) \
 118         __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
 119
 120 #define dma32_readl(ddev, name) \
 121         __raw_readl(&(__txx9dmac_regs32(ddev)->name))
 122 #define dma32_writel(ddev, name, val) \
 123         __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
 124
 125 #define dma_readl(ddev, name) \
 126         (__is_dmac64(ddev) ? \
 127         dma64_readl(ddev, name) : dma32_readl(ddev, name))
 128 #define dma_writel(ddev, name, val) \
 129         (__is_dmac64(ddev) ? \
 130         dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
 131
 132 static struct device *chan2dev(struct dma_chan *chan)
 133 {
 134         return &chan->dev->device;
 135 }
 136 static struct device *chan2parent(struct dma_chan *chan)
 137 {
 138         return chan->dev->device.parent;
 139 }
 140
 141 static struct txx9dmac_desc *
 142 txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
 143 {
 144         return container_of(txd, struct txx9dmac_desc, txd);
 145 }
 146
 147 static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
 148                                  const struct txx9dmac_desc *desc)
 149 {
 150         return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
 151 }
 152
 153 static void desc_write_CHAR(const struct txx9dmac_chan *dc,
 154                             struct txx9dmac_desc *desc, dma_addr_t val)
 155 {
 156         if (is_dmac64(dc))
 157                 desc->hwdesc.CHAR = val;
 158         else
 159                 desc->hwdesc32.CHAR = val;
 160 }
 161
 162 #define TXX9_DMA_MAX_COUNT      0x04000000
 163
 164 #define TXX9_DMA_INITIAL_DESC_COUNT     64
 165
 166 static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
 167 {
 168         return list_entry(dc->active_list.next,
 169                           struct txx9dmac_desc, desc_node);
 170 }
 171
 172 static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
 173 {
 174         return list_entry(dc->active_list.prev,
 175                           struct txx9dmac_desc, desc_node);
 176 }
 177
 178 static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
 179 {
 180         return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
 181 }
 182
 183 static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
 184 {
 185         if (!list_empty(&desc->tx_list))
 186                 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
 187         return desc;
 188 }
 189
 190 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
 191
 192 static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
 193                                                  gfp_t flags)
 194 {
 195         struct txx9dmac_dev *ddev = dc->ddev;
 196         struct txx9dmac_desc *desc;
 197
 198         desc = kzalloc(sizeof(*desc), flags);
 199         if (!desc)
 200                 return NULL;
 201         INIT_LIST_HEAD(&desc->tx_list);
 202         dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
 203         desc->txd.tx_submit = txx9dmac_tx_submit;
 204         /* txd.flags will be overwritten in prep funcs */
 205         desc->txd.flags = DMA_CTRL_ACK;
 206         desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
 207                                         ddev->descsize, DMA_TO_DEVICE);
 208         return desc;
 209 }
 210
 211 static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
 212 {
 213         struct txx9dmac_desc *desc, *_desc;
 214         struct txx9dmac_desc *ret = NULL;
 215         unsigned int i = 0;
 216
 217         spin_lock_bh(&dc->lock);
 218         list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
 219                 if (async_tx_test_ack(&desc->txd)) {
 220                         list_del(&desc->desc_node);
 221                         ret = desc;
 222                         break;
 223                 }
 224                 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
 225                 i++;
 226         }
 227         spin_unlock_bh(&dc->lock);
 228
 229         dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
 230                  i);
 231         if (!ret) {
 232                 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
 233                 if (ret) {
 234                         spin_lock_bh(&dc->lock);
 235                         dc->descs_allocated++;
 236                         spin_unlock_bh(&dc->lock);
 237                 } else
 238                         dev_err(chan2dev(&dc->chan),
 239                                 "not enough descriptors available\n");
 240         }
 241         return ret;
 242 }
 243
 244 static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
 245                                        struct txx9dmac_desc *desc)
 246 {
 247         struct txx9dmac_dev *ddev = dc->ddev;
 248         struct txx9dmac_desc *child;
 249
 250         list_for_each_entry(child, &desc->tx_list, desc_node)
 251                 dma_sync_single_for_cpu(chan2parent(&dc->chan),
 252                                 child->txd.phys, ddev->descsize,
 253                                 DMA_TO_DEVICE);
 254         dma_sync_single_for_cpu(chan2parent(&dc->chan),
 255                         desc->txd.phys, ddev->descsize,
 256                         DMA_TO_DEVICE);
 257 }
 258
 259 /*
 260  * Move a descriptor, including any children, to the free list.
 261  * `desc' must not be on any lists.
 262  */
 263 static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
 264                               struct txx9dmac_desc *desc)
 265 {
 266         if (desc) {
 267                 struct txx9dmac_desc *child;
 268
 269                 txx9dmac_sync_desc_for_cpu(dc, desc);
 270
 271                 spin_lock_bh(&dc->lock);
 272                 list_for_each_entry(child, &desc->tx_list, desc_node)
 273                         dev_vdbg(chan2dev(&dc->chan),
 274                                  "moving child desc %p to freelist\n",
 275                                  child);
 276                 list_splice_init(&desc->tx_list, &dc->free_list);
 277                 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
 278                          desc);
 279                 list_add(&desc->desc_node, &dc->free_list);
 280                 spin_unlock_bh(&dc->lock);
 281         }
 282 }
 283
 284 /*----------------------------------------------------------------------*/
 285
 286 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
 287 {
 288         if (is_dmac64(dc))
 289                 dev_err(chan2dev(&dc->chan),
 290                         "  CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
 291                         " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
 292                         (u64)channel64_read_CHAR(dc),
 293                         channel64_readq(dc, SAR),
 294                         channel64_readq(dc, DAR),
 295                         channel64_readl(dc, CNTR),
 296                         channel64_readl(dc, SAIR),
 297                         channel64_readl(dc, DAIR),
 298                         channel64_readl(dc, CCR),
 299                         channel64_readl(dc, CSR));
 300         else
 301                 dev_err(chan2dev(&dc->chan),
 302                         "  CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
 303                         " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
 304                         channel32_readl(dc, CHAR),
 305                         channel32_readl(dc, SAR),
 306                         channel32_readl(dc, DAR),
 307                         channel32_readl(dc, CNTR),
 308                         channel32_readl(dc, SAIR),
 309                         channel32_readl(dc, DAIR),
 310                         channel32_readl(dc, CCR),
 311                         channel32_readl(dc, CSR));
 312 }
 313
 314 static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
 315 {
 316         channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
 317         if (is_dmac64(dc)) {
 318                 channel64_clear_CHAR(dc);
 319                 channel_writeq(dc, SAR, 0);
 320                 channel_writeq(dc, DAR, 0);
 321         } else {
 322                 channel_writel(dc, CHAR, 0);
 323                 channel_writel(dc, SAR, 0);
 324                 channel_writel(dc, DAR, 0);
 325         }
 326         channel_writel(dc, CNTR, 0);
 327         channel_writel(dc, SAIR, 0);
 328         channel_writel(dc, DAIR, 0);
 329         channel_writel(dc, CCR, 0);
 330         mmiowb();
 331 }
 332
 333 /* Called with dc->lock held and bh disabled */
 334 static void txx9dmac_dostart(struct txx9dmac_chan *dc,
 335                              struct txx9dmac_desc *first)
 336 {
 337         struct txx9dmac_slave *ds = dc->chan.private;
 338         u32 sai, dai;
 339
 340         dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
 341                  first->txd.cookie, first);
 342         /* ASSERT:  channel is idle */
 343         if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
 344                 dev_err(chan2dev(&dc->chan),
 345                         "BUG: Attempted to start non-idle channel\n");
 346                 txx9dmac_dump_regs(dc);
 347                 /* The tasklet will hopefully advance the queue... */
 348                 return;
 349         }
 350
 351         if (is_dmac64(dc)) {
 352                 channel64_writel(dc, CNTR, 0);
 353                 channel64_writel(dc, CSR, 0xffffffff);
 354                 if (ds) {
 355                         if (ds->tx_reg) {
 356                                 sai = ds->reg_width;
 357                                 dai = 0;
 358                         } else {
 359                                 sai = 0;
 360                                 dai = ds->reg_width;
 361                         }
 362                 } else {
 363                         sai = 8;
 364                         dai = 8;
 365                 }
 366                 channel64_writel(dc, SAIR, sai);
 367                 channel64_writel(dc, DAIR, dai);
 368                 /* All 64-bit DMAC supports SMPCHN */
 369                 channel64_writel(dc, CCR, dc->ccr);
 370                 /* Writing a non zero value to CHAR will assert XFACT */
 371                 channel64_write_CHAR(dc, first->txd.phys);
 372         } else {
 373                 channel32_writel(dc, CNTR, 0);
 374                 channel32_writel(dc, CSR, 0xffffffff);
 375                 if (ds) {
 376                         if (ds->tx_reg) {
 377                                 sai = ds->reg_width;
 378                                 dai = 0;
 379                         } else {
 380                                 sai = 0;
 381                                 dai = ds->reg_width;
 382                         }
 383                 } else {
 384                         sai = 4;
 385                         dai = 4;
 386                 }
 387                 channel32_writel(dc, SAIR, sai);
 388                 channel32_writel(dc, DAIR, dai);
 389                 if (txx9_dma_have_SMPCHN()) {
 390                         channel32_writel(dc, CCR, dc->ccr);
 391                         /* Writing a non zero value to CHAR will assert XFACT */
 392                         channel32_writel(dc, CHAR, first->txd.phys);
 393                 } else {
 394                         channel32_writel(dc, CHAR, first->txd.phys);
 395                         channel32_writel(dc, CCR, dc->ccr);
 396                 }
 397         }
 398 }
 399
 400 /*----------------------------------------------------------------------*/
 401
 402 static void
 403 txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
 404                              struct txx9dmac_desc *desc)
 405 {
 406         dma_async_tx_callback callback;
 407         void *param;
 408         struct dma_async_tx_descriptor *txd = &desc->txd;
 409         struct txx9dmac_slave *ds = dc->chan.private;
 410
 411         dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
 412                  txd->cookie, desc);
 413
 414         dma_cookie_complete(txd);
 415         callback = txd->callback;
 416         param = txd->callback_param;
 417
 418         txx9dmac_sync_desc_for_cpu(dc, desc);
 419         list_splice_init(&desc->tx_list, &dc->free_list);
 420         list_move(&desc->desc_node, &dc->free_list);
 421
 422         dma_descriptor_unmap(txd);
 423         if (!ds) {
 424                 dma_addr_t dmaaddr;
 425                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 426                         dmaaddr = is_dmac64(dc) ?
 427                                 desc->hwdesc.DAR : desc->hwdesc32.DAR;
 428                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 429                                 dma_unmap_single(chan2parent(&dc->chan),
 430                                         dmaaddr, desc->len, DMA_FROM_DEVICE);
 431                         else
 432                                 dma_unmap_page(chan2parent(&dc->chan),
 433                                         dmaaddr, desc->len, DMA_FROM_DEVICE);
 434                 }
 435                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 436                         dmaaddr = is_dmac64(dc) ?
 437                                 desc->hwdesc.SAR : desc->hwdesc32.SAR;
 438                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 439                                 dma_unmap_single(chan2parent(&dc->chan),
 440                                         dmaaddr, desc->len, DMA_TO_DEVICE);
 441                         else
 442                                 dma_unmap_page(chan2parent(&dc->chan),
 443                                         dmaaddr, desc->len, DMA_TO_DEVICE);
 444                 }
 445         }
 446
 447         /*
 448          * The API requires that no submissions are done from a
 449          * callback, so we don't need to drop the lock here
 450          */
 451         if (callback)
 452                 callback(param);
 453         dma_run_dependencies(txd);
 454 }
 455
 456 static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
 457 {
 458         struct txx9dmac_dev *ddev = dc->ddev;
 459         struct txx9dmac_desc *desc;
 460         struct txx9dmac_desc *prev = NULL;
 461
 462         BUG_ON(!list_empty(list));
 463         do {
 464                 desc = txx9dmac_first_queued(dc);
 465                 if (prev) {
 466                         desc_write_CHAR(dc, prev, desc->txd.phys);
 467                         dma_sync_single_for_device(chan2parent(&dc->chan),
 468                                 prev->txd.phys, ddev->descsize,
 469                                 DMA_TO_DEVICE);
 470                 }
 471                 prev = txx9dmac_last_child(desc);
 472                 list_move_tail(&desc->desc_node, list);
 473                 /* Make chain-completion interrupt happen */
 474                 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
 475                     !txx9dmac_chan_INTENT(dc))
 476                         break;
 477         } while (!list_empty(&dc->queue));
 478 }
 479
 480 static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
 481 {
 482         struct txx9dmac_desc *desc, *_desc;
 483         LIST_HEAD(list);
 484
 485         /*
 486          * Submit queued descriptors ASAP, i.e. before we go through
 487          * the completed ones.
 488          */
 489         list_splice_init(&dc->active_list, &list);
 490         if (!list_empty(&dc->queue)) {
 491                 txx9dmac_dequeue(dc, &dc->active_list);
 492                 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
 493         }
 494
 495         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 496                 txx9dmac_descriptor_complete(dc, desc);
 497 }
 498
 499 static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
 500                                struct txx9dmac_hwdesc *desc)
 501 {
 502         if (is_dmac64(dc)) {
 503 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
 504                 dev_crit(chan2dev(&dc->chan),
 505                          "  desc: ch%#llx s%#llx d%#llx c%#x\n",
 506                          (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
 507 #else
 508                 dev_crit(chan2dev(&dc->chan),
 509                          "  desc: ch%#llx s%#llx d%#llx c%#x"
 510                          " si%#x di%#x cc%#x cs%#x\n",
 511                          (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
 512                          desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
 513 #endif
 514         } else {
 515                 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
 516 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
 517                 dev_crit(chan2dev(&dc->chan),
 518                          "  desc: ch%#x s%#x d%#x c%#x\n",
 519                          d->CHAR, d->SAR, d->DAR, d->CNTR);
 520 #else
 521                 dev_crit(chan2dev(&dc->chan),
 522                          "  desc: ch%#x s%#x d%#x c%#x"
 523                          " si%#x di%#x cc%#x cs%#x\n",
 524                          d->CHAR, d->SAR, d->DAR, d->CNTR,
 525                          d->SAIR, d->DAIR, d->CCR, d->CSR);
 526 #endif
 527         }
 528 }
 529
 530 static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
 531 {
 532         struct txx9dmac_desc *bad_desc;
 533         struct txx9dmac_desc *child;
 534         u32 errors;
 535
 536         /*
 537          * The descriptor currently at the head of the active list is
 538          * borked. Since we don't have any way to report errors, we'll
 539          * just have to scream loudly and try to carry on.
 540          */
 541         dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
 542         txx9dmac_dump_regs(dc);
 543
 544         bad_desc = txx9dmac_first_active(dc);
 545         list_del_init(&bad_desc->desc_node);
 546
 547         /* Clear all error flags and try to restart the controller */
 548         errors = csr & (TXX9_DMA_CSR_ABCHC |
 549                         TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
 550                         TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
 551         channel_writel(dc, CSR, errors);
 552
 553         if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
 554                 txx9dmac_dequeue(dc, &dc->active_list);
 555         if (!list_empty(&dc->active_list))
 556                 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
 557
 558         dev_crit(chan2dev(&dc->chan),
 559                  "Bad descriptor submitted for DMA! (cookie: %d)\n",
 560                  bad_desc->txd.cookie);
 561         txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
 562         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 563                 txx9dmac_dump_desc(dc, &child->hwdesc);
 564         /* Pretend the descriptor completed successfully */
 565         txx9dmac_descriptor_complete(dc, bad_desc);
 566 }
 567
 568 static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
 569 {
 570         dma_addr_t chain;
 571         struct txx9dmac_desc *desc, *_desc;
 572         struct txx9dmac_desc *child;
 573         u32 csr;
 574
 575         if (is_dmac64(dc)) {
 576                 chain = channel64_read_CHAR(dc);
 577                 csr = channel64_readl(dc, CSR);
 578                 channel64_writel(dc, CSR, csr);
 579         } else {
 580                 chain = channel32_readl(dc, CHAR);
 581                 csr = channel32_readl(dc, CSR);
 582                 channel32_writel(dc, CSR, csr);
 583         }
 584         /* For dynamic chain, we should look at XFACT instead of NCHNC */
 585         if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
 586                 /* Everything we've submitted is done */
 587                 txx9dmac_complete_all(dc);
 588                 return;
 589         }
 590         if (!(csr & TXX9_DMA_CSR_CHNEN))
 591                 chain = 0;      /* last descriptor of this chain */
 592
 593         dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
 594                  (u64)chain);
 595
 596         list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
 597                 if (desc_read_CHAR(dc, desc) == chain) {
 598                         /* This one is currently in progress */
 599                         if (csr & TXX9_DMA_CSR_ABCHC)
 600                                 goto scan_done;
 601                         return;
 602                 }
 603
 604                 list_for_each_entry(child, &desc->tx_list, desc_node)
 605                         if (desc_read_CHAR(dc, child) == chain) {
 606                                 /* Currently in progress */
 607                                 if (csr & TXX9_DMA_CSR_ABCHC)
 608                                         goto scan_done;
 609                                 return;
 610                         }
 611
 612                 /*
 613                  * No descriptors so far seem to be in progress, i.e.
 614                  * this one must be done.
 615                  */
 616                 txx9dmac_descriptor_complete(dc, desc);
 617         }
 618 scan_done:
 619         if (csr & TXX9_DMA_CSR_ABCHC) {
 620                 txx9dmac_handle_error(dc, csr);
 621                 return;
 622         }
 623
 624         dev_err(chan2dev(&dc->chan),
 625                 "BUG: All descriptors done, but channel not idle!\n");
 626
 627         /* Try to continue after resetting the channel... */
 628         txx9dmac_reset_chan(dc);
 629
 630         if (!list_empty(&dc->queue)) {
 631                 txx9dmac_dequeue(dc, &dc->active_list);
 632                 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
 633         }
 634 }
 635
 636 static void txx9dmac_chan_tasklet(unsigned long data)
 637 {
 638         int irq;
 639         u32 csr;
 640         struct txx9dmac_chan *dc;
 641
 642         dc = (struct txx9dmac_chan *)data;
 643         csr = channel_readl(dc, CSR);
 644         dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
 645
 646         spin_lock(&dc->lock);
 647         if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
 648                    TXX9_DMA_CSR_NTRNFC))
 649                 txx9dmac_scan_descriptors(dc);
 650         spin_unlock(&dc->lock);
 651         irq = dc->irq;
 652
 653         enable_irq(irq);
 654 }
 655
 656 static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
 657 {
 658         struct txx9dmac_chan *dc = dev_id;
 659
 660         dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
 661                         channel_readl(dc, CSR));
 662
 663         tasklet_schedule(&dc->tasklet);
 664         /*
 665          * Just disable the interrupts. We'll turn them back on in the
 666          * softirq handler.
 667          */
 668         disable_irq_nosync(irq);
 669
 670         return IRQ_HANDLED;
 671 }
 672
 673 static void txx9dmac_tasklet(unsigned long data)
 674 {
 675         int irq;
 676         u32 csr;
 677         struct txx9dmac_chan *dc;
 678
 679         struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
 680         u32 mcr;
 681         int i;
 682
 683         mcr = dma_readl(ddev, MCR);
 684         dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
 685         for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
 686                 if ((mcr >> (24 + i)) & 0x11) {
 687                         dc = ddev->chan[i];
 688                         csr = channel_readl(dc, CSR);
 689                         dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
 690                                  csr);
 691                         spin_lock(&dc->lock);
 692                         if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
 693                                    TXX9_DMA_CSR_NTRNFC))
 694                                 txx9dmac_scan_descriptors(dc);
 695                         spin_unlock(&dc->lock);
 696                 }
 697         }
 698         irq = ddev->irq;
 699
 700         enable_irq(irq);
 701 }
 702
 703 static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
 704 {
 705         struct txx9dmac_dev *ddev = dev_id;
 706
 707         dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
 708                         dma_readl(ddev, MCR));
 709
 710         tasklet_schedule(&ddev->tasklet);
 711         /*
 712          * Just disable the interrupts. We'll turn them back on in the
 713          * softirq handler.
 714          */
 715         disable_irq_nosync(irq);
 716
 717         return IRQ_HANDLED;
 718 }
 719
 720 /*----------------------------------------------------------------------*/
 721
 722 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
 723 {
 724         struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
 725         struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
 726         dma_cookie_t cookie;
 727
 728         spin_lock_bh(&dc->lock);
 729         cookie = dma_cookie_assign(tx);
 730
 731         dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
 732                  desc->txd.cookie, desc);
 733
 734         list_add_tail(&desc->desc_node, &dc->queue);
 735         spin_unlock_bh(&dc->lock);
 736
 737         return cookie;
 738 }
 739
 740 static struct dma_async_tx_descriptor *
 741 txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 742                 size_t len, unsigned long flags)
 743 {
 744         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
 745         struct txx9dmac_dev *ddev = dc->ddev;
 746         struct txx9dmac_desc *desc;
 747         struct txx9dmac_desc *first;
 748         struct txx9dmac_desc *prev;
 749         size_t xfer_count;
 750         size_t offset;
 751
 752         dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
 753                  (u64)dest, (u64)src, len, flags);
 754
 755         if (unlikely(!len)) {
 756                 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
 757                 return NULL;
 758         }
 759
 760         prev = first = NULL;
 761
 762         for (offset = 0; offset < len; offset += xfer_count) {
 763                 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
 764                 /*
 765                  * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
 766                  * ERT-TX49H4-016 (slightly conservative)
 767                  */
 768                 if (__is_dmac64(ddev)) {
 769                         if (xfer_count > 0x100 &&
 770                             (xfer_count & 0xff) >= 0xfa &&
 771                             (xfer_count & 0xff) <= 0xff)
 772                                 xfer_count -= 0x20;
 773                 } else {
 774                         if (xfer_count > 0x80 &&
 775                             (xfer_count & 0x7f) >= 0x7e &&
 776                             (xfer_count & 0x7f) <= 0x7f)
 777                                 xfer_count -= 0x20;
 778                 }
 779
 780                 desc = txx9dmac_desc_get(dc);
 781                 if (!desc) {
 782                         txx9dmac_desc_put(dc, first);
 783                         return NULL;
 784                 }
 785
 786                 if (__is_dmac64(ddev)) {
 787                         desc->hwdesc.SAR = src + offset;
 788                         desc->hwdesc.DAR = dest + offset;
 789                         desc->hwdesc.CNTR = xfer_count;
 790                         txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
 791                                         dc->ccr | TXX9_DMA_CCR_XFACT);
 792                 } else {
 793                         desc->hwdesc32.SAR = src + offset;
 794                         desc->hwdesc32.DAR = dest + offset;
 795                         desc->hwdesc32.CNTR = xfer_count;
 796                         txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
 797                                         dc->ccr | TXX9_DMA_CCR_XFACT);
 798                 }
 799
 800                 /*
 801                  * The descriptors on tx_list are not reachable from
 802                  * the dc->queue list or dc->active_list after a
 803                  * submit.  If we put all descriptors on active_list,
 804                  * calling of callback on the completion will be more
 805                  * complex.
 806                  */
 807                 if (!first) {
 808                         first = desc;
 809                 } else {
 810                         desc_write_CHAR(dc, prev, desc->txd.phys);
 811                         dma_sync_single_for_device(chan2parent(&dc->chan),
 812                                         prev->txd.phys, ddev->descsize,
 813                                         DMA_TO_DEVICE);
 814                         list_add_tail(&desc->desc_node, &first->tx_list);
 815                 }
 816                 prev = desc;
 817         }
 818
 819         /* Trigger interrupt after last block */
 820         if (flags & DMA_PREP_INTERRUPT)
 821                 txx9dmac_desc_set_INTENT(ddev, prev);
 822
 823         desc_write_CHAR(dc, prev, 0);
 824         dma_sync_single_for_device(chan2parent(&dc->chan),
 825                         prev->txd.phys, ddev->descsize,
 826                         DMA_TO_DEVICE);
 827
 828         first->txd.flags = flags;
 829         first->len = len;
 830
 831         return &first->txd;
 832 }
 833
 834 static struct dma_async_tx_descriptor *
 835 txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 836                 unsigned int sg_len, enum dma_transfer_direction direction,
 837                 unsigned long flags, void *context)
 838 {
 839         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
 840         struct txx9dmac_dev *ddev = dc->ddev;
 841         struct txx9dmac_slave *ds = chan->private;
 842         struct txx9dmac_desc *prev;
 843         struct txx9dmac_desc *first;
 844         unsigned int i;
 845         struct scatterlist *sg;
 846
 847         dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
 848
 849         BUG_ON(!ds || !ds->reg_width);
 850         if (ds->tx_reg)
 851                 BUG_ON(direction != DMA_MEM_TO_DEV);
 852         else
 853                 BUG_ON(direction != DMA_DEV_TO_MEM);
 854         if (unlikely(!sg_len))
 855                 return NULL;
 856
 857         prev = first = NULL;
 858
 859         for_each_sg(sgl, sg, sg_len, i) {
 860                 struct txx9dmac_desc *desc;
 861                 dma_addr_t mem;
 862                 u32 sai, dai;
 863
 864                 desc = txx9dmac_desc_get(dc);
 865                 if (!desc) {
 866                         txx9dmac_desc_put(dc, first);
 867                         return NULL;
 868                 }
 869
 870                 mem = sg_dma_address(sg);
 871
 872                 if (__is_dmac64(ddev)) {
 873                         if (direction == DMA_MEM_TO_DEV) {
 874                                 desc->hwdesc.SAR = mem;
 875                                 desc->hwdesc.DAR = ds->tx_reg;
 876                         } else {
 877                                 desc->hwdesc.SAR = ds->rx_reg;
 878                                 desc->hwdesc.DAR = mem;
 879                         }
 880                         desc->hwdesc.CNTR = sg_dma_len(sg);
 881                 } else {
 882                         if (direction == DMA_MEM_TO_DEV) {
 883                                 desc->hwdesc32.SAR = mem;
 884                                 desc->hwdesc32.DAR = ds->tx_reg;
 885                         } else {
 886                                 desc->hwdesc32.SAR = ds->rx_reg;
 887                                 desc->hwdesc32.DAR = mem;
 888                         }
 889                         desc->hwdesc32.CNTR = sg_dma_len(sg);
 890                 }
 891                 if (direction == DMA_MEM_TO_DEV) {
 892                         sai = ds->reg_width;
 893                         dai = 0;
 894                 } else {
 895                         sai = 0;
 896                         dai = ds->reg_width;
 897                 }
 898                 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
 899                                         dc->ccr | TXX9_DMA_CCR_XFACT);
 900
 901                 if (!first) {
 902                         first = desc;
 903                 } else {
 904                         desc_write_CHAR(dc, prev, desc->txd.phys);
 905                         dma_sync_single_for_device(chan2parent(&dc->chan),
 906                                         prev->txd.phys,
 907                                         ddev->descsize,
 908                                         DMA_TO_DEVICE);
 909                         list_add_tail(&desc->desc_node, &first->tx_list);
 910                 }
 911                 prev = desc;
 912         }
 913
 914         /* Trigger interrupt after last block */
 915         if (flags & DMA_PREP_INTERRUPT)
 916                 txx9dmac_desc_set_INTENT(ddev, prev);
 917
 918         desc_write_CHAR(dc, prev, 0);
 919         dma_sync_single_for_device(chan2parent(&dc->chan),
 920                         prev->txd.phys, ddev->descsize,
 921                         DMA_TO_DEVICE);
 922
 923         first->txd.flags = flags;
 924         first->len = 0;
 925
 926         return &first->txd;
 927 }
 928
 929 static int txx9dmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 930                             unsigned long arg)
 931 {
 932         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
 933         struct txx9dmac_desc *desc, *_desc;
 934         LIST_HEAD(list);
 935
 936         /* Only supports DMA_TERMINATE_ALL */
 937         if (cmd != DMA_TERMINATE_ALL)
 938                 return -EINVAL;
 939
 940         dev_vdbg(chan2dev(chan), "terminate_all\n");
 941         spin_lock_bh(&dc->lock);
 942
 943         txx9dmac_reset_chan(dc);
 944
 945         /* active_list entries will end up before queued entries */
 946         list_splice_init(&dc->queue, &list);
 947         list_splice_init(&dc->active_list, &list);
 948
 949         spin_unlock_bh(&dc->lock);
 950
 951         /* Flush all pending and queued descriptors */
 952         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 953                 txx9dmac_descriptor_complete(dc, desc);
 954
 955         return 0;
 956 }
 957
 958 static enum dma_status
 959 txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 960                    struct dma_tx_state *txstate)
 961 {
 962         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
 963         enum dma_status ret;
 964
 965         ret = dma_cookie_status(chan, cookie, txstate);
 966         if (ret == DMA_SUCCESS)
 967                 return DMA_SUCCESS;
 968
 969         spin_lock_bh(&dc->lock);
 970         txx9dmac_scan_descriptors(dc);
 971         spin_unlock_bh(&dc->lock);
 972
 973         return dma_cookie_status(chan, cookie, txstate);
 974 }
 975
 976 static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
 977                                    struct txx9dmac_desc *prev)
 978 {
 979         struct txx9dmac_dev *ddev = dc->ddev;
 980         struct txx9dmac_desc *desc;
 981         LIST_HEAD(list);
 982
 983         prev = txx9dmac_last_child(prev);
 984         txx9dmac_dequeue(dc, &list);
 985         desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
 986         desc_write_CHAR(dc, prev, desc->txd.phys);
 987         dma_sync_single_for_device(chan2parent(&dc->chan),
 988                                    prev->txd.phys, ddev->descsize,
 989                                    DMA_TO_DEVICE);
 990         mmiowb();
 991         if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
 992             channel_read_CHAR(dc) == prev->txd.phys)
 993                 /* Restart chain DMA */
 994                 channel_write_CHAR(dc, desc->txd.phys);
 995         list_splice_tail(&list, &dc->active_list);
 996 }
 997
 998 static void txx9dmac_issue_pending(struct dma_chan *chan)
 999 {
1000         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1001
1002         spin_lock_bh(&dc->lock);
1003
1004         if (!list_empty(&dc->active_list))
1005                 txx9dmac_scan_descriptors(dc);
1006         if (!list_empty(&dc->queue)) {
1007                 if (list_empty(&dc->active_list)) {
1008                         txx9dmac_dequeue(dc, &dc->active_list);
1009                         txx9dmac_dostart(dc, txx9dmac_first_active(dc));
1010                 } else if (txx9_dma_have_SMPCHN()) {
1011                         struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
1012
1013                         if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
1014                             txx9dmac_chan_INTENT(dc))
1015                                 txx9dmac_chain_dynamic(dc, prev);
1016                 }
1017         }
1018
1019         spin_unlock_bh(&dc->lock);
1020 }
1021
1022 static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
1023 {
1024         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1025         struct txx9dmac_slave *ds = chan->private;
1026         struct txx9dmac_desc *desc;
1027         int i;
1028
1029         dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1030
1031         /* ASSERT:  channel is idle */
1032         if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1033                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1034                 return -EIO;
1035         }
1036
1037         dma_cookie_init(chan);
1038
1039         dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1040         txx9dmac_chan_set_SMPCHN(dc);
1041         if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1042                 dc->ccr |= TXX9_DMA_CCR_INTENC;
1043         if (chan->device->device_prep_dma_memcpy) {
1044                 if (ds)
1045                         return -EINVAL;
1046                 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1047         } else {
1048                 if (!ds ||
1049                     (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1050                         return -EINVAL;
1051                 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1052                         TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1053                 txx9dmac_chan_set_INTENT(dc);
1054         }
1055
1056         spin_lock_bh(&dc->lock);
1057         i = dc->descs_allocated;
1058         while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1059                 spin_unlock_bh(&dc->lock);
1060
1061                 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1062                 if (!desc) {
1063                         dev_info(chan2dev(chan),
1064                                 "only allocated %d descriptors\n", i);
1065                         spin_lock_bh(&dc->lock);
1066                         break;
1067                 }
1068                 txx9dmac_desc_put(dc, desc);
1069
1070                 spin_lock_bh(&dc->lock);
1071                 i = ++dc->descs_allocated;
1072         }
1073         spin_unlock_bh(&dc->lock);
1074
1075         dev_dbg(chan2dev(chan),
1076                 "alloc_chan_resources allocated %d descriptors\n", i);
1077
1078         return i;
1079 }
1080
1081 static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1082 {
1083         struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1084         struct txx9dmac_dev *ddev = dc->ddev;
1085         struct txx9dmac_desc *desc, *_desc;
1086         LIST_HEAD(list);
1087
1088         dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1089                         dc->descs_allocated);
1090
1091         /* ASSERT:  channel is idle */
1092         BUG_ON(!list_empty(&dc->active_list));
1093         BUG_ON(!list_empty(&dc->queue));
1094         BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1095
1096         spin_lock_bh(&dc->lock);
1097         list_splice_init(&dc->free_list, &list);
1098         dc->descs_allocated = 0;
1099         spin_unlock_bh(&dc->lock);
1100
1101         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1102                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1103                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1104                                  ddev->descsize, DMA_TO_DEVICE);
1105                 kfree(desc);
1106         }
1107
1108         dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1109 }
1110
1111 /*----------------------------------------------------------------------*/
1112
1113 static void txx9dmac_off(struct txx9dmac_dev *ddev)
1114 {
1115         dma_writel(ddev, MCR, 0);
1116         mmiowb();
1117 }
1118
1119 static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1120 {
1121         struct txx9dmac_chan_platform_data *cpdata =
1122                         dev_get_platdata(&pdev->dev);
1123         struct platform_device *dmac_dev = cpdata->dmac_dev;
1124         struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
1125         struct txx9dmac_chan *dc;
1126         int err;
1127         int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1128         int irq;
1129
1130         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1131         if (!dc)
1132                 return -ENOMEM;
1133
1134         dc->dma.dev = &pdev->dev;
1135         dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1136         dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1137         dc->dma.device_control = txx9dmac_control;
1138         dc->dma.device_tx_status = txx9dmac_tx_status;
1139         dc->dma.device_issue_pending = txx9dmac_issue_pending;
1140         if (pdata && pdata->memcpy_chan == ch) {
1141                 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1142                 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1143         } else {
1144                 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1145                 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1146                 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1147         }
1148
1149         INIT_LIST_HEAD(&dc->dma.channels);
1150         dc->ddev = platform_get_drvdata(dmac_dev);
1151         if (dc->ddev->irq < 0) {
1152                 irq = platform_get_irq(pdev, 0);
1153                 if (irq < 0)
1154                         return irq;
1155                 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1156                                 (unsigned long)dc);
1157                 dc->irq = irq;
1158                 err = devm_request_irq(&pdev->dev, dc->irq,
1159                         txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1160                 if (err)
1161                         return err;
1162         } else
1163                 dc->irq = -1;
1164         dc->ddev->chan[ch] = dc;
1165         dc->chan.device = &dc->dma;
1166         list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1167         dma_cookie_init(&dc->chan);
1168
1169         if (is_dmac64(dc))
1170                 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1171         else
1172                 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1173         spin_lock_init(&dc->lock);
1174
1175         INIT_LIST_HEAD(&dc->active_list);
1176         INIT_LIST_HEAD(&dc->queue);
1177         INIT_LIST_HEAD(&dc->free_list);
1178
1179         txx9dmac_reset_chan(dc);
1180
1181         platform_set_drvdata(pdev, dc);
1182
1183         err = dma_async_device_register(&dc->dma);
1184         if (err)
1185                 return err;
1186         dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1187                 dc->dma.dev_id,
1188                 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1189                 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1190
1191         return 0;
1192 }
1193
1194 static int txx9dmac_chan_remove(struct platform_device *pdev)
1195 {
1196         struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1197
1198         dma_async_device_unregister(&dc->dma);
1199         if (dc->irq >= 0)
1200                 tasklet_kill(&dc->tasklet);
1201         dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1202         return 0;
1203 }
1204
1205 static int __init txx9dmac_probe(struct platform_device *pdev)
1206 {
1207         struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1208         struct resource *io;
1209         struct txx9dmac_dev *ddev;
1210         u32 mcr;
1211         int err;
1212
1213         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1214         if (!io)
1215                 return -EINVAL;
1216
1217         ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1218         if (!ddev)
1219                 return -ENOMEM;
1220
1221         if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1222                                      dev_name(&pdev->dev)))
1223                 return -EBUSY;
1224
1225         ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1226         if (!ddev->regs)
1227                 return -ENOMEM;
1228         ddev->have_64bit_regs = pdata->have_64bit_regs;
1229         if (__is_dmac64(ddev))
1230                 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1231         else
1232                 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1233
1234         /* force dma off, just in case */
1235         txx9dmac_off(ddev);
1236
1237         ddev->irq = platform_get_irq(pdev, 0);
1238         if (ddev->irq >= 0) {
1239                 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1240                                 (unsigned long)ddev);
1241                 err = devm_request_irq(&pdev->dev, ddev->irq,
1242                         txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1243                 if (err)
1244                         return err;
1245         }
1246
1247         mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1248         if (pdata && pdata->memcpy_chan >= 0)
1249                 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1250         dma_writel(ddev, MCR, mcr);
1251
1252         platform_set_drvdata(pdev, ddev);
1253         return 0;
1254 }
1255
1256 static int txx9dmac_remove(struct platform_device *pdev)
1257 {
1258         struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1259
1260         txx9dmac_off(ddev);
1261         if (ddev->irq >= 0)
1262                 tasklet_kill(&ddev->tasklet);
1263         return 0;
1264 }
1265
1266 static void txx9dmac_shutdown(struct platform_device *pdev)
1267 {
1268         struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1269
1270         txx9dmac_off(ddev);
1271 }
1272
1273 static int txx9dmac_suspend_noirq(struct device *dev)
1274 {
1275         struct platform_device *pdev = to_platform_device(dev);
1276         struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1277
1278         txx9dmac_off(ddev);
1279         return 0;
1280 }
1281
1282 static int txx9dmac_resume_noirq(struct device *dev)
1283 {
1284         struct platform_device *pdev = to_platform_device(dev);
1285         struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1286         struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1287         u32 mcr;
1288
1289         mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1290         if (pdata && pdata->memcpy_chan >= 0)
1291                 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1292         dma_writel(ddev, MCR, mcr);
1293         return 0;
1294
1295 }
1296
1297 static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1298         .suspend_noirq = txx9dmac_suspend_noirq,
1299         .resume_noirq = txx9dmac_resume_noirq,
1300 };
1301
1302 static struct platform_driver txx9dmac_chan_driver = {
1303         .remove         = txx9dmac_chan_remove,
1304         .driver = {
1305                 .name   = "txx9dmac-chan",
1306         },
1307 };
1308
1309 static struct platform_driver txx9dmac_driver = {
1310         .remove         = txx9dmac_remove,
1311         .shutdown       = txx9dmac_shutdown,
1312         .driver = {
1313                 .name   = "txx9dmac",
1314                 .pm     = &txx9dmac_dev_pm_ops,
1315         },
1316 };
1317
1318 static int __init txx9dmac_init(void)
1319 {
1320         int rc;
1321
1322         rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1323         if (!rc) {
1324                 rc = platform_driver_probe(&txx9dmac_chan_driver,
1325                                            txx9dmac_chan_probe);
1326                 if (rc)
1327                         platform_driver_unregister(&txx9dmac_driver);
1328         }
1329         return rc;
1330 }
1331 module_init(txx9dmac_init);
1332
1333 static void __exit txx9dmac_exit(void)
1334 {
1335         platform_driver_unregister(&txx9dmac_chan_driver);
1336         platform_driver_unregister(&txx9dmac_driver);
1337 }
1338 module_exit(txx9dmac_exit);
1339
1340 MODULE_LICENSE("GPL");
1341 MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1342 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1343 MODULE_ALIAS("platform:txx9dmac");
1344 MODULE_ALIAS("platform:txx9dmac-chan");