2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/byteorder.h>
43 #include <asm/system.h>
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
70 __le32 branch_address;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
81 struct descriptor descriptor;
82 struct ar_buffer *next;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
92 struct tasklet_struct tasklet;
97 typedef int (*descriptor_callback_t)(struct context *ctx,
99 struct descriptor *last);
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
110 struct descriptor buffer[0];
114 struct fw_ohci *ohci;
116 int total_allocation;
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
123 struct list_head buffer_list;
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
129 struct descriptor_buffer *buffer_tail;
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
135 struct descriptor *last;
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
141 struct descriptor *prev;
143 descriptor_callback_t callback;
145 struct tasklet_struct tasklet;
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
156 struct fw_iso_context base;
157 struct context context;
160 size_t header_length;
163 #define CONFIG_ROM_SIZE 1024
168 __iomem char *registers;
171 int request_generation; /* for timestamping incoming requests */
173 unsigned int pri_req_max;
178 * Spinlock for accessing fw_ohci data. Never call out of
179 * this driver with this lock held.
183 struct ar_context ar_request_ctx;
184 struct ar_context ar_response_ctx;
185 struct context at_request_ctx;
186 struct context at_response_ctx;
189 struct iso_context *it_context_list;
190 u64 ir_context_channels;
192 struct iso_context *ir_context_list;
195 dma_addr_t config_rom_bus;
196 __be32 *next_config_rom;
197 dma_addr_t next_config_rom_bus;
201 dma_addr_t self_id_bus;
202 struct tasklet_struct bus_reset_tasklet;
204 u32 self_id_buffer[512];
207 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
209 return container_of(card, struct fw_ohci, card);
212 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
213 #define IR_CONTEXT_BUFFER_FILL 0x80000000
214 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
215 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
216 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
217 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
219 #define CONTEXT_RUN 0x8000
220 #define CONTEXT_WAKE 0x1000
221 #define CONTEXT_DEAD 0x0800
222 #define CONTEXT_ACTIVE 0x0400
224 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
225 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
226 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
228 #define OHCI1394_REGISTER_SIZE 0x800
229 #define OHCI_LOOP_COUNT 500
230 #define OHCI1394_PCI_HCI_Control 0x40
231 #define SELF_ID_BUF_SIZE 0x800
232 #define OHCI_TCODE_PHY_PACKET 0x0e
233 #define OHCI_VERSION_1_1 0x010010
235 static char ohci_driver_name[] = KBUILD_MODNAME;
237 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
238 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
240 #define QUIRK_CYCLE_TIMER 1
241 #define QUIRK_RESET_PACKET 2
242 #define QUIRK_BE_HEADERS 4
243 #define QUIRK_NO_1394A 8
244 #define QUIRK_NO_MSI 16
246 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
247 static const struct {
248 unsigned short vendor, device, flags;
250 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
253 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
254 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
255 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
256 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
257 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
258 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
261 /* This overrides anything that was found in ohci_quirks[]. */
262 static int param_quirks;
263 module_param_named(quirks, param_quirks, int, 0644);
264 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
265 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
266 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
267 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
268 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
269 ", disable MSI = " __stringify(QUIRK_NO_MSI)
272 #define OHCI_PARAM_DEBUG_AT_AR 1
273 #define OHCI_PARAM_DEBUG_SELFIDS 2
274 #define OHCI_PARAM_DEBUG_IRQS 4
275 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
277 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
279 static int param_debug;
280 module_param_named(debug, param_debug, int, 0644);
281 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
282 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
283 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
284 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
285 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
286 ", or a combination, or all = -1)");
288 static void log_irqs(u32 evt)
290 if (likely(!(param_debug &
291 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
294 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
295 !(evt & OHCI1394_busReset))
298 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
299 evt & OHCI1394_selfIDComplete ? " selfID" : "",
300 evt & OHCI1394_RQPkt ? " AR_req" : "",
301 evt & OHCI1394_RSPkt ? " AR_resp" : "",
302 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
303 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
304 evt & OHCI1394_isochRx ? " IR" : "",
305 evt & OHCI1394_isochTx ? " IT" : "",
306 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
307 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
308 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
309 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
310 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
311 evt & OHCI1394_busReset ? " busReset" : "",
312 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
313 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
314 OHCI1394_respTxComplete | OHCI1394_isochRx |
315 OHCI1394_isochTx | OHCI1394_postedWriteErr |
316 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
317 OHCI1394_cycleInconsistent |
318 OHCI1394_regAccessFail | OHCI1394_busReset)
322 static const char *speed[] = {
323 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
325 static const char *power[] = {
326 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
327 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
329 static const char port[] = { '.', '-', 'p', 'c', };
331 static char _p(u32 *s, int shift)
333 return port[*s >> shift & 3];
336 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
338 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
341 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
342 self_id_count, generation, node_id);
344 for (; self_id_count--; ++s)
345 if ((*s & 1 << 23) == 0)
346 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
347 "%s gc=%d %s %s%s%s\n",
348 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
349 speed[*s >> 14 & 3], *s >> 16 & 63,
350 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
351 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
353 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
355 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
356 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
359 static const char *evts[] = {
360 [0x00] = "evt_no_status", [0x01] = "-reserved-",
361 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
362 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
363 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
364 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
365 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
366 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
367 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
368 [0x10] = "-reserved-", [0x11] = "ack_complete",
369 [0x12] = "ack_pending ", [0x13] = "-reserved-",
370 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
371 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
372 [0x18] = "-reserved-", [0x19] = "-reserved-",
373 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
374 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
375 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
376 [0x20] = "pending/cancelled",
378 static const char *tcodes[] = {
379 [0x0] = "QW req", [0x1] = "BW req",
380 [0x2] = "W resp", [0x3] = "-reserved-",
381 [0x4] = "QR req", [0x5] = "BR req",
382 [0x6] = "QR resp", [0x7] = "BR resp",
383 [0x8] = "cycle start", [0x9] = "Lk req",
384 [0xa] = "async stream packet", [0xb] = "Lk resp",
385 [0xc] = "-reserved-", [0xd] = "-reserved-",
386 [0xe] = "link internal", [0xf] = "-reserved-",
388 static const char *phys[] = {
389 [0x0] = "phy config packet", [0x1] = "link-on packet",
390 [0x2] = "self-id packet", [0x3] = "-reserved-",
393 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
395 int tcode = header[0] >> 4 & 0xf;
398 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
401 if (unlikely(evt >= ARRAY_SIZE(evts)))
404 if (evt == OHCI1394_evt_bus_reset) {
405 fw_notify("A%c evt_bus_reset, generation %d\n",
406 dir, (header[2] >> 16) & 0xff);
410 if (header[0] == ~header[1]) {
411 fw_notify("A%c %s, %s, %08x\n",
412 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
417 case 0x0: case 0x6: case 0x8:
418 snprintf(specific, sizeof(specific), " = %08x",
419 be32_to_cpu((__force __be32)header[3]));
421 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
422 snprintf(specific, sizeof(specific), " %x,%x",
423 header[3] >> 16, header[3] & 0xffff);
431 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
433 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
434 fw_notify("A%c spd %x tl %02x, "
437 dir, speed, header[0] >> 10 & 0x3f,
438 header[1] >> 16, header[0] >> 16, evts[evt],
439 tcodes[tcode], header[1] & 0xffff, header[2], specific);
442 fw_notify("A%c spd %x tl %02x, "
445 dir, speed, header[0] >> 10 & 0x3f,
446 header[1] >> 16, header[0] >> 16, evts[evt],
447 tcodes[tcode], specific);
453 #define param_debug 0
454 static inline void log_irqs(u32 evt) {}
455 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
456 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
458 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
460 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
462 writel(data, ohci->registers + offset);
465 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
467 return readl(ohci->registers + offset);
470 static inline void flush_writes(const struct fw_ohci *ohci)
472 /* Do a dummy read to flush writes. */
473 reg_read(ohci, OHCI1394_Version);
476 static int read_phy_reg(struct fw_ohci *ohci, int addr)
481 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
482 for (i = 0; i < 3 + 100; i++) {
483 val = reg_read(ohci, OHCI1394_PhyControl);
484 if (val & OHCI1394_PhyControl_ReadDone)
485 return OHCI1394_PhyControl_ReadData(val);
488 * Try a few times without waiting. Sleeping is necessary
489 * only when the link/PHY interface is busy.
494 fw_error("failed to read phy reg\n");
499 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
503 reg_write(ohci, OHCI1394_PhyControl,
504 OHCI1394_PhyControl_Write(addr, val));
505 for (i = 0; i < 3 + 100; i++) {
506 val = reg_read(ohci, OHCI1394_PhyControl);
507 if (!(val & OHCI1394_PhyControl_WritePending))
513 fw_error("failed to write phy reg\n");
518 static int ohci_update_phy_reg(struct fw_card *card, int addr,
519 int clear_bits, int set_bits)
521 struct fw_ohci *ohci = fw_ohci(card);
524 ret = read_phy_reg(ohci, addr);
529 * The interrupt status bits are cleared by writing a one bit.
530 * Avoid clearing them unless explicitly requested in set_bits.
533 clear_bits |= PHY_INT_STATUS_BITS;
535 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
538 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
542 ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
546 return read_phy_reg(ohci, addr);
549 static int ar_context_add_page(struct ar_context *ctx)
551 struct device *dev = ctx->ohci->card.device;
552 struct ar_buffer *ab;
553 dma_addr_t uninitialized_var(ab_bus);
556 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
561 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
562 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
564 DESCRIPTOR_BRANCH_ALWAYS);
565 offset = offsetof(struct ar_buffer, data);
566 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
567 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
568 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
569 ab->descriptor.branch_address = 0;
571 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
572 ctx->last_buffer->next = ab;
573 ctx->last_buffer = ab;
575 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
576 flush_writes(ctx->ohci);
581 static void ar_context_release(struct ar_context *ctx)
583 struct ar_buffer *ab, *ab_next;
587 for (ab = ctx->current_buffer; ab; ab = ab_next) {
589 offset = offsetof(struct ar_buffer, data);
590 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
591 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
596 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
597 #define cond_le32_to_cpu(v) \
598 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
600 #define cond_le32_to_cpu(v) le32_to_cpu(v)
603 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
605 struct fw_ohci *ohci = ctx->ohci;
607 u32 status, length, tcode;
610 p.header[0] = cond_le32_to_cpu(buffer[0]);
611 p.header[1] = cond_le32_to_cpu(buffer[1]);
612 p.header[2] = cond_le32_to_cpu(buffer[2]);
614 tcode = (p.header[0] >> 4) & 0x0f;
616 case TCODE_WRITE_QUADLET_REQUEST:
617 case TCODE_READ_QUADLET_RESPONSE:
618 p.header[3] = (__force __u32) buffer[3];
619 p.header_length = 16;
620 p.payload_length = 0;
623 case TCODE_READ_BLOCK_REQUEST :
624 p.header[3] = cond_le32_to_cpu(buffer[3]);
625 p.header_length = 16;
626 p.payload_length = 0;
629 case TCODE_WRITE_BLOCK_REQUEST:
630 case TCODE_READ_BLOCK_RESPONSE:
631 case TCODE_LOCK_REQUEST:
632 case TCODE_LOCK_RESPONSE:
633 p.header[3] = cond_le32_to_cpu(buffer[3]);
634 p.header_length = 16;
635 p.payload_length = p.header[3] >> 16;
638 case TCODE_WRITE_RESPONSE:
639 case TCODE_READ_QUADLET_REQUEST:
640 case OHCI_TCODE_PHY_PACKET:
641 p.header_length = 12;
642 p.payload_length = 0;
646 /* FIXME: Stop context, discard everything, and restart? */
648 p.payload_length = 0;
651 p.payload = (void *) buffer + p.header_length;
653 /* FIXME: What to do about evt_* errors? */
654 length = (p.header_length + p.payload_length + 3) / 4;
655 status = cond_le32_to_cpu(buffer[length]);
656 evt = (status >> 16) & 0x1f;
659 p.speed = (status >> 21) & 0x7;
660 p.timestamp = status & 0xffff;
661 p.generation = ohci->request_generation;
663 log_ar_at_event('R', p.speed, p.header, evt);
666 * The OHCI bus reset handler synthesizes a phy packet with
667 * the new generation number when a bus reset happens (see
668 * section 8.4.2.3). This helps us determine when a request
669 * was received and make sure we send the response in the same
670 * generation. We only need this for requests; for responses
671 * we use the unique tlabel for finding the matching
674 * Alas some chips sometimes emit bus reset packets with a
675 * wrong generation. We set the correct generation for these
676 * at a slightly incorrect time (in bus_reset_tasklet).
678 if (evt == OHCI1394_evt_bus_reset) {
679 if (!(ohci->quirks & QUIRK_RESET_PACKET))
680 ohci->request_generation = (p.header[2] >> 16) & 0xff;
681 } else if (ctx == &ohci->ar_request_ctx) {
682 fw_core_handle_request(&ohci->card, &p);
684 fw_core_handle_response(&ohci->card, &p);
687 return buffer + length + 1;
690 static void ar_context_tasklet(unsigned long data)
692 struct ar_context *ctx = (struct ar_context *)data;
693 struct fw_ohci *ohci = ctx->ohci;
694 struct ar_buffer *ab;
695 struct descriptor *d;
698 ab = ctx->current_buffer;
701 if (d->res_count == 0) {
702 size_t size, rest, offset;
703 dma_addr_t start_bus;
707 * This descriptor is finished and we may have a
708 * packet split across this and the next buffer. We
709 * reuse the page for reassembling the split packet.
712 offset = offsetof(struct ar_buffer, data);
714 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
718 size = buffer + PAGE_SIZE - ctx->pointer;
719 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
720 memmove(buffer, ctx->pointer, size);
721 memcpy(buffer + size, ab->data, rest);
722 ctx->current_buffer = ab;
723 ctx->pointer = (void *) ab->data + rest;
724 end = buffer + size + rest;
727 buffer = handle_ar_packet(ctx, buffer);
729 dma_free_coherent(ohci->card.device, PAGE_SIZE,
731 ar_context_add_page(ctx);
733 buffer = ctx->pointer;
735 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
738 buffer = handle_ar_packet(ctx, buffer);
742 static int ar_context_init(struct ar_context *ctx,
743 struct fw_ohci *ohci, u32 regs)
749 ctx->last_buffer = &ab;
750 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
752 ar_context_add_page(ctx);
753 ar_context_add_page(ctx);
754 ctx->current_buffer = ab.next;
755 ctx->pointer = ctx->current_buffer->data;
760 static void ar_context_run(struct ar_context *ctx)
762 struct ar_buffer *ab = ctx->current_buffer;
766 offset = offsetof(struct ar_buffer, data);
767 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
769 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
770 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
771 flush_writes(ctx->ohci);
774 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
778 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
779 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
781 /* figure out which descriptor the branch address goes in */
782 if (z == 2 && (b == 3 || key == 2))
788 static void context_tasklet(unsigned long data)
790 struct context *ctx = (struct context *) data;
791 struct descriptor *d, *last;
794 struct descriptor_buffer *desc;
796 desc = list_entry(ctx->buffer_list.next,
797 struct descriptor_buffer, list);
799 while (last->branch_address != 0) {
800 struct descriptor_buffer *old_desc = desc;
801 address = le32_to_cpu(last->branch_address);
805 /* If the branch address points to a buffer outside of the
806 * current buffer, advance to the next buffer. */
807 if (address < desc->buffer_bus ||
808 address >= desc->buffer_bus + desc->used)
809 desc = list_entry(desc->list.next,
810 struct descriptor_buffer, list);
811 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
812 last = find_branch_descriptor(d, z);
814 if (!ctx->callback(ctx, d, last))
817 if (old_desc != desc) {
818 /* If we've advanced to the next buffer, move the
819 * previous buffer to the free list. */
822 spin_lock_irqsave(&ctx->ohci->lock, flags);
823 list_move_tail(&old_desc->list, &ctx->buffer_list);
824 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
831 * Allocate a new buffer and add it to the list of free buffers for this
832 * context. Must be called with ohci->lock held.
834 static int context_add_buffer(struct context *ctx)
836 struct descriptor_buffer *desc;
837 dma_addr_t uninitialized_var(bus_addr);
841 * 16MB of descriptors should be far more than enough for any DMA
842 * program. This will catch run-away userspace or DoS attacks.
844 if (ctx->total_allocation >= 16*1024*1024)
847 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
848 &bus_addr, GFP_ATOMIC);
852 offset = (void *)&desc->buffer - (void *)desc;
853 desc->buffer_size = PAGE_SIZE - offset;
854 desc->buffer_bus = bus_addr + offset;
857 list_add_tail(&desc->list, &ctx->buffer_list);
858 ctx->total_allocation += PAGE_SIZE;
863 static int context_init(struct context *ctx, struct fw_ohci *ohci,
864 u32 regs, descriptor_callback_t callback)
868 ctx->total_allocation = 0;
870 INIT_LIST_HEAD(&ctx->buffer_list);
871 if (context_add_buffer(ctx) < 0)
874 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
875 struct descriptor_buffer, list);
877 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
878 ctx->callback = callback;
881 * We put a dummy descriptor in the buffer that has a NULL
882 * branch address and looks like it's been sent. That way we
883 * have a descriptor to append DMA programs to.
885 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
886 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
887 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
888 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
889 ctx->last = ctx->buffer_tail->buffer;
890 ctx->prev = ctx->buffer_tail->buffer;
895 static void context_release(struct context *ctx)
897 struct fw_card *card = &ctx->ohci->card;
898 struct descriptor_buffer *desc, *tmp;
900 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
901 dma_free_coherent(card->device, PAGE_SIZE, desc,
903 ((void *)&desc->buffer - (void *)desc));
906 /* Must be called with ohci->lock held */
907 static struct descriptor *context_get_descriptors(struct context *ctx,
908 int z, dma_addr_t *d_bus)
910 struct descriptor *d = NULL;
911 struct descriptor_buffer *desc = ctx->buffer_tail;
913 if (z * sizeof(*d) > desc->buffer_size)
916 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
917 /* No room for the descriptor in this buffer, so advance to the
920 if (desc->list.next == &ctx->buffer_list) {
921 /* If there is no free buffer next in the list,
923 if (context_add_buffer(ctx) < 0)
926 desc = list_entry(desc->list.next,
927 struct descriptor_buffer, list);
928 ctx->buffer_tail = desc;
931 d = desc->buffer + desc->used / sizeof(*d);
932 memset(d, 0, z * sizeof(*d));
933 *d_bus = desc->buffer_bus + desc->used;
938 static void context_run(struct context *ctx, u32 extra)
940 struct fw_ohci *ohci = ctx->ohci;
942 reg_write(ohci, COMMAND_PTR(ctx->regs),
943 le32_to_cpu(ctx->last->branch_address));
944 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
945 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
949 static void context_append(struct context *ctx,
950 struct descriptor *d, int z, int extra)
953 struct descriptor_buffer *desc = ctx->buffer_tail;
955 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
957 desc->used += (z + extra) * sizeof(*d);
958 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
959 ctx->prev = find_branch_descriptor(d, z);
961 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
962 flush_writes(ctx->ohci);
965 static void context_stop(struct context *ctx)
970 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
971 flush_writes(ctx->ohci);
973 for (i = 0; i < 10; i++) {
974 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
975 if ((reg & CONTEXT_ACTIVE) == 0)
980 fw_error("Error: DMA context still active (0x%08x)\n", reg);
984 struct fw_packet *packet;
988 * This function apppends a packet to the DMA queue for transmission.
989 * Must always be called with the ochi->lock held to ensure proper
990 * generation handling and locking around packet queue manipulation.
992 static int at_context_queue_packet(struct context *ctx,
993 struct fw_packet *packet)
995 struct fw_ohci *ohci = ctx->ohci;
996 dma_addr_t d_bus, uninitialized_var(payload_bus);
997 struct driver_data *driver_data;
998 struct descriptor *d, *last;
1003 d = context_get_descriptors(ctx, 4, &d_bus);
1005 packet->ack = RCODE_SEND_ERROR;
1009 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1010 d[0].res_count = cpu_to_le16(packet->timestamp);
1013 * The DMA format for asyncronous link packets is different
1014 * from the IEEE1394 layout, so shift the fields around
1015 * accordingly. If header_length is 8, it's a PHY packet, to
1016 * which we need to prepend an extra quadlet.
1019 header = (__le32 *) &d[1];
1020 switch (packet->header_length) {
1023 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1024 (packet->speed << 16));
1025 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1026 (packet->header[0] & 0xffff0000));
1027 header[2] = cpu_to_le32(packet->header[2]);
1029 tcode = (packet->header[0] >> 4) & 0x0f;
1030 if (TCODE_IS_BLOCK_PACKET(tcode))
1031 header[3] = cpu_to_le32(packet->header[3]);
1033 header[3] = (__force __le32) packet->header[3];
1035 d[0].req_count = cpu_to_le16(packet->header_length);
1039 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1040 (packet->speed << 16));
1041 header[1] = cpu_to_le32(packet->header[0]);
1042 header[2] = cpu_to_le32(packet->header[1]);
1043 d[0].req_count = cpu_to_le16(12);
1047 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1048 (packet->speed << 16));
1049 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1050 d[0].req_count = cpu_to_le16(8);
1055 packet->ack = RCODE_SEND_ERROR;
1059 driver_data = (struct driver_data *) &d[3];
1060 driver_data->packet = packet;
1061 packet->driver_data = driver_data;
1063 if (packet->payload_length > 0) {
1065 dma_map_single(ohci->card.device, packet->payload,
1066 packet->payload_length, DMA_TO_DEVICE);
1067 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1068 packet->ack = RCODE_SEND_ERROR;
1071 packet->payload_bus = payload_bus;
1072 packet->payload_mapped = true;
1074 d[2].req_count = cpu_to_le16(packet->payload_length);
1075 d[2].data_address = cpu_to_le32(payload_bus);
1083 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1084 DESCRIPTOR_IRQ_ALWAYS |
1085 DESCRIPTOR_BRANCH_ALWAYS);
1088 * If the controller and packet generations don't match, we need to
1089 * bail out and try again. If IntEvent.busReset is set, the AT context
1090 * is halted, so appending to the context and trying to run it is
1091 * futile. Most controllers do the right thing and just flush the AT
1092 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1093 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1094 * up stalling out. So we just bail out in software and try again
1095 * later, and everyone is happy.
1096 * FIXME: Document how the locking works.
1098 if (ohci->generation != packet->generation ||
1099 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1100 if (packet->payload_mapped)
1101 dma_unmap_single(ohci->card.device, payload_bus,
1102 packet->payload_length, DMA_TO_DEVICE);
1103 packet->ack = RCODE_GENERATION;
1107 context_append(ctx, d, z, 4 - z);
1109 /* If the context isn't already running, start it up. */
1110 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1111 if ((reg & CONTEXT_RUN) == 0)
1112 context_run(ctx, 0);
1117 static int handle_at_packet(struct context *context,
1118 struct descriptor *d,
1119 struct descriptor *last)
1121 struct driver_data *driver_data;
1122 struct fw_packet *packet;
1123 struct fw_ohci *ohci = context->ohci;
1126 if (last->transfer_status == 0)
1127 /* This descriptor isn't done yet, stop iteration. */
1130 driver_data = (struct driver_data *) &d[3];
1131 packet = driver_data->packet;
1133 /* This packet was cancelled, just continue. */
1136 if (packet->payload_mapped)
1137 dma_unmap_single(ohci->card.device, packet->payload_bus,
1138 packet->payload_length, DMA_TO_DEVICE);
1140 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1141 packet->timestamp = le16_to_cpu(last->res_count);
1143 log_ar_at_event('T', packet->speed, packet->header, evt);
1146 case OHCI1394_evt_timeout:
1147 /* Async response transmit timed out. */
1148 packet->ack = RCODE_CANCELLED;
1151 case OHCI1394_evt_flushed:
1153 * The packet was flushed should give same error as
1154 * when we try to use a stale generation count.
1156 packet->ack = RCODE_GENERATION;
1159 case OHCI1394_evt_missing_ack:
1161 * Using a valid (current) generation count, but the
1162 * node is not on the bus or not sending acks.
1164 packet->ack = RCODE_NO_ACK;
1167 case ACK_COMPLETE + 0x10:
1168 case ACK_PENDING + 0x10:
1169 case ACK_BUSY_X + 0x10:
1170 case ACK_BUSY_A + 0x10:
1171 case ACK_BUSY_B + 0x10:
1172 case ACK_DATA_ERROR + 0x10:
1173 case ACK_TYPE_ERROR + 0x10:
1174 packet->ack = evt - 0x10;
1178 packet->ack = RCODE_SEND_ERROR;
1182 packet->callback(packet, &ohci->card, packet->ack);
1187 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1188 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1189 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1190 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1191 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1193 static void handle_local_rom(struct fw_ohci *ohci,
1194 struct fw_packet *packet, u32 csr)
1196 struct fw_packet response;
1197 int tcode, length, i;
1199 tcode = HEADER_GET_TCODE(packet->header[0]);
1200 if (TCODE_IS_BLOCK_PACKET(tcode))
1201 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1205 i = csr - CSR_CONFIG_ROM;
1206 if (i + length > CONFIG_ROM_SIZE) {
1207 fw_fill_response(&response, packet->header,
1208 RCODE_ADDRESS_ERROR, NULL, 0);
1209 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1210 fw_fill_response(&response, packet->header,
1211 RCODE_TYPE_ERROR, NULL, 0);
1213 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1214 (void *) ohci->config_rom + i, length);
1217 fw_core_handle_response(&ohci->card, &response);
1220 static void handle_local_lock(struct fw_ohci *ohci,
1221 struct fw_packet *packet, u32 csr)
1223 struct fw_packet response;
1224 int tcode, length, ext_tcode, sel;
1225 __be32 *payload, lock_old;
1226 u32 lock_arg, lock_data;
1228 tcode = HEADER_GET_TCODE(packet->header[0]);
1229 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1230 payload = packet->payload;
1231 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1233 if (tcode == TCODE_LOCK_REQUEST &&
1234 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1235 lock_arg = be32_to_cpu(payload[0]);
1236 lock_data = be32_to_cpu(payload[1]);
1237 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1241 fw_fill_response(&response, packet->header,
1242 RCODE_TYPE_ERROR, NULL, 0);
1246 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1247 reg_write(ohci, OHCI1394_CSRData, lock_data);
1248 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1249 reg_write(ohci, OHCI1394_CSRControl, sel);
1251 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1252 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1254 fw_notify("swap not done yet\n");
1256 fw_fill_response(&response, packet->header,
1257 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1259 fw_core_handle_response(&ohci->card, &response);
1262 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1267 if (ctx == &ctx->ohci->at_request_ctx) {
1268 packet->ack = ACK_PENDING;
1269 packet->callback(packet, &ctx->ohci->card, packet->ack);
1273 ((unsigned long long)
1274 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1276 csr = offset - CSR_REGISTER_BASE;
1278 /* Handle config rom reads. */
1279 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1280 handle_local_rom(ctx->ohci, packet, csr);
1282 case CSR_BUS_MANAGER_ID:
1283 case CSR_BANDWIDTH_AVAILABLE:
1284 case CSR_CHANNELS_AVAILABLE_HI:
1285 case CSR_CHANNELS_AVAILABLE_LO:
1286 handle_local_lock(ctx->ohci, packet, csr);
1289 if (ctx == &ctx->ohci->at_request_ctx)
1290 fw_core_handle_request(&ctx->ohci->card, packet);
1292 fw_core_handle_response(&ctx->ohci->card, packet);
1296 if (ctx == &ctx->ohci->at_response_ctx) {
1297 packet->ack = ACK_COMPLETE;
1298 packet->callback(packet, &ctx->ohci->card, packet->ack);
1302 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1304 unsigned long flags;
1307 spin_lock_irqsave(&ctx->ohci->lock, flags);
1309 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1310 ctx->ohci->generation == packet->generation) {
1311 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1312 handle_local_request(ctx, packet);
1316 ret = at_context_queue_packet(ctx, packet);
1317 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1320 packet->callback(packet, &ctx->ohci->card, packet->ack);
1324 static u32 cycle_timer_ticks(u32 cycle_timer)
1328 ticks = cycle_timer & 0xfff;
1329 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1330 ticks += (3072 * 8000) * (cycle_timer >> 25);
1336 * Some controllers exhibit one or more of the following bugs when updating the
1337 * iso cycle timer register:
1338 * - When the lowest six bits are wrapping around to zero, a read that happens
1339 * at the same time will return garbage in the lowest ten bits.
1340 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1341 * not incremented for about 60 ns.
1342 * - Occasionally, the entire register reads zero.
1344 * To catch these, we read the register three times and ensure that the
1345 * difference between each two consecutive reads is approximately the same, i.e.
1346 * less than twice the other. Furthermore, any negative difference indicates an
1347 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1348 * execute, so we have enough precision to compute the ratio of the differences.)
1350 static u32 get_cycle_time(struct fw_ohci *ohci)
1357 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1359 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1362 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1366 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1367 t0 = cycle_timer_ticks(c0);
1368 t1 = cycle_timer_ticks(c1);
1369 t2 = cycle_timer_ticks(c2);
1372 } while ((diff01 <= 0 || diff12 <= 0 ||
1373 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1381 * This function has to be called at least every 64 seconds. The bus_time
1382 * field stores not only the upper 25 bits of the BUS_TIME register but also
1383 * the most significant bit of the cycle timer in bit 6 so that we can detect
1384 * changes in this bit.
1386 static u32 update_bus_time(struct fw_ohci *ohci)
1388 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1390 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1391 ohci->bus_time += 0x40;
1393 return ohci->bus_time | cycle_time_seconds;
1396 static void bus_reset_tasklet(unsigned long data)
1398 struct fw_ohci *ohci = (struct fw_ohci *)data;
1399 int self_id_count, i, j, reg;
1400 int generation, new_generation;
1401 unsigned long flags;
1402 void *free_rom = NULL;
1403 dma_addr_t free_rom_bus = 0;
1406 reg = reg_read(ohci, OHCI1394_NodeID);
1407 if (!(reg & OHCI1394_NodeID_idValid)) {
1408 fw_notify("node ID not valid, new bus reset in progress\n");
1411 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1412 fw_notify("malconfigured bus\n");
1415 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1416 OHCI1394_NodeID_nodeNumber);
1418 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1419 if (!(ohci->is_root && is_new_root))
1420 reg_write(ohci, OHCI1394_LinkControlSet,
1421 OHCI1394_LinkControl_cycleMaster);
1422 ohci->is_root = is_new_root;
1424 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1425 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1426 fw_notify("inconsistent self IDs\n");
1430 * The count in the SelfIDCount register is the number of
1431 * bytes in the self ID receive buffer. Since we also receive
1432 * the inverted quadlets and a header quadlet, we shift one
1433 * bit extra to get the actual number of self IDs.
1435 self_id_count = (reg >> 3) & 0xff;
1436 if (self_id_count == 0 || self_id_count > 252) {
1437 fw_notify("inconsistent self IDs\n");
1440 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1443 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1444 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1445 fw_notify("inconsistent self IDs\n");
1448 ohci->self_id_buffer[j] =
1449 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1454 * Check the consistency of the self IDs we just read. The
1455 * problem we face is that a new bus reset can start while we
1456 * read out the self IDs from the DMA buffer. If this happens,
1457 * the DMA buffer will be overwritten with new self IDs and we
1458 * will read out inconsistent data. The OHCI specification
1459 * (section 11.2) recommends a technique similar to
1460 * linux/seqlock.h, where we remember the generation of the
1461 * self IDs in the buffer before reading them out and compare
1462 * it to the current generation after reading them out. If
1463 * the two generations match we know we have a consistent set
1467 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1468 if (new_generation != generation) {
1469 fw_notify("recursive bus reset detected, "
1470 "discarding self ids\n");
1474 /* FIXME: Document how the locking works. */
1475 spin_lock_irqsave(&ohci->lock, flags);
1477 ohci->generation = generation;
1478 context_stop(&ohci->at_request_ctx);
1479 context_stop(&ohci->at_response_ctx);
1480 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1482 if (ohci->quirks & QUIRK_RESET_PACKET)
1483 ohci->request_generation = generation;
1486 * This next bit is unrelated to the AT context stuff but we
1487 * have to do it under the spinlock also. If a new config rom
1488 * was set up before this reset, the old one is now no longer
1489 * in use and we can free it. Update the config rom pointers
1490 * to point to the current config rom and clear the
1491 * next_config_rom pointer so a new udpate can take place.
1494 if (ohci->next_config_rom != NULL) {
1495 if (ohci->next_config_rom != ohci->config_rom) {
1496 free_rom = ohci->config_rom;
1497 free_rom_bus = ohci->config_rom_bus;
1499 ohci->config_rom = ohci->next_config_rom;
1500 ohci->config_rom_bus = ohci->next_config_rom_bus;
1501 ohci->next_config_rom = NULL;
1504 * Restore config_rom image and manually update
1505 * config_rom registers. Writing the header quadlet
1506 * will indicate that the config rom is ready, so we
1509 reg_write(ohci, OHCI1394_BusOptions,
1510 be32_to_cpu(ohci->config_rom[2]));
1511 ohci->config_rom[0] = ohci->next_header;
1512 reg_write(ohci, OHCI1394_ConfigROMhdr,
1513 be32_to_cpu(ohci->next_header));
1516 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1517 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1518 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1521 spin_unlock_irqrestore(&ohci->lock, flags);
1524 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1525 free_rom, free_rom_bus);
1527 log_selfids(ohci->node_id, generation,
1528 self_id_count, ohci->self_id_buffer);
1530 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1531 self_id_count, ohci->self_id_buffer);
1534 static irqreturn_t irq_handler(int irq, void *data)
1536 struct fw_ohci *ohci = data;
1537 u32 event, iso_event;
1540 event = reg_read(ohci, OHCI1394_IntEventClear);
1542 if (!event || !~event)
1545 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1546 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1549 if (event & OHCI1394_selfIDComplete)
1550 tasklet_schedule(&ohci->bus_reset_tasklet);
1552 if (event & OHCI1394_RQPkt)
1553 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1555 if (event & OHCI1394_RSPkt)
1556 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1558 if (event & OHCI1394_reqTxComplete)
1559 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1561 if (event & OHCI1394_respTxComplete)
1562 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1564 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1565 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1568 i = ffs(iso_event) - 1;
1569 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1570 iso_event &= ~(1 << i);
1573 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1574 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1577 i = ffs(iso_event) - 1;
1578 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1579 iso_event &= ~(1 << i);
1582 if (unlikely(event & OHCI1394_regAccessFail))
1583 fw_error("Register access failure - "
1584 "please notify linux1394-devel@lists.sf.net\n");
1586 if (unlikely(event & OHCI1394_postedWriteErr))
1587 fw_error("PCI posted write error\n");
1589 if (unlikely(event & OHCI1394_cycleTooLong)) {
1590 if (printk_ratelimit())
1591 fw_notify("isochronous cycle too long\n");
1592 reg_write(ohci, OHCI1394_LinkControlSet,
1593 OHCI1394_LinkControl_cycleMaster);
1596 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1598 * We need to clear this event bit in order to make
1599 * cycleMatch isochronous I/O work. In theory we should
1600 * stop active cycleMatch iso contexts now and restart
1601 * them at least two cycles later. (FIXME?)
1603 if (printk_ratelimit())
1604 fw_notify("isochronous cycle inconsistent\n");
1607 if (event & OHCI1394_cycle64Seconds) {
1608 spin_lock(&ohci->lock);
1609 update_bus_time(ohci);
1610 spin_unlock(&ohci->lock);
1616 static int software_reset(struct fw_ohci *ohci)
1620 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1622 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1623 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1624 OHCI1394_HCControl_softReset) == 0)
1632 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1634 size_t size = length * 4;
1636 memcpy(dest, src, size);
1637 if (size < CONFIG_ROM_SIZE)
1638 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1641 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1644 int ret, clear, set, offset;
1646 /* Check if the driver should configure link and PHY. */
1647 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1648 OHCI1394_HCControl_programPhyEnable))
1651 /* Paranoia: check whether the PHY supports 1394a, too. */
1652 enable_1394a = false;
1653 ret = read_phy_reg(ohci, 2);
1656 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1657 ret = read_paged_phy_reg(ohci, 1, 8);
1661 enable_1394a = true;
1664 if (ohci->quirks & QUIRK_NO_1394A)
1665 enable_1394a = false;
1667 /* Configure PHY and link consistently. */
1670 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1672 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1675 ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1680 offset = OHCI1394_HCControlSet;
1682 offset = OHCI1394_HCControlClear;
1683 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1685 /* Clean up: configuration has been taken care of. */
1686 reg_write(ohci, OHCI1394_HCControlClear,
1687 OHCI1394_HCControl_programPhyEnable);
1692 static int ohci_enable(struct fw_card *card,
1693 const __be32 *config_rom, size_t length)
1695 struct fw_ohci *ohci = fw_ohci(card);
1696 struct pci_dev *dev = to_pci_dev(card->device);
1697 u32 lps, seconds, irqs;
1700 if (software_reset(ohci)) {
1701 fw_error("Failed to reset ohci card.\n");
1706 * Now enable LPS, which we need in order to start accessing
1707 * most of the registers. In fact, on some cards (ALI M5251),
1708 * accessing registers in the SClk domain without LPS enabled
1709 * will lock up the machine. Wait 50msec to make sure we have
1710 * full link enabled. However, with some cards (well, at least
1711 * a JMicron PCIe card), we have to try again sometimes.
1713 reg_write(ohci, OHCI1394_HCControlSet,
1714 OHCI1394_HCControl_LPS |
1715 OHCI1394_HCControl_postedWriteEnable);
1718 for (lps = 0, i = 0; !lps && i < 3; i++) {
1720 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1721 OHCI1394_HCControl_LPS;
1725 fw_error("Failed to set Link Power Status\n");
1729 reg_write(ohci, OHCI1394_HCControlClear,
1730 OHCI1394_HCControl_noByteSwapData);
1732 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1733 reg_write(ohci, OHCI1394_LinkControlClear,
1734 OHCI1394_LinkControl_rcvPhyPkt);
1735 reg_write(ohci, OHCI1394_LinkControlSet,
1736 OHCI1394_LinkControl_rcvSelfID |
1737 OHCI1394_LinkControl_cycleTimerEnable |
1738 OHCI1394_LinkControl_cycleMaster);
1740 reg_write(ohci, OHCI1394_ATRetries,
1741 OHCI1394_MAX_AT_REQ_RETRIES |
1742 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1743 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1746 seconds = lower_32_bits(get_seconds());
1747 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1748 ohci->bus_time = seconds & ~0x3f;
1750 /* Get implemented bits of the priority arbitration request counter. */
1751 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1752 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1753 reg_write(ohci, OHCI1394_FairnessControl, 0);
1755 ar_context_run(&ohci->ar_request_ctx);
1756 ar_context_run(&ohci->ar_response_ctx);
1758 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1759 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1760 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1762 ret = configure_1394a_enhancements(ohci);
1766 /* Activate link_on bit and contender bit in our self ID packets.*/
1767 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1772 * When the link is not yet enabled, the atomic config rom
1773 * update mechanism described below in ohci_set_config_rom()
1774 * is not active. We have to update ConfigRomHeader and
1775 * BusOptions manually, and the write to ConfigROMmap takes
1776 * effect immediately. We tie this to the enabling of the
1777 * link, so we have a valid config rom before enabling - the
1778 * OHCI requires that ConfigROMhdr and BusOptions have valid
1779 * values before enabling.
1781 * However, when the ConfigROMmap is written, some controllers
1782 * always read back quadlets 0 and 2 from the config rom to
1783 * the ConfigRomHeader and BusOptions registers on bus reset.
1784 * They shouldn't do that in this initial case where the link
1785 * isn't enabled. This means we have to use the same
1786 * workaround here, setting the bus header to 0 and then write
1787 * the right values in the bus reset tasklet.
1791 ohci->next_config_rom =
1792 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1793 &ohci->next_config_rom_bus,
1795 if (ohci->next_config_rom == NULL)
1798 copy_config_rom(ohci->next_config_rom, config_rom, length);
1801 * In the suspend case, config_rom is NULL, which
1802 * means that we just reuse the old config rom.
1804 ohci->next_config_rom = ohci->config_rom;
1805 ohci->next_config_rom_bus = ohci->config_rom_bus;
1808 ohci->next_header = ohci->next_config_rom[0];
1809 ohci->next_config_rom[0] = 0;
1810 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1811 reg_write(ohci, OHCI1394_BusOptions,
1812 be32_to_cpu(ohci->next_config_rom[2]));
1813 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1815 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1817 if (!(ohci->quirks & QUIRK_NO_MSI))
1818 pci_enable_msi(dev);
1819 if (request_irq(dev->irq, irq_handler,
1820 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1821 ohci_driver_name, ohci)) {
1822 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1823 pci_disable_msi(dev);
1824 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1825 ohci->config_rom, ohci->config_rom_bus);
1829 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1830 OHCI1394_RQPkt | OHCI1394_RSPkt |
1831 OHCI1394_isochTx | OHCI1394_isochRx |
1832 OHCI1394_postedWriteErr |
1833 OHCI1394_selfIDComplete |
1834 OHCI1394_regAccessFail |
1835 OHCI1394_cycle64Seconds |
1836 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1837 OHCI1394_masterIntEnable;
1838 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1839 irqs |= OHCI1394_busReset;
1840 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1842 reg_write(ohci, OHCI1394_HCControlSet,
1843 OHCI1394_HCControl_linkEnable |
1844 OHCI1394_HCControl_BIBimageValid);
1848 * We are ready to go, initiate bus reset to finish the
1852 fw_core_initiate_bus_reset(&ohci->card, 1);
1857 static int ohci_set_config_rom(struct fw_card *card,
1858 const __be32 *config_rom, size_t length)
1860 struct fw_ohci *ohci;
1861 unsigned long flags;
1863 __be32 *next_config_rom;
1864 dma_addr_t uninitialized_var(next_config_rom_bus);
1866 ohci = fw_ohci(card);
1869 * When the OHCI controller is enabled, the config rom update
1870 * mechanism is a bit tricky, but easy enough to use. See
1871 * section 5.5.6 in the OHCI specification.
1873 * The OHCI controller caches the new config rom address in a
1874 * shadow register (ConfigROMmapNext) and needs a bus reset
1875 * for the changes to take place. When the bus reset is
1876 * detected, the controller loads the new values for the
1877 * ConfigRomHeader and BusOptions registers from the specified
1878 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1879 * shadow register. All automatically and atomically.
1881 * Now, there's a twist to this story. The automatic load of
1882 * ConfigRomHeader and BusOptions doesn't honor the
1883 * noByteSwapData bit, so with a be32 config rom, the
1884 * controller will load be32 values in to these registers
1885 * during the atomic update, even on litte endian
1886 * architectures. The workaround we use is to put a 0 in the
1887 * header quadlet; 0 is endian agnostic and means that the
1888 * config rom isn't ready yet. In the bus reset tasklet we
1889 * then set up the real values for the two registers.
1891 * We use ohci->lock to avoid racing with the code that sets
1892 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1896 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1897 &next_config_rom_bus, GFP_KERNEL);
1898 if (next_config_rom == NULL)
1901 spin_lock_irqsave(&ohci->lock, flags);
1903 if (ohci->next_config_rom == NULL) {
1904 ohci->next_config_rom = next_config_rom;
1905 ohci->next_config_rom_bus = next_config_rom_bus;
1907 copy_config_rom(ohci->next_config_rom, config_rom, length);
1909 ohci->next_header = config_rom[0];
1910 ohci->next_config_rom[0] = 0;
1912 reg_write(ohci, OHCI1394_ConfigROMmap,
1913 ohci->next_config_rom_bus);
1917 spin_unlock_irqrestore(&ohci->lock, flags);
1920 * Now initiate a bus reset to have the changes take
1921 * effect. We clean up the old config rom memory and DMA
1922 * mappings in the bus reset tasklet, since the OHCI
1923 * controller could need to access it before the bus reset
1927 fw_core_initiate_bus_reset(&ohci->card, 1);
1929 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1930 next_config_rom, next_config_rom_bus);
1935 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1937 struct fw_ohci *ohci = fw_ohci(card);
1939 at_context_transmit(&ohci->at_request_ctx, packet);
1942 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1944 struct fw_ohci *ohci = fw_ohci(card);
1946 at_context_transmit(&ohci->at_response_ctx, packet);
1949 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1951 struct fw_ohci *ohci = fw_ohci(card);
1952 struct context *ctx = &ohci->at_request_ctx;
1953 struct driver_data *driver_data = packet->driver_data;
1956 tasklet_disable(&ctx->tasklet);
1958 if (packet->ack != 0)
1961 if (packet->payload_mapped)
1962 dma_unmap_single(ohci->card.device, packet->payload_bus,
1963 packet->payload_length, DMA_TO_DEVICE);
1965 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1966 driver_data->packet = NULL;
1967 packet->ack = RCODE_CANCELLED;
1968 packet->callback(packet, &ohci->card, packet->ack);
1971 tasklet_enable(&ctx->tasklet);
1976 static int ohci_enable_phys_dma(struct fw_card *card,
1977 int node_id, int generation)
1979 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1982 struct fw_ohci *ohci = fw_ohci(card);
1983 unsigned long flags;
1987 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1988 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1991 spin_lock_irqsave(&ohci->lock, flags);
1993 if (ohci->generation != generation) {
1999 * Note, if the node ID contains a non-local bus ID, physical DMA is
2000 * enabled for _all_ nodes on remote buses.
2003 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2005 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2007 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2011 spin_unlock_irqrestore(&ohci->lock, flags);
2014 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2017 static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset)
2019 struct fw_ohci *ohci = fw_ohci(card);
2020 unsigned long flags;
2023 switch (csr_offset) {
2024 case CSR_STATE_CLEAR:
2026 /* the controller driver handles only the cmstr bit */
2027 if (ohci->is_root &&
2028 (reg_read(ohci, OHCI1394_LinkControlSet) &
2029 OHCI1394_LinkControl_cycleMaster))
2030 return CSR_STATE_BIT_CMSTR;
2035 return reg_read(ohci, OHCI1394_NodeID) << 16;
2037 case CSR_CYCLE_TIME:
2038 return get_cycle_time(ohci);
2042 * We might be called just after the cycle timer has wrapped
2043 * around but just before the cycle64Seconds handler, so we
2044 * better check here, too, if the bus time needs to be updated.
2046 spin_lock_irqsave(&ohci->lock, flags);
2047 value = update_bus_time(ohci);
2048 spin_unlock_irqrestore(&ohci->lock, flags);
2051 case CSR_BUSY_TIMEOUT:
2052 value = reg_read(ohci, OHCI1394_ATRetries);
2053 return (value >> 4) & 0x0ffff00f;
2055 case CSR_PRIORITY_BUDGET:
2056 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2057 (ohci->pri_req_max << 8);
2065 static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
2067 struct fw_ohci *ohci = fw_ohci(card);
2068 unsigned long flags;
2070 switch (csr_offset) {
2071 case CSR_STATE_CLEAR:
2072 /* the controller driver handles only the cmstr bit */
2073 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2074 reg_write(ohci, OHCI1394_LinkControlClear,
2075 OHCI1394_LinkControl_cycleMaster);
2081 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2082 reg_write(ohci, OHCI1394_LinkControlSet,
2083 OHCI1394_LinkControl_cycleMaster);
2089 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2093 case CSR_CYCLE_TIME:
2094 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2095 reg_write(ohci, OHCI1394_IntEventSet,
2096 OHCI1394_cycleInconsistent);
2101 spin_lock_irqsave(&ohci->lock, flags);
2102 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2103 spin_unlock_irqrestore(&ohci->lock, flags);
2106 case CSR_BUSY_TIMEOUT:
2107 value = (value & 0xf) | ((value & 0xf) << 4) |
2108 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2109 reg_write(ohci, OHCI1394_ATRetries, value);
2113 case CSR_PRIORITY_BUDGET:
2114 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2124 static unsigned int ohci_get_features(struct fw_card *card)
2126 struct fw_ohci *ohci = fw_ohci(card);
2127 unsigned int features = 0;
2129 if (ohci->pri_req_max != 0)
2130 features |= FEATURE_PRIORITY_BUDGET;
2135 static void copy_iso_headers(struct iso_context *ctx, void *p)
2137 int i = ctx->header_length;
2139 if (i + ctx->base.header_size > PAGE_SIZE)
2143 * The iso header is byteswapped to little endian by
2144 * the controller, but the remaining header quadlets
2145 * are big endian. We want to present all the headers
2146 * as big endian, so we have to swap the first quadlet.
2148 if (ctx->base.header_size > 0)
2149 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2150 if (ctx->base.header_size > 4)
2151 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2152 if (ctx->base.header_size > 8)
2153 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2154 ctx->header_length += ctx->base.header_size;
2157 static int handle_ir_packet_per_buffer(struct context *context,
2158 struct descriptor *d,
2159 struct descriptor *last)
2161 struct iso_context *ctx =
2162 container_of(context, struct iso_context, context);
2163 struct descriptor *pd;
2167 for (pd = d; pd <= last; pd++) {
2168 if (pd->transfer_status)
2172 /* Descriptor(s) not done yet, stop iteration */
2176 copy_iso_headers(ctx, p);
2178 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2179 ir_header = (__le32 *) p;
2180 ctx->base.callback(&ctx->base,
2181 le32_to_cpu(ir_header[0]) & 0xffff,
2182 ctx->header_length, ctx->header,
2183 ctx->base.callback_data);
2184 ctx->header_length = 0;
2190 static int handle_it_packet(struct context *context,
2191 struct descriptor *d,
2192 struct descriptor *last)
2194 struct iso_context *ctx =
2195 container_of(context, struct iso_context, context);
2197 struct descriptor *pd;
2199 for (pd = d; pd <= last; pd++)
2200 if (pd->transfer_status)
2203 /* Descriptor(s) not done yet, stop iteration */
2206 i = ctx->header_length;
2207 if (i + 4 < PAGE_SIZE) {
2208 /* Present this value as big-endian to match the receive code */
2209 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2210 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2211 le16_to_cpu(pd->res_count));
2212 ctx->header_length += 4;
2214 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2215 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2216 ctx->header_length, ctx->header,
2217 ctx->base.callback_data);
2218 ctx->header_length = 0;
2223 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2224 int type, int channel, size_t header_size)
2226 struct fw_ohci *ohci = fw_ohci(card);
2227 struct iso_context *ctx, *list;
2228 descriptor_callback_t callback;
2229 u64 *channels, dont_care = ~0ULL;
2231 unsigned long flags;
2232 int index, ret = -ENOMEM;
2234 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2235 channels = &dont_care;
2236 mask = &ohci->it_context_mask;
2237 list = ohci->it_context_list;
2238 callback = handle_it_packet;
2240 channels = &ohci->ir_context_channels;
2241 mask = &ohci->ir_context_mask;
2242 list = ohci->ir_context_list;
2243 callback = handle_ir_packet_per_buffer;
2246 spin_lock_irqsave(&ohci->lock, flags);
2247 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2249 *channels &= ~(1ULL << channel);
2250 *mask &= ~(1 << index);
2252 spin_unlock_irqrestore(&ohci->lock, flags);
2255 return ERR_PTR(-EBUSY);
2257 if (type == FW_ISO_CONTEXT_TRANSMIT)
2258 regs = OHCI1394_IsoXmitContextBase(index);
2260 regs = OHCI1394_IsoRcvContextBase(index);
2263 memset(ctx, 0, sizeof(*ctx));
2264 ctx->header_length = 0;
2265 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2266 if (ctx->header == NULL)
2269 ret = context_init(&ctx->context, ohci, regs, callback);
2271 goto out_with_header;
2276 free_page((unsigned long)ctx->header);
2278 spin_lock_irqsave(&ohci->lock, flags);
2279 *mask |= 1 << index;
2280 spin_unlock_irqrestore(&ohci->lock, flags);
2282 return ERR_PTR(ret);
2285 static int ohci_start_iso(struct fw_iso_context *base,
2286 s32 cycle, u32 sync, u32 tags)
2288 struct iso_context *ctx = container_of(base, struct iso_context, base);
2289 struct fw_ohci *ohci = ctx->context.ohci;
2293 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2294 index = ctx - ohci->it_context_list;
2297 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2298 (cycle & 0x7fff) << 16;
2300 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2301 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2302 context_run(&ctx->context, match);
2304 index = ctx - ohci->ir_context_list;
2305 control = IR_CONTEXT_ISOCH_HEADER;
2306 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2308 match |= (cycle & 0x07fff) << 12;
2309 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2312 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2313 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2314 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2315 context_run(&ctx->context, control);
2321 static int ohci_stop_iso(struct fw_iso_context *base)
2323 struct fw_ohci *ohci = fw_ohci(base->card);
2324 struct iso_context *ctx = container_of(base, struct iso_context, base);
2327 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2328 index = ctx - ohci->it_context_list;
2329 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2331 index = ctx - ohci->ir_context_list;
2332 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2335 context_stop(&ctx->context);
2340 static void ohci_free_iso_context(struct fw_iso_context *base)
2342 struct fw_ohci *ohci = fw_ohci(base->card);
2343 struct iso_context *ctx = container_of(base, struct iso_context, base);
2344 unsigned long flags;
2347 ohci_stop_iso(base);
2348 context_release(&ctx->context);
2349 free_page((unsigned long)ctx->header);
2351 spin_lock_irqsave(&ohci->lock, flags);
2353 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2354 index = ctx - ohci->it_context_list;
2355 ohci->it_context_mask |= 1 << index;
2357 index = ctx - ohci->ir_context_list;
2358 ohci->ir_context_mask |= 1 << index;
2359 ohci->ir_context_channels |= 1ULL << base->channel;
2362 spin_unlock_irqrestore(&ohci->lock, flags);
2365 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2366 struct fw_iso_packet *packet,
2367 struct fw_iso_buffer *buffer,
2368 unsigned long payload)
2370 struct iso_context *ctx = container_of(base, struct iso_context, base);
2371 struct descriptor *d, *last, *pd;
2372 struct fw_iso_packet *p;
2374 dma_addr_t d_bus, page_bus;
2375 u32 z, header_z, payload_z, irq;
2376 u32 payload_index, payload_end_index, next_page_index;
2377 int page, end_page, i, length, offset;
2380 payload_index = payload;
2386 if (p->header_length > 0)
2389 /* Determine the first page the payload isn't contained in. */
2390 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2391 if (p->payload_length > 0)
2392 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2398 /* Get header size in number of descriptors. */
2399 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2401 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2406 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2407 d[0].req_count = cpu_to_le16(8);
2409 * Link the skip address to this descriptor itself. This causes
2410 * a context to skip a cycle whenever lost cycles or FIFO
2411 * overruns occur, without dropping the data. The application
2412 * should then decide whether this is an error condition or not.
2413 * FIXME: Make the context's cycle-lost behaviour configurable?
2415 d[0].branch_address = cpu_to_le32(d_bus | z);
2417 header = (__le32 *) &d[1];
2418 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2419 IT_HEADER_TAG(p->tag) |
2420 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2421 IT_HEADER_CHANNEL(ctx->base.channel) |
2422 IT_HEADER_SPEED(ctx->base.speed));
2424 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2425 p->payload_length));
2428 if (p->header_length > 0) {
2429 d[2].req_count = cpu_to_le16(p->header_length);
2430 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2431 memcpy(&d[z], p->header, p->header_length);
2434 pd = d + z - payload_z;
2435 payload_end_index = payload_index + p->payload_length;
2436 for (i = 0; i < payload_z; i++) {
2437 page = payload_index >> PAGE_SHIFT;
2438 offset = payload_index & ~PAGE_MASK;
2439 next_page_index = (page + 1) << PAGE_SHIFT;
2441 min(next_page_index, payload_end_index) - payload_index;
2442 pd[i].req_count = cpu_to_le16(length);
2444 page_bus = page_private(buffer->pages[page]);
2445 pd[i].data_address = cpu_to_le32(page_bus + offset);
2447 payload_index += length;
2451 irq = DESCRIPTOR_IRQ_ALWAYS;
2453 irq = DESCRIPTOR_NO_IRQ;
2455 last = z == 2 ? d : d + z - 1;
2456 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2458 DESCRIPTOR_BRANCH_ALWAYS |
2461 context_append(&ctx->context, d, z, header_z);
2466 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2467 struct fw_iso_packet *packet,
2468 struct fw_iso_buffer *buffer,
2469 unsigned long payload)
2471 struct iso_context *ctx = container_of(base, struct iso_context, base);
2472 struct descriptor *d, *pd;
2473 struct fw_iso_packet *p = packet;
2474 dma_addr_t d_bus, page_bus;
2475 u32 z, header_z, rest;
2477 int page, offset, packet_count, header_size, payload_per_buffer;
2480 * The OHCI controller puts the isochronous header and trailer in the
2481 * buffer, so we need at least 8 bytes.
2483 packet_count = p->header_length / ctx->base.header_size;
2484 header_size = max(ctx->base.header_size, (size_t)8);
2486 /* Get header size in number of descriptors. */
2487 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2488 page = payload >> PAGE_SHIFT;
2489 offset = payload & ~PAGE_MASK;
2490 payload_per_buffer = p->payload_length / packet_count;
2492 for (i = 0; i < packet_count; i++) {
2493 /* d points to the header descriptor */
2494 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2495 d = context_get_descriptors(&ctx->context,
2496 z + header_z, &d_bus);
2500 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2501 DESCRIPTOR_INPUT_MORE);
2502 if (p->skip && i == 0)
2503 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2504 d->req_count = cpu_to_le16(header_size);
2505 d->res_count = d->req_count;
2506 d->transfer_status = 0;
2507 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2509 rest = payload_per_buffer;
2511 for (j = 1; j < z; j++) {
2513 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2514 DESCRIPTOR_INPUT_MORE);
2516 if (offset + rest < PAGE_SIZE)
2519 length = PAGE_SIZE - offset;
2520 pd->req_count = cpu_to_le16(length);
2521 pd->res_count = pd->req_count;
2522 pd->transfer_status = 0;
2524 page_bus = page_private(buffer->pages[page]);
2525 pd->data_address = cpu_to_le32(page_bus + offset);
2527 offset = (offset + length) & ~PAGE_MASK;
2532 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2533 DESCRIPTOR_INPUT_LAST |
2534 DESCRIPTOR_BRANCH_ALWAYS);
2535 if (p->interrupt && i == packet_count - 1)
2536 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2538 context_append(&ctx->context, d, z, header_z);
2544 static int ohci_queue_iso(struct fw_iso_context *base,
2545 struct fw_iso_packet *packet,
2546 struct fw_iso_buffer *buffer,
2547 unsigned long payload)
2549 struct iso_context *ctx = container_of(base, struct iso_context, base);
2550 unsigned long flags;
2553 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2554 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2555 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2557 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2559 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2564 static const struct fw_card_driver ohci_driver = {
2565 .enable = ohci_enable,
2566 .update_phy_reg = ohci_update_phy_reg,
2567 .set_config_rom = ohci_set_config_rom,
2568 .send_request = ohci_send_request,
2569 .send_response = ohci_send_response,
2570 .cancel_packet = ohci_cancel_packet,
2571 .enable_phys_dma = ohci_enable_phys_dma,
2572 .read_csr_reg = ohci_read_csr_reg,
2573 .write_csr_reg = ohci_write_csr_reg,
2574 .get_features = ohci_get_features,
2576 .allocate_iso_context = ohci_allocate_iso_context,
2577 .free_iso_context = ohci_free_iso_context,
2578 .queue_iso = ohci_queue_iso,
2579 .start_iso = ohci_start_iso,
2580 .stop_iso = ohci_stop_iso,
2583 #ifdef CONFIG_PPC_PMAC
2584 static void pmac_ohci_on(struct pci_dev *dev)
2586 if (machine_is(powermac)) {
2587 struct device_node *ofn = pci_device_to_OF_node(dev);
2590 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2591 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2596 static void pmac_ohci_off(struct pci_dev *dev)
2598 if (machine_is(powermac)) {
2599 struct device_node *ofn = pci_device_to_OF_node(dev);
2602 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2603 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2608 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2609 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2610 #endif /* CONFIG_PPC_PMAC */
2612 static int __devinit pci_probe(struct pci_dev *dev,
2613 const struct pci_device_id *ent)
2615 struct fw_ohci *ohci;
2616 u32 bus_options, max_receive, link_speed, version, link_enh;
2618 int i, err, n_ir, n_it;
2621 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2627 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2631 err = pci_enable_device(dev);
2633 fw_error("Failed to enable OHCI hardware\n");
2637 pci_set_master(dev);
2638 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2639 pci_set_drvdata(dev, ohci);
2641 spin_lock_init(&ohci->lock);
2643 tasklet_init(&ohci->bus_reset_tasklet,
2644 bus_reset_tasklet, (unsigned long)ohci);
2646 err = pci_request_region(dev, 0, ohci_driver_name);
2648 fw_error("MMIO resource unavailable\n");
2652 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2653 if (ohci->registers == NULL) {
2654 fw_error("Failed to remap registers\n");
2659 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2660 if (ohci_quirks[i].vendor == dev->vendor &&
2661 (ohci_quirks[i].device == dev->device ||
2662 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2663 ohci->quirks = ohci_quirks[i].flags;
2667 ohci->quirks = param_quirks;
2669 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2670 if (dev->vendor == PCI_VENDOR_ID_TI) {
2671 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2673 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2674 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2675 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2677 /* use priority arbitration for asynchronous responses */
2678 link_enh |= TI_LinkEnh_enab_unfair;
2680 /* required for aPhyEnhanceEnable to work */
2681 link_enh |= TI_LinkEnh_enab_accel;
2683 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2686 ar_context_init(&ohci->ar_request_ctx, ohci,
2687 OHCI1394_AsReqRcvContextControlSet);
2689 ar_context_init(&ohci->ar_response_ctx, ohci,
2690 OHCI1394_AsRspRcvContextControlSet);
2692 context_init(&ohci->at_request_ctx, ohci,
2693 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2695 context_init(&ohci->at_response_ctx, ohci,
2696 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2698 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2699 ohci->ir_context_channels = ~0ULL;
2700 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2701 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2702 n_ir = hweight32(ohci->ir_context_mask);
2703 size = sizeof(struct iso_context) * n_ir;
2704 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2706 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2707 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2708 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2709 n_it = hweight32(ohci->it_context_mask);
2710 size = sizeof(struct iso_context) * n_it;
2711 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2713 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2718 /* self-id dma buffer allocation */
2719 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2723 if (ohci->self_id_cpu == NULL) {
2728 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2729 max_receive = (bus_options >> 12) & 0xf;
2730 link_speed = bus_options & 0x7;
2731 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2732 reg_read(ohci, OHCI1394_GUIDLo);
2734 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2738 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2739 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2740 "%d IR + %d IT contexts, quirks 0x%x\n",
2741 dev_name(&dev->dev), version >> 16, version & 0xff,
2742 n_ir, n_it, ohci->quirks);
2747 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2748 ohci->self_id_cpu, ohci->self_id_bus);
2750 kfree(ohci->ir_context_list);
2751 kfree(ohci->it_context_list);
2752 context_release(&ohci->at_response_ctx);
2753 context_release(&ohci->at_request_ctx);
2754 ar_context_release(&ohci->ar_response_ctx);
2755 ar_context_release(&ohci->ar_request_ctx);
2756 pci_iounmap(dev, ohci->registers);
2758 pci_release_region(dev, 0);
2760 pci_disable_device(dev);
2766 fw_error("Out of memory\n");
2771 static void pci_remove(struct pci_dev *dev)
2773 struct fw_ohci *ohci;
2775 ohci = pci_get_drvdata(dev);
2776 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2778 fw_core_remove_card(&ohci->card);
2781 * FIXME: Fail all pending packets here, now that the upper
2782 * layers can't queue any more.
2785 software_reset(ohci);
2786 free_irq(dev->irq, ohci);
2788 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2789 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2790 ohci->next_config_rom, ohci->next_config_rom_bus);
2791 if (ohci->config_rom)
2792 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2793 ohci->config_rom, ohci->config_rom_bus);
2794 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2795 ohci->self_id_cpu, ohci->self_id_bus);
2796 ar_context_release(&ohci->ar_request_ctx);
2797 ar_context_release(&ohci->ar_response_ctx);
2798 context_release(&ohci->at_request_ctx);
2799 context_release(&ohci->at_response_ctx);
2800 kfree(ohci->it_context_list);
2801 kfree(ohci->ir_context_list);
2802 pci_disable_msi(dev);
2803 pci_iounmap(dev, ohci->registers);
2804 pci_release_region(dev, 0);
2805 pci_disable_device(dev);
2809 fw_notify("Removed fw-ohci device.\n");
2813 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2815 struct fw_ohci *ohci = pci_get_drvdata(dev);
2818 software_reset(ohci);
2819 free_irq(dev->irq, ohci);
2820 pci_disable_msi(dev);
2821 err = pci_save_state(dev);
2823 fw_error("pci_save_state failed\n");
2826 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2828 fw_error("pci_set_power_state failed with %d\n", err);
2834 static int pci_resume(struct pci_dev *dev)
2836 struct fw_ohci *ohci = pci_get_drvdata(dev);
2840 pci_set_power_state(dev, PCI_D0);
2841 pci_restore_state(dev);
2842 err = pci_enable_device(dev);
2844 fw_error("pci_enable_device failed\n");
2848 return ohci_enable(&ohci->card, NULL, 0);
2852 static const struct pci_device_id pci_table[] = {
2853 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2857 MODULE_DEVICE_TABLE(pci, pci_table);
2859 static struct pci_driver fw_ohci_pci_driver = {
2860 .name = ohci_driver_name,
2861 .id_table = pci_table,
2863 .remove = pci_remove,
2865 .resume = pci_resume,
2866 .suspend = pci_suspend,
2870 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2871 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2872 MODULE_LICENSE("GPL");
2874 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2875 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2876 MODULE_ALIAS("ohci1394");
2879 static int __init fw_ohci_init(void)
2881 return pci_register_driver(&fw_ohci_pci_driver);
2884 static void __exit fw_ohci_cleanup(void)
2886 pci_unregister_driver(&fw_ohci_pci_driver);
2889 module_init(fw_ohci_init);
2890 module_exit(fw_ohci_cleanup);