2 * Copyright (C) 2008, 2009 Provigent Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
10 * Data sheet: ARM DDI 0190B, September 2000
12 #include <linux/spinlock.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/bitops.h>
20 #include <linux/workqueue.h>
21 #include <linux/gpio.h>
22 #include <linux/device.h>
23 #include <linux/amba/bus.h>
24 #include <linux/amba/pl061.h>
25 #include <linux/slab.h>
27 #include <asm/mach/irq.h>
38 #define PL061_GPIO_NR 8
41 struct pl061_context_save_regs {
55 struct irq_domain *domain;
59 struct pl061_context_save_regs csave_regs;
63 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
65 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
67 unsigned char gpiodir;
69 if (offset >= gc->ngpio)
72 spin_lock_irqsave(&chip->lock, flags);
73 gpiodir = readb(chip->base + GPIODIR);
74 gpiodir &= ~(1 << offset);
75 writeb(gpiodir, chip->base + GPIODIR);
76 spin_unlock_irqrestore(&chip->lock, flags);
81 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
84 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
86 unsigned char gpiodir;
88 if (offset >= gc->ngpio)
91 spin_lock_irqsave(&chip->lock, flags);
92 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
93 gpiodir = readb(chip->base + GPIODIR);
94 gpiodir |= 1 << offset;
95 writeb(gpiodir, chip->base + GPIODIR);
98 * gpio value is set again, because pl061 doesn't allow to set value of
99 * a gpio pin before configuring it in OUT mode.
101 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
102 spin_unlock_irqrestore(&chip->lock, flags);
107 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
109 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
111 return !!readb(chip->base + (1 << (offset + 2)));
114 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
116 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
118 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
121 static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
123 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
125 return irq_create_mapping(chip->domain, offset);
128 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
130 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
131 int offset = irqd_to_hwirq(d);
133 u8 gpiois, gpioibe, gpioiev;
135 if (offset < 0 || offset >= PL061_GPIO_NR)
138 spin_lock_irqsave(&chip->lock, flags);
140 gpioiev = readb(chip->base + GPIOIEV);
142 gpiois = readb(chip->base + GPIOIS);
143 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
144 gpiois |= 1 << offset;
145 if (trigger & IRQ_TYPE_LEVEL_HIGH)
146 gpioiev |= 1 << offset;
148 gpioiev &= ~(1 << offset);
150 gpiois &= ~(1 << offset);
151 writeb(gpiois, chip->base + GPIOIS);
153 gpioibe = readb(chip->base + GPIOIBE);
154 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
155 gpioibe |= 1 << offset;
157 gpioibe &= ~(1 << offset);
158 if (trigger & IRQ_TYPE_EDGE_RISING)
159 gpioiev |= 1 << offset;
160 else if (trigger & IRQ_TYPE_EDGE_FALLING)
161 gpioiev &= ~(1 << offset);
163 writeb(gpioibe, chip->base + GPIOIBE);
165 writeb(gpioiev, chip->base + GPIOIEV);
167 spin_unlock_irqrestore(&chip->lock, flags);
172 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
174 unsigned long pending;
176 struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
177 struct irq_chip *irqchip = irq_desc_get_chip(desc);
179 chained_irq_enter(irqchip, desc);
181 pending = readb(chip->base + GPIOMIS);
182 writeb(pending, chip->base + GPIOIC);
184 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
185 generic_handle_irq(pl061_to_irq(&chip->gc, offset));
188 chained_irq_exit(irqchip, desc);
191 static void pl061_irq_mask(struct irq_data *d)
193 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
194 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
197 spin_lock(&chip->lock);
198 gpioie = readb(chip->base + GPIOIE) & ~mask;
199 writeb(gpioie, chip->base + GPIOIE);
200 spin_unlock(&chip->lock);
203 static void pl061_irq_unmask(struct irq_data *d)
205 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
206 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
209 spin_lock(&chip->lock);
210 gpioie = readb(chip->base + GPIOIE) | mask;
211 writeb(gpioie, chip->base + GPIOIE);
212 spin_unlock(&chip->lock);
215 static struct irq_chip pl061_irqchip = {
216 .name = "pl061 gpio",
217 .irq_mask = pl061_irq_mask,
218 .irq_unmask = pl061_irq_unmask,
219 .irq_set_type = pl061_irq_type,
222 static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
225 struct pl061_gpio *chip = d->host_data;
227 irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
229 irq_set_chip_data(virq, chip);
230 irq_set_irq_type(virq, IRQ_TYPE_NONE);
235 static const struct irq_domain_ops pl061_domain_ops = {
236 .map = pl061_irq_map,
237 .xlate = irq_domain_xlate_twocell,
240 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
242 struct device *dev = &adev->dev;
243 struct pl061_platform_data *pdata = dev->platform_data;
244 struct pl061_gpio *chip;
245 int ret, irq, i, irq_base;
247 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
252 chip->gc.base = pdata->gpio_base;
253 irq_base = pdata->irq_base;
261 if (!devm_request_mem_region(dev, adev->res.start,
262 resource_size(&adev->res), "pl061"))
265 chip->base = devm_ioremap(dev, adev->res.start,
266 resource_size(&adev->res));
270 chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
271 irq_base, &pl061_domain_ops, chip);
275 spin_lock_init(&chip->lock);
277 chip->gc.direction_input = pl061_direction_input;
278 chip->gc.direction_output = pl061_direction_output;
279 chip->gc.get = pl061_get_value;
280 chip->gc.set = pl061_set_value;
281 chip->gc.to_irq = pl061_to_irq;
282 chip->gc.ngpio = PL061_GPIO_NR;
283 chip->gc.label = dev_name(dev);
285 chip->gc.owner = THIS_MODULE;
287 ret = gpiochip_add(&chip->gc);
294 writeb(0, chip->base + GPIOIE); /* disable irqs */
299 irq_set_chained_handler(irq, pl061_irq_handler);
300 irq_set_handler_data(irq, chip);
302 for (i = 0; i < PL061_GPIO_NR; i++) {
304 if (pdata->directions & (1 << i))
305 pl061_direction_output(&chip->gc, i,
306 pdata->values & (1 << i));
308 pl061_direction_input(&chip->gc, i);
312 amba_set_drvdata(adev, chip);
318 static int pl061_suspend(struct device *dev)
320 struct pl061_gpio *chip = dev_get_drvdata(dev);
323 chip->csave_regs.gpio_data = 0;
324 chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
325 chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
326 chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
327 chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
328 chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
330 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
331 if (chip->csave_regs.gpio_dir & (1 << offset))
332 chip->csave_regs.gpio_data |=
333 pl061_get_value(&chip->gc, offset) << offset;
339 static int pl061_resume(struct device *dev)
341 struct pl061_gpio *chip = dev_get_drvdata(dev);
344 for (offset = 0; offset < PL061_GPIO_NR; offset++) {
345 if (chip->csave_regs.gpio_dir & (1 << offset))
346 pl061_direction_output(&chip->gc, offset,
347 chip->csave_regs.gpio_data &
350 pl061_direction_input(&chip->gc, offset);
353 writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
354 writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
355 writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
356 writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
361 static const struct dev_pm_ops pl061_dev_pm_ops = {
362 .suspend = pl061_suspend,
363 .resume = pl061_resume,
364 .freeze = pl061_suspend,
365 .restore = pl061_resume,
369 static struct amba_id pl061_ids[] = {
377 MODULE_DEVICE_TABLE(amba, pl061_ids);
379 static struct amba_driver pl061_gpio_driver = {
381 .name = "pl061_gpio",
383 .pm = &pl061_dev_pm_ops,
386 .id_table = pl061_ids,
387 .probe = pl061_probe,
390 static int __init pl061_gpio_init(void)
392 return amba_driver_register(&pl061_gpio_driver);
394 module_init(pl061_gpio_init);
396 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
397 MODULE_DESCRIPTION("PL061 GPIO driver");
398 MODULE_LICENSE("GPL");