drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.
  48  */
  49
  50 /**
  51  * amdgpu_fence_write - write a fence value
  52  *
  53  * @ring: ring the fence is associated with
  54  * @seq: sequence number to write
  55  *
  56  * Writes a fence value to memory (all asics).
  57  */
  58 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  59 {
  60         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  61
  62         if (drv->cpu_addr)
  63                 *drv->cpu_addr = cpu_to_le32(seq);
  64 }
  65
  66 /**
  67  * amdgpu_fence_read - read a fence value
  68  *
  69  * @ring: ring the fence is associated with
  70  *
  71  * Reads a fence value from memory (all asics).
  72  * Returns the value of the fence read from memory.
  73  */
  74 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
  75 {
  76         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  77         u32 seq = 0;
  78
  79         if (drv->cpu_addr)
  80                 seq = le32_to_cpu(*drv->cpu_addr);
  81         else
  82                 seq = lower_32_bits(atomic64_read(&drv->last_seq));
  83
  84         return seq;
  85 }
  86
  87 /**
  88  * amdgpu_fence_schedule_check - schedule lockup check
  89  *
  90  * @ring: pointer to struct amdgpu_ring
  91  *
  92  * Queues a delayed work item to check for lockups.
  93  */
  94 static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring)
  95 {
  96         /*
  97          * Do not reset the timer here with mod_delayed_work,
  98          * this can livelock in an interaction with TTM delayed destroy.
  99          */
 100         queue_delayed_work(system_power_efficient_wq,
 101                 &ring->fence_drv.lockup_work,
 102                 AMDGPU_FENCE_JIFFIES_TIMEOUT);
 103 }
 104
 105 /**
 106  * amdgpu_fence_emit - emit a fence on the requested ring
 107  *
 108  * @ring: ring the fence is associated with
 109  * @owner: creator of the fence
 110  * @fence: amdgpu fence object
 111  *
 112  * Emits a fence command on the requested ring (all asics).
 113  * Returns 0 on success, -ENOMEM on failure.
 114  */
 115 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
 116                       struct amdgpu_fence **fence)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         /* we are protected by the ring emission mutex */
 121         *fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
 122         if ((*fence) == NULL) {
 123                 return -ENOMEM;
 124         }
 125         (*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
 126         (*fence)->ring = ring;
 127         (*fence)->owner = owner;
 128         fence_init(&(*fence)->base, &amdgpu_fence_ops,
 129                 &adev->fence_queue.lock, adev->fence_context + ring->idx,
 130                 (*fence)->seq);
 131         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 132                                (*fence)->seq,
 133                                AMDGPU_FENCE_FLAG_INT);
 134         trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq);
 135         return 0;
 136 }
 137
 138 /**
 139  * amdgpu_fence_check_signaled - callback from fence_queue
 140  *
 141  * this function is called with fence_queue lock held, which is also used
 142  * for the fence locking itself, so unlocked variants are used for
 143  * fence_signal, and remove_wait_queue.
 144  */
 145 static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
 146 {
 147         struct amdgpu_fence *fence;
 148         struct amdgpu_device *adev;
 149         u64 seq;
 150         int ret;
 151
 152         fence = container_of(wait, struct amdgpu_fence, fence_wake);
 153         adev = fence->ring->adev;
 154
 155         /*
 156          * We cannot use amdgpu_fence_process here because we're already
 157          * in the waitqueue, in a call from wake_up_all.
 158          */
 159         seq = atomic64_read(&fence->ring->fence_drv.last_seq);
 160         if (seq >= fence->seq) {
 161                 ret = fence_signal_locked(&fence->base);
 162                 if (!ret)
 163                         FENCE_TRACE(&fence->base, "signaled from irq context\n");
 164                 else
 165                         FENCE_TRACE(&fence->base, "was already signaled\n");
 166
 167                 __remove_wait_queue(&adev->fence_queue, &fence->fence_wake);
 168                 fence_put(&fence->base);
 169         } else
 170                 FENCE_TRACE(&fence->base, "pending\n");
 171         return 0;
 172 }
 173
 174 /**
 175  * amdgpu_fence_activity - check for fence activity
 176  *
 177  * @ring: pointer to struct amdgpu_ring
 178  *
 179  * Checks the current fence value and calculates the last
 180  * signalled fence value. Returns true if activity occured
 181  * on the ring, and the fence_queue should be waken up.
 182  */
 183 static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
 184 {
 185         uint64_t seq, last_seq, last_emitted;
 186         unsigned count_loop = 0;
 187         bool wake = false;
 188
 189         /* Note there is a scenario here for an infinite loop but it's
 190          * very unlikely to happen. For it to happen, the current polling
 191          * process need to be interrupted by another process and another
 192          * process needs to update the last_seq btw the atomic read and
 193          * xchg of the current process.
 194          *
 195          * More over for this to go in infinite loop there need to be
 196          * continuously new fence signaled ie amdgpu_fence_read needs
 197          * to return a different value each time for both the currently
 198          * polling process and the other process that xchg the last_seq
 199          * btw atomic read and xchg of the current process. And the
 200          * value the other process set as last seq must be higher than
 201          * the seq value we just read. Which means that current process
 202          * need to be interrupted after amdgpu_fence_read and before
 203          * atomic xchg.
 204          *
 205          * To be even more safe we count the number of time we loop and
 206          * we bail after 10 loop just accepting the fact that we might
 207          * have temporarly set the last_seq not to the true real last
 208          * seq but to an older one.
 209          */
 210         last_seq = atomic64_read(&ring->fence_drv.last_seq);
 211         do {
 212                 last_emitted = ring->fence_drv.sync_seq[ring->idx];
 213                 seq = amdgpu_fence_read(ring);
 214                 seq |= last_seq & 0xffffffff00000000LL;
 215                 if (seq < last_seq) {
 216                         seq &= 0xffffffff;
 217                         seq |= last_emitted & 0xffffffff00000000LL;
 218                 }
 219
 220                 if (seq <= last_seq || seq > last_emitted) {
 221                         break;
 222                 }
 223                 /* If we loop over we don't want to return without
 224                  * checking if a fence is signaled as it means that the
 225                  * seq we just read is different from the previous on.
 226                  */
 227                 wake = true;
 228                 last_seq = seq;
 229                 if ((count_loop++) > 10) {
 230                         /* We looped over too many time leave with the
 231                          * fact that we might have set an older fence
 232                          * seq then the current real last seq as signaled
 233                          * by the hw.
 234                          */
 235                         break;
 236                 }
 237         } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
 238
 239         if (seq < last_emitted)
 240                 amdgpu_fence_schedule_check(ring);
 241
 242         return wake;
 243 }
 244
 245 /**
 246  * amdgpu_fence_check_lockup - check for hardware lockup
 247  *
 248  * @work: delayed work item
 249  *
 250  * Checks for fence activity and if there is none probe
 251  * the hardware if a lockup occured.
 252  */
 253 static void amdgpu_fence_check_lockup(struct work_struct *work)
 254 {
 255         struct amdgpu_fence_driver *fence_drv;
 256         struct amdgpu_ring *ring;
 257
 258         fence_drv = container_of(work, struct amdgpu_fence_driver,
 259                                 lockup_work.work);
 260         ring = fence_drv->ring;
 261
 262         if (!down_read_trylock(&ring->adev->exclusive_lock)) {
 263                 /* just reschedule the check if a reset is going on */
 264                 amdgpu_fence_schedule_check(ring);
 265                 return;
 266         }
 267
 268         if (amdgpu_fence_activity(ring))
 269                 wake_up_all(&ring->adev->fence_queue);
 270         else if (amdgpu_ring_is_lockup(ring)) {
 271                 /* good news we believe it's a lockup */
 272                 dev_warn(ring->adev->dev, "GPU lockup (current fence id "
 273                         "0x%016llx last fence id 0x%016llx on ring %d)\n",
 274                         (uint64_t)atomic64_read(&fence_drv->last_seq),
 275                         fence_drv->sync_seq[ring->idx], ring->idx);
 276
 277                 /* remember that we need an reset */
 278                 ring->adev->needs_reset = true;
 279                 wake_up_all(&ring->adev->fence_queue);
 280         }
 281         up_read(&ring->adev->exclusive_lock);
 282 }
 283
 284 /**
 285  * amdgpu_fence_process - process a fence
 286  *
 287  * @adev: amdgpu_device pointer
 288  * @ring: ring index the fence is associated with
 289  *
 290  * Checks the current fence value and wakes the fence queue
 291  * if the sequence number has increased (all asics).
 292  */
 293 void amdgpu_fence_process(struct amdgpu_ring *ring)
 294 {
 295         uint64_t seq, last_seq, last_emitted;
 296         unsigned count_loop = 0;
 297         bool wake = false;
 298         unsigned long irqflags;
 299
 300         /* Note there is a scenario here for an infinite loop but it's
 301          * very unlikely to happen. For it to happen, the current polling
 302          * process need to be interrupted by another process and another
 303          * process needs to update the last_seq btw the atomic read and
 304          * xchg of the current process.
 305          *
 306          * More over for this to go in infinite loop there need to be
 307          * continuously new fence signaled ie amdgpu_fence_read needs
 308          * to return a different value each time for both the currently
 309          * polling process and the other process that xchg the last_seq
 310          * btw atomic read and xchg of the current process. And the
 311          * value the other process set as last seq must be higher than
 312          * the seq value we just read. Which means that current process
 313          * need to be interrupted after amdgpu_fence_read and before
 314          * atomic xchg.
 315          *
 316          * To be even more safe we count the number of time we loop and
 317          * we bail after 10 loop just accepting the fact that we might
 318          * have temporarly set the last_seq not to the true real last
 319          * seq but to an older one.
 320          */
 321         spin_lock_irqsave(&ring->fence_lock, irqflags);
 322         last_seq = atomic64_read(&ring->fence_drv.last_seq);
 323         do {
 324                 last_emitted = ring->fence_drv.sync_seq[ring->idx];
 325                 seq = amdgpu_fence_read(ring);
 326                 seq |= last_seq & 0xffffffff00000000LL;
 327                 if (seq < last_seq) {
 328                         seq &= 0xffffffff;
 329                         seq |= last_emitted & 0xffffffff00000000LL;
 330                 }
 331
 332                 if (seq <= last_seq || seq > last_emitted) {
 333                         break;
 334                 }
 335                 /* If we loop over we don't want to return without
 336                  * checking if a fence is signaled as it means that the
 337                  * seq we just read is different from the previous on.
 338                  */
 339                 wake = true;
 340                 last_seq = seq;
 341                 if ((count_loop++) > 10) {
 342                         /* We looped over too many time leave with the
 343                          * fact that we might have set an older fence
 344                          * seq then the current real last seq as signaled
 345                          * by the hw.
 346                          */
 347                         break;
 348                 }
 349         } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
 350
 351         if (wake) {
 352                 if (amdgpu_enable_scheduler) {
 353                         uint64_t handled_seq =
 354                                 amd_sched_get_handled_seq(ring->scheduler);
 355                         uint64_t latest_seq =
 356                                 atomic64_read(&ring->fence_drv.last_seq);
 357                         if (handled_seq == latest_seq) {
 358                                 DRM_ERROR("ring %d, EOP without seq update (lastest_seq=%llu)\n",
 359                                           ring->idx, latest_seq);
 360                                 goto exit;
 361                         }
 362                         do {
 363                                 amd_sched_isr(ring->scheduler);
 364                         } while (amd_sched_get_handled_seq(ring->scheduler) < latest_seq);
 365                 }
 366
 367                 wake_up_all(&ring->adev->fence_queue);
 368         }
 369 exit:
 370         spin_unlock_irqrestore(&ring->fence_lock, irqflags);
 371 }
 372
 373 /**
 374  * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
 375  *
 376  * @ring: ring the fence is associated with
 377  * @seq: sequence number
 378  *
 379  * Check if the last signaled fence sequnce number is >= the requested
 380  * sequence number (all asics).
 381  * Returns true if the fence has signaled (current fence value
 382  * is >= requested value) or false if it has not (current fence
 383  * value is < the requested value.  Helper function for
 384  * amdgpu_fence_signaled().
 385  */
 386 static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
 387 {
 388         if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
 389                 return true;
 390
 391         /* poll new last sequence at least once */
 392         amdgpu_fence_process(ring);
 393         if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
 394                 return true;
 395
 396         return false;
 397 }
 398
 399 static bool amdgpu_fence_is_signaled(struct fence *f)
 400 {
 401         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 402         struct amdgpu_ring *ring = fence->ring;
 403         struct amdgpu_device *adev = ring->adev;
 404
 405         if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
 406                 return true;
 407
 408         if (down_read_trylock(&adev->exclusive_lock)) {
 409                 amdgpu_fence_process(ring);
 410                 up_read(&adev->exclusive_lock);
 411
 412                 if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
 413                         return true;
 414         }
 415         return false;
 416 }
 417
 418 /**
 419  * amdgpu_fence_enable_signaling - enable signalling on fence
 420  * @fence: fence
 421  *
 422  * This function is called with fence_queue lock held, and adds a callback
 423  * to fence_queue that checks if this fence is signaled, and if so it
 424  * signals the fence and removes itself.
 425  */
 426 static bool amdgpu_fence_enable_signaling(struct fence *f)
 427 {
 428         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 429         struct amdgpu_ring *ring = fence->ring;
 430         struct amdgpu_device *adev = ring->adev;
 431
 432         if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
 433                 return false;
 434
 435         fence->fence_wake.flags = 0;
 436         fence->fence_wake.private = NULL;
 437         fence->fence_wake.func = amdgpu_fence_check_signaled;
 438         __add_wait_queue(&adev->fence_queue, &fence->fence_wake);
 439         fence_get(f);
 440         FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 441         return true;
 442 }
 443
 444 /**
 445  * amdgpu_fence_signaled - check if a fence has signaled
 446  *
 447  * @fence: amdgpu fence object
 448  *
 449  * Check if the requested fence has signaled (all asics).
 450  * Returns true if the fence has signaled or false if it has not.
 451  */
 452 bool amdgpu_fence_signaled(struct amdgpu_fence *fence)
 453 {
 454         if (!fence)
 455                 return true;
 456
 457         if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) {
 458                 if (!fence_signal(&fence->base))
 459                         FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n");
 460                 return true;
 461         }
 462
 463         return false;
 464 }
 465
 466 /**
 467  * amdgpu_fence_any_seq_signaled - check if any sequence number is signaled
 468  *
 469  * @adev: amdgpu device pointer
 470  * @seq: sequence numbers
 471  *
 472  * Check if the last signaled fence sequnce number is >= the requested
 473  * sequence number (all asics).
 474  * Returns true if any has signaled (current value is >= requested value)
 475  * or false if it has not. Helper function for amdgpu_fence_wait_seq.
 476  */
 477 static bool amdgpu_fence_any_seq_signaled(struct amdgpu_device *adev, u64 *seq)
 478 {
 479         unsigned i;
 480
 481         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 482                 if (!adev->rings[i] || !seq[i])
 483                         continue;
 484
 485                 if (amdgpu_fence_seq_signaled(adev->rings[i], seq[i]))
 486                         return true;
 487         }
 488
 489         return false;
 490 }
 491
 492 /**
 493  * amdgpu_fence_wait_seq_timeout - wait for a specific sequence numbers
 494  *
 495  * @adev: amdgpu device pointer
 496  * @target_seq: sequence number(s) we want to wait for
 497  * @intr: use interruptable sleep
 498  * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
 499  *
 500  * Wait for the requested sequence number(s) to be written by any ring
 501  * (all asics).  Sequnce number array is indexed by ring id.
 502  * @intr selects whether to use interruptable (true) or non-interruptable
 503  * (false) sleep when waiting for the sequence number.  Helper function
 504  * for amdgpu_fence_wait_*().
 505  * Returns remaining time if the sequence number has passed, 0 when
 506  * the wait timeout, or an error for all other cases.
 507  * -EDEADLK is returned when a GPU lockup has been detected.
 508  */
 509 static long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev,
 510                                           u64 *target_seq, bool intr,
 511                                           long timeout)
 512 {
 513         uint64_t last_seq[AMDGPU_MAX_RINGS];
 514         bool signaled;
 515         int i;
 516         long r;
 517
 518         if (timeout == 0) {
 519                 return amdgpu_fence_any_seq_signaled(adev, target_seq);
 520         }
 521
 522         while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) {
 523
 524                 /* Save current sequence values, used to check for GPU lockups */
 525                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 526                         struct amdgpu_ring *ring = adev->rings[i];
 527
 528                         if (!ring || !target_seq[i])
 529                                 continue;
 530
 531                         last_seq[i] = atomic64_read(&ring->fence_drv.last_seq);
 532                         trace_amdgpu_fence_wait_begin(adev->ddev, i, target_seq[i]);
 533                 }
 534
 535                 if (intr) {
 536                         r = wait_event_interruptible_timeout(adev->fence_queue, (
 537                                 (signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
 538                                  || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
 539                 } else {
 540                         r = wait_event_timeout(adev->fence_queue, (
 541                                 (signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
 542                                  || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
 543                 }
 544
 545                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 546                         struct amdgpu_ring *ring = adev->rings[i];
 547
 548                         if (!ring || !target_seq[i])
 549                                 continue;
 550
 551                         trace_amdgpu_fence_wait_end(adev->ddev, i, target_seq[i]);
 552                 }
 553
 554                 if (unlikely(r < 0))
 555                         return r;
 556
 557                 if (unlikely(!signaled)) {
 558
 559                         if (adev->needs_reset)
 560                                 return -EDEADLK;
 561
 562                         /* we were interrupted for some reason and fence
 563                          * isn't signaled yet, resume waiting */
 564                         if (r)
 565                                 continue;
 566
 567                         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 568                                 struct amdgpu_ring *ring = adev->rings[i];
 569
 570                                 if (!ring || !target_seq[i])
 571                                         continue;
 572
 573                                 if (last_seq[i] != atomic64_read(&ring->fence_drv.last_seq))
 574                                         break;
 575                         }
 576
 577                         if (i != AMDGPU_MAX_RINGS)
 578                                 continue;
 579
 580                         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 581                                 if (!adev->rings[i] || !target_seq[i])
 582                                         continue;
 583
 584                                 if (amdgpu_ring_is_lockup(adev->rings[i]))
 585                                         break;
 586                         }
 587
 588                         if (i < AMDGPU_MAX_RINGS) {
 589                                 /* good news we believe it's a lockup */
 590                                 dev_warn(adev->dev, "GPU lockup (waiting for "
 591                                          "0x%016llx last fence id 0x%016llx on"
 592                                          " ring %d)\n",
 593                                          target_seq[i], last_seq[i], i);
 594
 595                                 /* remember that we need an reset */
 596                                 adev->needs_reset = true;
 597                                 wake_up_all(&adev->fence_queue);
 598                                 return -EDEADLK;
 599                         }
 600
 601                         if (timeout < MAX_SCHEDULE_TIMEOUT) {
 602                                 timeout -= AMDGPU_FENCE_JIFFIES_TIMEOUT;
 603                                 if (timeout <= 0) {
 604                                         return 0;
 605                                 }
 606                         }
 607                 }
 608         }
 609         return timeout;
 610 }
 611
 612 /**
 613  * amdgpu_fence_wait - wait for a fence to signal
 614  *
 615  * @fence: amdgpu fence object
 616  * @intr: use interruptable sleep
 617  *
 618  * Wait for the requested fence to signal (all asics).
 619  * @intr selects whether to use interruptable (true) or non-interruptable
 620  * (false) sleep when waiting for the fence.
 621  * Returns 0 if the fence has passed, error for all other cases.
 622  */
 623 int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr)
 624 {
 625         uint64_t seq[AMDGPU_MAX_RINGS] = {};
 626         long r;
 627
 628         seq[fence->ring->idx] = fence->seq;
 629         r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
 630         if (r < 0) {
 631                 return r;
 632         }
 633
 634         r = fence_signal(&fence->base);
 635         if (!r)
 636                 FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
 637         return 0;
 638 }
 639
 640 /**
 641  * amdgpu_fence_wait_any - wait for a fence to signal on any ring
 642  *
 643  * @adev: amdgpu device pointer
 644  * @fences: amdgpu fence object(s)
 645  * @intr: use interruptable sleep
 646  *
 647  * Wait for any requested fence to signal (all asics).  Fence
 648  * array is indexed by ring id.  @intr selects whether to use
 649  * interruptable (true) or non-interruptable (false) sleep when
 650  * waiting for the fences. Used by the suballocator.
 651  * Returns 0 if any fence has passed, error for all other cases.
 652  */
 653 int amdgpu_fence_wait_any(struct amdgpu_device *adev,
 654                           struct amdgpu_fence **fences,
 655                           bool intr)
 656 {
 657         uint64_t seq[AMDGPU_MAX_RINGS];
 658         unsigned i, num_rings = 0;
 659         long r;
 660
 661         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 662                 seq[i] = 0;
 663
 664                 if (!fences[i]) {
 665                         continue;
 666                 }
 667
 668                 seq[i] = fences[i]->seq;
 669                 ++num_rings;
 670         }
 671
 672         /* nothing to wait for ? */
 673         if (num_rings == 0)
 674                 return -ENOENT;
 675
 676         r = amdgpu_fence_wait_seq_timeout(adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
 677         if (r < 0) {
 678                 return r;
 679         }
 680         return 0;
 681 }
 682
 683 /**
 684  * amdgpu_fence_wait_next - wait for the next fence to signal
 685  *
 686  * @adev: amdgpu device pointer
 687  * @ring: ring index the fence is associated with
 688  *
 689  * Wait for the next fence on the requested ring to signal (all asics).
 690  * Returns 0 if the next fence has passed, error for all other cases.
 691  * Caller must hold ring lock.
 692  */
 693 int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
 694 {
 695         uint64_t seq[AMDGPU_MAX_RINGS] = {};
 696         long r;
 697
 698         seq[ring->idx] = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
 699         if (seq[ring->idx] >= ring->fence_drv.sync_seq[ring->idx]) {
 700                 /* nothing to wait for, last_seq is
 701                    already the last emited fence */
 702                 return -ENOENT;
 703         }
 704         r = amdgpu_fence_wait_seq_timeout(ring->adev, seq, false, MAX_SCHEDULE_TIMEOUT);
 705         if (r < 0)
 706                 return r;
 707         return 0;
 708 }
 709
 710 /**
 711  * amdgpu_fence_wait_empty - wait for all fences to signal
 712  *
 713  * @adev: amdgpu device pointer
 714  * @ring: ring index the fence is associated with
 715  *
 716  * Wait for all fences on the requested ring to signal (all asics).
 717  * Returns 0 if the fences have passed, error for all other cases.
 718  * Caller must hold ring lock.
 719  */
 720 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 721 {
 722         struct amdgpu_device *adev = ring->adev;
 723         uint64_t seq[AMDGPU_MAX_RINGS] = {};
 724         long r;
 725
 726         seq[ring->idx] = ring->fence_drv.sync_seq[ring->idx];
 727         if (!seq[ring->idx])
 728                 return 0;
 729
 730         r = amdgpu_fence_wait_seq_timeout(adev, seq, false, MAX_SCHEDULE_TIMEOUT);
 731         if (r < 0) {
 732                 if (r == -EDEADLK)
 733                         return -EDEADLK;
 734
 735                 dev_err(adev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
 736                         ring->idx, r);
 737         }
 738         return 0;
 739 }
 740
 741 /**
 742  * amdgpu_fence_ref - take a ref on a fence
 743  *
 744  * @fence: amdgpu fence object
 745  *
 746  * Take a reference on a fence (all asics).
 747  * Returns the fence.
 748  */
 749 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence)
 750 {
 751         fence_get(&fence->base);
 752         return fence;
 753 }
 754
 755 /**
 756  * amdgpu_fence_unref - remove a ref on a fence
 757  *
 758  * @fence: amdgpu fence object
 759  *
 760  * Remove a reference on a fence (all asics).
 761  */
 762 void amdgpu_fence_unref(struct amdgpu_fence **fence)
 763 {
 764         struct amdgpu_fence *tmp = *fence;
 765
 766         *fence = NULL;
 767         if (tmp)
 768                 fence_put(&tmp->base);
 769 }
 770
 771 /**
 772  * amdgpu_fence_count_emitted - get the count of emitted fences
 773  *
 774  * @ring: ring the fence is associated with
 775  *
 776  * Get the number of fences emitted on the requested ring (all asics).
 777  * Returns the number of emitted fences on the ring.  Used by the
 778  * dynpm code to ring track activity.
 779  */
 780 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 781 {
 782         uint64_t emitted;
 783
 784         /* We are not protected by ring lock when reading the last sequence
 785          * but it's ok to report slightly wrong fence count here.
 786          */
 787         amdgpu_fence_process(ring);
 788         emitted = ring->fence_drv.sync_seq[ring->idx]
 789                 - atomic64_read(&ring->fence_drv.last_seq);
 790         /* to avoid 32bits warp around */
 791         if (emitted > 0x10000000)
 792                 emitted = 0x10000000;
 793
 794         return (unsigned)emitted;
 795 }
 796
 797 /**
 798  * amdgpu_fence_need_sync - do we need a semaphore
 799  *
 800  * @fence: amdgpu fence object
 801  * @dst_ring: which ring to check against
 802  *
 803  * Check if the fence needs to be synced against another ring
 804  * (all asics).  If so, we need to emit a semaphore.
 805  * Returns true if we need to sync with another ring, false if
 806  * not.
 807  */
 808 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
 809                             struct amdgpu_ring *dst_ring)
 810 {
 811         struct amdgpu_fence_driver *fdrv;
 812
 813         if (!fence)
 814                 return false;
 815
 816         if (fence->ring == dst_ring)
 817                 return false;
 818
 819         /* we are protected by the ring mutex */
 820         fdrv = &dst_ring->fence_drv;
 821         if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
 822                 return false;
 823
 824         return true;
 825 }
 826
 827 /**
 828  * amdgpu_fence_note_sync - record the sync point
 829  *
 830  * @fence: amdgpu fence object
 831  * @dst_ring: which ring to check against
 832  *
 833  * Note the sequence number at which point the fence will
 834  * be synced with the requested ring (all asics).
 835  */
 836 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
 837                             struct amdgpu_ring *dst_ring)
 838 {
 839         struct amdgpu_fence_driver *dst, *src;
 840         unsigned i;
 841
 842         if (!fence)
 843                 return;
 844
 845         if (fence->ring == dst_ring)
 846                 return;
 847
 848         /* we are protected by the ring mutex */
 849         src = &fence->ring->fence_drv;
 850         dst = &dst_ring->fence_drv;
 851         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 852                 if (i == dst_ring->idx)
 853                         continue;
 854
 855                 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
 856         }
 857 }
 858
 859 /**
 860  * amdgpu_fence_driver_start_ring - make the fence driver
 861  * ready for use on the requested ring.
 862  *
 863  * @ring: ring to start the fence driver on
 864  * @irq_src: interrupt source to use for this ring
 865  * @irq_type: interrupt type to use for this ring
 866  *
 867  * Make the fence driver ready for processing (all asics).
 868  * Not all asics have all rings, so each asic will only
 869  * start the fence driver on the rings it has.
 870  * Returns 0 for success, errors for failure.
 871  */
 872 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 873                                    struct amdgpu_irq_src *irq_src,
 874                                    unsigned irq_type)
 875 {
 876         struct amdgpu_device *adev = ring->adev;
 877         uint64_t index;
 878
 879         if (ring != &adev->uvd.ring) {
 880                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 881                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 882         } else {
 883                 /* put fence directly behind firmware */
 884                 index = ALIGN(adev->uvd.fw->size, 8);
 885                 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
 886                 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
 887         }
 888         amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
 889         amdgpu_irq_get(adev, irq_src, irq_type);
 890
 891         ring->fence_drv.irq_src = irq_src;
 892         ring->fence_drv.irq_type = irq_type;
 893         ring->fence_drv.initialized = true;
 894
 895         dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 896                  "cpu addr 0x%p\n", ring->idx,
 897                  ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 898         return 0;
 899 }
 900
 901 /**
 902  * amdgpu_fence_driver_init_ring - init the fence driver
 903  * for the requested ring.
 904  *
 905  * @ring: ring to init the fence driver on
 906  *
 907  * Init the fence driver for the requested ring (all asics).
 908  * Helper function for amdgpu_fence_driver_init().
 909  */
 910 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
 911 {
 912         int i;
 913
 914         ring->fence_drv.cpu_addr = NULL;
 915         ring->fence_drv.gpu_addr = 0;
 916         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
 917                 ring->fence_drv.sync_seq[i] = 0;
 918
 919         atomic64_set(&ring->fence_drv.last_seq, 0);
 920         ring->fence_drv.initialized = false;
 921
 922         INIT_DELAYED_WORK(&ring->fence_drv.lockup_work,
 923                         amdgpu_fence_check_lockup);
 924         ring->fence_drv.ring = ring;
 925
 926         if (amdgpu_enable_scheduler) {
 927                 ring->scheduler = amd_sched_create((void *)ring->adev,
 928                                                    &amdgpu_sched_ops,
 929                                                    ring->idx, 5, 0,
 930                                                    amdgpu_sched_hw_submission);
 931                 if (!ring->scheduler)
 932                         DRM_ERROR("Failed to create scheduler on ring %d.\n",
 933                                   ring->idx);
 934         }
 935 }
 936
 937 /**
 938  * amdgpu_fence_driver_init - init the fence driver
 939  * for all possible rings.
 940  *
 941  * @adev: amdgpu device pointer
 942  *
 943  * Init the fence driver for all possible rings (all asics).
 944  * Not all asics have all rings, so each asic will only
 945  * start the fence driver on the rings it has using
 946  * amdgpu_fence_driver_start_ring().
 947  * Returns 0 for success.
 948  */
 949 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 950 {
 951         init_waitqueue_head(&adev->fence_queue);
 952         if (amdgpu_debugfs_fence_init(adev))
 953                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 954
 955         return 0;
 956 }
 957
 958 /**
 959  * amdgpu_fence_driver_fini - tear down the fence driver
 960  * for all possible rings.
 961  *
 962  * @adev: amdgpu device pointer
 963  *
 964  * Tear down the fence driver for all possible rings (all asics).
 965  */
 966 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 967 {
 968         int i, r;
 969
 970         mutex_lock(&adev->ring_lock);
 971         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 972                 struct amdgpu_ring *ring = adev->rings[i];
 973                 if (!ring || !ring->fence_drv.initialized)
 974                         continue;
 975                 r = amdgpu_fence_wait_empty(ring);
 976                 if (r) {
 977                         /* no need to trigger GPU reset as we are unloading */
 978                         amdgpu_fence_driver_force_completion(adev);
 979                 }
 980                 wake_up_all(&adev->fence_queue);
 981                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 982                                ring->fence_drv.irq_type);
 983                 if (ring->scheduler)
 984                         amd_sched_destroy(ring->scheduler);
 985                 ring->fence_drv.initialized = false;
 986         }
 987         mutex_unlock(&adev->ring_lock);
 988 }
 989
 990 /**
 991  * amdgpu_fence_driver_suspend - suspend the fence driver
 992  * for all possible rings.
 993  *
 994  * @adev: amdgpu device pointer
 995  *
 996  * Suspend the fence driver for all possible rings (all asics).
 997  */
 998 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 999 {
1000         int i, r;
1001
1002         mutex_lock(&adev->ring_lock);
1003         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1004                 struct amdgpu_ring *ring = adev->rings[i];
1005                 if (!ring || !ring->fence_drv.initialized)
1006                         continue;
1007
1008                 /* wait for gpu to finish processing current batch */
1009                 r = amdgpu_fence_wait_empty(ring);
1010                 if (r) {
1011                         /* delay GPU reset to resume */
1012                         amdgpu_fence_driver_force_completion(adev);
1013                 }
1014
1015                 /* disable the interrupt */
1016                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
1017                                ring->fence_drv.irq_type);
1018         }
1019         mutex_unlock(&adev->ring_lock);
1020 }
1021
1022 /**
1023  * amdgpu_fence_driver_resume - resume the fence driver
1024  * for all possible rings.
1025  *
1026  * @adev: amdgpu device pointer
1027  *
1028  * Resume the fence driver for all possible rings (all asics).
1029  * Not all asics have all rings, so each asic will only
1030  * start the fence driver on the rings it has using
1031  * amdgpu_fence_driver_start_ring().
1032  * Returns 0 for success.
1033  */
1034 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
1035 {
1036         int i;
1037
1038         mutex_lock(&adev->ring_lock);
1039         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1040                 struct amdgpu_ring *ring = adev->rings[i];
1041                 if (!ring || !ring->fence_drv.initialized)
1042                         continue;
1043
1044                 /* enable the interrupt */
1045                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
1046                                ring->fence_drv.irq_type);
1047         }
1048         mutex_unlock(&adev->ring_lock);
1049 }
1050
1051 /**
1052  * amdgpu_fence_driver_force_completion - force all fence waiter to complete
1053  *
1054  * @adev: amdgpu device pointer
1055  *
1056  * In case of GPU reset failure make sure no process keep waiting on fence
1057  * that will never complete.
1058  */
1059 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
1060 {
1061         int i;
1062
1063         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1064                 struct amdgpu_ring *ring = adev->rings[i];
1065                 if (!ring || !ring->fence_drv.initialized)
1066                         continue;
1067
1068                 amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
1069         }
1070 }
1071
1072
1073 /*
1074  * Fence debugfs
1075  */
1076 #if defined(CONFIG_DEBUG_FS)
1077 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
1078 {
1079         struct drm_info_node *node = (struct drm_info_node *)m->private;
1080         struct drm_device *dev = node->minor->dev;
1081         struct amdgpu_device *adev = dev->dev_private;
1082         int i, j;
1083
1084         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1085                 struct amdgpu_ring *ring = adev->rings[i];
1086                 if (!ring || !ring->fence_drv.initialized)
1087                         continue;
1088
1089                 amdgpu_fence_process(ring);
1090
1091                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
1092                 seq_printf(m, "Last signaled fence 0x%016llx\n",
1093                            (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
1094                 seq_printf(m, "Last emitted        0x%016llx\n",
1095                            ring->fence_drv.sync_seq[i]);
1096
1097                 for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
1098                         struct amdgpu_ring *other = adev->rings[j];
1099                         if (i != j && other && other->fence_drv.initialized &&
1100                             ring->fence_drv.sync_seq[j])
1101                                 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
1102                                            j, ring->fence_drv.sync_seq[j]);
1103                 }
1104         }
1105         return 0;
1106 }
1107
1108 static struct drm_info_list amdgpu_debugfs_fence_list[] = {
1109         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
1110 };
1111 #endif
1112
1113 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
1114 {
1115 #if defined(CONFIG_DEBUG_FS)
1116         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1);
1117 #else
1118         return 0;
1119 #endif
1120 }
1121
1122 static const char *amdgpu_fence_get_driver_name(struct fence *fence)
1123 {
1124         return "amdgpu";
1125 }
1126
1127 static const char *amdgpu_fence_get_timeline_name(struct fence *f)
1128 {
1129         struct amdgpu_fence *fence = to_amdgpu_fence(f);
1130         return (const char *)fence->ring->name;
1131 }
1132
1133 static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence)
1134 {
1135         return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
1136 }
1137
1138 struct amdgpu_wait_cb {
1139         struct fence_cb base;
1140         struct task_struct *task;
1141 };
1142
1143 static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
1144 {
1145         struct amdgpu_wait_cb *wait =
1146                 container_of(cb, struct amdgpu_wait_cb, base);
1147         wake_up_process(wait->task);
1148 }
1149
1150 static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
1151                                              signed long t)
1152 {
1153         struct amdgpu_fence *fence = to_amdgpu_fence(f);
1154         struct amdgpu_device *adev = fence->ring->adev;
1155         struct amdgpu_wait_cb cb;
1156
1157         cb.task = current;
1158
1159         if (fence_add_callback(f, &cb.base, amdgpu_fence_wait_cb))
1160                 return t;
1161
1162         while (t > 0) {
1163                 if (intr)
1164                         set_current_state(TASK_INTERRUPTIBLE);
1165                 else
1166                         set_current_state(TASK_UNINTERRUPTIBLE);
1167
1168                 /*
1169                  * amdgpu_test_signaled must be called after
1170                  * set_current_state to prevent a race with wake_up_process
1171                  */
1172                 if (amdgpu_test_signaled(fence))
1173                         break;
1174
1175                 if (adev->needs_reset) {
1176                         t = -EDEADLK;
1177                         break;
1178                 }
1179
1180                 t = schedule_timeout(t);
1181
1182                 if (t > 0 && intr && signal_pending(current))
1183                         t = -ERESTARTSYS;
1184         }
1185
1186         __set_current_state(TASK_RUNNING);
1187         fence_remove_callback(f, &cb.base);
1188
1189         return t;
1190 }
1191
1192 const struct fence_ops amdgpu_fence_ops = {
1193         .get_driver_name = amdgpu_fence_get_driver_name,
1194         .get_timeline_name = amdgpu_fence_get_timeline_name,
1195         .enable_signaling = amdgpu_fence_enable_signaling,
1196         .signaled = amdgpu_fence_is_signaled,
1197         .wait = amdgpu_fence_default_wait,
1198         .release = NULL,
1199 };