drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <ttm/ttm_memory.h>
  38 #include <drm/drmP.h>
  39 #include <drm/amdgpu_drm.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/slab.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include <linux/debugfs.h>
  46 #include "amdgpu.h"
  47 #include "bif/bif_4_1_d.h"
  48
  49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  50
  51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  53
  54 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  55 {
  56         struct amdgpu_mman *mman;
  57         struct amdgpu_device *adev;
  58
  59         mman = container_of(bdev, struct amdgpu_mman, bdev);
  60         adev = container_of(mman, struct amdgpu_device, mman);
  61         return adev;
  62 }
  63
  64
  65 /*
  66  * Global memory.
  67  */
  68 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  69 {
  70         return ttm_mem_global_init(ref->object);
  71 }
  72
  73 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  74 {
  75         ttm_mem_global_release(ref->object);
  76 }
  77
  78 int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  79 {
  80         struct drm_global_reference *global_ref;
  81         struct amdgpu_ring *ring;
  82         struct amd_sched_rq *rq;
  83         int r;
  84
  85         adev->mman.mem_global_referenced = false;
  86         global_ref = &adev->mman.mem_global_ref;
  87         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  88         global_ref->size = sizeof(struct ttm_mem_global);
  89         global_ref->init = &amdgpu_ttm_mem_global_init;
  90         global_ref->release = &amdgpu_ttm_mem_global_release;
  91         r = drm_global_item_ref(global_ref);
  92         if (r != 0) {
  93                 DRM_ERROR("Failed setting up TTM memory accounting "
  94                           "subsystem.\n");
  95                 return r;
  96         }
  97
  98         adev->mman.bo_global_ref.mem_glob =
  99                 adev->mman.mem_global_ref.object;
 100         global_ref = &adev->mman.bo_global_ref.ref;
 101         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 102         global_ref->size = sizeof(struct ttm_bo_global);
 103         global_ref->init = &ttm_bo_global_init;
 104         global_ref->release = &ttm_bo_global_release;
 105         r = drm_global_item_ref(global_ref);
 106         if (r != 0) {
 107                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 108                 drm_global_item_unref(&adev->mman.mem_global_ref);
 109                 return r;
 110         }
 111
 112         ring = adev->mman.buffer_funcs_ring;
 113         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 114         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 115                                   rq, amdgpu_sched_jobs);
 116         if (r != 0) {
 117                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 118                 drm_global_item_unref(&adev->mman.mem_global_ref);
 119                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 120                 return r;
 121         }
 122
 123         adev->mman.mem_global_referenced = true;
 124
 125         return 0;
 126 }
 127
 128 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 129 {
 130         if (adev->mman.mem_global_referenced) {
 131                 amd_sched_entity_fini(adev->mman.entity.sched,
 132                                       &adev->mman.entity);
 133                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 134                 drm_global_item_unref(&adev->mman.mem_global_ref);
 135                 adev->mman.mem_global_referenced = false;
 136         }
 137 }
 138
 139 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 140 {
 141         return 0;
 142 }
 143
 144 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 145                                 struct ttm_mem_type_manager *man)
 146 {
 147         struct amdgpu_device *adev;
 148
 149         adev = amdgpu_get_adev(bdev);
 150
 151         switch (type) {
 152         case TTM_PL_SYSTEM:
 153                 /* System memory */
 154                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 155                 man->available_caching = TTM_PL_MASK_CACHING;
 156                 man->default_caching = TTM_PL_FLAG_CACHED;
 157                 break;
 158         case TTM_PL_TT:
 159                 man->func = &ttm_bo_manager_func;
 160                 man->gpu_offset = adev->mc.gtt_start;
 161                 man->available_caching = TTM_PL_MASK_CACHING;
 162                 man->default_caching = TTM_PL_FLAG_CACHED;
 163                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 164                 break;
 165         case TTM_PL_VRAM:
 166                 /* "On-card" video ram */
 167                 man->func = &ttm_bo_manager_func;
 168                 man->gpu_offset = adev->mc.vram_start;
 169                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 170                              TTM_MEMTYPE_FLAG_MAPPABLE;
 171                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 172                 man->default_caching = TTM_PL_FLAG_WC;
 173                 break;
 174         case AMDGPU_PL_GDS:
 175         case AMDGPU_PL_GWS:
 176         case AMDGPU_PL_OA:
 177                 /* On-chip GDS memory*/
 178                 man->func = &ttm_bo_manager_func;
 179                 man->gpu_offset = 0;
 180                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 181                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 182                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 183                 break;
 184         default:
 185                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 186                 return -EINVAL;
 187         }
 188         return 0;
 189 }
 190
 191 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 192                                 struct ttm_placement *placement)
 193 {
 194         struct amdgpu_bo *rbo;
 195         static struct ttm_place placements = {
 196                 .fpfn = 0,
 197                 .lpfn = 0,
 198                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 199         };
 200
 201         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 202                 placement->placement = &placements;
 203                 placement->busy_placement = &placements;
 204                 placement->num_placement = 1;
 205                 placement->num_busy_placement = 1;
 206                 return;
 207         }
 208         rbo = container_of(bo, struct amdgpu_bo, tbo);
 209         switch (bo->mem.mem_type) {
 210         case TTM_PL_VRAM:
 211                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 212                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 213                 else
 214                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 215                 break;
 216         case TTM_PL_TT:
 217         default:
 218                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 219         }
 220         *placement = rbo->placement;
 221 }
 222
 223 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 224 {
 225         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 226
 227         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 228                 return -EPERM;
 229         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 230 }
 231
 232 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 233                              struct ttm_mem_reg *new_mem)
 234 {
 235         struct ttm_mem_reg *old_mem = &bo->mem;
 236
 237         BUG_ON(old_mem->mm_node != NULL);
 238         *old_mem = *new_mem;
 239         new_mem->mm_node = NULL;
 240 }
 241
 242 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 243                         bool evict, bool no_wait_gpu,
 244                         struct ttm_mem_reg *new_mem,
 245                         struct ttm_mem_reg *old_mem)
 246 {
 247         struct amdgpu_device *adev;
 248         struct amdgpu_ring *ring;
 249         uint64_t old_start, new_start;
 250         struct fence *fence;
 251         int r;
 252
 253         adev = amdgpu_get_adev(bo->bdev);
 254         ring = adev->mman.buffer_funcs_ring;
 255         old_start = old_mem->start << PAGE_SHIFT;
 256         new_start = new_mem->start << PAGE_SHIFT;
 257
 258         switch (old_mem->mem_type) {
 259         case TTM_PL_TT:
 260                 r = amdgpu_ttm_bind(bo->ttm, old_mem);
 261                 if (r)
 262                         return r;
 263
 264         case TTM_PL_VRAM:
 265                 old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
 266                 break;
 267         default:
 268                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 269                 return -EINVAL;
 270         }
 271         switch (new_mem->mem_type) {
 272         case TTM_PL_TT:
 273                 r = amdgpu_ttm_bind(bo->ttm, new_mem);
 274                 if (r)
 275                         return r;
 276
 277         case TTM_PL_VRAM:
 278                 new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
 279                 break;
 280         default:
 281                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 282                 return -EINVAL;
 283         }
 284         if (!ring->ready) {
 285                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 286                 return -EINVAL;
 287         }
 288
 289         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 290
 291         r = amdgpu_copy_buffer(ring, old_start, new_start,
 292                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 293                                bo->resv, &fence, false);
 294         if (r)
 295                 return r;
 296
 297         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 298         fence_put(fence);
 299         return r;
 300 }
 301
 302 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 303                                 bool evict, bool interruptible,
 304                                 bool no_wait_gpu,
 305                                 struct ttm_mem_reg *new_mem)
 306 {
 307         struct amdgpu_device *adev;
 308         struct ttm_mem_reg *old_mem = &bo->mem;
 309         struct ttm_mem_reg tmp_mem;
 310         struct ttm_place placements;
 311         struct ttm_placement placement;
 312         int r;
 313
 314         adev = amdgpu_get_adev(bo->bdev);
 315         tmp_mem = *new_mem;
 316         tmp_mem.mm_node = NULL;
 317         placement.num_placement = 1;
 318         placement.placement = &placements;
 319         placement.num_busy_placement = 1;
 320         placement.busy_placement = &placements;
 321         placements.fpfn = 0;
 322         placements.lpfn = 0;
 323         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 324         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 325                              interruptible, no_wait_gpu);
 326         if (unlikely(r)) {
 327                 return r;
 328         }
 329
 330         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 331         if (unlikely(r)) {
 332                 goto out_cleanup;
 333         }
 334
 335         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 336         if (unlikely(r)) {
 337                 goto out_cleanup;
 338         }
 339         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 340         if (unlikely(r)) {
 341                 goto out_cleanup;
 342         }
 343         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 344 out_cleanup:
 345         ttm_bo_mem_put(bo, &tmp_mem);
 346         return r;
 347 }
 348
 349 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 350                                 bool evict, bool interruptible,
 351                                 bool no_wait_gpu,
 352                                 struct ttm_mem_reg *new_mem)
 353 {
 354         struct amdgpu_device *adev;
 355         struct ttm_mem_reg *old_mem = &bo->mem;
 356         struct ttm_mem_reg tmp_mem;
 357         struct ttm_placement placement;
 358         struct ttm_place placements;
 359         int r;
 360
 361         adev = amdgpu_get_adev(bo->bdev);
 362         tmp_mem = *new_mem;
 363         tmp_mem.mm_node = NULL;
 364         placement.num_placement = 1;
 365         placement.placement = &placements;
 366         placement.num_busy_placement = 1;
 367         placement.busy_placement = &placements;
 368         placements.fpfn = 0;
 369         placements.lpfn = 0;
 370         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 371         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 372                              interruptible, no_wait_gpu);
 373         if (unlikely(r)) {
 374                 return r;
 375         }
 376         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 377         if (unlikely(r)) {
 378                 goto out_cleanup;
 379         }
 380         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 381         if (unlikely(r)) {
 382                 goto out_cleanup;
 383         }
 384 out_cleanup:
 385         ttm_bo_mem_put(bo, &tmp_mem);
 386         return r;
 387 }
 388
 389 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 390                         bool evict, bool interruptible,
 391                         bool no_wait_gpu,
 392                         struct ttm_mem_reg *new_mem)
 393 {
 394         struct amdgpu_device *adev;
 395         struct amdgpu_bo *abo;
 396         struct ttm_mem_reg *old_mem = &bo->mem;
 397         int r;
 398
 399         /* Can't move a pinned BO */
 400         abo = container_of(bo, struct amdgpu_bo, tbo);
 401         if (WARN_ON_ONCE(abo->pin_count > 0))
 402                 return -EINVAL;
 403
 404         adev = amdgpu_get_adev(bo->bdev);
 405
 406         /* remember the eviction */
 407         if (evict)
 408                 atomic64_inc(&adev->num_evictions);
 409
 410         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 411                 amdgpu_move_null(bo, new_mem);
 412                 return 0;
 413         }
 414         if ((old_mem->mem_type == TTM_PL_TT &&
 415              new_mem->mem_type == TTM_PL_SYSTEM) ||
 416             (old_mem->mem_type == TTM_PL_SYSTEM &&
 417              new_mem->mem_type == TTM_PL_TT)) {
 418                 /* bind is enough */
 419                 amdgpu_move_null(bo, new_mem);
 420                 return 0;
 421         }
 422         if (adev->mman.buffer_funcs == NULL ||
 423             adev->mman.buffer_funcs_ring == NULL ||
 424             !adev->mman.buffer_funcs_ring->ready) {
 425                 /* use memcpy */
 426                 goto memcpy;
 427         }
 428
 429         if (old_mem->mem_type == TTM_PL_VRAM &&
 430             new_mem->mem_type == TTM_PL_SYSTEM) {
 431                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 432                                         no_wait_gpu, new_mem);
 433         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 434                    new_mem->mem_type == TTM_PL_VRAM) {
 435                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 436                                             no_wait_gpu, new_mem);
 437         } else {
 438                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 439         }
 440
 441         if (r) {
 442 memcpy:
 443                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 444                 if (r) {
 445                         return r;
 446                 }
 447         }
 448
 449         /* update statistics */
 450         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 451         return 0;
 452 }
 453
 454 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 455 {
 456         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 457         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 458
 459         mem->bus.addr = NULL;
 460         mem->bus.offset = 0;
 461         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 462         mem->bus.base = 0;
 463         mem->bus.is_iomem = false;
 464         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 465                 return -EINVAL;
 466         switch (mem->mem_type) {
 467         case TTM_PL_SYSTEM:
 468                 /* system memory */
 469                 return 0;
 470         case TTM_PL_TT:
 471                 break;
 472         case TTM_PL_VRAM:
 473                 mem->bus.offset = mem->start << PAGE_SHIFT;
 474                 /* check if it's visible */
 475                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 476                         return -EINVAL;
 477                 mem->bus.base = adev->mc.aper_base;
 478                 mem->bus.is_iomem = true;
 479 #ifdef __alpha__
 480                 /*
 481                  * Alpha: use bus.addr to hold the ioremap() return,
 482                  * so we can modify bus.base below.
 483                  */
 484                 if (mem->placement & TTM_PL_FLAG_WC)
 485                         mem->bus.addr =
 486                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 487                                            mem->bus.size);
 488                 else
 489                         mem->bus.addr =
 490                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 491                                                 mem->bus.size);
 492
 493                 /*
 494                  * Alpha: Use just the bus offset plus
 495                  * the hose/domain memory base for bus.base.
 496                  * It then can be used to build PTEs for VRAM
 497                  * access, as done in ttm_bo_vm_fault().
 498                  */
 499                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 500                         adev->ddev->hose->dense_mem_base;
 501 #endif
 502                 break;
 503         default:
 504                 return -EINVAL;
 505         }
 506         return 0;
 507 }
 508
 509 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 510 {
 511 }
 512
 513 /*
 514  * TTM backend functions.
 515  */
 516 struct amdgpu_ttm_gup_task_list {
 517         struct list_head        list;
 518         struct task_struct      *task;
 519 };
 520
 521 struct amdgpu_ttm_tt {
 522         struct ttm_dma_tt       ttm;
 523         struct amdgpu_device    *adev;
 524         u64                     offset;
 525         uint64_t                userptr;
 526         struct mm_struct        *usermm;
 527         uint32_t                userflags;
 528         spinlock_t              guptasklock;
 529         struct list_head        guptasks;
 530         atomic_t                mmu_invalidations;
 531         struct list_head        list;
 532 };
 533
 534 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 535 {
 536         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 537         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 538         unsigned pinned = 0;
 539         int r;
 540
 541         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 542                 /* check that we only use anonymous memory
 543                    to prevent problems with writeback */
 544                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 545                 struct vm_area_struct *vma;
 546
 547                 vma = find_vma(gtt->usermm, gtt->userptr);
 548                 if (!vma || vma->vm_file || vma->vm_end < end)
 549                         return -EPERM;
 550         }
 551
 552         do {
 553                 unsigned num_pages = ttm->num_pages - pinned;
 554                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 555                 struct page **p = pages + pinned;
 556                 struct amdgpu_ttm_gup_task_list guptask;
 557
 558                 guptask.task = current;
 559                 spin_lock(&gtt->guptasklock);
 560                 list_add(&guptask.list, &gtt->guptasks);
 561                 spin_unlock(&gtt->guptasklock);
 562
 563                 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
 564
 565                 spin_lock(&gtt->guptasklock);
 566                 list_del(&guptask.list);
 567                 spin_unlock(&gtt->guptasklock);
 568
 569                 if (r < 0)
 570                         goto release_pages;
 571
 572                 pinned += r;
 573
 574         } while (pinned < ttm->num_pages);
 575
 576         return 0;
 577
 578 release_pages:
 579         release_pages(pages, pinned, 0);
 580         return r;
 581 }
 582
 583 /* prepare the sg table with the user pages */
 584 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 585 {
 586         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 587         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 588         unsigned nents;
 589         int r;
 590
 591         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 592         enum dma_data_direction direction = write ?
 593                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 594
 595         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 596                                       ttm->num_pages << PAGE_SHIFT,
 597                                       GFP_KERNEL);
 598         if (r)
 599                 goto release_sg;
 600
 601         r = -ENOMEM;
 602         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 603         if (nents != ttm->sg->nents)
 604                 goto release_sg;
 605
 606         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 607                                          gtt->ttm.dma_address, ttm->num_pages);
 608
 609         return 0;
 610
 611 release_sg:
 612         kfree(ttm->sg);
 613         return r;
 614 }
 615
 616 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 617 {
 618         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 619         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 620         struct sg_page_iter sg_iter;
 621
 622         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 623         enum dma_data_direction direction = write ?
 624                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 625
 626         /* double check that we don't free the table twice */
 627         if (!ttm->sg->sgl)
 628                 return;
 629
 630         /* free the sg table and pages again */
 631         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 632
 633         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 634                 struct page *page = sg_page_iter_page(&sg_iter);
 635                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 636                         set_page_dirty(page);
 637
 638                 mark_page_accessed(page);
 639                 put_page(page);
 640         }
 641
 642         sg_free_table(ttm->sg);
 643 }
 644
 645 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 646                                    struct ttm_mem_reg *bo_mem)
 647 {
 648         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 649         int r;
 650
 651         if (gtt->userptr) {
 652                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 653                 if (r) {
 654                         DRM_ERROR("failed to pin userptr\n");
 655                         return r;
 656                 }
 657         }
 658         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 659         if (!ttm->num_pages) {
 660                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 661                      ttm->num_pages, bo_mem, ttm);
 662         }
 663
 664         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 665             bo_mem->mem_type == AMDGPU_PL_GWS ||
 666             bo_mem->mem_type == AMDGPU_PL_OA)
 667                 return -EINVAL;
 668
 669         return 0;
 670 }
 671
 672 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 673 {
 674         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 675
 676         return gtt && !list_empty(&gtt->list);
 677 }
 678
 679 int amdgpu_ttm_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
 680 {
 681         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 682         uint32_t flags;
 683         int r;
 684
 685         if (!ttm || amdgpu_ttm_is_bound(ttm))
 686                 return 0;
 687
 688         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 689         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 690                 ttm->pages, gtt->ttm.dma_address, flags);
 691
 692         if (r) {
 693                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 694                           ttm->num_pages, gtt->offset);
 695                 return r;
 696         }
 697         spin_lock(&gtt->adev->gtt_list_lock);
 698         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 699         spin_unlock(&gtt->adev->gtt_list_lock);
 700         return 0;
 701 }
 702
 703 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 704 {
 705         struct amdgpu_ttm_tt *gtt, *tmp;
 706         struct ttm_mem_reg bo_mem;
 707         uint32_t flags;
 708         int r;
 709
 710         bo_mem.mem_type = TTM_PL_TT;
 711         spin_lock(&adev->gtt_list_lock);
 712         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 713                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 714                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 715                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 716                                      flags);
 717                 if (r) {
 718                         spin_unlock(&adev->gtt_list_lock);
 719                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 720                                   gtt->ttm.ttm.num_pages, gtt->offset);
 721                         return r;
 722                 }
 723         }
 724         spin_unlock(&adev->gtt_list_lock);
 725         return 0;
 726 }
 727
 728 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 729 {
 730         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 731
 732         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 733         if (gtt->adev->gart.ready)
 734                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 735
 736         if (gtt->userptr)
 737                 amdgpu_ttm_tt_unpin_userptr(ttm);
 738
 739         spin_lock(&gtt->adev->gtt_list_lock);
 740         list_del_init(&gtt->list);
 741         spin_unlock(&gtt->adev->gtt_list_lock);
 742
 743         return 0;
 744 }
 745
 746 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 747 {
 748         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 749
 750         ttm_dma_tt_fini(&gtt->ttm);
 751         kfree(gtt);
 752 }
 753
 754 static struct ttm_backend_func amdgpu_backend_func = {
 755         .bind = &amdgpu_ttm_backend_bind,
 756         .unbind = &amdgpu_ttm_backend_unbind,
 757         .destroy = &amdgpu_ttm_backend_destroy,
 758 };
 759
 760 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 761                                     unsigned long size, uint32_t page_flags,
 762                                     struct page *dummy_read_page)
 763 {
 764         struct amdgpu_device *adev;
 765         struct amdgpu_ttm_tt *gtt;
 766
 767         adev = amdgpu_get_adev(bdev);
 768
 769         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 770         if (gtt == NULL) {
 771                 return NULL;
 772         }
 773         gtt->ttm.ttm.func = &amdgpu_backend_func;
 774         gtt->adev = adev;
 775         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 776                 kfree(gtt);
 777                 return NULL;
 778         }
 779         INIT_LIST_HEAD(&gtt->list);
 780         return &gtt->ttm.ttm;
 781 }
 782
 783 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 784 {
 785         struct amdgpu_device *adev;
 786         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 787         unsigned i;
 788         int r;
 789         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 790
 791         if (ttm->state != tt_unpopulated)
 792                 return 0;
 793
 794         if (gtt && gtt->userptr) {
 795                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 796                 if (!ttm->sg)
 797                         return -ENOMEM;
 798
 799                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 800                 ttm->state = tt_unbound;
 801                 return 0;
 802         }
 803
 804         if (slave && ttm->sg) {
 805                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 806                                                  gtt->ttm.dma_address, ttm->num_pages);
 807                 ttm->state = tt_unbound;
 808                 return 0;
 809         }
 810
 811         adev = amdgpu_get_adev(ttm->bdev);
 812
 813 #ifdef CONFIG_SWIOTLB
 814         if (swiotlb_nr_tbl()) {
 815                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 816         }
 817 #endif
 818
 819         r = ttm_pool_populate(ttm);
 820         if (r) {
 821                 return r;
 822         }
 823
 824         for (i = 0; i < ttm->num_pages; i++) {
 825                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 826                                                        0, PAGE_SIZE,
 827                                                        PCI_DMA_BIDIRECTIONAL);
 828                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 829                         while (i--) {
 830                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 831                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 832                                 gtt->ttm.dma_address[i] = 0;
 833                         }
 834                         ttm_pool_unpopulate(ttm);
 835                         return -EFAULT;
 836                 }
 837         }
 838         return 0;
 839 }
 840
 841 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 842 {
 843         struct amdgpu_device *adev;
 844         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 845         unsigned i;
 846         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 847
 848         if (gtt && gtt->userptr) {
 849                 kfree(ttm->sg);
 850                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 851                 return;
 852         }
 853
 854         if (slave)
 855                 return;
 856
 857         adev = amdgpu_get_adev(ttm->bdev);
 858
 859 #ifdef CONFIG_SWIOTLB
 860         if (swiotlb_nr_tbl()) {
 861                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 862                 return;
 863         }
 864 #endif
 865
 866         for (i = 0; i < ttm->num_pages; i++) {
 867                 if (gtt->ttm.dma_address[i]) {
 868                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 869                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 870                 }
 871         }
 872
 873         ttm_pool_unpopulate(ttm);
 874 }
 875
 876 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 877                               uint32_t flags)
 878 {
 879         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 880
 881         if (gtt == NULL)
 882                 return -EINVAL;
 883
 884         gtt->userptr = addr;
 885         gtt->usermm = current->mm;
 886         gtt->userflags = flags;
 887         spin_lock_init(&gtt->guptasklock);
 888         INIT_LIST_HEAD(&gtt->guptasks);
 889         atomic_set(&gtt->mmu_invalidations, 0);
 890
 891         return 0;
 892 }
 893
 894 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 895 {
 896         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 897
 898         if (gtt == NULL)
 899                 return NULL;
 900
 901         return gtt->usermm;
 902 }
 903
 904 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 905                                   unsigned long end)
 906 {
 907         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 908         struct amdgpu_ttm_gup_task_list *entry;
 909         unsigned long size;
 910
 911         if (gtt == NULL || !gtt->userptr)
 912                 return false;
 913
 914         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 915         if (gtt->userptr > end || gtt->userptr + size <= start)
 916                 return false;
 917
 918         spin_lock(&gtt->guptasklock);
 919         list_for_each_entry(entry, &gtt->guptasks, list) {
 920                 if (entry->task == current) {
 921                         spin_unlock(&gtt->guptasklock);
 922                         return false;
 923                 }
 924         }
 925         spin_unlock(&gtt->guptasklock);
 926
 927         atomic_inc(&gtt->mmu_invalidations);
 928
 929         return true;
 930 }
 931
 932 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 933                                        int *last_invalidated)
 934 {
 935         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 936         int prev_invalidated = *last_invalidated;
 937
 938         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 939         return prev_invalidated != *last_invalidated;
 940 }
 941
 942 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 943 {
 944         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 945
 946         if (gtt == NULL)
 947                 return false;
 948
 949         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 950 }
 951
 952 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 953                                  struct ttm_mem_reg *mem)
 954 {
 955         uint32_t flags = 0;
 956
 957         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 958                 flags |= AMDGPU_PTE_VALID;
 959
 960         if (mem && mem->mem_type == TTM_PL_TT) {
 961                 flags |= AMDGPU_PTE_SYSTEM;
 962
 963                 if (ttm->caching_state == tt_cached)
 964                         flags |= AMDGPU_PTE_SNOOPED;
 965         }
 966
 967         if (adev->asic_type >= CHIP_TONGA)
 968                 flags |= AMDGPU_PTE_EXECUTABLE;
 969
 970         flags |= AMDGPU_PTE_READABLE;
 971
 972         if (!amdgpu_ttm_tt_is_readonly(ttm))
 973                 flags |= AMDGPU_PTE_WRITEABLE;
 974
 975         return flags;
 976 }
 977
 978 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
 979 {
 980         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
 981         unsigned i, j;
 982
 983         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
 984                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
 985
 986                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
 987                         if (&tbo->lru == lru->lru[j])
 988                                 lru->lru[j] = tbo->lru.prev;
 989
 990                 if (&tbo->swap == lru->swap_lru)
 991                         lru->swap_lru = tbo->swap.prev;
 992         }
 993 }
 994
 995 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
 996 {
 997         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
 998         unsigned log2_size = min(ilog2(tbo->num_pages),
 999                                  AMDGPU_TTM_LRU_SIZE - 1);
1000
1001         return &adev->mman.log2_size[log2_size];
1002 }
1003
1004 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1005 {
1006         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1007         struct list_head *res = lru->lru[tbo->mem.mem_type];
1008
1009         lru->lru[tbo->mem.mem_type] = &tbo->lru;
1010         while ((++lru)->lru[tbo->mem.mem_type] == res)
1011                 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1012
1013         return res;
1014 }
1015
1016 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1017 {
1018         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1019         struct list_head *res = lru->swap_lru;
1020
1021         lru->swap_lru = &tbo->swap;
1022         while ((++lru)->swap_lru == res)
1023                 lru->swap_lru = &tbo->swap;
1024
1025         return res;
1026 }
1027
1028 static struct ttm_bo_driver amdgpu_bo_driver = {
1029         .ttm_tt_create = &amdgpu_ttm_tt_create,
1030         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1031         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1032         .invalidate_caches = &amdgpu_invalidate_caches,
1033         .init_mem_type = &amdgpu_init_mem_type,
1034         .evict_flags = &amdgpu_evict_flags,
1035         .move = &amdgpu_bo_move,
1036         .verify_access = &amdgpu_verify_access,
1037         .move_notify = &amdgpu_bo_move_notify,
1038         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1039         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1040         .io_mem_free = &amdgpu_ttm_io_mem_free,
1041         .lru_removal = &amdgpu_ttm_lru_removal,
1042         .lru_tail = &amdgpu_ttm_lru_tail,
1043         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1044 };
1045
1046 int amdgpu_ttm_init(struct amdgpu_device *adev)
1047 {
1048         unsigned i, j;
1049         int r;
1050
1051         /* No others user of address space so set it to 0 */
1052         r = ttm_bo_device_init(&adev->mman.bdev,
1053                                adev->mman.bo_global_ref.ref.object,
1054                                &amdgpu_bo_driver,
1055                                adev->ddev->anon_inode->i_mapping,
1056                                DRM_FILE_PAGE_OFFSET,
1057                                adev->need_dma32);
1058         if (r) {
1059                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1060                 return r;
1061         }
1062
1063         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1064                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1065
1066                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1067                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1068                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1069         }
1070
1071         for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1072                 adev->mman.guard.lru[j] = NULL;
1073         adev->mman.guard.swap_lru = NULL;
1074
1075         adev->mman.initialized = true;
1076         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1077                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1078         if (r) {
1079                 DRM_ERROR("Failed initializing VRAM heap.\n");
1080                 return r;
1081         }
1082         /* Change the size here instead of the init above so only lpfn is affected */
1083         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1084
1085         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1086                              AMDGPU_GEM_DOMAIN_VRAM,
1087                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1088                              NULL, NULL, &adev->stollen_vga_memory);
1089         if (r) {
1090                 return r;
1091         }
1092         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1093         if (r)
1094                 return r;
1095         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1096         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1097         if (r) {
1098                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1099                 return r;
1100         }
1101         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1102                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1103         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1104                                 adev->mc.gtt_size >> PAGE_SHIFT);
1105         if (r) {
1106                 DRM_ERROR("Failed initializing GTT heap.\n");
1107                 return r;
1108         }
1109         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1110                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1111
1112         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1113         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1114         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1115         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1116         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1117         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1118         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1119         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1120         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1121         /* GDS Memory */
1122         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1123                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1124         if (r) {
1125                 DRM_ERROR("Failed initializing GDS heap.\n");
1126                 return r;
1127         }
1128
1129         /* GWS */
1130         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1131                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1132         if (r) {
1133                 DRM_ERROR("Failed initializing gws heap.\n");
1134                 return r;
1135         }
1136
1137         /* OA */
1138         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1139                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1140         if (r) {
1141                 DRM_ERROR("Failed initializing oa heap.\n");
1142                 return r;
1143         }
1144
1145         r = amdgpu_ttm_debugfs_init(adev);
1146         if (r) {
1147                 DRM_ERROR("Failed to init debugfs\n");
1148                 return r;
1149         }
1150         return 0;
1151 }
1152
1153 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1154 {
1155         int r;
1156
1157         if (!adev->mman.initialized)
1158                 return;
1159         amdgpu_ttm_debugfs_fini(adev);
1160         if (adev->stollen_vga_memory) {
1161                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1162                 if (r == 0) {
1163                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1164                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1165                 }
1166                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1167         }
1168         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1169         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1170         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1171         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1172         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1173         ttm_bo_device_release(&adev->mman.bdev);
1174         amdgpu_gart_fini(adev);
1175         amdgpu_ttm_global_fini(adev);
1176         adev->mman.initialized = false;
1177         DRM_INFO("amdgpu: ttm finalized\n");
1178 }
1179
1180 /* this should only be called at bootup or when userspace
1181  * isn't running */
1182 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1183 {
1184         struct ttm_mem_type_manager *man;
1185
1186         if (!adev->mman.initialized)
1187                 return;
1188
1189         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1190         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1191         man->size = size >> PAGE_SHIFT;
1192 }
1193
1194 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1195 {
1196         struct drm_file *file_priv;
1197         struct amdgpu_device *adev;
1198
1199         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1200                 return -EINVAL;
1201
1202         file_priv = filp->private_data;
1203         adev = file_priv->minor->dev->dev_private;
1204         if (adev == NULL)
1205                 return -EINVAL;
1206
1207         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1208 }
1209
1210 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1211                        uint64_t src_offset,
1212                        uint64_t dst_offset,
1213                        uint32_t byte_count,
1214                        struct reservation_object *resv,
1215                        struct fence **fence, bool direct_submit)
1216 {
1217         struct amdgpu_device *adev = ring->adev;
1218         struct amdgpu_job *job;
1219
1220         uint32_t max_bytes;
1221         unsigned num_loops, num_dw;
1222         unsigned i;
1223         int r;
1224
1225         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1226         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1227         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1228
1229         /* for IB padding */
1230         while (num_dw & 0x7)
1231                 num_dw++;
1232
1233         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1234         if (r)
1235                 return r;
1236
1237         if (resv) {
1238                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1239                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1240                 if (r) {
1241                         DRM_ERROR("sync failed (%d).\n", r);
1242                         goto error_free;
1243                 }
1244         }
1245
1246         for (i = 0; i < num_loops; i++) {
1247                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1248
1249                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1250                                         dst_offset, cur_size_in_bytes);
1251
1252                 src_offset += cur_size_in_bytes;
1253                 dst_offset += cur_size_in_bytes;
1254                 byte_count -= cur_size_in_bytes;
1255         }
1256
1257         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1258         WARN_ON(job->ibs[0].length_dw > num_dw);
1259         if (direct_submit) {
1260                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1261                                        NULL, NULL, fence);
1262                 job->fence = fence_get(*fence);
1263                 if (r)
1264                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1265                 amdgpu_job_free(job);
1266         } else {
1267                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1268                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1269                 if (r)
1270                         goto error_free;
1271         }
1272
1273         return r;
1274
1275 error_free:
1276         amdgpu_job_free(job);
1277         return r;
1278 }
1279
1280 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1281                 uint32_t src_data,
1282                 struct reservation_object *resv,
1283                 struct fence **fence)
1284 {
1285         struct amdgpu_device *adev = bo->adev;
1286         struct amdgpu_job *job;
1287         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1288
1289         uint32_t max_bytes, byte_count;
1290         uint64_t dst_offset;
1291         unsigned int num_loops, num_dw;
1292         unsigned int i;
1293         int r;
1294
1295         byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1296         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1297         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1298         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1299
1300         /* for IB padding */
1301         while (num_dw & 0x7)
1302                 num_dw++;
1303
1304         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1305         if (r)
1306                 return r;
1307
1308         if (resv) {
1309                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1310                                 AMDGPU_FENCE_OWNER_UNDEFINED);
1311                 if (r) {
1312                         DRM_ERROR("sync failed (%d).\n", r);
1313                         goto error_free;
1314                 }
1315         }
1316
1317         dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1318         for (i = 0; i < num_loops; i++) {
1319                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1320
1321                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1322                                 dst_offset, cur_size_in_bytes);
1323
1324                 dst_offset += cur_size_in_bytes;
1325                 byte_count -= cur_size_in_bytes;
1326         }
1327
1328         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1329         WARN_ON(job->ibs[0].length_dw > num_dw);
1330         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1331                         AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1332         if (r)
1333                 goto error_free;
1334
1335         return 0;
1336
1337 error_free:
1338         amdgpu_job_free(job);
1339         return r;
1340 }
1341
1342 #if defined(CONFIG_DEBUG_FS)
1343
1344 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1345 {
1346         struct drm_info_node *node = (struct drm_info_node *)m->private;
1347         unsigned ttm_pl = *(int *)node->info_ent->data;
1348         struct drm_device *dev = node->minor->dev;
1349         struct amdgpu_device *adev = dev->dev_private;
1350         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1351         int ret;
1352         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1353
1354         spin_lock(&glob->lru_lock);
1355         ret = drm_mm_dump_table(m, mm);
1356         spin_unlock(&glob->lru_lock);
1357         if (ttm_pl == TTM_PL_VRAM)
1358                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1359                            adev->mman.bdev.man[ttm_pl].size,
1360                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1361                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1362         return ret;
1363 }
1364
1365 static int ttm_pl_vram = TTM_PL_VRAM;
1366 static int ttm_pl_tt = TTM_PL_TT;
1367
1368 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1369         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1370         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1371         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1372 #ifdef CONFIG_SWIOTLB
1373         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1374 #endif
1375 };
1376
1377 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1378                                     size_t size, loff_t *pos)
1379 {
1380         struct amdgpu_device *adev = f->f_inode->i_private;
1381         ssize_t result = 0;
1382         int r;
1383
1384         if (size & 0x3 || *pos & 0x3)
1385                 return -EINVAL;
1386
1387         while (size) {
1388                 unsigned long flags;
1389                 uint32_t value;
1390
1391                 if (*pos >= adev->mc.mc_vram_size)
1392                         return result;
1393
1394                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1395                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1396                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1397                 value = RREG32(mmMM_DATA);
1398                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1399
1400                 r = put_user(value, (uint32_t *)buf);
1401                 if (r)
1402                         return r;
1403
1404                 result += 4;
1405                 buf += 4;
1406                 *pos += 4;
1407                 size -= 4;
1408         }
1409
1410         return result;
1411 }
1412
1413 static const struct file_operations amdgpu_ttm_vram_fops = {
1414         .owner = THIS_MODULE,
1415         .read = amdgpu_ttm_vram_read,
1416         .llseek = default_llseek
1417 };
1418
1419 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1420
1421 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1422                                    size_t size, loff_t *pos)
1423 {
1424         struct amdgpu_device *adev = f->f_inode->i_private;
1425         ssize_t result = 0;
1426         int r;
1427
1428         while (size) {
1429                 loff_t p = *pos / PAGE_SIZE;
1430                 unsigned off = *pos & ~PAGE_MASK;
1431                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1432                 struct page *page;
1433                 void *ptr;
1434
1435                 if (p >= adev->gart.num_cpu_pages)
1436                         return result;
1437
1438                 page = adev->gart.pages[p];
1439                 if (page) {
1440                         ptr = kmap(page);
1441                         ptr += off;
1442
1443                         r = copy_to_user(buf, ptr, cur_size);
1444                         kunmap(adev->gart.pages[p]);
1445                 } else
1446                         r = clear_user(buf, cur_size);
1447
1448                 if (r)
1449                         return -EFAULT;
1450
1451                 result += cur_size;
1452                 buf += cur_size;
1453                 *pos += cur_size;
1454                 size -= cur_size;
1455         }
1456
1457         return result;
1458 }
1459
1460 static const struct file_operations amdgpu_ttm_gtt_fops = {
1461         .owner = THIS_MODULE,
1462         .read = amdgpu_ttm_gtt_read,
1463         .llseek = default_llseek
1464 };
1465
1466 #endif
1467
1468 #endif
1469
1470 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1471 {
1472 #if defined(CONFIG_DEBUG_FS)
1473         unsigned count;
1474
1475         struct drm_minor *minor = adev->ddev->primary;
1476         struct dentry *ent, *root = minor->debugfs_root;
1477
1478         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1479                                   adev, &amdgpu_ttm_vram_fops);
1480         if (IS_ERR(ent))
1481                 return PTR_ERR(ent);
1482         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1483         adev->mman.vram = ent;
1484
1485 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1486         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1487                                   adev, &amdgpu_ttm_gtt_fops);
1488         if (IS_ERR(ent))
1489                 return PTR_ERR(ent);
1490         i_size_write(ent->d_inode, adev->mc.gtt_size);
1491         adev->mman.gtt = ent;
1492
1493 #endif
1494         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1495
1496 #ifdef CONFIG_SWIOTLB
1497         if (!swiotlb_nr_tbl())
1498                 --count;
1499 #endif
1500
1501         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1502 #else
1503
1504         return 0;
1505 #endif
1506 }
1507
1508 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1509 {
1510 #if defined(CONFIG_DEBUG_FS)
1511
1512         debugfs_remove(adev->mman.vram);
1513         adev->mman.vram = NULL;
1514
1515 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1516         debugfs_remove(adev->mman.gtt);
1517         adev->mman.gtt = NULL;
1518 #endif
1519
1520 #endif
1521 }
1522
1523 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1524 {
1525         return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1526 }