drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <ttm/ttm_memory.h>
  38 #include <drm/drmP.h>
  39 #include <drm/amdgpu_drm.h>
  40 #include <linux/seq_file.h>
  41 #include <linux/slab.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/swap.h>
  44 #include <linux/pagemap.h>
  45 #include <linux/debugfs.h>
  46 #include "amdgpu.h"
  47 #include "bif/bif_4_1_d.h"
  48
  49 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  50
  51 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  52 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  53
  54 static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
  55 {
  56         struct amdgpu_mman *mman;
  57         struct amdgpu_device *adev;
  58
  59         mman = container_of(bdev, struct amdgpu_mman, bdev);
  60         adev = container_of(mman, struct amdgpu_device, mman);
  61         return adev;
  62 }
  63
  64
  65 /*
  66  * Global memory.
  67  */
  68 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  69 {
  70         return ttm_mem_global_init(ref->object);
  71 }
  72
  73 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  74 {
  75         ttm_mem_global_release(ref->object);
  76 }
  77
  78 int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  79 {
  80         struct drm_global_reference *global_ref;
  81         struct amdgpu_ring *ring;
  82         struct amd_sched_rq *rq;
  83         int r;
  84
  85         adev->mman.mem_global_referenced = false;
  86         global_ref = &adev->mman.mem_global_ref;
  87         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  88         global_ref->size = sizeof(struct ttm_mem_global);
  89         global_ref->init = &amdgpu_ttm_mem_global_init;
  90         global_ref->release = &amdgpu_ttm_mem_global_release;
  91         r = drm_global_item_ref(global_ref);
  92         if (r != 0) {
  93                 DRM_ERROR("Failed setting up TTM memory accounting "
  94                           "subsystem.\n");
  95                 return r;
  96         }
  97
  98         adev->mman.bo_global_ref.mem_glob =
  99                 adev->mman.mem_global_ref.object;
 100         global_ref = &adev->mman.bo_global_ref.ref;
 101         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 102         global_ref->size = sizeof(struct ttm_bo_global);
 103         global_ref->init = &ttm_bo_global_init;
 104         global_ref->release = &ttm_bo_global_release;
 105         r = drm_global_item_ref(global_ref);
 106         if (r != 0) {
 107                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 108                 drm_global_item_unref(&adev->mman.mem_global_ref);
 109                 return r;
 110         }
 111
 112         ring = adev->mman.buffer_funcs_ring;
 113         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 114         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 115                                   rq, amdgpu_sched_jobs);
 116         if (r != 0) {
 117                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 118                 drm_global_item_unref(&adev->mman.mem_global_ref);
 119                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 120                 return r;
 121         }
 122
 123         adev->mman.mem_global_referenced = true;
 124
 125         return 0;
 126 }
 127
 128 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 129 {
 130         if (adev->mman.mem_global_referenced) {
 131                 amd_sched_entity_fini(adev->mman.entity.sched,
 132                                       &adev->mman.entity);
 133                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 134                 drm_global_item_unref(&adev->mman.mem_global_ref);
 135                 adev->mman.mem_global_referenced = false;
 136         }
 137 }
 138
 139 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 140 {
 141         return 0;
 142 }
 143
 144 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 145                                 struct ttm_mem_type_manager *man)
 146 {
 147         struct amdgpu_device *adev;
 148
 149         adev = amdgpu_get_adev(bdev);
 150
 151         switch (type) {
 152         case TTM_PL_SYSTEM:
 153                 /* System memory */
 154                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 155                 man->available_caching = TTM_PL_MASK_CACHING;
 156                 man->default_caching = TTM_PL_FLAG_CACHED;
 157                 break;
 158         case TTM_PL_TT:
 159                 man->func = &ttm_bo_manager_func;
 160                 man->gpu_offset = adev->mc.gtt_start;
 161                 man->available_caching = TTM_PL_MASK_CACHING;
 162                 man->default_caching = TTM_PL_FLAG_CACHED;
 163                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 164                 break;
 165         case TTM_PL_VRAM:
 166                 /* "On-card" video ram */
 167                 man->func = &ttm_bo_manager_func;
 168                 man->gpu_offset = adev->mc.vram_start;
 169                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 170                              TTM_MEMTYPE_FLAG_MAPPABLE;
 171                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 172                 man->default_caching = TTM_PL_FLAG_WC;
 173                 break;
 174         case AMDGPU_PL_GDS:
 175         case AMDGPU_PL_GWS:
 176         case AMDGPU_PL_OA:
 177                 /* On-chip GDS memory*/
 178                 man->func = &ttm_bo_manager_func;
 179                 man->gpu_offset = 0;
 180                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 181                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 182                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 183                 break;
 184         default:
 185                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 186                 return -EINVAL;
 187         }
 188         return 0;
 189 }
 190
 191 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 192                                 struct ttm_placement *placement)
 193 {
 194         struct amdgpu_bo *rbo;
 195         static struct ttm_place placements = {
 196                 .fpfn = 0,
 197                 .lpfn = 0,
 198                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 199         };
 200
 201         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 202                 placement->placement = &placements;
 203                 placement->busy_placement = &placements;
 204                 placement->num_placement = 1;
 205                 placement->num_busy_placement = 1;
 206                 return;
 207         }
 208         rbo = container_of(bo, struct amdgpu_bo, tbo);
 209         switch (bo->mem.mem_type) {
 210         case TTM_PL_VRAM:
 211                 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
 212                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 213                 else
 214                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
 215                 break;
 216         case TTM_PL_TT:
 217         default:
 218                 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
 219         }
 220         *placement = rbo->placement;
 221 }
 222
 223 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 224 {
 225         struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 226
 227         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 228                 return -EPERM;
 229         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 230 }
 231
 232 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 233                              struct ttm_mem_reg *new_mem)
 234 {
 235         struct ttm_mem_reg *old_mem = &bo->mem;
 236
 237         BUG_ON(old_mem->mm_node != NULL);
 238         *old_mem = *new_mem;
 239         new_mem->mm_node = NULL;
 240 }
 241
 242 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 243                         bool evict, bool no_wait_gpu,
 244                         struct ttm_mem_reg *new_mem,
 245                         struct ttm_mem_reg *old_mem)
 246 {
 247         struct amdgpu_device *adev;
 248         struct amdgpu_ring *ring;
 249         uint64_t old_start, new_start;
 250         struct fence *fence;
 251         int r;
 252
 253         adev = amdgpu_get_adev(bo->bdev);
 254         ring = adev->mman.buffer_funcs_ring;
 255         old_start = old_mem->start << PAGE_SHIFT;
 256         new_start = new_mem->start << PAGE_SHIFT;
 257
 258         switch (old_mem->mem_type) {
 259         case TTM_PL_VRAM:
 260                 old_start += adev->mc.vram_start;
 261                 break;
 262         case TTM_PL_TT:
 263                 old_start += adev->mc.gtt_start;
 264                 break;
 265         default:
 266                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 267                 return -EINVAL;
 268         }
 269         switch (new_mem->mem_type) {
 270         case TTM_PL_VRAM:
 271                 new_start += adev->mc.vram_start;
 272                 break;
 273         case TTM_PL_TT:
 274                 new_start += adev->mc.gtt_start;
 275                 break;
 276         default:
 277                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 278                 return -EINVAL;
 279         }
 280         if (!ring->ready) {
 281                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 282                 return -EINVAL;
 283         }
 284
 285         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 286
 287         r = amdgpu_copy_buffer(ring, old_start, new_start,
 288                                new_mem->num_pages * PAGE_SIZE, /* bytes */
 289                                bo->resv, &fence);
 290         if (r)
 291                 return r;
 292
 293         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 294         fence_put(fence);
 295         return r;
 296 }
 297
 298 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 299                                 bool evict, bool interruptible,
 300                                 bool no_wait_gpu,
 301                                 struct ttm_mem_reg *new_mem)
 302 {
 303         struct amdgpu_device *adev;
 304         struct ttm_mem_reg *old_mem = &bo->mem;
 305         struct ttm_mem_reg tmp_mem;
 306         struct ttm_place placements;
 307         struct ttm_placement placement;
 308         int r;
 309
 310         adev = amdgpu_get_adev(bo->bdev);
 311         tmp_mem = *new_mem;
 312         tmp_mem.mm_node = NULL;
 313         placement.num_placement = 1;
 314         placement.placement = &placements;
 315         placement.num_busy_placement = 1;
 316         placement.busy_placement = &placements;
 317         placements.fpfn = 0;
 318         placements.lpfn = 0;
 319         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 320         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 321                              interruptible, no_wait_gpu);
 322         if (unlikely(r)) {
 323                 return r;
 324         }
 325
 326         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 327         if (unlikely(r)) {
 328                 goto out_cleanup;
 329         }
 330
 331         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 332         if (unlikely(r)) {
 333                 goto out_cleanup;
 334         }
 335         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 336         if (unlikely(r)) {
 337                 goto out_cleanup;
 338         }
 339         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 340 out_cleanup:
 341         ttm_bo_mem_put(bo, &tmp_mem);
 342         return r;
 343 }
 344
 345 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 346                                 bool evict, bool interruptible,
 347                                 bool no_wait_gpu,
 348                                 struct ttm_mem_reg *new_mem)
 349 {
 350         struct amdgpu_device *adev;
 351         struct ttm_mem_reg *old_mem = &bo->mem;
 352         struct ttm_mem_reg tmp_mem;
 353         struct ttm_placement placement;
 354         struct ttm_place placements;
 355         int r;
 356
 357         adev = amdgpu_get_adev(bo->bdev);
 358         tmp_mem = *new_mem;
 359         tmp_mem.mm_node = NULL;
 360         placement.num_placement = 1;
 361         placement.placement = &placements;
 362         placement.num_busy_placement = 1;
 363         placement.busy_placement = &placements;
 364         placements.fpfn = 0;
 365         placements.lpfn = 0;
 366         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 367         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 368                              interruptible, no_wait_gpu);
 369         if (unlikely(r)) {
 370                 return r;
 371         }
 372         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 373         if (unlikely(r)) {
 374                 goto out_cleanup;
 375         }
 376         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 377         if (unlikely(r)) {
 378                 goto out_cleanup;
 379         }
 380 out_cleanup:
 381         ttm_bo_mem_put(bo, &tmp_mem);
 382         return r;
 383 }
 384
 385 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 386                         bool evict, bool interruptible,
 387                         bool no_wait_gpu,
 388                         struct ttm_mem_reg *new_mem)
 389 {
 390         struct amdgpu_device *adev;
 391         struct amdgpu_bo *abo;
 392         struct ttm_mem_reg *old_mem = &bo->mem;
 393         int r;
 394
 395         /* Can't move a pinned BO */
 396         abo = container_of(bo, struct amdgpu_bo, tbo);
 397         if (WARN_ON_ONCE(abo->pin_count > 0))
 398                 return -EINVAL;
 399
 400         adev = amdgpu_get_adev(bo->bdev);
 401
 402         /* remember the eviction */
 403         if (evict)
 404                 atomic64_inc(&adev->num_evictions);
 405
 406         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 407                 amdgpu_move_null(bo, new_mem);
 408                 return 0;
 409         }
 410         if ((old_mem->mem_type == TTM_PL_TT &&
 411              new_mem->mem_type == TTM_PL_SYSTEM) ||
 412             (old_mem->mem_type == TTM_PL_SYSTEM &&
 413              new_mem->mem_type == TTM_PL_TT)) {
 414                 /* bind is enough */
 415                 amdgpu_move_null(bo, new_mem);
 416                 return 0;
 417         }
 418         if (adev->mman.buffer_funcs == NULL ||
 419             adev->mman.buffer_funcs_ring == NULL ||
 420             !adev->mman.buffer_funcs_ring->ready) {
 421                 /* use memcpy */
 422                 goto memcpy;
 423         }
 424
 425         if (old_mem->mem_type == TTM_PL_VRAM &&
 426             new_mem->mem_type == TTM_PL_SYSTEM) {
 427                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 428                                         no_wait_gpu, new_mem);
 429         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 430                    new_mem->mem_type == TTM_PL_VRAM) {
 431                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 432                                             no_wait_gpu, new_mem);
 433         } else {
 434                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 435         }
 436
 437         if (r) {
 438 memcpy:
 439                 r = ttm_bo_move_memcpy(bo, evict, interruptible,
 440                                        no_wait_gpu, new_mem);
 441                 if (r) {
 442                         return r;
 443                 }
 444         }
 445
 446         /* update statistics */
 447         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 448         return 0;
 449 }
 450
 451 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 452 {
 453         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 454         struct amdgpu_device *adev = amdgpu_get_adev(bdev);
 455
 456         mem->bus.addr = NULL;
 457         mem->bus.offset = 0;
 458         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 459         mem->bus.base = 0;
 460         mem->bus.is_iomem = false;
 461         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 462                 return -EINVAL;
 463         switch (mem->mem_type) {
 464         case TTM_PL_SYSTEM:
 465                 /* system memory */
 466                 return 0;
 467         case TTM_PL_TT:
 468                 break;
 469         case TTM_PL_VRAM:
 470                 mem->bus.offset = mem->start << PAGE_SHIFT;
 471                 /* check if it's visible */
 472                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 473                         return -EINVAL;
 474                 mem->bus.base = adev->mc.aper_base;
 475                 mem->bus.is_iomem = true;
 476 #ifdef __alpha__
 477                 /*
 478                  * Alpha: use bus.addr to hold the ioremap() return,
 479                  * so we can modify bus.base below.
 480                  */
 481                 if (mem->placement & TTM_PL_FLAG_WC)
 482                         mem->bus.addr =
 483                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 484                                            mem->bus.size);
 485                 else
 486                         mem->bus.addr =
 487                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 488                                                 mem->bus.size);
 489
 490                 /*
 491                  * Alpha: Use just the bus offset plus
 492                  * the hose/domain memory base for bus.base.
 493                  * It then can be used to build PTEs for VRAM
 494                  * access, as done in ttm_bo_vm_fault().
 495                  */
 496                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 497                         adev->ddev->hose->dense_mem_base;
 498 #endif
 499                 break;
 500         default:
 501                 return -EINVAL;
 502         }
 503         return 0;
 504 }
 505
 506 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 507 {
 508 }
 509
 510 /*
 511  * TTM backend functions.
 512  */
 513 struct amdgpu_ttm_gup_task_list {
 514         struct list_head        list;
 515         struct task_struct      *task;
 516 };
 517
 518 struct amdgpu_ttm_tt {
 519         struct ttm_dma_tt       ttm;
 520         struct amdgpu_device    *adev;
 521         u64                     offset;
 522         uint64_t                userptr;
 523         struct mm_struct        *usermm;
 524         uint32_t                userflags;
 525         spinlock_t              guptasklock;
 526         struct list_head        guptasks;
 527         atomic_t                mmu_invalidations;
 528 };
 529
 530 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 531 {
 532         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 533         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 534         unsigned pinned = 0;
 535         int r;
 536
 537         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 538                 /* check that we only use anonymous memory
 539                    to prevent problems with writeback */
 540                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 541                 struct vm_area_struct *vma;
 542
 543                 vma = find_vma(gtt->usermm, gtt->userptr);
 544                 if (!vma || vma->vm_file || vma->vm_end < end)
 545                         return -EPERM;
 546         }
 547
 548         do {
 549                 unsigned num_pages = ttm->num_pages - pinned;
 550                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 551                 struct page **p = pages + pinned;
 552                 struct amdgpu_ttm_gup_task_list guptask;
 553
 554                 guptask.task = current;
 555                 spin_lock(&gtt->guptasklock);
 556                 list_add(&guptask.list, &gtt->guptasks);
 557                 spin_unlock(&gtt->guptasklock);
 558
 559                 r = get_user_pages(userptr, num_pages, write, 0, p, NULL);
 560
 561                 spin_lock(&gtt->guptasklock);
 562                 list_del(&guptask.list);
 563                 spin_unlock(&gtt->guptasklock);
 564
 565                 if (r < 0)
 566                         goto release_pages;
 567
 568                 pinned += r;
 569
 570         } while (pinned < ttm->num_pages);
 571
 572         return 0;
 573
 574 release_pages:
 575         release_pages(pages, pinned, 0);
 576         return r;
 577 }
 578
 579 /* prepare the sg table with the user pages */
 580 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 581 {
 582         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 583         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 584         unsigned nents;
 585         int r;
 586
 587         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 588         enum dma_data_direction direction = write ?
 589                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 590
 591         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 592                                       ttm->num_pages << PAGE_SHIFT,
 593                                       GFP_KERNEL);
 594         if (r)
 595                 goto release_sg;
 596
 597         r = -ENOMEM;
 598         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 599         if (nents != ttm->sg->nents)
 600                 goto release_sg;
 601
 602         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 603                                          gtt->ttm.dma_address, ttm->num_pages);
 604
 605         return 0;
 606
 607 release_sg:
 608         kfree(ttm->sg);
 609         return r;
 610 }
 611
 612 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 613 {
 614         struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
 615         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 616         struct sg_page_iter sg_iter;
 617
 618         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 619         enum dma_data_direction direction = write ?
 620                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 621
 622         /* double check that we don't free the table twice */
 623         if (!ttm->sg->sgl)
 624                 return;
 625
 626         /* free the sg table and pages again */
 627         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 628
 629         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 630                 struct page *page = sg_page_iter_page(&sg_iter);
 631                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 632                         set_page_dirty(page);
 633
 634                 mark_page_accessed(page);
 635                 put_page(page);
 636         }
 637
 638         sg_free_table(ttm->sg);
 639 }
 640
 641 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 642                                    struct ttm_mem_reg *bo_mem)
 643 {
 644         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 645         uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 646         int r;
 647
 648         if (gtt->userptr) {
 649                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 650                 if (r) {
 651                         DRM_ERROR("failed to pin userptr\n");
 652                         return r;
 653                 }
 654         }
 655         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 656         if (!ttm->num_pages) {
 657                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 658                      ttm->num_pages, bo_mem, ttm);
 659         }
 660
 661         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 662             bo_mem->mem_type == AMDGPU_PL_GWS ||
 663             bo_mem->mem_type == AMDGPU_PL_OA)
 664                 return -EINVAL;
 665
 666         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 667                 ttm->pages, gtt->ttm.dma_address, flags);
 668
 669         if (r) {
 670                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 671                           ttm->num_pages, (unsigned)gtt->offset);
 672                 return r;
 673         }
 674         return 0;
 675 }
 676
 677 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 678 {
 679         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 680
 681         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 682         if (gtt->adev->gart.ready)
 683                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 684
 685         if (gtt->userptr)
 686                 amdgpu_ttm_tt_unpin_userptr(ttm);
 687
 688         return 0;
 689 }
 690
 691 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 692 {
 693         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 694
 695         ttm_dma_tt_fini(&gtt->ttm);
 696         kfree(gtt);
 697 }
 698
 699 static struct ttm_backend_func amdgpu_backend_func = {
 700         .bind = &amdgpu_ttm_backend_bind,
 701         .unbind = &amdgpu_ttm_backend_unbind,
 702         .destroy = &amdgpu_ttm_backend_destroy,
 703 };
 704
 705 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 706                                     unsigned long size, uint32_t page_flags,
 707                                     struct page *dummy_read_page)
 708 {
 709         struct amdgpu_device *adev;
 710         struct amdgpu_ttm_tt *gtt;
 711
 712         adev = amdgpu_get_adev(bdev);
 713
 714         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 715         if (gtt == NULL) {
 716                 return NULL;
 717         }
 718         gtt->ttm.ttm.func = &amdgpu_backend_func;
 719         gtt->adev = adev;
 720         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 721                 kfree(gtt);
 722                 return NULL;
 723         }
 724         return &gtt->ttm.ttm;
 725 }
 726
 727 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 728 {
 729         struct amdgpu_device *adev;
 730         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 731         unsigned i;
 732         int r;
 733         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 734
 735         if (ttm->state != tt_unpopulated)
 736                 return 0;
 737
 738         if (gtt && gtt->userptr) {
 739                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 740                 if (!ttm->sg)
 741                         return -ENOMEM;
 742
 743                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 744                 ttm->state = tt_unbound;
 745                 return 0;
 746         }
 747
 748         if (slave && ttm->sg) {
 749                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 750                                                  gtt->ttm.dma_address, ttm->num_pages);
 751                 ttm->state = tt_unbound;
 752                 return 0;
 753         }
 754
 755         adev = amdgpu_get_adev(ttm->bdev);
 756
 757 #ifdef CONFIG_SWIOTLB
 758         if (swiotlb_nr_tbl()) {
 759                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 760         }
 761 #endif
 762
 763         r = ttm_pool_populate(ttm);
 764         if (r) {
 765                 return r;
 766         }
 767
 768         for (i = 0; i < ttm->num_pages; i++) {
 769                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 770                                                        0, PAGE_SIZE,
 771                                                        PCI_DMA_BIDIRECTIONAL);
 772                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 773                         while (i--) {
 774                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 775                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 776                                 gtt->ttm.dma_address[i] = 0;
 777                         }
 778                         ttm_pool_unpopulate(ttm);
 779                         return -EFAULT;
 780                 }
 781         }
 782         return 0;
 783 }
 784
 785 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 786 {
 787         struct amdgpu_device *adev;
 788         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 789         unsigned i;
 790         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 791
 792         if (gtt && gtt->userptr) {
 793                 kfree(ttm->sg);
 794                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 795                 return;
 796         }
 797
 798         if (slave)
 799                 return;
 800
 801         adev = amdgpu_get_adev(ttm->bdev);
 802
 803 #ifdef CONFIG_SWIOTLB
 804         if (swiotlb_nr_tbl()) {
 805                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 806                 return;
 807         }
 808 #endif
 809
 810         for (i = 0; i < ttm->num_pages; i++) {
 811                 if (gtt->ttm.dma_address[i]) {
 812                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 813                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 814                 }
 815         }
 816
 817         ttm_pool_unpopulate(ttm);
 818 }
 819
 820 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 821                               uint32_t flags)
 822 {
 823         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 824
 825         if (gtt == NULL)
 826                 return -EINVAL;
 827
 828         gtt->userptr = addr;
 829         gtt->usermm = current->mm;
 830         gtt->userflags = flags;
 831         spin_lock_init(&gtt->guptasklock);
 832         INIT_LIST_HEAD(&gtt->guptasks);
 833         atomic_set(&gtt->mmu_invalidations, 0);
 834
 835         return 0;
 836 }
 837
 838 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 839 {
 840         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 841
 842         if (gtt == NULL)
 843                 return NULL;
 844
 845         return gtt->usermm;
 846 }
 847
 848 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 849                                   unsigned long end)
 850 {
 851         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 852         struct amdgpu_ttm_gup_task_list *entry;
 853         unsigned long size;
 854
 855         if (gtt == NULL || !gtt->userptr)
 856                 return false;
 857
 858         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 859         if (gtt->userptr > end || gtt->userptr + size <= start)
 860                 return false;
 861
 862         spin_lock(&gtt->guptasklock);
 863         list_for_each_entry(entry, &gtt->guptasks, list) {
 864                 if (entry->task == current) {
 865                         spin_unlock(&gtt->guptasklock);
 866                         return false;
 867                 }
 868         }
 869         spin_unlock(&gtt->guptasklock);
 870
 871         atomic_inc(&gtt->mmu_invalidations);
 872
 873         return true;
 874 }
 875
 876 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 877                                        int *last_invalidated)
 878 {
 879         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 880         int prev_invalidated = *last_invalidated;
 881
 882         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
 883         return prev_invalidated != *last_invalidated;
 884 }
 885
 886 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 887 {
 888         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 889
 890         if (gtt == NULL)
 891                 return false;
 892
 893         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 894 }
 895
 896 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 897                                  struct ttm_mem_reg *mem)
 898 {
 899         uint32_t flags = 0;
 900
 901         if (mem && mem->mem_type != TTM_PL_SYSTEM)
 902                 flags |= AMDGPU_PTE_VALID;
 903
 904         if (mem && mem->mem_type == TTM_PL_TT) {
 905                 flags |= AMDGPU_PTE_SYSTEM;
 906
 907                 if (ttm->caching_state == tt_cached)
 908                         flags |= AMDGPU_PTE_SNOOPED;
 909         }
 910
 911         if (adev->asic_type >= CHIP_TONGA)
 912                 flags |= AMDGPU_PTE_EXECUTABLE;
 913
 914         flags |= AMDGPU_PTE_READABLE;
 915
 916         if (!amdgpu_ttm_tt_is_readonly(ttm))
 917                 flags |= AMDGPU_PTE_WRITEABLE;
 918
 919         return flags;
 920 }
 921
 922 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
 923 {
 924         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
 925         unsigned i, j;
 926
 927         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
 928                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
 929
 930                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
 931                         if (&tbo->lru == lru->lru[j])
 932                                 lru->lru[j] = tbo->lru.prev;
 933
 934                 if (&tbo->swap == lru->swap_lru)
 935                         lru->swap_lru = tbo->swap.prev;
 936         }
 937 }
 938
 939 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
 940 {
 941         struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev);
 942         unsigned log2_size = min(ilog2(tbo->num_pages),
 943                                  AMDGPU_TTM_LRU_SIZE - 1);
 944
 945         return &adev->mman.log2_size[log2_size];
 946 }
 947
 948 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
 949 {
 950         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
 951         struct list_head *res = lru->lru[tbo->mem.mem_type];
 952
 953         lru->lru[tbo->mem.mem_type] = &tbo->lru;
 954
 955         return res;
 956 }
 957
 958 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
 959 {
 960         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
 961         struct list_head *res = lru->swap_lru;
 962
 963         lru->swap_lru = &tbo->swap;
 964
 965         return res;
 966 }
 967
 968 static struct ttm_bo_driver amdgpu_bo_driver = {
 969         .ttm_tt_create = &amdgpu_ttm_tt_create,
 970         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
 971         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
 972         .invalidate_caches = &amdgpu_invalidate_caches,
 973         .init_mem_type = &amdgpu_init_mem_type,
 974         .evict_flags = &amdgpu_evict_flags,
 975         .move = &amdgpu_bo_move,
 976         .verify_access = &amdgpu_verify_access,
 977         .move_notify = &amdgpu_bo_move_notify,
 978         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
 979         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
 980         .io_mem_free = &amdgpu_ttm_io_mem_free,
 981         .lru_removal = &amdgpu_ttm_lru_removal,
 982         .lru_tail = &amdgpu_ttm_lru_tail,
 983         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
 984 };
 985
 986 int amdgpu_ttm_init(struct amdgpu_device *adev)
 987 {
 988         unsigned i, j;
 989         int r;
 990
 991         /* No others user of address space so set it to 0 */
 992         r = ttm_bo_device_init(&adev->mman.bdev,
 993                                adev->mman.bo_global_ref.ref.object,
 994                                &amdgpu_bo_driver,
 995                                adev->ddev->anon_inode->i_mapping,
 996                                DRM_FILE_PAGE_OFFSET,
 997                                adev->need_dma32);
 998         if (r) {
 999                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1000                 return r;
1001         }
1002
1003         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1004                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1005
1006                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1007                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1008                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1009         }
1010
1011         adev->mman.initialized = true;
1012         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1013                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1014         if (r) {
1015                 DRM_ERROR("Failed initializing VRAM heap.\n");
1016                 return r;
1017         }
1018         /* Change the size here instead of the init above so only lpfn is affected */
1019         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1020
1021         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1022                              AMDGPU_GEM_DOMAIN_VRAM,
1023                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
1024                              NULL, NULL, &adev->stollen_vga_memory);
1025         if (r) {
1026                 return r;
1027         }
1028         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1029         if (r)
1030                 return r;
1031         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1032         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1033         if (r) {
1034                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1035                 return r;
1036         }
1037         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1038                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1039         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1040                                 adev->mc.gtt_size >> PAGE_SHIFT);
1041         if (r) {
1042                 DRM_ERROR("Failed initializing GTT heap.\n");
1043                 return r;
1044         }
1045         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1046                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1047
1048         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1049         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1050         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1051         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1052         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1053         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1054         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1055         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1056         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1057         /* GDS Memory */
1058         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1059                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1060         if (r) {
1061                 DRM_ERROR("Failed initializing GDS heap.\n");
1062                 return r;
1063         }
1064
1065         /* GWS */
1066         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1067                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1068         if (r) {
1069                 DRM_ERROR("Failed initializing gws heap.\n");
1070                 return r;
1071         }
1072
1073         /* OA */
1074         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1075                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1076         if (r) {
1077                 DRM_ERROR("Failed initializing oa heap.\n");
1078                 return r;
1079         }
1080
1081         r = amdgpu_ttm_debugfs_init(adev);
1082         if (r) {
1083                 DRM_ERROR("Failed to init debugfs\n");
1084                 return r;
1085         }
1086         return 0;
1087 }
1088
1089 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1090 {
1091         int r;
1092
1093         if (!adev->mman.initialized)
1094                 return;
1095         amdgpu_ttm_debugfs_fini(adev);
1096         if (adev->stollen_vga_memory) {
1097                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1098                 if (r == 0) {
1099                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1100                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1101                 }
1102                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1103         }
1104         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1105         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1106         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1107         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1108         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1109         ttm_bo_device_release(&adev->mman.bdev);
1110         amdgpu_gart_fini(adev);
1111         amdgpu_ttm_global_fini(adev);
1112         adev->mman.initialized = false;
1113         DRM_INFO("amdgpu: ttm finalized\n");
1114 }
1115
1116 /* this should only be called at bootup or when userspace
1117  * isn't running */
1118 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1119 {
1120         struct ttm_mem_type_manager *man;
1121
1122         if (!adev->mman.initialized)
1123                 return;
1124
1125         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1126         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1127         man->size = size >> PAGE_SHIFT;
1128 }
1129
1130 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1131 {
1132         struct drm_file *file_priv;
1133         struct amdgpu_device *adev;
1134
1135         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1136                 return -EINVAL;
1137
1138         file_priv = filp->private_data;
1139         adev = file_priv->minor->dev->dev_private;
1140         if (adev == NULL)
1141                 return -EINVAL;
1142
1143         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1144 }
1145
1146 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1147                        uint64_t src_offset,
1148                        uint64_t dst_offset,
1149                        uint32_t byte_count,
1150                        struct reservation_object *resv,
1151                        struct fence **fence)
1152 {
1153         struct amdgpu_device *adev = ring->adev;
1154         struct amdgpu_job *job;
1155
1156         uint32_t max_bytes;
1157         unsigned num_loops, num_dw;
1158         unsigned i;
1159         int r;
1160
1161         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1162         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1163         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1164
1165         /* for IB padding */
1166         while (num_dw & 0x7)
1167                 num_dw++;
1168
1169         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1170         if (r)
1171                 return r;
1172
1173         if (resv) {
1174                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1175                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1176                 if (r) {
1177                         DRM_ERROR("sync failed (%d).\n", r);
1178                         goto error_free;
1179                 }
1180         }
1181
1182         for (i = 0; i < num_loops; i++) {
1183                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1184
1185                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1186                                         dst_offset, cur_size_in_bytes);
1187
1188                 src_offset += cur_size_in_bytes;
1189                 dst_offset += cur_size_in_bytes;
1190                 byte_count -= cur_size_in_bytes;
1191         }
1192
1193         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1194         WARN_ON(job->ibs[0].length_dw > num_dw);
1195         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1196                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1197         if (r)
1198                 goto error_free;
1199
1200         return 0;
1201
1202 error_free:
1203         amdgpu_job_free(job);
1204         return r;
1205 }
1206
1207 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1208                 uint32_t src_data,
1209                 struct reservation_object *resv,
1210                 struct fence **fence)
1211 {
1212         struct amdgpu_device *adev = bo->adev;
1213         struct amdgpu_job *job;
1214         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1215
1216         uint32_t max_bytes, byte_count;
1217         uint64_t dst_offset;
1218         unsigned int num_loops, num_dw;
1219         unsigned int i;
1220         int r;
1221
1222         byte_count = bo->tbo.num_pages << PAGE_SHIFT;
1223         max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1224         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1225         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1226
1227         /* for IB padding */
1228         while (num_dw & 0x7)
1229                 num_dw++;
1230
1231         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1232         if (r)
1233                 return r;
1234
1235         if (resv) {
1236                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1237                                 AMDGPU_FENCE_OWNER_UNDEFINED);
1238                 if (r) {
1239                         DRM_ERROR("sync failed (%d).\n", r);
1240                         goto error_free;
1241                 }
1242         }
1243
1244         dst_offset = bo->tbo.mem.start << PAGE_SHIFT;
1245         for (i = 0; i < num_loops; i++) {
1246                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1247
1248                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1249                                 dst_offset, cur_size_in_bytes);
1250
1251                 dst_offset += cur_size_in_bytes;
1252                 byte_count -= cur_size_in_bytes;
1253         }
1254
1255         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1256         WARN_ON(job->ibs[0].length_dw > num_dw);
1257         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1258                         AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1259         if (r)
1260                 goto error_free;
1261
1262         return 0;
1263
1264 error_free:
1265         amdgpu_job_free(job);
1266         return r;
1267 }
1268
1269 #if defined(CONFIG_DEBUG_FS)
1270
1271 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1272 {
1273         struct drm_info_node *node = (struct drm_info_node *)m->private;
1274         unsigned ttm_pl = *(int *)node->info_ent->data;
1275         struct drm_device *dev = node->minor->dev;
1276         struct amdgpu_device *adev = dev->dev_private;
1277         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1278         int ret;
1279         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1280
1281         spin_lock(&glob->lru_lock);
1282         ret = drm_mm_dump_table(m, mm);
1283         spin_unlock(&glob->lru_lock);
1284         if (ttm_pl == TTM_PL_VRAM)
1285                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1286                            adev->mman.bdev.man[ttm_pl].size,
1287                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1288                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1289         return ret;
1290 }
1291
1292 static int ttm_pl_vram = TTM_PL_VRAM;
1293 static int ttm_pl_tt = TTM_PL_TT;
1294
1295 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1296         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1297         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1298         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1299 #ifdef CONFIG_SWIOTLB
1300         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1301 #endif
1302 };
1303
1304 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1305                                     size_t size, loff_t *pos)
1306 {
1307         struct amdgpu_device *adev = f->f_inode->i_private;
1308         ssize_t result = 0;
1309         int r;
1310
1311         if (size & 0x3 || *pos & 0x3)
1312                 return -EINVAL;
1313
1314         while (size) {
1315                 unsigned long flags;
1316                 uint32_t value;
1317
1318                 if (*pos >= adev->mc.mc_vram_size)
1319                         return result;
1320
1321                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1322                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1323                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1324                 value = RREG32(mmMM_DATA);
1325                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1326
1327                 r = put_user(value, (uint32_t *)buf);
1328                 if (r)
1329                         return r;
1330
1331                 result += 4;
1332                 buf += 4;
1333                 *pos += 4;
1334                 size -= 4;
1335         }
1336
1337         return result;
1338 }
1339
1340 static const struct file_operations amdgpu_ttm_vram_fops = {
1341         .owner = THIS_MODULE,
1342         .read = amdgpu_ttm_vram_read,
1343         .llseek = default_llseek
1344 };
1345
1346 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1347
1348 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1349                                    size_t size, loff_t *pos)
1350 {
1351         struct amdgpu_device *adev = f->f_inode->i_private;
1352         ssize_t result = 0;
1353         int r;
1354
1355         while (size) {
1356                 loff_t p = *pos / PAGE_SIZE;
1357                 unsigned off = *pos & ~PAGE_MASK;
1358                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1359                 struct page *page;
1360                 void *ptr;
1361
1362                 if (p >= adev->gart.num_cpu_pages)
1363                         return result;
1364
1365                 page = adev->gart.pages[p];
1366                 if (page) {
1367                         ptr = kmap(page);
1368                         ptr += off;
1369
1370                         r = copy_to_user(buf, ptr, cur_size);
1371                         kunmap(adev->gart.pages[p]);
1372                 } else
1373                         r = clear_user(buf, cur_size);
1374
1375                 if (r)
1376                         return -EFAULT;
1377
1378                 result += cur_size;
1379                 buf += cur_size;
1380                 *pos += cur_size;
1381                 size -= cur_size;
1382         }
1383
1384         return result;
1385 }
1386
1387 static const struct file_operations amdgpu_ttm_gtt_fops = {
1388         .owner = THIS_MODULE,
1389         .read = amdgpu_ttm_gtt_read,
1390         .llseek = default_llseek
1391 };
1392
1393 #endif
1394
1395 #endif
1396
1397 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1398 {
1399 #if defined(CONFIG_DEBUG_FS)
1400         unsigned count;
1401
1402         struct drm_minor *minor = adev->ddev->primary;
1403         struct dentry *ent, *root = minor->debugfs_root;
1404
1405         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1406                                   adev, &amdgpu_ttm_vram_fops);
1407         if (IS_ERR(ent))
1408                 return PTR_ERR(ent);
1409         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1410         adev->mman.vram = ent;
1411
1412 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1413         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1414                                   adev, &amdgpu_ttm_gtt_fops);
1415         if (IS_ERR(ent))
1416                 return PTR_ERR(ent);
1417         i_size_write(ent->d_inode, adev->mc.gtt_size);
1418         adev->mman.gtt = ent;
1419
1420 #endif
1421         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1422
1423 #ifdef CONFIG_SWIOTLB
1424         if (!swiotlb_nr_tbl())
1425                 --count;
1426 #endif
1427
1428         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1429 #else
1430
1431         return 0;
1432 #endif
1433 }
1434
1435 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1436 {
1437 #if defined(CONFIG_DEBUG_FS)
1438
1439         debugfs_remove(adev->mman.vram);
1440         adev->mman.vram = NULL;
1441
1442 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1443         debugfs_remove(adev->mman.gtt);
1444         adev->mman.gtt = NULL;
1445 #endif
1446
1447 #endif
1448 }
1449
1450 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1451 {
1452         return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1453 }