drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "radeon/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "radeon/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_vce.bin"
  54 #define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
  55
  56 #ifdef CONFIG_DRM_AMDGPU_CIK
  57 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  58 MODULE_FIRMWARE(FIRMWARE_KABINI);
  59 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  60 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  61 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  62 #endif
  63 MODULE_FIRMWARE(FIRMWARE_TONGA);
  64 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  65 MODULE_FIRMWARE(FIRMWARE_FIJI);
  66 MODULE_FIRMWARE(FIRMWARE_STONEY);
  67 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
  68 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
  69
  70 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  71
  72 /**
  73  * amdgpu_vce_init - allocate memory, load vce firmware
  74  *
  75  * @adev: amdgpu_device pointer
  76  *
  77  * First step to get VCE online, allocate memory and load the firmware
  78  */
  79 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  80 {
  81         struct amdgpu_ring *ring;
  82         struct amd_sched_rq *rq;
  83         const char *fw_name;
  84         const struct common_firmware_header *hdr;
  85         unsigned ucode_version, version_major, version_minor, binary_id;
  86         int i, r;
  87
  88         switch (adev->asic_type) {
  89 #ifdef CONFIG_DRM_AMDGPU_CIK
  90         case CHIP_BONAIRE:
  91                 fw_name = FIRMWARE_BONAIRE;
  92                 break;
  93         case CHIP_KAVERI:
  94                 fw_name = FIRMWARE_KAVERI;
  95                 break;
  96         case CHIP_KABINI:
  97                 fw_name = FIRMWARE_KABINI;
  98                 break;
  99         case CHIP_HAWAII:
 100                 fw_name = FIRMWARE_HAWAII;
 101                 break;
 102         case CHIP_MULLINS:
 103                 fw_name = FIRMWARE_MULLINS;
 104                 break;
 105 #endif
 106         case CHIP_TONGA:
 107                 fw_name = FIRMWARE_TONGA;
 108                 break;
 109         case CHIP_CARRIZO:
 110                 fw_name = FIRMWARE_CARRIZO;
 111                 break;
 112         case CHIP_FIJI:
 113                 fw_name = FIRMWARE_FIJI;
 114                 break;
 115         case CHIP_STONEY:
 116                 fw_name = FIRMWARE_STONEY;
 117                 break;
 118         case CHIP_POLARIS10:
 119                 fw_name = FIRMWARE_POLARIS10;
 120                 break;
 121         case CHIP_POLARIS11:
 122                 fw_name = FIRMWARE_POLARIS11;
 123                 break;
 124
 125         default:
 126                 return -EINVAL;
 127         }
 128
 129         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 130         if (r) {
 131                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 132                         fw_name);
 133                 return r;
 134         }
 135
 136         r = amdgpu_ucode_validate(adev->vce.fw);
 137         if (r) {
 138                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 139                         fw_name);
 140                 release_firmware(adev->vce.fw);
 141                 adev->vce.fw = NULL;
 142                 return r;
 143         }
 144
 145         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 146
 147         ucode_version = le32_to_cpu(hdr->ucode_version);
 148         version_major = (ucode_version >> 20) & 0xfff;
 149         version_minor = (ucode_version >> 8) & 0xfff;
 150         binary_id = ucode_version & 0xff;
 151         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 152                 version_major, version_minor, binary_id);
 153         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 154                                 (binary_id << 8));
 155
 156         /* allocate firmware, stack and heap BO */
 157
 158         r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
 159                              AMDGPU_GEM_DOMAIN_VRAM,
 160                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 161                              NULL, NULL, &adev->vce.vcpu_bo);
 162         if (r) {
 163                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 164                 return r;
 165         }
 166
 167         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 168         if (r) {
 169                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 170                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 171                 return r;
 172         }
 173
 174         r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 175                           &adev->vce.gpu_addr);
 176         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 177         if (r) {
 178                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 179                 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
 180                 return r;
 181         }
 182
 183
 184         ring = &adev->vce.ring[0];
 185         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 186         r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
 187                                   rq, amdgpu_sched_jobs);
 188         if (r != 0) {
 189                 DRM_ERROR("Failed setting up VCE run queue.\n");
 190                 return r;
 191         }
 192
 193         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 194                 atomic_set(&adev->vce.handles[i], 0);
 195                 adev->vce.filp[i] = NULL;
 196         }
 197
 198         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
 199         mutex_init(&adev->vce.idle_mutex);
 200
 201         return 0;
 202 }
 203
 204 /**
 205  * amdgpu_vce_fini - free memory
 206  *
 207  * @adev: amdgpu_device pointer
 208  *
 209  * Last step on VCE teardown, free firmware memory
 210  */
 211 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 212 {
 213         if (adev->vce.vcpu_bo == NULL)
 214                 return 0;
 215
 216         amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
 217
 218         amdgpu_bo_unref(&adev->vce.vcpu_bo);
 219
 220         amdgpu_ring_fini(&adev->vce.ring[0]);
 221         amdgpu_ring_fini(&adev->vce.ring[1]);
 222
 223         release_firmware(adev->vce.fw);
 224         mutex_destroy(&adev->vce.idle_mutex);
 225
 226         return 0;
 227 }
 228
 229 /**
 230  * amdgpu_vce_suspend - unpin VCE fw memory
 231  *
 232  * @adev: amdgpu_device pointer
 233  *
 234  */
 235 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 236 {
 237         int i;
 238
 239         if (adev->vce.vcpu_bo == NULL)
 240                 return 0;
 241
 242         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 243                 if (atomic_read(&adev->vce.handles[i]))
 244                         break;
 245
 246         if (i == AMDGPU_MAX_VCE_HANDLES)
 247                 return 0;
 248
 249         cancel_delayed_work_sync(&adev->vce.idle_work);
 250         /* TODO: suspending running encoding sessions isn't supported */
 251         return -EINVAL;
 252 }
 253
 254 /**
 255  * amdgpu_vce_resume - pin VCE fw memory
 256  *
 257  * @adev: amdgpu_device pointer
 258  *
 259  */
 260 int amdgpu_vce_resume(struct amdgpu_device *adev)
 261 {
 262         void *cpu_addr;
 263         const struct common_firmware_header *hdr;
 264         unsigned offset;
 265         int r;
 266
 267         if (adev->vce.vcpu_bo == NULL)
 268                 return -EINVAL;
 269
 270         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 271         if (r) {
 272                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 273                 return r;
 274         }
 275
 276         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 277         if (r) {
 278                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 279                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 280                 return r;
 281         }
 282
 283         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 284         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 285         memcpy_toio(cpu_addr, adev->vce.fw->data + offset,
 286                     adev->vce.fw->size - offset);
 287
 288         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 289
 290         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 291
 292         return 0;
 293 }
 294
 295 /**
 296  * amdgpu_vce_idle_work_handler - power off VCE
 297  *
 298  * @work: pointer to work structure
 299  *
 300  * power of VCE when it's not used any more
 301  */
 302 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 303 {
 304         struct amdgpu_device *adev =
 305                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 306         unsigned i, count = 0;
 307
 308         for (i = 0; i < adev->vce.num_rings; i++)
 309                 count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 310
 311         if (count == 0) {
 312                 if (adev->pm.dpm_enabled) {
 313                         amdgpu_dpm_enable_vce(adev, false);
 314                 } else {
 315                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 316                 }
 317         } else {
 318                 schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 319         }
 320 }
 321
 322 /**
 323  * amdgpu_vce_ring_begin_use - power up VCE
 324  *
 325  * @ring: amdgpu ring
 326  *
 327  * Make sure VCE is powerd up when we want to use it
 328  */
 329 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
 330 {
 331         struct amdgpu_device *adev = ring->adev;
 332         bool set_clocks;
 333
 334         mutex_lock(&adev->vce.idle_mutex);
 335         set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 336         if (set_clocks) {
 337                 if (adev->pm.dpm_enabled) {
 338                         amdgpu_dpm_enable_vce(adev, true);
 339                 } else {
 340                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 341                 }
 342         }
 343         mutex_unlock(&adev->vce.idle_mutex);
 344 }
 345
 346 /**
 347  * amdgpu_vce_ring_end_use - power VCE down
 348  *
 349  * @ring: amdgpu ring
 350  *
 351  * Schedule work to power VCE down again
 352  */
 353 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring)
 354 {
 355         schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);
 356 }
 357
 358 /**
 359  * amdgpu_vce_free_handles - free still open VCE handles
 360  *
 361  * @adev: amdgpu_device pointer
 362  * @filp: drm file pointer
 363  *
 364  * Close all VCE handles still open by this file pointer
 365  */
 366 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 367 {
 368         struct amdgpu_ring *ring = &adev->vce.ring[0];
 369         int i, r;
 370         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 371                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 372
 373                 if (!handle || adev->vce.filp[i] != filp)
 374                         continue;
 375
 376                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 377                 if (r)
 378                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 379
 380                 adev->vce.filp[i] = NULL;
 381                 atomic_set(&adev->vce.handles[i], 0);
 382         }
 383 }
 384
 385 /**
 386  * amdgpu_vce_get_create_msg - generate a VCE create msg
 387  *
 388  * @adev: amdgpu_device pointer
 389  * @ring: ring we should submit the msg to
 390  * @handle: VCE session handle to use
 391  * @fence: optional fence to return
 392  *
 393  * Open up a stream for HW test
 394  */
 395 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 396                               struct fence **fence)
 397 {
 398         const unsigned ib_size_dw = 1024;
 399         struct amdgpu_job *job;
 400         struct amdgpu_ib *ib;
 401         struct fence *f = NULL;
 402         uint64_t dummy;
 403         int i, r;
 404
 405         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 406         if (r)
 407                 return r;
 408
 409         ib = &job->ibs[0];
 410
 411         dummy = ib->gpu_addr + 1024;
 412
 413         /* stitch together an VCE create msg */
 414         ib->length_dw = 0;
 415         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 416         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 417         ib->ptr[ib->length_dw++] = handle;
 418
 419         if ((ring->adev->vce.fw_version >> 24) >= 52)
 420                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 421         else
 422                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 423         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 424         ib->ptr[ib->length_dw++] = 0x00000000;
 425         ib->ptr[ib->length_dw++] = 0x00000042;
 426         ib->ptr[ib->length_dw++] = 0x0000000a;
 427         ib->ptr[ib->length_dw++] = 0x00000001;
 428         ib->ptr[ib->length_dw++] = 0x00000080;
 429         ib->ptr[ib->length_dw++] = 0x00000060;
 430         ib->ptr[ib->length_dw++] = 0x00000100;
 431         ib->ptr[ib->length_dw++] = 0x00000100;
 432         ib->ptr[ib->length_dw++] = 0x0000000c;
 433         ib->ptr[ib->length_dw++] = 0x00000000;
 434         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 435                 ib->ptr[ib->length_dw++] = 0x00000000;
 436                 ib->ptr[ib->length_dw++] = 0x00000000;
 437                 ib->ptr[ib->length_dw++] = 0x00000000;
 438                 ib->ptr[ib->length_dw++] = 0x00000000;
 439         }
 440
 441         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 442         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 443         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 444         ib->ptr[ib->length_dw++] = dummy;
 445         ib->ptr[ib->length_dw++] = 0x00000001;
 446
 447         for (i = ib->length_dw; i < ib_size_dw; ++i)
 448                 ib->ptr[i] = 0x0;
 449
 450         r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
 451         job->fence = fence_get(f);
 452         if (r)
 453                 goto err;
 454
 455         amdgpu_job_free(job);
 456         if (fence)
 457                 *fence = fence_get(f);
 458         fence_put(f);
 459         return 0;
 460
 461 err:
 462         amdgpu_job_free(job);
 463         return r;
 464 }
 465
 466 /**
 467  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 468  *
 469  * @adev: amdgpu_device pointer
 470  * @ring: ring we should submit the msg to
 471  * @handle: VCE session handle to use
 472  * @fence: optional fence to return
 473  *
 474  * Close up a stream for HW test or if userspace failed to do so
 475  */
 476 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 477                                bool direct, struct fence **fence)
 478 {
 479         const unsigned ib_size_dw = 1024;
 480         struct amdgpu_job *job;
 481         struct amdgpu_ib *ib;
 482         struct fence *f = NULL;
 483         int i, r;
 484
 485         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 486         if (r)
 487                 return r;
 488
 489         ib = &job->ibs[0];
 490
 491         /* stitch together an VCE destroy msg */
 492         ib->length_dw = 0;
 493         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 494         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 495         ib->ptr[ib->length_dw++] = handle;
 496
 497         ib->ptr[ib->length_dw++] = 0x00000020; /* len */
 498         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 499         ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
 500         ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
 501         ib->ptr[ib->length_dw++] = 0x00000000;
 502         ib->ptr[ib->length_dw++] = 0x00000000;
 503         ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
 504         ib->ptr[ib->length_dw++] = 0x00000000;
 505
 506         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 507         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 508
 509         for (i = ib->length_dw; i < ib_size_dw; ++i)
 510                 ib->ptr[i] = 0x0;
 511
 512         if (direct) {
 513                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
 514                 job->fence = fence_get(f);
 515                 if (r)
 516                         goto err;
 517
 518                 amdgpu_job_free(job);
 519         } else {
 520                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 521                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 522                 if (r)
 523                         goto err;
 524         }
 525
 526         if (fence)
 527                 *fence = fence_get(f);
 528         fence_put(f);
 529         return 0;
 530
 531 err:
 532         amdgpu_job_free(job);
 533         return r;
 534 }
 535
 536 /**
 537  * amdgpu_vce_cs_reloc - command submission relocation
 538  *
 539  * @p: parser context
 540  * @lo: address of lower dword
 541  * @hi: address of higher dword
 542  * @size: minimum size
 543  *
 544  * Patch relocation inside command stream with real buffer address
 545  */
 546 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 547                                int lo, int hi, unsigned size, uint32_t index)
 548 {
 549         struct amdgpu_bo_va_mapping *mapping;
 550         struct amdgpu_bo *bo;
 551         uint64_t addr;
 552
 553         if (index == 0xffffffff)
 554                 index = 0;
 555
 556         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 557                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 558         addr += ((uint64_t)size) * ((uint64_t)index);
 559
 560         mapping = amdgpu_cs_find_mapping(p, addr, &bo);
 561         if (mapping == NULL) {
 562                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 563                           addr, lo, hi, size, index);
 564                 return -EINVAL;
 565         }
 566
 567         if ((addr + (uint64_t)size) >
 568             ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 569                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 570                           addr, lo, hi);
 571                 return -EINVAL;
 572         }
 573
 574         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 575         addr += amdgpu_bo_gpu_offset(bo);
 576         addr -= ((uint64_t)size) * ((uint64_t)index);
 577
 578         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 579         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 580
 581         return 0;
 582 }
 583
 584 /**
 585  * amdgpu_vce_validate_handle - validate stream handle
 586  *
 587  * @p: parser context
 588  * @handle: handle to validate
 589  * @allocated: allocated a new handle?
 590  *
 591  * Validates the handle and return the found session index or -EINVAL
 592  * we we don't have another free session index.
 593  */
 594 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 595                                       uint32_t handle, uint32_t *allocated)
 596 {
 597         unsigned i;
 598
 599         /* validate the handle */
 600         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 601                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 602                         if (p->adev->vce.filp[i] != p->filp) {
 603                                 DRM_ERROR("VCE handle collision detected!\n");
 604                                 return -EINVAL;
 605                         }
 606                         return i;
 607                 }
 608         }
 609
 610         /* handle not found try to alloc a new one */
 611         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 612                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 613                         p->adev->vce.filp[i] = p->filp;
 614                         p->adev->vce.img_size[i] = 0;
 615                         *allocated |= 1 << i;
 616                         return i;
 617                 }
 618         }
 619
 620         DRM_ERROR("No more free VCE handles!\n");
 621         return -EINVAL;
 622 }
 623
 624 /**
 625  * amdgpu_vce_cs_parse - parse and validate the command stream
 626  *
 627  * @p: parser context
 628  *
 629  */
 630 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 631 {
 632         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 633         unsigned fb_idx = 0, bs_idx = 0;
 634         int session_idx = -1;
 635         uint32_t destroyed = 0;
 636         uint32_t created = 0;
 637         uint32_t allocated = 0;
 638         uint32_t tmp, handle = 0;
 639         uint32_t *size = &tmp;
 640         int i, r, idx = 0;
 641
 642         r = amdgpu_cs_sysvm_access_required(p);
 643         if (r)
 644                 return r;
 645
 646         while (idx < ib->length_dw) {
 647                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 648                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 649
 650                 if ((len < 8) || (len & 3)) {
 651                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 652                         r = -EINVAL;
 653                         goto out;
 654                 }
 655
 656                 switch (cmd) {
 657                 case 0x00000001: /* session */
 658                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 659                         session_idx = amdgpu_vce_validate_handle(p, handle,
 660                                                                  &allocated);
 661                         if (session_idx < 0) {
 662                                 r = session_idx;
 663                                 goto out;
 664                         }
 665                         size = &p->adev->vce.img_size[session_idx];
 666                         break;
 667
 668                 case 0x00000002: /* task info */
 669                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 670                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 671                         break;
 672
 673                 case 0x01000001: /* create */
 674                         created |= 1 << session_idx;
 675                         if (destroyed & (1 << session_idx)) {
 676                                 destroyed &= ~(1 << session_idx);
 677                                 allocated |= 1 << session_idx;
 678
 679                         } else if (!(allocated & (1 << session_idx))) {
 680                                 DRM_ERROR("Handle already in use!\n");
 681                                 r = -EINVAL;
 682                                 goto out;
 683                         }
 684
 685                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 686                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 687                                 8 * 3 / 2;
 688                         break;
 689
 690                 case 0x04000001: /* config extension */
 691                 case 0x04000002: /* pic control */
 692                 case 0x04000005: /* rate control */
 693                 case 0x04000007: /* motion estimation */
 694                 case 0x04000008: /* rdo */
 695                 case 0x04000009: /* vui */
 696                 case 0x05000002: /* auxiliary buffer */
 697                 case 0x05000009: /* clock table */
 698                         break;
 699
 700                 case 0x03000001: /* encode */
 701                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 702                                                 *size, 0);
 703                         if (r)
 704                                 goto out;
 705
 706                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 707                                                 *size / 3, 0);
 708                         if (r)
 709                                 goto out;
 710                         break;
 711
 712                 case 0x02000001: /* destroy */
 713                         destroyed |= 1 << session_idx;
 714                         break;
 715
 716                 case 0x05000001: /* context buffer */
 717                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 718                                                 *size * 2, 0);
 719                         if (r)
 720                                 goto out;
 721                         break;
 722
 723                 case 0x05000004: /* video bitstream buffer */
 724                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 725                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 726                                                 tmp, bs_idx);
 727                         if (r)
 728                                 goto out;
 729                         break;
 730
 731                 case 0x05000005: /* feedback buffer */
 732                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 733                                                 4096, fb_idx);
 734                         if (r)
 735                                 goto out;
 736                         break;
 737
 738                 default:
 739                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 740                         r = -EINVAL;
 741                         goto out;
 742                 }
 743
 744                 if (session_idx == -1) {
 745                         DRM_ERROR("no session command at start of IB\n");
 746                         r = -EINVAL;
 747                         goto out;
 748                 }
 749
 750                 idx += len / 4;
 751         }
 752
 753         if (allocated & ~created) {
 754                 DRM_ERROR("New session without create command!\n");
 755                 r = -ENOENT;
 756         }
 757
 758 out:
 759         if (!r) {
 760                 /* No error, free all destroyed handle slots */
 761                 tmp = destroyed;
 762         } else {
 763                 /* Error during parsing, free all allocated handle slots */
 764                 tmp = allocated;
 765         }
 766
 767         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 768                 if (tmp & (1 << i))
 769                         atomic_set(&p->adev->vce.handles[i], 0);
 770
 771         return r;
 772 }
 773
 774 /**
 775  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 776  *
 777  * @ring: engine to use
 778  * @ib: the IB to execute
 779  *
 780  */
 781 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
 782                              unsigned vm_id, bool ctx_switch)
 783 {
 784         amdgpu_ring_write(ring, VCE_CMD_IB);
 785         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 786         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 787         amdgpu_ring_write(ring, ib->length_dw);
 788 }
 789
 790 /**
 791  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
 792  *
 793  * @ring: engine to use
 794  * @fence: the fence
 795  *
 796  */
 797 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 798                                 unsigned flags)
 799 {
 800         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 801
 802         amdgpu_ring_write(ring, VCE_CMD_FENCE);
 803         amdgpu_ring_write(ring, addr);
 804         amdgpu_ring_write(ring, upper_32_bits(addr));
 805         amdgpu_ring_write(ring, seq);
 806         amdgpu_ring_write(ring, VCE_CMD_TRAP);
 807         amdgpu_ring_write(ring, VCE_CMD_END);
 808 }
 809
 810 unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 811 {
 812         return
 813                 4; /* amdgpu_vce_ring_emit_ib */
 814 }
 815
 816 unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 817 {
 818         return
 819                 6; /* amdgpu_vce_ring_emit_fence  x1 no user fence */
 820 }
 821
 822 /**
 823  * amdgpu_vce_ring_test_ring - test if VCE ring is working
 824  *
 825  * @ring: the engine to test on
 826  *
 827  */
 828 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
 829 {
 830         struct amdgpu_device *adev = ring->adev;
 831         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 832         unsigned i;
 833         int r;
 834
 835         r = amdgpu_ring_alloc(ring, 16);
 836         if (r) {
 837                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
 838                           ring->idx, r);
 839                 return r;
 840         }
 841         amdgpu_ring_write(ring, VCE_CMD_END);
 842         amdgpu_ring_commit(ring);
 843
 844         for (i = 0; i < adev->usec_timeout; i++) {
 845                 if (amdgpu_ring_get_rptr(ring) != rptr)
 846                         break;
 847                 DRM_UDELAY(1);
 848         }
 849
 850         if (i < adev->usec_timeout) {
 851                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 852                          ring->idx, i);
 853         } else {
 854                 DRM_ERROR("amdgpu: ring %d test failed\n",
 855                           ring->idx);
 856                 r = -ETIMEDOUT;
 857         }
 858
 859         return r;
 860 }
 861
 862 /**
 863  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
 864  *
 865  * @ring: the engine to test on
 866  *
 867  */
 868 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 869 {
 870         struct fence *fence = NULL;
 871         long r;
 872
 873         /* skip vce ring1/2 ib test for now, since it's not reliable */
 874         if (ring != &ring->adev->vce.ring[0])
 875                 return 0;
 876
 877         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
 878         if (r) {
 879                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 880                 goto error;
 881         }
 882
 883         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
 884         if (r) {
 885                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 886                 goto error;
 887         }
 888
 889         r = fence_wait_timeout(fence, false, timeout);
 890         if (r == 0) {
 891                 DRM_ERROR("amdgpu: IB test timed out.\n");
 892                 r = -ETIMEDOUT;
 893         } else if (r < 0) {
 894                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 895         } else {
 896                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 897                 r = 0;
 898         }
 899 error:
 900         fence_put(fence);
 901         return r;
 902 }