drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  * Authors: Christian König <christian.koenig@amd.com>
  26  */
  27
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_vce.h"
  36 #include "cikd.h"
  37
  38 /* 1 second timeout */
  39 #define VCE_IDLE_TIMEOUT_MS     1000
  40
  41 /* Firmware Names */
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #define FIRMWARE_BONAIRE        "radeon/bonaire_vce.bin"
  44 #define FIRMWARE_KABINI         "radeon/kabini_vce.bin"
  45 #define FIRMWARE_KAVERI         "radeon/kaveri_vce.bin"
  46 #define FIRMWARE_HAWAII         "radeon/hawaii_vce.bin"
  47 #define FIRMWARE_MULLINS        "radeon/mullins_vce.bin"
  48 #endif
  49 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
  50 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
  51 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
  52 #define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
  53
  54 #ifdef CONFIG_DRM_AMDGPU_CIK
  55 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  56 MODULE_FIRMWARE(FIRMWARE_KABINI);
  57 MODULE_FIRMWARE(FIRMWARE_KAVERI);
  58 MODULE_FIRMWARE(FIRMWARE_HAWAII);
  59 MODULE_FIRMWARE(FIRMWARE_MULLINS);
  60 #endif
  61 MODULE_FIRMWARE(FIRMWARE_TONGA);
  62 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
  63 MODULE_FIRMWARE(FIRMWARE_FIJI);
  64 MODULE_FIRMWARE(FIRMWARE_STONEY);
  65
  66 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
  67
  68 /**
  69  * amdgpu_vce_init - allocate memory, load vce firmware
  70  *
  71  * @adev: amdgpu_device pointer
  72  *
  73  * First step to get VCE online, allocate memory and load the firmware
  74  */
  75 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
  76 {
  77         struct amdgpu_ring *ring;
  78         struct amd_sched_rq *rq;
  79         const char *fw_name;
  80         const struct common_firmware_header *hdr;
  81         unsigned ucode_version, version_major, version_minor, binary_id;
  82         int i, r;
  83
  84         INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
  85
  86         switch (adev->asic_type) {
  87 #ifdef CONFIG_DRM_AMDGPU_CIK
  88         case CHIP_BONAIRE:
  89                 fw_name = FIRMWARE_BONAIRE;
  90                 break;
  91         case CHIP_KAVERI:
  92                 fw_name = FIRMWARE_KAVERI;
  93                 break;
  94         case CHIP_KABINI:
  95                 fw_name = FIRMWARE_KABINI;
  96                 break;
  97         case CHIP_HAWAII:
  98                 fw_name = FIRMWARE_HAWAII;
  99                 break;
 100         case CHIP_MULLINS:
 101                 fw_name = FIRMWARE_MULLINS;
 102                 break;
 103 #endif
 104         case CHIP_TONGA:
 105                 fw_name = FIRMWARE_TONGA;
 106                 break;
 107         case CHIP_CARRIZO:
 108                 fw_name = FIRMWARE_CARRIZO;
 109                 break;
 110         case CHIP_FIJI:
 111                 fw_name = FIRMWARE_FIJI;
 112                 break;
 113         case CHIP_STONEY:
 114                 fw_name = FIRMWARE_STONEY;
 115                 break;
 116
 117         default:
 118                 return -EINVAL;
 119         }
 120
 121         r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
 122         if (r) {
 123                 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
 124                         fw_name);
 125                 return r;
 126         }
 127
 128         r = amdgpu_ucode_validate(adev->vce.fw);
 129         if (r) {
 130                 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
 131                         fw_name);
 132                 release_firmware(adev->vce.fw);
 133                 adev->vce.fw = NULL;
 134                 return r;
 135         }
 136
 137         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 138
 139         ucode_version = le32_to_cpu(hdr->ucode_version);
 140         version_major = (ucode_version >> 20) & 0xfff;
 141         version_minor = (ucode_version >> 8) & 0xfff;
 142         binary_id = ucode_version & 0xff;
 143         DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
 144                 version_major, version_minor, binary_id);
 145         adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
 146                                 (binary_id << 8));
 147
 148         /* allocate firmware, stack and heap BO */
 149
 150         r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
 151                              AMDGPU_GEM_DOMAIN_VRAM,
 152                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 153                              NULL, NULL, &adev->vce.vcpu_bo);
 154         if (r) {
 155                 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 156                 return r;
 157         }
 158
 159         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 160         if (r) {
 161                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 162                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 163                 return r;
 164         }
 165
 166         r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
 167                           &adev->vce.gpu_addr);
 168         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 169         if (r) {
 170                 amdgpu_bo_unref(&adev->vce.vcpu_bo);
 171                 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
 172                 return r;
 173         }
 174
 175
 176         ring = &adev->vce.ring[0];
 177         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
 178         r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
 179                                   rq, amdgpu_sched_jobs);
 180         if (r != 0) {
 181                 DRM_ERROR("Failed setting up VCE run queue.\n");
 182                 return r;
 183         }
 184
 185         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 186                 atomic_set(&adev->vce.handles[i], 0);
 187                 adev->vce.filp[i] = NULL;
 188         }
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * amdgpu_vce_fini - free memory
 195  *
 196  * @adev: amdgpu_device pointer
 197  *
 198  * Last step on VCE teardown, free firmware memory
 199  */
 200 int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
 201 {
 202         if (adev->vce.vcpu_bo == NULL)
 203                 return 0;
 204
 205         amd_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
 206
 207         amdgpu_bo_unref(&adev->vce.vcpu_bo);
 208
 209         amdgpu_ring_fini(&adev->vce.ring[0]);
 210         amdgpu_ring_fini(&adev->vce.ring[1]);
 211
 212         release_firmware(adev->vce.fw);
 213
 214         return 0;
 215 }
 216
 217 /**
 218  * amdgpu_vce_suspend - unpin VCE fw memory
 219  *
 220  * @adev: amdgpu_device pointer
 221  *
 222  */
 223 int amdgpu_vce_suspend(struct amdgpu_device *adev)
 224 {
 225         int i;
 226
 227         if (adev->vce.vcpu_bo == NULL)
 228                 return 0;
 229
 230         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 231                 if (atomic_read(&adev->vce.handles[i]))
 232                         break;
 233
 234         if (i == AMDGPU_MAX_VCE_HANDLES)
 235                 return 0;
 236
 237         cancel_delayed_work_sync(&adev->vce.idle_work);
 238         /* TODO: suspending running encoding sessions isn't supported */
 239         return -EINVAL;
 240 }
 241
 242 /**
 243  * amdgpu_vce_resume - pin VCE fw memory
 244  *
 245  * @adev: amdgpu_device pointer
 246  *
 247  */
 248 int amdgpu_vce_resume(struct amdgpu_device *adev)
 249 {
 250         void *cpu_addr;
 251         const struct common_firmware_header *hdr;
 252         unsigned offset;
 253         int r;
 254
 255         if (adev->vce.vcpu_bo == NULL)
 256                 return -EINVAL;
 257
 258         r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
 259         if (r) {
 260                 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
 261                 return r;
 262         }
 263
 264         r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
 265         if (r) {
 266                 amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 267                 dev_err(adev->dev, "(%d) VCE map failed\n", r);
 268                 return r;
 269         }
 270
 271         hdr = (const struct common_firmware_header *)adev->vce.fw->data;
 272         offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 273         memcpy(cpu_addr, (adev->vce.fw->data) + offset,
 274                 (adev->vce.fw->size) - offset);
 275
 276         amdgpu_bo_kunmap(adev->vce.vcpu_bo);
 277
 278         amdgpu_bo_unreserve(adev->vce.vcpu_bo);
 279
 280         return 0;
 281 }
 282
 283 /**
 284  * amdgpu_vce_idle_work_handler - power off VCE
 285  *
 286  * @work: pointer to work structure
 287  *
 288  * power of VCE when it's not used any more
 289  */
 290 static void amdgpu_vce_idle_work_handler(struct work_struct *work)
 291 {
 292         struct amdgpu_device *adev =
 293                 container_of(work, struct amdgpu_device, vce.idle_work.work);
 294
 295         if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
 296             (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
 297                 if (adev->pm.dpm_enabled) {
 298                         amdgpu_dpm_enable_vce(adev, false);
 299                 } else {
 300                         amdgpu_asic_set_vce_clocks(adev, 0, 0);
 301                 }
 302         } else {
 303                 schedule_delayed_work(&adev->vce.idle_work,
 304                                       msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
 305         }
 306 }
 307
 308 /**
 309  * amdgpu_vce_note_usage - power up VCE
 310  *
 311  * @adev: amdgpu_device pointer
 312  *
 313  * Make sure VCE is powerd up when we want to use it
 314  */
 315 static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
 316 {
 317         bool streams_changed = false;
 318         bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
 319         set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
 320                                             msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
 321
 322         if (adev->pm.dpm_enabled) {
 323                 /* XXX figure out if the streams changed */
 324                 streams_changed = false;
 325         }
 326
 327         if (set_clocks || streams_changed) {
 328                 if (adev->pm.dpm_enabled) {
 329                         amdgpu_dpm_enable_vce(adev, true);
 330                 } else {
 331                         amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
 332                 }
 333         }
 334 }
 335
 336 /**
 337  * amdgpu_vce_free_handles - free still open VCE handles
 338  *
 339  * @adev: amdgpu_device pointer
 340  * @filp: drm file pointer
 341  *
 342  * Close all VCE handles still open by this file pointer
 343  */
 344 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 345 {
 346         struct amdgpu_ring *ring = &adev->vce.ring[0];
 347         int i, r;
 348         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 349                 uint32_t handle = atomic_read(&adev->vce.handles[i]);
 350                 if (!handle || adev->vce.filp[i] != filp)
 351                         continue;
 352
 353                 amdgpu_vce_note_usage(adev);
 354
 355                 r = amdgpu_vce_get_destroy_msg(ring, handle, false, NULL);
 356                 if (r)
 357                         DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
 358
 359                 adev->vce.filp[i] = NULL;
 360                 atomic_set(&adev->vce.handles[i], 0);
 361         }
 362 }
 363
 364 /**
 365  * amdgpu_vce_get_create_msg - generate a VCE create msg
 366  *
 367  * @adev: amdgpu_device pointer
 368  * @ring: ring we should submit the msg to
 369  * @handle: VCE session handle to use
 370  * @fence: optional fence to return
 371  *
 372  * Open up a stream for HW test
 373  */
 374 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 375                               struct fence **fence)
 376 {
 377         const unsigned ib_size_dw = 1024;
 378         struct amdgpu_job *job;
 379         struct amdgpu_ib *ib;
 380         struct fence *f = NULL;
 381         uint64_t dummy;
 382         int i, r;
 383
 384         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 385         if (r)
 386                 return r;
 387
 388         ib = &job->ibs[0];
 389
 390         dummy = ib->gpu_addr + 1024;
 391
 392         /* stitch together an VCE create msg */
 393         ib->length_dw = 0;
 394         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 395         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 396         ib->ptr[ib->length_dw++] = handle;
 397
 398         if ((ring->adev->vce.fw_version >> 24) >= 52)
 399                 ib->ptr[ib->length_dw++] = 0x00000040; /* len */
 400         else
 401                 ib->ptr[ib->length_dw++] = 0x00000030; /* len */
 402         ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
 403         ib->ptr[ib->length_dw++] = 0x00000000;
 404         ib->ptr[ib->length_dw++] = 0x00000042;
 405         ib->ptr[ib->length_dw++] = 0x0000000a;
 406         ib->ptr[ib->length_dw++] = 0x00000001;
 407         ib->ptr[ib->length_dw++] = 0x00000080;
 408         ib->ptr[ib->length_dw++] = 0x00000060;
 409         ib->ptr[ib->length_dw++] = 0x00000100;
 410         ib->ptr[ib->length_dw++] = 0x00000100;
 411         ib->ptr[ib->length_dw++] = 0x0000000c;
 412         ib->ptr[ib->length_dw++] = 0x00000000;
 413         if ((ring->adev->vce.fw_version >> 24) >= 52) {
 414                 ib->ptr[ib->length_dw++] = 0x00000000;
 415                 ib->ptr[ib->length_dw++] = 0x00000000;
 416                 ib->ptr[ib->length_dw++] = 0x00000000;
 417                 ib->ptr[ib->length_dw++] = 0x00000000;
 418         }
 419
 420         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 421         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 422         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 423         ib->ptr[ib->length_dw++] = dummy;
 424         ib->ptr[ib->length_dw++] = 0x00000001;
 425
 426         for (i = ib->length_dw; i < ib_size_dw; ++i)
 427                 ib->ptr[i] = 0x0;
 428
 429         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 430         job->fence = f;
 431         if (r)
 432                 goto err;
 433
 434         amdgpu_job_free(job);
 435         if (fence)
 436                 *fence = fence_get(f);
 437         fence_put(f);
 438         return 0;
 439
 440 err:
 441         amdgpu_job_free(job);
 442         return r;
 443 }
 444
 445 /**
 446  * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
 447  *
 448  * @adev: amdgpu_device pointer
 449  * @ring: ring we should submit the msg to
 450  * @handle: VCE session handle to use
 451  * @fence: optional fence to return
 452  *
 453  * Close up a stream for HW test or if userspace failed to do so
 454  */
 455 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 456                                bool direct, struct fence **fence)
 457 {
 458         const unsigned ib_size_dw = 1024;
 459         struct amdgpu_job *job;
 460         struct amdgpu_ib *ib;
 461         struct fence *f = NULL;
 462         uint64_t dummy;
 463         int i, r;
 464
 465         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 466         if (r)
 467                 return r;
 468
 469         ib = &job->ibs[0];
 470         dummy = ib->gpu_addr + 1024;
 471
 472         /* stitch together an VCE destroy msg */
 473         ib->length_dw = 0;
 474         ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
 475         ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
 476         ib->ptr[ib->length_dw++] = handle;
 477
 478         ib->ptr[ib->length_dw++] = 0x00000014; /* len */
 479         ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
 480         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 481         ib->ptr[ib->length_dw++] = dummy;
 482         ib->ptr[ib->length_dw++] = 0x00000001;
 483
 484         ib->ptr[ib->length_dw++] = 0x00000008; /* len */
 485         ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
 486
 487         for (i = ib->length_dw; i < ib_size_dw; ++i)
 488                 ib->ptr[i] = 0x0;
 489
 490         if (direct) {
 491                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 492                 job->fence = f;
 493                 if (r)
 494                         goto err;
 495
 496                 amdgpu_job_free(job);
 497         } else {
 498                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 499                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 500                 if (r)
 501                         goto err;
 502         }
 503
 504         if (fence)
 505                 *fence = fence_get(f);
 506         fence_put(f);
 507         return 0;
 508
 509 err:
 510         amdgpu_job_free(job);
 511         return r;
 512 }
 513
 514 /**
 515  * amdgpu_vce_cs_reloc - command submission relocation
 516  *
 517  * @p: parser context
 518  * @lo: address of lower dword
 519  * @hi: address of higher dword
 520  * @size: minimum size
 521  *
 522  * Patch relocation inside command stream with real buffer address
 523  */
 524 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
 525                                int lo, int hi, unsigned size, uint32_t index)
 526 {
 527         struct amdgpu_bo_va_mapping *mapping;
 528         struct amdgpu_bo *bo;
 529         uint64_t addr;
 530
 531         if (index == 0xffffffff)
 532                 index = 0;
 533
 534         addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
 535                ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
 536         addr += ((uint64_t)size) * ((uint64_t)index);
 537
 538         mapping = amdgpu_cs_find_mapping(p, addr, &bo);
 539         if (mapping == NULL) {
 540                 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
 541                           addr, lo, hi, size, index);
 542                 return -EINVAL;
 543         }
 544
 545         if ((addr + (uint64_t)size) >
 546             ((uint64_t)mapping->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 547                 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
 548                           addr, lo, hi);
 549                 return -EINVAL;
 550         }
 551
 552         addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
 553         addr += amdgpu_bo_gpu_offset(bo);
 554         addr -= ((uint64_t)size) * ((uint64_t)index);
 555
 556         amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));
 557         amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));
 558
 559         return 0;
 560 }
 561
 562 /**
 563  * amdgpu_vce_validate_handle - validate stream handle
 564  *
 565  * @p: parser context
 566  * @handle: handle to validate
 567  * @allocated: allocated a new handle?
 568  *
 569  * Validates the handle and return the found session index or -EINVAL
 570  * we we don't have another free session index.
 571  */
 572 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser *p,
 573                                       uint32_t handle, bool *allocated)
 574 {
 575         unsigned i;
 576
 577         *allocated = false;
 578
 579         /* validate the handle */
 580         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 581                 if (atomic_read(&p->adev->vce.handles[i]) == handle) {
 582                         if (p->adev->vce.filp[i] != p->filp) {
 583                                 DRM_ERROR("VCE handle collision detected!\n");
 584                                 return -EINVAL;
 585                         }
 586                         return i;
 587                 }
 588         }
 589
 590         /* handle not found try to alloc a new one */
 591         for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
 592                 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
 593                         p->adev->vce.filp[i] = p->filp;
 594                         p->adev->vce.img_size[i] = 0;
 595                         *allocated = true;
 596                         return i;
 597                 }
 598         }
 599
 600         DRM_ERROR("No more free VCE handles!\n");
 601         return -EINVAL;
 602 }
 603
 604 /**
 605  * amdgpu_vce_cs_parse - parse and validate the command stream
 606  *
 607  * @p: parser context
 608  *
 609  */
 610 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
 611 {
 612         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
 613         unsigned fb_idx = 0, bs_idx = 0;
 614         int session_idx = -1;
 615         bool destroyed = false;
 616         bool created = false;
 617         bool allocated = false;
 618         uint32_t tmp, handle = 0;
 619         uint32_t *size = &tmp;
 620         int i, r = 0, idx = 0;
 621
 622         amdgpu_vce_note_usage(p->adev);
 623
 624         while (idx < ib->length_dw) {
 625                 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
 626                 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
 627
 628                 if ((len < 8) || (len & 3)) {
 629                         DRM_ERROR("invalid VCE command length (%d)!\n", len);
 630                         r = -EINVAL;
 631                         goto out;
 632                 }
 633
 634                 if (destroyed) {
 635                         DRM_ERROR("No other command allowed after destroy!\n");
 636                         r = -EINVAL;
 637                         goto out;
 638                 }
 639
 640                 switch (cmd) {
 641                 case 0x00000001: // session
 642                         handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
 643                         session_idx = amdgpu_vce_validate_handle(p, handle,
 644                                                                  &allocated);
 645                         if (session_idx < 0)
 646                                 return session_idx;
 647                         size = &p->adev->vce.img_size[session_idx];
 648                         break;
 649
 650                 case 0x00000002: // task info
 651                         fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
 652                         bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
 653                         break;
 654
 655                 case 0x01000001: // create
 656                         created = true;
 657                         if (!allocated) {
 658                                 DRM_ERROR("Handle already in use!\n");
 659                                 r = -EINVAL;
 660                                 goto out;
 661                         }
 662
 663                         *size = amdgpu_get_ib_value(p, ib_idx, idx + 8) *
 664                                 amdgpu_get_ib_value(p, ib_idx, idx + 10) *
 665                                 8 * 3 / 2;
 666                         break;
 667
 668                 case 0x04000001: // config extension
 669                 case 0x04000002: // pic control
 670                 case 0x04000005: // rate control
 671                 case 0x04000007: // motion estimation
 672                 case 0x04000008: // rdo
 673                 case 0x04000009: // vui
 674                 case 0x05000002: // auxiliary buffer
 675                         break;
 676
 677                 case 0x03000001: // encode
 678                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9,
 679                                                 *size, 0);
 680                         if (r)
 681                                 goto out;
 682
 683                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11,
 684                                                 *size / 3, 0);
 685                         if (r)
 686                                 goto out;
 687                         break;
 688
 689                 case 0x02000001: // destroy
 690                         destroyed = true;
 691                         break;
 692
 693                 case 0x05000001: // context buffer
 694                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 695                                                 *size * 2, 0);
 696                         if (r)
 697                                 goto out;
 698                         break;
 699
 700                 case 0x05000004: // video bitstream buffer
 701                         tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
 702                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 703                                                 tmp, bs_idx);
 704                         if (r)
 705                                 goto out;
 706                         break;
 707
 708                 case 0x05000005: // feedback buffer
 709                         r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2,
 710                                                 4096, fb_idx);
 711                         if (r)
 712                                 goto out;
 713                         break;
 714
 715                 default:
 716                         DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
 717                         r = -EINVAL;
 718                         goto out;
 719                 }
 720
 721                 if (session_idx == -1) {
 722                         DRM_ERROR("no session command at start of IB\n");
 723                         r = -EINVAL;
 724                         goto out;
 725                 }
 726
 727                 idx += len / 4;
 728         }
 729
 730         if (allocated && !created) {
 731                 DRM_ERROR("New session without create command!\n");
 732                 r = -ENOENT;
 733         }
 734
 735 out:
 736         if ((!r && destroyed) || (r && allocated)) {
 737                 /*
 738                  * IB contains a destroy msg or we have allocated an
 739                  * handle and got an error, anyway free the handle
 740                  */
 741                 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
 742                         atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
 743         }
 744
 745         return r;
 746 }
 747
 748 /**
 749  * amdgpu_vce_ring_emit_ib - execute indirect buffer
 750  *
 751  * @ring: engine to use
 752  * @ib: the IB to execute
 753  *
 754  */
 755 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 756 {
 757         amdgpu_ring_write(ring, VCE_CMD_IB);
 758         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 759         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 760         amdgpu_ring_write(ring, ib->length_dw);
 761 }
 762
 763 /**
 764  * amdgpu_vce_ring_emit_fence - add a fence command to the ring
 765  *
 766  * @ring: engine to use
 767  * @fence: the fence
 768  *
 769  */
 770 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 771                                 unsigned flags)
 772 {
 773         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 774
 775         amdgpu_ring_write(ring, VCE_CMD_FENCE);
 776         amdgpu_ring_write(ring, addr);
 777         amdgpu_ring_write(ring, upper_32_bits(addr));
 778         amdgpu_ring_write(ring, seq);
 779         amdgpu_ring_write(ring, VCE_CMD_TRAP);
 780         amdgpu_ring_write(ring, VCE_CMD_END);
 781 }
 782
 783 /**
 784  * amdgpu_vce_ring_test_ring - test if VCE ring is working
 785  *
 786  * @ring: the engine to test on
 787  *
 788  */
 789 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
 790 {
 791         struct amdgpu_device *adev = ring->adev;
 792         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 793         unsigned i;
 794         int r;
 795
 796         r = amdgpu_ring_alloc(ring, 16);
 797         if (r) {
 798                 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
 799                           ring->idx, r);
 800                 return r;
 801         }
 802         amdgpu_ring_write(ring, VCE_CMD_END);
 803         amdgpu_ring_commit(ring);
 804
 805         for (i = 0; i < adev->usec_timeout; i++) {
 806                 if (amdgpu_ring_get_rptr(ring) != rptr)
 807                         break;
 808                 DRM_UDELAY(1);
 809         }
 810
 811         if (i < adev->usec_timeout) {
 812                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 813                          ring->idx, i);
 814         } else {
 815                 DRM_ERROR("amdgpu: ring %d test failed\n",
 816                           ring->idx);
 817                 r = -ETIMEDOUT;
 818         }
 819
 820         return r;
 821 }
 822
 823 /**
 824  * amdgpu_vce_ring_test_ib - test if VCE IBs are working
 825  *
 826  * @ring: the engine to test on
 827  *
 828  */
 829 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
 830 {
 831         struct fence *fence = NULL;
 832         int r;
 833
 834         /* skip vce ring1 ib test for now, since it's not reliable */
 835         if (ring == &ring->adev->vce.ring[1])
 836                 return 0;
 837
 838         r = amdgpu_vce_get_create_msg(ring, 1, NULL);
 839         if (r) {
 840                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 841                 goto error;
 842         }
 843
 844         r = amdgpu_vce_get_destroy_msg(ring, 1, true, &fence);
 845         if (r) {
 846                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 847                 goto error;
 848         }
 849
 850         r = fence_wait(fence, false);
 851         if (r) {
 852                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 853         } else {
 854                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 855         }
 856 error:
 857         fence_put(fence);
 858         return r;
 859 }