2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46 static const u32 crtc_offsets[] =
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
57 static const u32 hpd_offsets[] =
67 static const uint32_t dig_offsets[] = {
85 } interrupt_status_offsets[] = { {
86 .reg = mmDISP_INTERRUPT_STATUS,
87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
117 static const u32 cz_golden_settings_a11[] =
119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
120 mmFBC_MISC, 0x1f311fff, 0x14300000,
123 static const u32 cz_mgcg_cgcg_init[] =
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
129 static const u32 stoney_golden_settings_a11[] =
131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
132 mmFBC_MISC, 0x1f311fff, 0x14302000,
135 static const u32 polaris11_golden_settings_a11[] =
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
140 mmFBC_MISC, 0x9f313fff, 0x14302008,
141 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
144 static const u32 polaris10_golden_settings_a11[] =
146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
148 mmFBC_MISC, 0x9f313fff, 0x14302008,
149 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154 switch (adev->asic_type) {
156 amdgpu_program_register_sequence(adev,
158 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev,
160 cz_golden_settings_a11,
161 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
164 amdgpu_program_register_sequence(adev,
165 stoney_golden_settings_a11,
166 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
169 amdgpu_program_register_sequence(adev,
170 polaris11_golden_settings_a11,
171 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
174 amdgpu_program_register_sequence(adev,
175 polaris10_golden_settings_a11,
176 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
184 u32 block_offset, u32 reg)
189 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
191 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
192 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
198 u32 block_offset, u32 reg, u32 v)
202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
210 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
221 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
222 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
231 * dce_v11_0_vblank_wait - vblank wait asic callback.
233 * @adev: amdgpu_device pointer
234 * @crtc: crtc to wait for vblank on
236 * Wait for vblank on the requested crtc (evergreen+).
238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
242 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
245 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
248 /* depending on when we hit vblank, we may be close to active; if so,
249 * wait for another frame.
251 while (dce_v11_0_is_in_vblank(adev, crtc)) {
254 if (!dce_v11_0_is_counter_moving(adev, crtc))
259 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
262 if (!dce_v11_0_is_counter_moving(adev, crtc))
268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
270 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
273 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
280 /* Enable pflip interrupts */
281 for (i = 0; i < adev->mode_info.num_crtc; i++)
282 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
289 /* Disable pflip interrupts */
290 for (i = 0; i < adev->mode_info.num_crtc; i++)
291 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
295 * dce_v11_0_page_flip - pageflip callback.
297 * @adev: amdgpu_device pointer
298 * @crtc_id: crtc to cleanup pageflip on
299 * @crtc_base: new address of the crtc (GPU MC address)
301 * Triggers the actual pageflip by updating the primary
302 * surface base address.
304 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
305 int crtc_id, u64 crtc_base, bool async)
307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
310 /* flip at hsync for async, default is vsync */
311 /* use UPDATE_IMMEDIATE_EN instead for async? */
312 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
313 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
314 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
315 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
316 /* update the scanout addresses */
317 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
318 upper_32_bits(crtc_base));
319 /* writing to the low address triggers the update */
320 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
321 lower_32_bits(crtc_base));
323 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
326 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
327 u32 *vbl, u32 *position)
329 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
332 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
333 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
339 * dce_v11_0_hpd_sense - hpd sense callback.
341 * @adev: amdgpu_device pointer
342 * @hpd: hpd (hotplug detect) pin
344 * Checks if a digital monitor is connected (evergreen+).
345 * Returns true if connected, false if not connected.
347 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
348 enum amdgpu_hpd_id hpd)
351 bool connected = false;
376 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
377 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
384 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
386 * @adev: amdgpu_device pointer
387 * @hpd: hpd (hotplug detect) pin
389 * Set the polarity of the hpd pin (evergreen+).
391 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
392 enum amdgpu_hpd_id hpd)
395 bool connected = dce_v11_0_hpd_sense(adev, hpd);
421 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
423 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
425 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
426 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
430 * dce_v11_0_hpd_init - hpd setup callback.
432 * @adev: amdgpu_device pointer
434 * Setup the hpd pins used by the card (evergreen+).
435 * Enable the pin, set the polarity, and enable the hpd interrupts.
437 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
439 struct drm_device *dev = adev->ddev;
440 struct drm_connector *connector;
444 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
445 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
447 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
448 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
449 /* don't try to enable hpd on eDP or LVDS avoid breaking the
450 * aux dp channel on imac and help (but not completely fix)
451 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
452 * also avoid interrupt storms during dpms.
457 switch (amdgpu_connector->hpd.hpd) {
480 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
481 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
482 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
484 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
485 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
486 DC_HPD_CONNECT_INT_DELAY,
487 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
488 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
489 DC_HPD_DISCONNECT_INT_DELAY,
490 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
491 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
493 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
494 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
499 * dce_v11_0_hpd_fini - hpd tear down callback.
501 * @adev: amdgpu_device pointer
503 * Tear down the hpd pins used by the card (evergreen+).
504 * Disable the hpd interrupts.
506 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
508 struct drm_device *dev = adev->ddev;
509 struct drm_connector *connector;
513 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
514 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
516 switch (amdgpu_connector->hpd.hpd) {
539 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
540 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
541 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
543 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
547 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
549 return mmDC_GPIO_HPD_A;
552 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
558 for (i = 0; i < adev->mode_info.num_crtc; i++) {
559 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
560 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
561 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
562 crtc_hung |= (1 << i);
566 for (j = 0; j < 10; j++) {
567 for (i = 0; i < adev->mode_info.num_crtc; i++) {
568 if (crtc_hung & (1 << i)) {
569 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
570 if (tmp != crtc_status[i])
571 crtc_hung &= ~(1 << i);
582 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
583 struct amdgpu_mode_mc_save *save)
585 u32 crtc_enabled, tmp;
588 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
589 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
591 /* disable VGA render */
592 tmp = RREG32(mmVGA_RENDER_CONTROL);
593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
594 WREG32(mmVGA_RENDER_CONTROL, tmp);
596 /* blank the display controllers */
597 for (i = 0; i < adev->mode_info.num_crtc; i++) {
598 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
599 CRTC_CONTROL, CRTC_MASTER_EN);
602 save->crtc_enabled[i] = true;
603 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
604 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
605 /*it is correct only for RGB ; black is 0*/
606 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
607 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
608 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
611 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
612 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
613 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
614 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
615 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
616 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
617 save->crtc_enabled[i] = false;
621 save->crtc_enabled[i] = false;
626 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
627 struct amdgpu_mode_mc_save *save)
632 /* update crtc base addresses */
633 for (i = 0; i < adev->mode_info.num_crtc; i++) {
634 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
635 upper_32_bits(adev->mc.vram_start));
636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
637 (u32)adev->mc.vram_start);
639 if (save->crtc_enabled[i]) {
640 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
641 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
642 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
646 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
647 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
649 /* Unlock vga access */
650 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
652 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
655 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
660 /* Lockout access through VGA aperture*/
661 tmp = RREG32(mmVGA_HDP_CONTROL);
663 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
665 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
666 WREG32(mmVGA_HDP_CONTROL, tmp);
668 /* disable VGA render */
669 tmp = RREG32(mmVGA_RENDER_CONTROL);
671 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
673 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
674 WREG32(mmVGA_RENDER_CONTROL, tmp);
677 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
679 struct drm_device *dev = encoder->dev;
680 struct amdgpu_device *adev = dev->dev_private;
681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
683 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
686 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
689 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
690 bpc = amdgpu_connector_get_monitor_bpc(connector);
691 dither = amdgpu_connector->dither;
694 /* LVDS/eDP FMT is set up by atom */
695 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
698 /* not needed for analog */
699 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
700 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
708 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
709 /* XXX sort out optimal dither settings */
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
711 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
712 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
713 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
715 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
716 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
720 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
721 /* XXX sort out optimal dither settings */
722 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
723 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
724 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
725 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
726 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
729 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
733 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
734 /* XXX sort out optimal dither settings */
735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
739 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
750 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
754 /* display watermark setup */
756 * dce_v11_0_line_buffer_adjust - Set up the line buffer
758 * @adev: amdgpu_device pointer
759 * @amdgpu_crtc: the selected display controller
760 * @mode: the current display mode on the selected display
763 * Setup up the line buffer allocation for
764 * the selected display controller (CIK).
765 * Returns the line buffer size in pixels.
767 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
768 struct amdgpu_crtc *amdgpu_crtc,
769 struct drm_display_mode *mode)
771 u32 tmp, buffer_alloc, i, mem_cfg;
772 u32 pipe_offset = amdgpu_crtc->crtc_id;
775 * There are 6 line buffers, one for each display controllers.
776 * There are 3 partitions per LB. Select the number of partitions
777 * to enable based on the display width. For display widths larger
778 * than 4096, you need use to use 2 display controllers and combine
779 * them using the stereo blender.
781 if (amdgpu_crtc->base.enabled && mode) {
782 if (mode->crtc_hdisplay < 1920) {
785 } else if (mode->crtc_hdisplay < 2560) {
788 } else if (mode->crtc_hdisplay < 4096) {
790 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
792 DRM_DEBUG_KMS("Mode too big for LB!\n");
794 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
801 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
802 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
803 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
805 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
806 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
807 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
809 for (i = 0; i < adev->usec_timeout; i++) {
810 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
811 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
816 if (amdgpu_crtc->base.enabled && mode) {
828 /* controller not enabled, so no lb used */
833 * cik_get_number_of_dram_channels - get the number of dram channels
835 * @adev: amdgpu_device pointer
837 * Look up the number of video ram channels (CIK).
838 * Used for display watermark bandwidth calculations
839 * Returns the number of dram channels
841 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
843 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
845 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
868 struct dce10_wm_params {
869 u32 dram_channels; /* number of dram channels */
870 u32 yclk; /* bandwidth per dram data pin in kHz */
871 u32 sclk; /* engine clock in kHz */
872 u32 disp_clk; /* display clock in kHz */
873 u32 src_width; /* viewport width */
874 u32 active_time; /* active display time in ns */
875 u32 blank_time; /* blank time in ns */
876 bool interlaced; /* mode is interlaced */
877 fixed20_12 vsc; /* vertical scale ratio */
878 u32 num_heads; /* number of active crtcs */
879 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
880 u32 lb_size; /* line buffer allocated to pipe */
881 u32 vtaps; /* vertical scaler taps */
885 * dce_v11_0_dram_bandwidth - get the dram bandwidth
887 * @wm: watermark calculation data
889 * Calculate the raw dram bandwidth (CIK).
890 * Used for display watermark bandwidth calculations
891 * Returns the dram bandwidth in MBytes/s
893 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
895 /* Calculate raw DRAM Bandwidth */
896 fixed20_12 dram_efficiency; /* 0.7 */
897 fixed20_12 yclk, dram_channels, bandwidth;
900 a.full = dfixed_const(1000);
901 yclk.full = dfixed_const(wm->yclk);
902 yclk.full = dfixed_div(yclk, a);
903 dram_channels.full = dfixed_const(wm->dram_channels * 4);
904 a.full = dfixed_const(10);
905 dram_efficiency.full = dfixed_const(7);
906 dram_efficiency.full = dfixed_div(dram_efficiency, a);
907 bandwidth.full = dfixed_mul(dram_channels, yclk);
908 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
910 return dfixed_trunc(bandwidth);
914 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
916 * @wm: watermark calculation data
918 * Calculate the dram bandwidth used for display (CIK).
919 * Used for display watermark bandwidth calculations
920 * Returns the dram bandwidth for display in MBytes/s
922 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
924 /* Calculate DRAM Bandwidth and the part allocated to display. */
925 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
926 fixed20_12 yclk, dram_channels, bandwidth;
929 a.full = dfixed_const(1000);
930 yclk.full = dfixed_const(wm->yclk);
931 yclk.full = dfixed_div(yclk, a);
932 dram_channels.full = dfixed_const(wm->dram_channels * 4);
933 a.full = dfixed_const(10);
934 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
935 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
936 bandwidth.full = dfixed_mul(dram_channels, yclk);
937 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
939 return dfixed_trunc(bandwidth);
943 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
945 * @wm: watermark calculation data
947 * Calculate the data return bandwidth used for display (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns the data return bandwidth in MBytes/s
951 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
953 /* Calculate the display Data return Bandwidth */
954 fixed20_12 return_efficiency; /* 0.8 */
955 fixed20_12 sclk, bandwidth;
958 a.full = dfixed_const(1000);
959 sclk.full = dfixed_const(wm->sclk);
960 sclk.full = dfixed_div(sclk, a);
961 a.full = dfixed_const(10);
962 return_efficiency.full = dfixed_const(8);
963 return_efficiency.full = dfixed_div(return_efficiency, a);
964 a.full = dfixed_const(32);
965 bandwidth.full = dfixed_mul(a, sclk);
966 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
968 return dfixed_trunc(bandwidth);
972 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
974 * @wm: watermark calculation data
976 * Calculate the dmif bandwidth used for display (CIK).
977 * Used for display watermark bandwidth calculations
978 * Returns the dmif bandwidth in MBytes/s
980 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
982 /* Calculate the DMIF Request Bandwidth */
983 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
984 fixed20_12 disp_clk, bandwidth;
987 a.full = dfixed_const(1000);
988 disp_clk.full = dfixed_const(wm->disp_clk);
989 disp_clk.full = dfixed_div(disp_clk, a);
990 a.full = dfixed_const(32);
991 b.full = dfixed_mul(a, disp_clk);
993 a.full = dfixed_const(10);
994 disp_clk_request_efficiency.full = dfixed_const(8);
995 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
997 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
999 return dfixed_trunc(bandwidth);
1003 * dce_v11_0_available_bandwidth - get the min available bandwidth
1005 * @wm: watermark calculation data
1007 * Calculate the min available bandwidth used for display (CIK).
1008 * Used for display watermark bandwidth calculations
1009 * Returns the min available bandwidth in MBytes/s
1011 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1013 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1014 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1015 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1016 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1018 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1022 * dce_v11_0_average_bandwidth - get the average available bandwidth
1024 * @wm: watermark calculation data
1026 * Calculate the average available bandwidth used for display (CIK).
1027 * Used for display watermark bandwidth calculations
1028 * Returns the average available bandwidth in MBytes/s
1030 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1032 /* Calculate the display mode Average Bandwidth
1033 * DisplayMode should contain the source and destination dimensions,
1037 fixed20_12 line_time;
1038 fixed20_12 src_width;
1039 fixed20_12 bandwidth;
1042 a.full = dfixed_const(1000);
1043 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1044 line_time.full = dfixed_div(line_time, a);
1045 bpp.full = dfixed_const(wm->bytes_per_pixel);
1046 src_width.full = dfixed_const(wm->src_width);
1047 bandwidth.full = dfixed_mul(src_width, bpp);
1048 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1049 bandwidth.full = dfixed_div(bandwidth, line_time);
1051 return dfixed_trunc(bandwidth);
1055 * dce_v11_0_latency_watermark - get the latency watermark
1057 * @wm: watermark calculation data
1059 * Calculate the latency watermark (CIK).
1060 * Used for display watermark bandwidth calculations
1061 * Returns the latency watermark in ns
1063 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1065 /* First calculate the latency in ns */
1066 u32 mc_latency = 2000; /* 2000 ns. */
1067 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1068 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1069 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1070 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1071 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1072 (wm->num_heads * cursor_line_pair_return_time);
1073 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1074 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1075 u32 tmp, dmif_size = 12288;
1078 if (wm->num_heads == 0)
1081 a.full = dfixed_const(2);
1082 b.full = dfixed_const(1);
1083 if ((wm->vsc.full > a.full) ||
1084 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1086 ((wm->vsc.full >= a.full) && wm->interlaced))
1087 max_src_lines_per_dst_line = 4;
1089 max_src_lines_per_dst_line = 2;
1091 a.full = dfixed_const(available_bandwidth);
1092 b.full = dfixed_const(wm->num_heads);
1093 a.full = dfixed_div(a, b);
1095 b.full = dfixed_const(mc_latency + 512);
1096 c.full = dfixed_const(wm->disp_clk);
1097 b.full = dfixed_div(b, c);
1099 c.full = dfixed_const(dmif_size);
1100 b.full = dfixed_div(c, b);
1102 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1104 b.full = dfixed_const(1000);
1105 c.full = dfixed_const(wm->disp_clk);
1106 b.full = dfixed_div(c, b);
1107 c.full = dfixed_const(wm->bytes_per_pixel);
1108 b.full = dfixed_mul(b, c);
1110 lb_fill_bw = min(tmp, dfixed_trunc(b));
1112 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1113 b.full = dfixed_const(1000);
1114 c.full = dfixed_const(lb_fill_bw);
1115 b.full = dfixed_div(c, b);
1116 a.full = dfixed_div(a, b);
1117 line_fill_time = dfixed_trunc(a);
1119 if (line_fill_time < wm->active_time)
1122 return latency + (line_fill_time - wm->active_time);
1127 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1128 * average and available dram bandwidth
1130 * @wm: watermark calculation data
1132 * Check if the display average bandwidth fits in the display
1133 * dram bandwidth (CIK).
1134 * Used for display watermark bandwidth calculations
1135 * Returns true if the display fits, false if not.
1137 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1139 if (dce_v11_0_average_bandwidth(wm) <=
1140 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1147 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1148 * average and available bandwidth
1150 * @wm: watermark calculation data
1152 * Check if the display average bandwidth fits in the display
1153 * available bandwidth (CIK).
1154 * Used for display watermark bandwidth calculations
1155 * Returns true if the display fits, false if not.
1157 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1159 if (dce_v11_0_average_bandwidth(wm) <=
1160 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1167 * dce_v11_0_check_latency_hiding - check latency hiding
1169 * @wm: watermark calculation data
1171 * Check latency hiding (CIK).
1172 * Used for display watermark bandwidth calculations
1173 * Returns true if the display fits, false if not.
1175 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1177 u32 lb_partitions = wm->lb_size / wm->src_width;
1178 u32 line_time = wm->active_time + wm->blank_time;
1179 u32 latency_tolerant_lines;
1183 a.full = dfixed_const(1);
1184 if (wm->vsc.full > a.full)
1185 latency_tolerant_lines = 1;
1187 if (lb_partitions <= (wm->vtaps + 1))
1188 latency_tolerant_lines = 1;
1190 latency_tolerant_lines = 2;
1193 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1195 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1202 * dce_v11_0_program_watermarks - program display watermarks
1204 * @adev: amdgpu_device pointer
1205 * @amdgpu_crtc: the selected display controller
1206 * @lb_size: line buffer size
1207 * @num_heads: number of display controllers in use
1209 * Calculate and program the display watermarks for the
1210 * selected display controller (CIK).
1212 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1213 struct amdgpu_crtc *amdgpu_crtc,
1214 u32 lb_size, u32 num_heads)
1216 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1217 struct dce10_wm_params wm_low, wm_high;
1220 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1221 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1223 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1224 pixel_period = 1000000 / (u32)mode->clock;
1225 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1227 /* watermark for high clocks */
1228 if (adev->pm.dpm_enabled) {
1230 amdgpu_dpm_get_mclk(adev, false) * 10;
1232 amdgpu_dpm_get_sclk(adev, false) * 10;
1234 wm_high.yclk = adev->pm.current_mclk * 10;
1235 wm_high.sclk = adev->pm.current_sclk * 10;
1238 wm_high.disp_clk = mode->clock;
1239 wm_high.src_width = mode->crtc_hdisplay;
1240 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1241 wm_high.blank_time = line_time - wm_high.active_time;
1242 wm_high.interlaced = false;
1243 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1244 wm_high.interlaced = true;
1245 wm_high.vsc = amdgpu_crtc->vsc;
1247 if (amdgpu_crtc->rmx_type != RMX_OFF)
1249 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1250 wm_high.lb_size = lb_size;
1251 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1252 wm_high.num_heads = num_heads;
1254 /* set for high clocks */
1255 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1257 /* possibly force display priority to high */
1258 /* should really do this at mode validation time... */
1259 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1260 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1261 !dce_v11_0_check_latency_hiding(&wm_high) ||
1262 (adev->mode_info.disp_priority == 2)) {
1263 DRM_DEBUG_KMS("force priority to high\n");
1266 /* watermark for low clocks */
1267 if (adev->pm.dpm_enabled) {
1269 amdgpu_dpm_get_mclk(adev, true) * 10;
1271 amdgpu_dpm_get_sclk(adev, true) * 10;
1273 wm_low.yclk = adev->pm.current_mclk * 10;
1274 wm_low.sclk = adev->pm.current_sclk * 10;
1277 wm_low.disp_clk = mode->clock;
1278 wm_low.src_width = mode->crtc_hdisplay;
1279 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1280 wm_low.blank_time = line_time - wm_low.active_time;
1281 wm_low.interlaced = false;
1282 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1283 wm_low.interlaced = true;
1284 wm_low.vsc = amdgpu_crtc->vsc;
1286 if (amdgpu_crtc->rmx_type != RMX_OFF)
1288 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1289 wm_low.lb_size = lb_size;
1290 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1291 wm_low.num_heads = num_heads;
1293 /* set for low clocks */
1294 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1296 /* possibly force display priority to high */
1297 /* should really do this at mode validation time... */
1298 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1299 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1300 !dce_v11_0_check_latency_hiding(&wm_low) ||
1301 (adev->mode_info.disp_priority == 2)) {
1302 DRM_DEBUG_KMS("force priority to high\n");
1304 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1308 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1309 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1310 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1311 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1312 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1313 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1314 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1316 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1317 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1318 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1319 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1320 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1321 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1322 /* restore original selection */
1323 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1325 /* save values for DPM */
1326 amdgpu_crtc->line_time = line_time;
1327 amdgpu_crtc->wm_high = latency_watermark_a;
1328 amdgpu_crtc->wm_low = latency_watermark_b;
1329 /* Save number of lines the linebuffer leads before the scanout */
1330 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1334 * dce_v11_0_bandwidth_update - program display watermarks
1336 * @adev: amdgpu_device pointer
1338 * Calculate and program the display watermarks and line
1339 * buffer allocation (CIK).
1341 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1343 struct drm_display_mode *mode = NULL;
1344 u32 num_heads = 0, lb_size;
1347 amdgpu_update_display_priority(adev);
1349 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1350 if (adev->mode_info.crtcs[i]->base.enabled)
1353 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1354 mode = &adev->mode_info.crtcs[i]->base.mode;
1355 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1356 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1357 lb_size, num_heads);
1361 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1366 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1367 offset = adev->mode_info.audio.pin[i].offset;
1368 tmp = RREG32_AUDIO_ENDPT(offset,
1369 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1371 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1372 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1373 adev->mode_info.audio.pin[i].connected = false;
1375 adev->mode_info.audio.pin[i].connected = true;
1379 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1383 dce_v11_0_audio_get_connected_pins(adev);
1385 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1386 if (adev->mode_info.audio.pin[i].connected)
1387 return &adev->mode_info.audio.pin[i];
1389 DRM_ERROR("No connected audio pins found!\n");
1393 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1395 struct amdgpu_device *adev = encoder->dev->dev_private;
1396 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1397 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1400 if (!dig || !dig->afmt || !dig->afmt->pin)
1403 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1404 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1405 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1408 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1409 struct drm_display_mode *mode)
1411 struct amdgpu_device *adev = encoder->dev->dev_private;
1412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1413 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1414 struct drm_connector *connector;
1415 struct amdgpu_connector *amdgpu_connector = NULL;
1419 if (!dig || !dig->afmt || !dig->afmt->pin)
1422 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1423 if (connector->encoder == encoder) {
1424 amdgpu_connector = to_amdgpu_connector(connector);
1429 if (!amdgpu_connector) {
1430 DRM_ERROR("Couldn't find encoder's connector\n");
1434 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1436 if (connector->latency_present[interlace]) {
1437 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1438 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1439 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1440 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1442 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1444 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1447 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1448 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1451 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1453 struct amdgpu_device *adev = encoder->dev->dev_private;
1454 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1455 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1456 struct drm_connector *connector;
1457 struct amdgpu_connector *amdgpu_connector = NULL;
1462 if (!dig || !dig->afmt || !dig->afmt->pin)
1465 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1466 if (connector->encoder == encoder) {
1467 amdgpu_connector = to_amdgpu_connector(connector);
1472 if (!amdgpu_connector) {
1473 DRM_ERROR("Couldn't find encoder's connector\n");
1477 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1478 if (sad_count < 0) {
1479 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1483 /* program the speaker allocation */
1484 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1485 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1486 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1489 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1490 HDMI_CONNECTION, 1);
1492 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1493 SPEAKER_ALLOCATION, sadb[0]);
1495 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1496 SPEAKER_ALLOCATION, 5); /* stereo */
1497 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1498 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1503 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1505 struct amdgpu_device *adev = encoder->dev->dev_private;
1506 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1507 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1508 struct drm_connector *connector;
1509 struct amdgpu_connector *amdgpu_connector = NULL;
1510 struct cea_sad *sads;
1513 static const u16 eld_reg_to_type[][2] = {
1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1520 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1521 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1522 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1523 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1524 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1525 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1528 if (!dig || !dig->afmt || !dig->afmt->pin)
1531 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1532 if (connector->encoder == encoder) {
1533 amdgpu_connector = to_amdgpu_connector(connector);
1538 if (!amdgpu_connector) {
1539 DRM_ERROR("Couldn't find encoder's connector\n");
1543 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1544 if (sad_count <= 0) {
1545 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1550 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1552 u8 stereo_freqs = 0;
1553 int max_channels = -1;
1556 for (j = 0; j < sad_count; j++) {
1557 struct cea_sad *sad = &sads[j];
1559 if (sad->format == eld_reg_to_type[i][1]) {
1560 if (sad->channels > max_channels) {
1561 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1562 MAX_CHANNELS, sad->channels);
1563 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1564 DESCRIPTOR_BYTE_2, sad->byte2);
1565 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1566 SUPPORTED_FREQUENCIES, sad->freq);
1567 max_channels = sad->channels;
1570 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1571 stereo_freqs |= sad->freq;
1577 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1578 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1579 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1585 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1586 struct amdgpu_audio_pin *pin,
1592 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1593 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1596 static const u32 pin_offsets[] =
1598 AUD0_REGISTER_OFFSET,
1599 AUD1_REGISTER_OFFSET,
1600 AUD2_REGISTER_OFFSET,
1601 AUD3_REGISTER_OFFSET,
1602 AUD4_REGISTER_OFFSET,
1603 AUD5_REGISTER_OFFSET,
1604 AUD6_REGISTER_OFFSET,
1605 AUD7_REGISTER_OFFSET,
1608 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1615 adev->mode_info.audio.enabled = true;
1617 switch (adev->asic_type) {
1620 adev->mode_info.audio.num_pins = 7;
1622 case CHIP_POLARIS10:
1623 adev->mode_info.audio.num_pins = 8;
1625 case CHIP_POLARIS11:
1626 adev->mode_info.audio.num_pins = 6;
1632 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1633 adev->mode_info.audio.pin[i].channels = -1;
1634 adev->mode_info.audio.pin[i].rate = -1;
1635 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1636 adev->mode_info.audio.pin[i].status_bits = 0;
1637 adev->mode_info.audio.pin[i].category_code = 0;
1638 adev->mode_info.audio.pin[i].connected = false;
1639 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1640 adev->mode_info.audio.pin[i].id = i;
1641 /* disable audio. it will be set up later */
1642 /* XXX remove once we switch to ip funcs */
1643 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1649 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1656 if (!adev->mode_info.audio.enabled)
1659 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1660 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1662 adev->mode_info.audio.enabled = false;
1666 * update the N and CTS parameters for a given pixel clock rate
1668 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1670 struct drm_device *dev = encoder->dev;
1671 struct amdgpu_device *adev = dev->dev_private;
1672 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1673 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1674 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1677 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1678 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1679 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1680 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1682 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1684 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1685 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1686 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1687 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1689 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1691 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1692 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1693 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1694 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1696 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1701 * build a HDMI Video Info Frame
1703 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1704 void *buffer, size_t size)
1706 struct drm_device *dev = encoder->dev;
1707 struct amdgpu_device *adev = dev->dev_private;
1708 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1709 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1710 uint8_t *frame = buffer + 3;
1711 uint8_t *header = buffer;
1713 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1714 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1715 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1716 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1717 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1718 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1719 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1720 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1723 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_device *adev = dev->dev_private;
1727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1730 u32 dto_phase = 24 * 1000;
1731 u32 dto_modulo = clock;
1734 if (!dig || !dig->afmt)
1737 /* XXX two dtos; generally use dto0 for hdmi */
1738 /* Express [24MHz / target pixel clock] as an exact rational
1739 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1740 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1742 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1743 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1744 amdgpu_crtc->crtc_id);
1745 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1746 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1747 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1751 * update the info frames with the data from the current display mode
1753 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1754 struct drm_display_mode *mode)
1756 struct drm_device *dev = encoder->dev;
1757 struct amdgpu_device *adev = dev->dev_private;
1758 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1759 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1760 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1761 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1762 struct hdmi_avi_infoframe frame;
1767 if (!dig || !dig->afmt)
1770 /* Silent, r600_hdmi_enable will raise WARN for us */
1771 if (!dig->afmt->enabled)
1774 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1775 if (encoder->crtc) {
1776 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1777 bpc = amdgpu_crtc->bpc;
1780 /* disable audio prior to setting up hw */
1781 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1782 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1784 dce_v11_0_audio_set_dto(encoder, mode->clock);
1786 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1787 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1788 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1790 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1792 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1799 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1800 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1801 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1802 connector->name, bpc);
1805 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1806 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1807 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1811 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1812 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1813 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1817 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1819 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1820 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1821 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1822 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1823 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1825 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1826 /* enable audio info frames (frames won't be set until audio is enabled) */
1827 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1828 /* required for audio info values to be updated */
1829 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1830 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1832 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1833 /* required for audio info values to be updated */
1834 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1835 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1837 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1838 /* anything other than 0 */
1839 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1840 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1842 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1844 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1845 /* set the default audio delay */
1846 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1847 /* should be suffient for all audio modes and small enough for all hblanks */
1848 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1849 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1851 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1852 /* allow 60958 channel status fields to be updated */
1853 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1854 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1856 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1858 /* clear SW CTS value */
1859 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1861 /* select SW CTS value */
1862 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1863 /* allow hw to sent ACR packets when required */
1864 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1865 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1867 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1869 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1870 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1871 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1873 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1874 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1875 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1877 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1878 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1879 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1880 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1881 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1883 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1884 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1886 dce_v11_0_audio_write_speaker_allocation(encoder);
1888 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1889 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1891 dce_v11_0_afmt_audio_select_pin(encoder);
1892 dce_v11_0_audio_write_sad_regs(encoder);
1893 dce_v11_0_audio_write_latency_fields(encoder, mode);
1895 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1897 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1901 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1903 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1907 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1909 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1910 /* enable AVI info frames */
1911 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1912 /* required for audio info values to be updated */
1913 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1914 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1916 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1917 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1918 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1920 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1921 /* send audio packets */
1922 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1923 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1925 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1926 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1927 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1928 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1930 /* enable audio after to setting up hw */
1931 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1934 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1936 struct drm_device *dev = encoder->dev;
1937 struct amdgpu_device *adev = dev->dev_private;
1938 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1939 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1941 if (!dig || !dig->afmt)
1944 /* Silent, r600_hdmi_enable will raise WARN for us */
1945 if (enable && dig->afmt->enabled)
1947 if (!enable && !dig->afmt->enabled)
1950 if (!enable && dig->afmt->pin) {
1951 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1952 dig->afmt->pin = NULL;
1955 dig->afmt->enabled = enable;
1957 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1958 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1961 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1965 for (i = 0; i < adev->mode_info.num_dig; i++)
1966 adev->mode_info.afmt[i] = NULL;
1968 /* DCE11 has audio blocks tied to DIG encoders */
1969 for (i = 0; i < adev->mode_info.num_dig; i++) {
1970 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1971 if (adev->mode_info.afmt[i]) {
1972 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1973 adev->mode_info.afmt[i]->id = i;
1976 for (j = 0; j < i; j++) {
1977 kfree(adev->mode_info.afmt[j]);
1978 adev->mode_info.afmt[j] = NULL;
1986 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1990 for (i = 0; i < adev->mode_info.num_dig; i++) {
1991 kfree(adev->mode_info.afmt[i]);
1992 adev->mode_info.afmt[i] = NULL;
1996 static const u32 vga_control_regs[6] =
2006 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2008 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009 struct drm_device *dev = crtc->dev;
2010 struct amdgpu_device *adev = dev->dev_private;
2013 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2015 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2017 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2020 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2022 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2023 struct drm_device *dev = crtc->dev;
2024 struct amdgpu_device *adev = dev->dev_private;
2027 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2029 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2032 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2033 struct drm_framebuffer *fb,
2034 int x, int y, int atomic)
2036 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2037 struct drm_device *dev = crtc->dev;
2038 struct amdgpu_device *adev = dev->dev_private;
2039 struct amdgpu_framebuffer *amdgpu_fb;
2040 struct drm_framebuffer *target_fb;
2041 struct drm_gem_object *obj;
2042 struct amdgpu_bo *rbo;
2043 uint64_t fb_location, tiling_flags;
2044 uint32_t fb_format, fb_pitch_pixels;
2045 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2047 u32 tmp, viewport_w, viewport_h;
2049 bool bypass_lut = false;
2052 if (!atomic && !crtc->primary->fb) {
2053 DRM_DEBUG_KMS("No FB bound\n");
2058 amdgpu_fb = to_amdgpu_framebuffer(fb);
2061 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2062 target_fb = crtc->primary->fb;
2065 /* If atomic, assume fb object is pinned & idle & fenced and
2066 * just update base pointers
2068 obj = amdgpu_fb->obj;
2069 rbo = gem_to_amdgpu_bo(obj);
2070 r = amdgpu_bo_reserve(rbo, false);
2071 if (unlikely(r != 0))
2075 fb_location = amdgpu_bo_gpu_offset(rbo);
2077 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2078 if (unlikely(r != 0)) {
2079 amdgpu_bo_unreserve(rbo);
2084 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2085 amdgpu_bo_unreserve(rbo);
2087 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2089 switch (target_fb->pixel_format) {
2091 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2092 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2094 case DRM_FORMAT_XRGB4444:
2095 case DRM_FORMAT_ARGB4444:
2096 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2097 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2099 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2103 case DRM_FORMAT_XRGB1555:
2104 case DRM_FORMAT_ARGB1555:
2105 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2106 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2108 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2112 case DRM_FORMAT_BGRX5551:
2113 case DRM_FORMAT_BGRA5551:
2114 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2115 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2117 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2121 case DRM_FORMAT_RGB565:
2122 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2123 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2125 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2129 case DRM_FORMAT_XRGB8888:
2130 case DRM_FORMAT_ARGB8888:
2131 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2132 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2134 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2138 case DRM_FORMAT_XRGB2101010:
2139 case DRM_FORMAT_ARGB2101010:
2140 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2143 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2146 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2149 case DRM_FORMAT_BGRX1010102:
2150 case DRM_FORMAT_BGRA1010102:
2151 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2154 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2157 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2161 DRM_ERROR("Unsupported screen format %s\n",
2162 drm_get_format_name(target_fb->pixel_format));
2166 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2167 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2169 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2170 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2171 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2172 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2173 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2175 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2176 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2177 ARRAY_2D_TILED_THIN1);
2178 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2180 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2181 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2182 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2184 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2185 ADDR_SURF_MICRO_TILING_DISPLAY);
2186 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2188 ARRAY_1D_TILED_THIN1);
2191 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2194 dce_v11_0_vga_enable(crtc, false);
2196 /* Make sure surface address is updated at vertical blank rather than
2199 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2200 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2201 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2202 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2204 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2205 upper_32_bits(fb_location));
2206 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2207 upper_32_bits(fb_location));
2208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2209 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2210 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2211 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2212 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2213 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2216 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2217 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2218 * retain the full precision throughout the pipeline.
2220 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2222 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2224 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2225 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2228 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2230 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2231 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2232 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2233 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2234 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2235 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2237 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2238 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2240 dce_v11_0_grph_enable(crtc, true);
2242 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2247 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2249 viewport_w = crtc->mode.hdisplay;
2250 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2251 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2252 (viewport_w << 16) | viewport_h);
2254 /* set pageflip to happen only at start of vblank interval (front porch) */
2255 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2257 if (!atomic && fb && fb != crtc->primary->fb) {
2258 amdgpu_fb = to_amdgpu_framebuffer(fb);
2259 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2260 r = amdgpu_bo_reserve(rbo, false);
2261 if (unlikely(r != 0))
2263 amdgpu_bo_unpin(rbo);
2264 amdgpu_bo_unreserve(rbo);
2267 /* Bytes per pixel may have changed */
2268 dce_v11_0_bandwidth_update(adev);
2273 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2274 struct drm_display_mode *mode)
2276 struct drm_device *dev = crtc->dev;
2277 struct amdgpu_device *adev = dev->dev_private;
2278 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2281 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2282 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2283 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2285 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2286 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2289 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2291 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2292 struct drm_device *dev = crtc->dev;
2293 struct amdgpu_device *adev = dev->dev_private;
2297 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2299 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2300 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2301 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2303 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2304 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2305 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2307 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2308 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2309 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2311 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2313 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2314 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2315 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2317 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2318 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2319 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2321 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2322 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2324 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2325 for (i = 0; i < 256; i++) {
2326 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2327 (amdgpu_crtc->lut_r[i] << 20) |
2328 (amdgpu_crtc->lut_g[i] << 10) |
2329 (amdgpu_crtc->lut_b[i] << 0));
2332 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2333 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2334 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2335 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2336 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2338 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2339 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2340 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2342 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2343 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2344 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2346 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2347 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2348 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2350 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2351 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2352 /* XXX this only needs to be programmed once per crtc at startup,
2353 * not sure where the best place for it is
2355 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2356 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2357 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2360 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2362 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2363 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2365 switch (amdgpu_encoder->encoder_id) {
2366 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2372 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2378 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2384 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2388 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2394 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2398 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2399 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2400 * monitors a dedicated PPLL must be used. If a particular board has
2401 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2402 * as there is no need to program the PLL itself. If we are not able to
2403 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2404 * avoid messing up an existing monitor.
2406 * Asic specific PLL information
2410 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2412 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2415 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2417 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2418 struct drm_device *dev = crtc->dev;
2419 struct amdgpu_device *adev = dev->dev_private;
2423 if ((adev->asic_type == CHIP_POLARIS10) ||
2424 (adev->asic_type == CHIP_POLARIS11)) {
2425 struct amdgpu_encoder *amdgpu_encoder =
2426 to_amdgpu_encoder(amdgpu_crtc->encoder);
2427 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2429 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2432 switch (amdgpu_encoder->encoder_id) {
2433 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2435 return ATOM_COMBOPHY_PLL1;
2437 return ATOM_COMBOPHY_PLL0;
2439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2441 return ATOM_COMBOPHY_PLL3;
2443 return ATOM_COMBOPHY_PLL2;
2445 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2447 return ATOM_COMBOPHY_PLL5;
2449 return ATOM_COMBOPHY_PLL4;
2452 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2453 return ATOM_PPLL_INVALID;
2457 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2458 if (adev->clock.dp_extclk)
2459 /* skip PPLL programming if using ext clock */
2460 return ATOM_PPLL_INVALID;
2462 /* use the same PPLL for all DP monitors */
2463 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2464 if (pll != ATOM_PPLL_INVALID)
2468 /* use the same PPLL for all monitors with the same clock */
2469 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2470 if (pll != ATOM_PPLL_INVALID)
2474 /* XXX need to determine what plls are available on each DCE11 part */
2475 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2476 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2477 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2479 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2481 DRM_ERROR("unable to allocate a PPLL\n");
2482 return ATOM_PPLL_INVALID;
2484 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2486 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2488 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2490 DRM_ERROR("unable to allocate a PPLL\n");
2491 return ATOM_PPLL_INVALID;
2493 return ATOM_PPLL_INVALID;
2496 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2498 struct amdgpu_device *adev = crtc->dev->dev_private;
2499 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2502 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2504 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2506 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2507 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2510 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513 struct amdgpu_device *adev = crtc->dev->dev_private;
2516 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2517 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2518 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2521 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2523 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2524 struct amdgpu_device *adev = crtc->dev->dev_private;
2527 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2528 upper_32_bits(amdgpu_crtc->cursor_addr));
2529 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2530 lower_32_bits(amdgpu_crtc->cursor_addr));
2532 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2533 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2534 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2535 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2538 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2542 struct amdgpu_device *adev = crtc->dev->dev_private;
2543 int xorigin = 0, yorigin = 0;
2545 /* avivo cursor are offset into the total surface */
2548 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2551 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2555 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2559 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2560 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2561 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2562 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2564 amdgpu_crtc->cursor_x = x;
2565 amdgpu_crtc->cursor_y = y;
2570 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2575 dce_v11_0_lock_cursor(crtc, true);
2576 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2577 dce_v11_0_lock_cursor(crtc, false);
2582 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2583 struct drm_file *file_priv,
2590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2591 struct drm_gem_object *obj;
2592 struct amdgpu_bo *aobj;
2596 /* turn off cursor */
2597 dce_v11_0_hide_cursor(crtc);
2602 if ((width > amdgpu_crtc->max_cursor_width) ||
2603 (height > amdgpu_crtc->max_cursor_height)) {
2604 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2608 obj = drm_gem_object_lookup(file_priv, handle);
2610 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2614 aobj = gem_to_amdgpu_bo(obj);
2615 ret = amdgpu_bo_reserve(aobj, false);
2617 drm_gem_object_unreference_unlocked(obj);
2621 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2622 amdgpu_bo_unreserve(aobj);
2624 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2625 drm_gem_object_unreference_unlocked(obj);
2629 amdgpu_crtc->cursor_width = width;
2630 amdgpu_crtc->cursor_height = height;
2632 dce_v11_0_lock_cursor(crtc, true);
2634 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2635 hot_y != amdgpu_crtc->cursor_hot_y) {
2638 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2639 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2641 dce_v11_0_cursor_move_locked(crtc, x, y);
2643 amdgpu_crtc->cursor_hot_x = hot_x;
2644 amdgpu_crtc->cursor_hot_y = hot_y;
2647 dce_v11_0_show_cursor(crtc);
2648 dce_v11_0_lock_cursor(crtc, false);
2651 if (amdgpu_crtc->cursor_bo) {
2652 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2653 ret = amdgpu_bo_reserve(aobj, false);
2654 if (likely(ret == 0)) {
2655 amdgpu_bo_unpin(aobj);
2656 amdgpu_bo_unreserve(aobj);
2658 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2661 amdgpu_crtc->cursor_bo = obj;
2665 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2667 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2669 if (amdgpu_crtc->cursor_bo) {
2670 dce_v11_0_lock_cursor(crtc, true);
2672 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2673 amdgpu_crtc->cursor_y);
2675 dce_v11_0_show_cursor(crtc);
2677 dce_v11_0_lock_cursor(crtc, false);
2681 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2682 u16 *blue, uint32_t size)
2684 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2687 /* userspace palettes are always correct as is */
2688 for (i = 0; i < size; i++) {
2689 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2690 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2691 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2693 dce_v11_0_crtc_load_lut(crtc);
2698 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2700 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2702 drm_crtc_cleanup(crtc);
2706 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2707 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2708 .cursor_move = dce_v11_0_crtc_cursor_move,
2709 .gamma_set = dce_v11_0_crtc_gamma_set,
2710 .set_config = amdgpu_crtc_set_config,
2711 .destroy = dce_v11_0_crtc_destroy,
2712 .page_flip = amdgpu_crtc_page_flip,
2715 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2717 struct drm_device *dev = crtc->dev;
2718 struct amdgpu_device *adev = dev->dev_private;
2719 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2723 case DRM_MODE_DPMS_ON:
2724 amdgpu_crtc->enabled = true;
2725 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2726 dce_v11_0_vga_enable(crtc, true);
2727 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2728 dce_v11_0_vga_enable(crtc, false);
2729 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2730 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2731 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2732 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2733 drm_crtc_vblank_on(crtc);
2734 dce_v11_0_crtc_load_lut(crtc);
2736 case DRM_MODE_DPMS_STANDBY:
2737 case DRM_MODE_DPMS_SUSPEND:
2738 case DRM_MODE_DPMS_OFF:
2739 drm_crtc_vblank_off(crtc);
2740 if (amdgpu_crtc->enabled) {
2741 dce_v11_0_vga_enable(crtc, true);
2742 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2743 dce_v11_0_vga_enable(crtc, false);
2745 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2746 amdgpu_crtc->enabled = false;
2749 /* adjust pm to dpms */
2750 amdgpu_pm_compute_clocks(adev);
2753 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2755 /* disable crtc pair power gating before programming */
2756 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2757 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2758 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2761 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2763 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2764 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2767 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2769 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2770 struct drm_device *dev = crtc->dev;
2771 struct amdgpu_device *adev = dev->dev_private;
2772 struct amdgpu_atom_ss ss;
2775 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2776 if (crtc->primary->fb) {
2778 struct amdgpu_framebuffer *amdgpu_fb;
2779 struct amdgpu_bo *rbo;
2781 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2782 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2783 r = amdgpu_bo_reserve(rbo, false);
2785 DRM_ERROR("failed to reserve rbo before unpin\n");
2787 amdgpu_bo_unpin(rbo);
2788 amdgpu_bo_unreserve(rbo);
2791 /* disable the GRPH */
2792 dce_v11_0_grph_enable(crtc, false);
2794 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2796 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2797 if (adev->mode_info.crtcs[i] &&
2798 adev->mode_info.crtcs[i]->enabled &&
2799 i != amdgpu_crtc->crtc_id &&
2800 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2801 /* one other crtc is using this pll don't turn
2808 switch (amdgpu_crtc->pll_id) {
2812 /* disable the ppll */
2813 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2814 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2816 case ATOM_COMBOPHY_PLL0:
2817 case ATOM_COMBOPHY_PLL1:
2818 case ATOM_COMBOPHY_PLL2:
2819 case ATOM_COMBOPHY_PLL3:
2820 case ATOM_COMBOPHY_PLL4:
2821 case ATOM_COMBOPHY_PLL5:
2822 /* disable the ppll */
2823 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2824 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2830 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2831 amdgpu_crtc->adjusted_clock = 0;
2832 amdgpu_crtc->encoder = NULL;
2833 amdgpu_crtc->connector = NULL;
2836 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2837 struct drm_display_mode *mode,
2838 struct drm_display_mode *adjusted_mode,
2839 int x, int y, struct drm_framebuffer *old_fb)
2841 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2842 struct drm_device *dev = crtc->dev;
2843 struct amdgpu_device *adev = dev->dev_private;
2845 if (!amdgpu_crtc->adjusted_clock)
2848 if ((adev->asic_type == CHIP_POLARIS10) ||
2849 (adev->asic_type == CHIP_POLARIS11)) {
2850 struct amdgpu_encoder *amdgpu_encoder =
2851 to_amdgpu_encoder(amdgpu_crtc->encoder);
2853 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2855 /* SetPixelClock calculates the plls and ss values now */
2856 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2857 amdgpu_crtc->pll_id,
2858 encoder_mode, amdgpu_encoder->encoder_id,
2859 adjusted_mode->clock, 0, 0, 0, 0,
2860 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2862 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2864 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2865 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2866 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2867 amdgpu_atombios_crtc_scaler_setup(crtc);
2868 dce_v11_0_cursor_reset(crtc);
2869 /* update the hw version fpr dpm */
2870 amdgpu_crtc->hw_mode = *adjusted_mode;
2875 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2876 const struct drm_display_mode *mode,
2877 struct drm_display_mode *adjusted_mode)
2879 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2880 struct drm_device *dev = crtc->dev;
2881 struct drm_encoder *encoder;
2883 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2885 if (encoder->crtc == crtc) {
2886 amdgpu_crtc->encoder = encoder;
2887 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2891 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2892 amdgpu_crtc->encoder = NULL;
2893 amdgpu_crtc->connector = NULL;
2896 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2898 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2901 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2902 /* if we can't get a PPLL for a non-DP encoder, fail */
2903 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2904 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2910 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2911 struct drm_framebuffer *old_fb)
2913 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2916 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2917 struct drm_framebuffer *fb,
2918 int x, int y, enum mode_set_atomic state)
2920 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2923 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2924 .dpms = dce_v11_0_crtc_dpms,
2925 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2926 .mode_set = dce_v11_0_crtc_mode_set,
2927 .mode_set_base = dce_v11_0_crtc_set_base,
2928 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2929 .prepare = dce_v11_0_crtc_prepare,
2930 .commit = dce_v11_0_crtc_commit,
2931 .load_lut = dce_v11_0_crtc_load_lut,
2932 .disable = dce_v11_0_crtc_disable,
2935 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2937 struct amdgpu_crtc *amdgpu_crtc;
2940 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2941 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2942 if (amdgpu_crtc == NULL)
2945 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2947 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2948 amdgpu_crtc->crtc_id = index;
2949 adev->mode_info.crtcs[index] = amdgpu_crtc;
2951 amdgpu_crtc->max_cursor_width = 128;
2952 amdgpu_crtc->max_cursor_height = 128;
2953 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2954 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2956 for (i = 0; i < 256; i++) {
2957 amdgpu_crtc->lut_r[i] = i << 2;
2958 amdgpu_crtc->lut_g[i] = i << 2;
2959 amdgpu_crtc->lut_b[i] = i << 2;
2962 switch (amdgpu_crtc->crtc_id) {
2965 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2968 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2971 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2974 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2977 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2980 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2984 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2985 amdgpu_crtc->adjusted_clock = 0;
2986 amdgpu_crtc->encoder = NULL;
2987 amdgpu_crtc->connector = NULL;
2988 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2993 static int dce_v11_0_early_init(void *handle)
2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2997 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2998 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
3000 dce_v11_0_set_display_funcs(adev);
3001 dce_v11_0_set_irq_funcs(adev);
3003 switch (adev->asic_type) {
3005 adev->mode_info.num_crtc = 3;
3006 adev->mode_info.num_hpd = 6;
3007 adev->mode_info.num_dig = 9;
3010 adev->mode_info.num_crtc = 2;
3011 adev->mode_info.num_hpd = 6;
3012 adev->mode_info.num_dig = 9;
3014 case CHIP_POLARIS10:
3015 adev->mode_info.num_crtc = 6;
3016 adev->mode_info.num_hpd = 6;
3017 adev->mode_info.num_dig = 6;
3019 case CHIP_POLARIS11:
3020 adev->mode_info.num_crtc = 5;
3021 adev->mode_info.num_hpd = 5;
3022 adev->mode_info.num_dig = 5;
3025 /* FIXME: not supported yet */
3032 static int dce_v11_0_sw_init(void *handle)
3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3037 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3038 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3043 for (i = 8; i < 20; i += 2) {
3044 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3050 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3054 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3056 adev->ddev->mode_config.async_page_flip = true;
3058 adev->ddev->mode_config.max_width = 16384;
3059 adev->ddev->mode_config.max_height = 16384;
3061 adev->ddev->mode_config.preferred_depth = 24;
3062 adev->ddev->mode_config.prefer_shadow = 1;
3064 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3066 r = amdgpu_modeset_create_props(adev);
3070 adev->ddev->mode_config.max_width = 16384;
3071 adev->ddev->mode_config.max_height = 16384;
3074 /* allocate crtcs */
3075 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3076 r = dce_v11_0_crtc_init(adev, i);
3081 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3082 amdgpu_print_display_setup(adev->ddev);
3087 r = dce_v11_0_afmt_init(adev);
3091 r = dce_v11_0_audio_init(adev);
3095 drm_kms_helper_poll_init(adev->ddev);
3097 adev->mode_info.mode_config_initialized = true;
3101 static int dce_v11_0_sw_fini(void *handle)
3103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3105 kfree(adev->mode_info.bios_hardcoded_edid);
3107 drm_kms_helper_poll_fini(adev->ddev);
3109 dce_v11_0_audio_fini(adev);
3111 dce_v11_0_afmt_fini(adev);
3113 adev->mode_info.mode_config_initialized = false;
3118 static int dce_v11_0_hw_init(void *handle)
3121 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3123 dce_v11_0_init_golden_registers(adev);
3125 /* init dig PHYs, disp eng pll */
3126 amdgpu_atombios_crtc_powergate_init(adev);
3127 amdgpu_atombios_encoder_init_dig(adev);
3128 if ((adev->asic_type == CHIP_POLARIS10) ||
3129 (adev->asic_type == CHIP_POLARIS11)) {
3130 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3131 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3132 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3133 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3135 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3138 /* initialize hpd */
3139 dce_v11_0_hpd_init(adev);
3141 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3142 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3145 dce_v11_0_pageflip_interrupt_init(adev);
3150 static int dce_v11_0_hw_fini(void *handle)
3153 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3155 dce_v11_0_hpd_fini(adev);
3157 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3158 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3161 dce_v11_0_pageflip_interrupt_fini(adev);
3166 static int dce_v11_0_suspend(void *handle)
3168 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3170 amdgpu_atombios_scratch_regs_save(adev);
3172 return dce_v11_0_hw_fini(handle);
3175 static int dce_v11_0_resume(void *handle)
3177 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3180 ret = dce_v11_0_hw_init(handle);
3182 amdgpu_atombios_scratch_regs_restore(adev);
3184 /* turn on the BL */
3185 if (adev->mode_info.bl_encoder) {
3186 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3187 adev->mode_info.bl_encoder);
3188 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3195 static bool dce_v11_0_is_idle(void *handle)
3200 static int dce_v11_0_wait_for_idle(void *handle)
3205 static int dce_v11_0_soft_reset(void *handle)
3207 u32 srbm_soft_reset = 0, tmp;
3208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3210 if (dce_v11_0_is_display_hung(adev))
3211 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3213 if (srbm_soft_reset) {
3214 tmp = RREG32(mmSRBM_SOFT_RESET);
3215 tmp |= srbm_soft_reset;
3216 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3217 WREG32(mmSRBM_SOFT_RESET, tmp);
3218 tmp = RREG32(mmSRBM_SOFT_RESET);
3222 tmp &= ~srbm_soft_reset;
3223 WREG32(mmSRBM_SOFT_RESET, tmp);
3224 tmp = RREG32(mmSRBM_SOFT_RESET);
3226 /* Wait a little for things to settle down */
3232 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3234 enum amdgpu_interrupt_state state)
3236 u32 lb_interrupt_mask;
3238 if (crtc >= adev->mode_info.num_crtc) {
3239 DRM_DEBUG("invalid crtc %d\n", crtc);
3244 case AMDGPU_IRQ_STATE_DISABLE:
3245 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3246 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3247 VBLANK_INTERRUPT_MASK, 0);
3248 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3250 case AMDGPU_IRQ_STATE_ENABLE:
3251 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3252 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3253 VBLANK_INTERRUPT_MASK, 1);
3254 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3261 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3263 enum amdgpu_interrupt_state state)
3265 u32 lb_interrupt_mask;
3267 if (crtc >= adev->mode_info.num_crtc) {
3268 DRM_DEBUG("invalid crtc %d\n", crtc);
3273 case AMDGPU_IRQ_STATE_DISABLE:
3274 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3275 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3276 VLINE_INTERRUPT_MASK, 0);
3277 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3279 case AMDGPU_IRQ_STATE_ENABLE:
3280 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3281 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3282 VLINE_INTERRUPT_MASK, 1);
3283 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3290 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3291 struct amdgpu_irq_src *source,
3293 enum amdgpu_interrupt_state state)
3297 if (hpd >= adev->mode_info.num_hpd) {
3298 DRM_DEBUG("invalid hdp %d\n", hpd);
3303 case AMDGPU_IRQ_STATE_DISABLE:
3304 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3305 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3306 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3308 case AMDGPU_IRQ_STATE_ENABLE:
3309 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3310 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3311 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3320 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3321 struct amdgpu_irq_src *source,
3323 enum amdgpu_interrupt_state state)
3326 case AMDGPU_CRTC_IRQ_VBLANK1:
3327 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3329 case AMDGPU_CRTC_IRQ_VBLANK2:
3330 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3332 case AMDGPU_CRTC_IRQ_VBLANK3:
3333 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3335 case AMDGPU_CRTC_IRQ_VBLANK4:
3336 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3338 case AMDGPU_CRTC_IRQ_VBLANK5:
3339 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3341 case AMDGPU_CRTC_IRQ_VBLANK6:
3342 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3344 case AMDGPU_CRTC_IRQ_VLINE1:
3345 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3347 case AMDGPU_CRTC_IRQ_VLINE2:
3348 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3350 case AMDGPU_CRTC_IRQ_VLINE3:
3351 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3353 case AMDGPU_CRTC_IRQ_VLINE4:
3354 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3356 case AMDGPU_CRTC_IRQ_VLINE5:
3357 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3359 case AMDGPU_CRTC_IRQ_VLINE6:
3360 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3368 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3369 struct amdgpu_irq_src *src,
3371 enum amdgpu_interrupt_state state)
3375 if (type >= adev->mode_info.num_crtc) {
3376 DRM_ERROR("invalid pageflip crtc %d\n", type);
3380 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3381 if (state == AMDGPU_IRQ_STATE_DISABLE)
3382 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3383 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3385 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3386 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3391 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3392 struct amdgpu_irq_src *source,
3393 struct amdgpu_iv_entry *entry)
3395 unsigned long flags;
3397 struct amdgpu_crtc *amdgpu_crtc;
3398 struct amdgpu_flip_work *works;
3400 crtc_id = (entry->src_id - 8) >> 1;
3401 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3403 if (crtc_id >= adev->mode_info.num_crtc) {
3404 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3408 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3409 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3410 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3411 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3413 /* IRQ could occur when in initial stage */
3414 if(amdgpu_crtc == NULL)
3417 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3418 works = amdgpu_crtc->pflip_works;
3419 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3420 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3421 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3422 amdgpu_crtc->pflip_status,
3423 AMDGPU_FLIP_SUBMITTED);
3424 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3428 /* page flip completed. clean up */
3429 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3430 amdgpu_crtc->pflip_works = NULL;
3432 /* wakeup usersapce */
3434 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3436 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3438 drm_crtc_vblank_put(&amdgpu_crtc->base);
3439 schedule_work(&works->unpin_work);
3444 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3449 if (hpd >= adev->mode_info.num_hpd) {
3450 DRM_DEBUG("invalid hdp %d\n", hpd);
3454 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3455 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3456 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3459 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3464 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3465 DRM_DEBUG("invalid crtc %d\n", crtc);
3469 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3470 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3471 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3474 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3479 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3480 DRM_DEBUG("invalid crtc %d\n", crtc);
3484 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3485 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3486 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3489 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3490 struct amdgpu_irq_src *source,
3491 struct amdgpu_iv_entry *entry)
3493 unsigned crtc = entry->src_id - 1;
3494 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3495 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3497 switch (entry->src_data) {
3498 case 0: /* vblank */
3499 if (disp_int & interrupt_status_offsets[crtc].vblank)
3500 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3502 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3504 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3505 drm_handle_vblank(adev->ddev, crtc);
3507 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3511 if (disp_int & interrupt_status_offsets[crtc].vline)
3512 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3514 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3516 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3520 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3527 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3528 struct amdgpu_irq_src *source,
3529 struct amdgpu_iv_entry *entry)
3531 uint32_t disp_int, mask;
3534 if (entry->src_data >= adev->mode_info.num_hpd) {
3535 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3539 hpd = entry->src_data;
3540 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3541 mask = interrupt_status_offsets[hpd].hpd;
3543 if (disp_int & mask) {
3544 dce_v11_0_hpd_int_ack(adev, hpd);
3545 schedule_work(&adev->hotplug_work);
3546 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3552 static int dce_v11_0_set_clockgating_state(void *handle,
3553 enum amd_clockgating_state state)
3558 static int dce_v11_0_set_powergating_state(void *handle,
3559 enum amd_powergating_state state)
3564 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3565 .name = "dce_v11_0",
3566 .early_init = dce_v11_0_early_init,
3568 .sw_init = dce_v11_0_sw_init,
3569 .sw_fini = dce_v11_0_sw_fini,
3570 .hw_init = dce_v11_0_hw_init,
3571 .hw_fini = dce_v11_0_hw_fini,
3572 .suspend = dce_v11_0_suspend,
3573 .resume = dce_v11_0_resume,
3574 .is_idle = dce_v11_0_is_idle,
3575 .wait_for_idle = dce_v11_0_wait_for_idle,
3576 .soft_reset = dce_v11_0_soft_reset,
3577 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3578 .set_powergating_state = dce_v11_0_set_powergating_state,
3582 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3583 struct drm_display_mode *mode,
3584 struct drm_display_mode *adjusted_mode)
3586 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3588 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3590 /* need to call this here rather than in prepare() since we need some crtc info */
3591 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3593 /* set scaler clears this on some chips */
3594 dce_v11_0_set_interleave(encoder->crtc, mode);
3596 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3597 dce_v11_0_afmt_enable(encoder, true);
3598 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3602 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3604 struct amdgpu_device *adev = encoder->dev->dev_private;
3605 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3606 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3608 if ((amdgpu_encoder->active_device &
3609 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3610 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3611 ENCODER_OBJECT_ID_NONE)) {
3612 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3614 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3615 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3616 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3620 amdgpu_atombios_scratch_regs_lock(adev, true);
3623 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3625 /* select the clock/data port if it uses a router */
3626 if (amdgpu_connector->router.cd_valid)
3627 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3629 /* turn eDP panel on for mode set */
3630 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3631 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3632 ATOM_TRANSMITTER_ACTION_POWER_ON);
3635 /* this is needed for the pll/ss setup to work correctly in some cases */
3636 amdgpu_atombios_encoder_set_crtc_source(encoder);
3637 /* set up the FMT blocks */
3638 dce_v11_0_program_fmt(encoder);
3641 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3643 struct drm_device *dev = encoder->dev;
3644 struct amdgpu_device *adev = dev->dev_private;
3646 /* need to call this here as we need the crtc set up */
3647 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3648 amdgpu_atombios_scratch_regs_lock(adev, false);
3651 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3653 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3654 struct amdgpu_encoder_atom_dig *dig;
3656 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3658 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3659 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3660 dce_v11_0_afmt_enable(encoder, false);
3661 dig = amdgpu_encoder->enc_priv;
3662 dig->dig_encoder = -1;
3664 amdgpu_encoder->active_device = 0;
3667 /* these are handled by the primary encoders */
3668 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3673 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3679 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3680 struct drm_display_mode *mode,
3681 struct drm_display_mode *adjusted_mode)
3686 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3692 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3697 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3698 .dpms = dce_v11_0_ext_dpms,
3699 .prepare = dce_v11_0_ext_prepare,
3700 .mode_set = dce_v11_0_ext_mode_set,
3701 .commit = dce_v11_0_ext_commit,
3702 .disable = dce_v11_0_ext_disable,
3703 /* no detect for TMDS/LVDS yet */
3706 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3707 .dpms = amdgpu_atombios_encoder_dpms,
3708 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3709 .prepare = dce_v11_0_encoder_prepare,
3710 .mode_set = dce_v11_0_encoder_mode_set,
3711 .commit = dce_v11_0_encoder_commit,
3712 .disable = dce_v11_0_encoder_disable,
3713 .detect = amdgpu_atombios_encoder_dig_detect,
3716 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3717 .dpms = amdgpu_atombios_encoder_dpms,
3718 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3719 .prepare = dce_v11_0_encoder_prepare,
3720 .mode_set = dce_v11_0_encoder_mode_set,
3721 .commit = dce_v11_0_encoder_commit,
3722 .detect = amdgpu_atombios_encoder_dac_detect,
3725 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3728 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3729 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3730 kfree(amdgpu_encoder->enc_priv);
3731 drm_encoder_cleanup(encoder);
3732 kfree(amdgpu_encoder);
3735 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3736 .destroy = dce_v11_0_encoder_destroy,
3739 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3740 uint32_t encoder_enum,
3741 uint32_t supported_device,
3744 struct drm_device *dev = adev->ddev;
3745 struct drm_encoder *encoder;
3746 struct amdgpu_encoder *amdgpu_encoder;
3748 /* see if we already added it */
3749 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3750 amdgpu_encoder = to_amdgpu_encoder(encoder);
3751 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3752 amdgpu_encoder->devices |= supported_device;
3759 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3760 if (!amdgpu_encoder)
3763 encoder = &amdgpu_encoder->base;
3764 switch (adev->mode_info.num_crtc) {
3766 encoder->possible_crtcs = 0x1;
3770 encoder->possible_crtcs = 0x3;
3773 encoder->possible_crtcs = 0xf;
3776 encoder->possible_crtcs = 0x3f;
3780 amdgpu_encoder->enc_priv = NULL;
3782 amdgpu_encoder->encoder_enum = encoder_enum;
3783 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3784 amdgpu_encoder->devices = supported_device;
3785 amdgpu_encoder->rmx_type = RMX_OFF;
3786 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3787 amdgpu_encoder->is_ext_encoder = false;
3788 amdgpu_encoder->caps = caps;
3790 switch (amdgpu_encoder->encoder_id) {
3791 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3792 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3793 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3794 DRM_MODE_ENCODER_DAC, NULL);
3795 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3797 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3801 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3802 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3803 amdgpu_encoder->rmx_type = RMX_FULL;
3804 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3805 DRM_MODE_ENCODER_LVDS, NULL);
3806 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3807 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3808 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3809 DRM_MODE_ENCODER_DAC, NULL);
3810 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3812 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3813 DRM_MODE_ENCODER_TMDS, NULL);
3814 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3816 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3818 case ENCODER_OBJECT_ID_SI170B:
3819 case ENCODER_OBJECT_ID_CH7303:
3820 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3821 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3822 case ENCODER_OBJECT_ID_TITFP513:
3823 case ENCODER_OBJECT_ID_VT1623:
3824 case ENCODER_OBJECT_ID_HDMI_SI1930:
3825 case ENCODER_OBJECT_ID_TRAVIS:
3826 case ENCODER_OBJECT_ID_NUTMEG:
3827 /* these are handled by the primary encoders */
3828 amdgpu_encoder->is_ext_encoder = true;
3829 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3830 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3831 DRM_MODE_ENCODER_LVDS, NULL);
3832 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3833 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3834 DRM_MODE_ENCODER_DAC, NULL);
3836 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3837 DRM_MODE_ENCODER_TMDS, NULL);
3838 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3843 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3844 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3845 .bandwidth_update = &dce_v11_0_bandwidth_update,
3846 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3847 .vblank_wait = &dce_v11_0_vblank_wait,
3848 .is_display_hung = &dce_v11_0_is_display_hung,
3849 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3850 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3851 .hpd_sense = &dce_v11_0_hpd_sense,
3852 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3853 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3854 .page_flip = &dce_v11_0_page_flip,
3855 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3856 .add_encoder = &dce_v11_0_encoder_add,
3857 .add_connector = &amdgpu_connector_add,
3858 .stop_mc_access = &dce_v11_0_stop_mc_access,
3859 .resume_mc_access = &dce_v11_0_resume_mc_access,
3862 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3864 if (adev->mode_info.funcs == NULL)
3865 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3868 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3869 .set = dce_v11_0_set_crtc_irq_state,
3870 .process = dce_v11_0_crtc_irq,
3873 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3874 .set = dce_v11_0_set_pageflip_irq_state,
3875 .process = dce_v11_0_pageflip_irq,
3878 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3879 .set = dce_v11_0_set_hpd_irq_state,
3880 .process = dce_v11_0_hpd_irq,
3883 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3885 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3886 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3888 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3889 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3891 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3892 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;