drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  63
  64
  65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  66 {
  67         SDMA0_REGISTER_OFFSET,
  68         SDMA1_REGISTER_OFFSET
  69 };
  70
  71 static const u32 golden_settings_tonga_a11[] =
  72 {
  73         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  74         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  75         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  76         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  77         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  78         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  79         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  80         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  81         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  82         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  83 };
  84
  85 static const u32 tonga_mgcg_cgcg_init[] =
  86 {
  87         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  88         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  89 };
  90
  91 static const u32 golden_settings_fiji_a10[] =
  92 {
  93         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  94         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  95         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  96         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  97         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  98         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  99         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 100         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 101 };
 102
 103 static const u32 fiji_mgcg_cgcg_init[] =
 104 {
 105         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 106         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 107 };
 108
 109 static const u32 golden_settings_polaris11_a11[] =
 110 {
 111         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 112         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 113         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 114         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 115         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 116         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 117         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 118         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 119         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 120         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 121 };
 122
 123 static const u32 golden_settings_polaris10_a11[] =
 124 {
 125         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 131         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 132         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 133         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 134         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 135 };
 136
 137 static const u32 cz_golden_settings_a11[] =
 138 {
 139         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 140         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 141         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 142         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 143         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 144         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 145         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 146         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 147         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 148         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 149         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 150         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 151 };
 152
 153 static const u32 cz_mgcg_cgcg_init[] =
 154 {
 155         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 156         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 157 };
 158
 159 static const u32 stoney_golden_settings_a11[] =
 160 {
 161         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 162         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 163         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 164         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 165 };
 166
 167 static const u32 stoney_mgcg_cgcg_init[] =
 168 {
 169         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 170 };
 171
 172 /*
 173  * sDMA - System DMA
 174  * Starting with CIK, the GPU has new asynchronous
 175  * DMA engines.  These engines are used for compute
 176  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 177  * and each one supports 1 ring buffer used for gfx
 178  * and 2 queues used for compute.
 179  *
 180  * The programming model is very similar to the CP
 181  * (ring buffer, IBs, etc.), but sDMA has it's own
 182  * packet format that is different from the PM4 format
 183  * used by the CP. sDMA supports copying data, writing
 184  * embedded data, solid fills, and a number of other
 185  * things.  It also has support for tiling/detiling of
 186  * buffers.
 187  */
 188
 189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 190 {
 191         switch (adev->asic_type) {
 192         case CHIP_FIJI:
 193                 amdgpu_program_register_sequence(adev,
 194                                                  fiji_mgcg_cgcg_init,
 195                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 196                 amdgpu_program_register_sequence(adev,
 197                                                  golden_settings_fiji_a10,
 198                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 199                 break;
 200         case CHIP_TONGA:
 201                 amdgpu_program_register_sequence(adev,
 202                                                  tonga_mgcg_cgcg_init,
 203                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 204                 amdgpu_program_register_sequence(adev,
 205                                                  golden_settings_tonga_a11,
 206                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 207                 break;
 208         case CHIP_POLARIS11:
 209                 amdgpu_program_register_sequence(adev,
 210                                                  golden_settings_polaris11_a11,
 211                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 212                 break;
 213         case CHIP_POLARIS10:
 214                 amdgpu_program_register_sequence(adev,
 215                                                  golden_settings_polaris10_a11,
 216                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 217                 break;
 218         case CHIP_CARRIZO:
 219                 amdgpu_program_register_sequence(adev,
 220                                                  cz_mgcg_cgcg_init,
 221                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 222                 amdgpu_program_register_sequence(adev,
 223                                                  cz_golden_settings_a11,
 224                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 225                 break;
 226         case CHIP_STONEY:
 227                 amdgpu_program_register_sequence(adev,
 228                                                  stoney_mgcg_cgcg_init,
 229                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 230                 amdgpu_program_register_sequence(adev,
 231                                                  stoney_golden_settings_a11,
 232                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 233                 break;
 234         default:
 235                 break;
 236         }
 237 }
 238
 239 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 240 {
 241         int i;
 242         for (i = 0; i < adev->sdma.num_instances; i++) {
 243                 release_firmware(adev->sdma.instance[i].fw);
 244                 adev->sdma.instance[i].fw = NULL;
 245         }
 246 }
 247
 248 /**
 249  * sdma_v3_0_init_microcode - load ucode images from disk
 250  *
 251  * @adev: amdgpu_device pointer
 252  *
 253  * Use the firmware interface to load the ucode images into
 254  * the driver (not loaded into hw).
 255  * Returns 0 on success, error on failure.
 256  */
 257 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 258 {
 259         const char *chip_name;
 260         char fw_name[30];
 261         int err = 0, i;
 262         struct amdgpu_firmware_info *info = NULL;
 263         const struct common_firmware_header *header = NULL;
 264         const struct sdma_firmware_header_v1_0 *hdr;
 265
 266         DRM_DEBUG("\n");
 267
 268         switch (adev->asic_type) {
 269         case CHIP_TONGA:
 270                 chip_name = "tonga";
 271                 break;
 272         case CHIP_FIJI:
 273                 chip_name = "fiji";
 274                 break;
 275         case CHIP_POLARIS11:
 276                 chip_name = "polaris11";
 277                 break;
 278         case CHIP_POLARIS10:
 279                 chip_name = "polaris10";
 280                 break;
 281         case CHIP_CARRIZO:
 282                 chip_name = "carrizo";
 283                 break;
 284         case CHIP_STONEY:
 285                 chip_name = "stoney";
 286                 break;
 287         default: BUG();
 288         }
 289
 290         for (i = 0; i < adev->sdma.num_instances; i++) {
 291                 if (i == 0)
 292                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 293                 else
 294                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 295                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 296                 if (err)
 297                         goto out;
 298                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 299                 if (err)
 300                         goto out;
 301                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 302                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 303                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 304                 if (adev->sdma.instance[i].feature_version >= 20)
 305                         adev->sdma.instance[i].burst_nop = true;
 306
 307                 if (adev->firmware.smu_load) {
 308                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 309                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 310                         info->fw = adev->sdma.instance[i].fw;
 311                         header = (const struct common_firmware_header *)info->fw->data;
 312                         adev->firmware.fw_size +=
 313                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 314                 }
 315         }
 316 out:
 317         if (err) {
 318                 printk(KERN_ERR
 319                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 320                        fw_name);
 321                 for (i = 0; i < adev->sdma.num_instances; i++) {
 322                         release_firmware(adev->sdma.instance[i].fw);
 323                         adev->sdma.instance[i].fw = NULL;
 324                 }
 325         }
 326         return err;
 327 }
 328
 329 /**
 330  * sdma_v3_0_ring_get_rptr - get the current read pointer
 331  *
 332  * @ring: amdgpu ring pointer
 333  *
 334  * Get the current rptr from the hardware (VI+).
 335  */
 336 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 337 {
 338         u32 rptr;
 339
 340         /* XXX check if swapping is necessary on BE */
 341         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 342
 343         return rptr;
 344 }
 345
 346 /**
 347  * sdma_v3_0_ring_get_wptr - get the current write pointer
 348  *
 349  * @ring: amdgpu ring pointer
 350  *
 351  * Get the current wptr from the hardware (VI+).
 352  */
 353 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 354 {
 355         struct amdgpu_device *adev = ring->adev;
 356         u32 wptr;
 357
 358         if (ring->use_doorbell) {
 359                 /* XXX check if swapping is necessary on BE */
 360                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 361         } else {
 362                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 363
 364                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 365         }
 366
 367         return wptr;
 368 }
 369
 370 /**
 371  * sdma_v3_0_ring_set_wptr - commit the write pointer
 372  *
 373  * @ring: amdgpu ring pointer
 374  *
 375  * Write the wptr back to the hardware (VI+).
 376  */
 377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 378 {
 379         struct amdgpu_device *adev = ring->adev;
 380
 381         if (ring->use_doorbell) {
 382                 /* XXX check if swapping is necessary on BE */
 383                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 384                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 385         } else {
 386                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 387
 388                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 389         }
 390 }
 391
 392 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 393 {
 394         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 395         int i;
 396
 397         for (i = 0; i < count; i++)
 398                 if (sdma && sdma->burst_nop && (i == 0))
 399                         amdgpu_ring_write(ring, ring->nop |
 400                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 401                 else
 402                         amdgpu_ring_write(ring, ring->nop);
 403 }
 404
 405 /**
 406  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 407  *
 408  * @ring: amdgpu ring pointer
 409  * @ib: IB object to schedule
 410  *
 411  * Schedule an IB in the DMA ring (VI).
 412  */
 413 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 414                                    struct amdgpu_ib *ib,
 415                                    unsigned vm_id, bool ctx_switch)
 416 {
 417         u32 vmid = vm_id & 0xf;
 418
 419         /* IB packet must end on a 8 DW boundary */
 420         sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 421
 422         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 423                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 424         /* base must be 32 byte aligned */
 425         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 426         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 427         amdgpu_ring_write(ring, ib->length_dw);
 428         amdgpu_ring_write(ring, 0);
 429         amdgpu_ring_write(ring, 0);
 430
 431 }
 432
 433 /**
 434  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 435  *
 436  * @ring: amdgpu ring pointer
 437  *
 438  * Emit an hdp flush packet on the requested DMA ring.
 439  */
 440 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 441 {
 442         u32 ref_and_mask = 0;
 443
 444         if (ring == &ring->adev->sdma.instance[0].ring)
 445                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 446         else
 447                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 448
 449         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 450                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 451                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 452         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 453         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 454         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 455         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 456         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 457                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 458 }
 459
 460 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 461 {
 462         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 463                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 464         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 465         amdgpu_ring_write(ring, 1);
 466 }
 467
 468 /**
 469  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 470  *
 471  * @ring: amdgpu ring pointer
 472  * @fence: amdgpu fence object
 473  *
 474  * Add a DMA fence packet to the ring to write
 475  * the fence seq number and DMA trap packet to generate
 476  * an interrupt if needed (VI).
 477  */
 478 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 479                                       unsigned flags)
 480 {
 481         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 482         /* write the fence */
 483         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 484         amdgpu_ring_write(ring, lower_32_bits(addr));
 485         amdgpu_ring_write(ring, upper_32_bits(addr));
 486         amdgpu_ring_write(ring, lower_32_bits(seq));
 487
 488         /* optionally write high bits as well */
 489         if (write64bit) {
 490                 addr += 4;
 491                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 492                 amdgpu_ring_write(ring, lower_32_bits(addr));
 493                 amdgpu_ring_write(ring, upper_32_bits(addr));
 494                 amdgpu_ring_write(ring, upper_32_bits(seq));
 495         }
 496
 497         /* generate an interrupt */
 498         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 499         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 500 }
 501
 502 /**
 503  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Stop the gfx async dma ring buffers (VI).
 508  */
 509 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 510 {
 511         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 512         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 513         u32 rb_cntl, ib_cntl;
 514         int i;
 515
 516         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 517             (adev->mman.buffer_funcs_ring == sdma1))
 518                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 519
 520         for (i = 0; i < adev->sdma.num_instances; i++) {
 521                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 522                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 523                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 524                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 525                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 526                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 527         }
 528         sdma0->ready = false;
 529         sdma1->ready = false;
 530 }
 531
 532 /**
 533  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 534  *
 535  * @adev: amdgpu_device pointer
 536  *
 537  * Stop the compute async dma queues (VI).
 538  */
 539 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 540 {
 541         /* XXX todo */
 542 }
 543
 544 /**
 545  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 546  *
 547  * @adev: amdgpu_device pointer
 548  * @enable: enable/disable the DMA MEs context switch.
 549  *
 550  * Halt or unhalt the async dma engines context switch (VI).
 551  */
 552 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 553 {
 554         u32 f32_cntl;
 555         int i;
 556
 557         for (i = 0; i < adev->sdma.num_instances; i++) {
 558                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 559                 if (enable)
 560                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 561                                         AUTO_CTXSW_ENABLE, 1);
 562                 else
 563                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 564                                         AUTO_CTXSW_ENABLE, 0);
 565                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 566         }
 567 }
 568
 569 /**
 570  * sdma_v3_0_enable - stop the async dma engines
 571  *
 572  * @adev: amdgpu_device pointer
 573  * @enable: enable/disable the DMA MEs.
 574  *
 575  * Halt or unhalt the async dma engines (VI).
 576  */
 577 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 578 {
 579         u32 f32_cntl;
 580         int i;
 581
 582         if (!enable) {
 583                 sdma_v3_0_gfx_stop(adev);
 584                 sdma_v3_0_rlc_stop(adev);
 585         }
 586
 587         for (i = 0; i < adev->sdma.num_instances; i++) {
 588                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 589                 if (enable)
 590                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 591                 else
 592                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 593                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 594         }
 595 }
 596
 597 /**
 598  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 599  *
 600  * @adev: amdgpu_device pointer
 601  *
 602  * Set up the gfx DMA ring buffers and enable them (VI).
 603  * Returns 0 for success, error for failure.
 604  */
 605 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 606 {
 607         struct amdgpu_ring *ring;
 608         u32 rb_cntl, ib_cntl;
 609         u32 rb_bufsz;
 610         u32 wb_offset;
 611         u32 doorbell;
 612         int i, j, r;
 613
 614         for (i = 0; i < adev->sdma.num_instances; i++) {
 615                 ring = &adev->sdma.instance[i].ring;
 616                 wb_offset = (ring->rptr_offs * 4);
 617
 618                 mutex_lock(&adev->srbm_mutex);
 619                 for (j = 0; j < 16; j++) {
 620                         vi_srbm_select(adev, 0, 0, 0, j);
 621                         /* SDMA GFX */
 622                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 623                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 624                 }
 625                 vi_srbm_select(adev, 0, 0, 0, 0);
 626                 mutex_unlock(&adev->srbm_mutex);
 627
 628                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 629                        adev->gfx.config.gb_addr_config & 0x70);
 630
 631                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 632
 633                 /* Set ring buffer size in dwords */
 634                 rb_bufsz = order_base_2(ring->ring_size / 4);
 635                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 636                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 637 #ifdef __BIG_ENDIAN
 638                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 639                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 640                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 641 #endif
 642                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 643
 644                 /* Initialize the ring buffer's read and write pointers */
 645                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 646                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 647                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 648                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 649
 650                 /* set the wb address whether it's enabled or not */
 651                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 652                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 653                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 654                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 655
 656                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 657
 658                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 659                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 660
 661                 ring->wptr = 0;
 662                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 663
 664                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 665
 666                 if (ring->use_doorbell) {
 667                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 668                                                  OFFSET, ring->doorbell_index);
 669                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 670                 } else {
 671                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 672                 }
 673                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 674
 675                 /* enable DMA RB */
 676                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 677                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 678
 679                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 680                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 681 #ifdef __BIG_ENDIAN
 682                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 683 #endif
 684                 /* enable DMA IBs */
 685                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 686
 687                 ring->ready = true;
 688         }
 689
 690         /* unhalt the MEs */
 691         sdma_v3_0_enable(adev, true);
 692         /* enable sdma ring preemption */
 693         sdma_v3_0_ctx_switch_enable(adev, true);
 694
 695         for (i = 0; i < adev->sdma.num_instances; i++) {
 696                 ring = &adev->sdma.instance[i].ring;
 697                 r = amdgpu_ring_test_ring(ring);
 698                 if (r) {
 699                         ring->ready = false;
 700                         return r;
 701                 }
 702
 703                 if (adev->mman.buffer_funcs_ring == ring)
 704                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 705         }
 706
 707         return 0;
 708 }
 709
 710 /**
 711  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 712  *
 713  * @adev: amdgpu_device pointer
 714  *
 715  * Set up the compute DMA queues and enable them (VI).
 716  * Returns 0 for success, error for failure.
 717  */
 718 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 719 {
 720         /* XXX todo */
 721         return 0;
 722 }
 723
 724 /**
 725  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 726  *
 727  * @adev: amdgpu_device pointer
 728  *
 729  * Loads the sDMA0/1 ucode.
 730  * Returns 0 for success, -EINVAL if the ucode is not available.
 731  */
 732 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 733 {
 734         const struct sdma_firmware_header_v1_0 *hdr;
 735         const __le32 *fw_data;
 736         u32 fw_size;
 737         int i, j;
 738
 739         /* halt the MEs */
 740         sdma_v3_0_enable(adev, false);
 741
 742         for (i = 0; i < adev->sdma.num_instances; i++) {
 743                 if (!adev->sdma.instance[i].fw)
 744                         return -EINVAL;
 745                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 746                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 747                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 748                 fw_data = (const __le32 *)
 749                         (adev->sdma.instance[i].fw->data +
 750                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 751                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 752                 for (j = 0; j < fw_size; j++)
 753                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 754                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 755         }
 756
 757         return 0;
 758 }
 759
 760 /**
 761  * sdma_v3_0_start - setup and start the async dma engines
 762  *
 763  * @adev: amdgpu_device pointer
 764  *
 765  * Set up the DMA engines and enable them (VI).
 766  * Returns 0 for success, error for failure.
 767  */
 768 static int sdma_v3_0_start(struct amdgpu_device *adev)
 769 {
 770         int r, i;
 771
 772         if (!adev->pp_enabled) {
 773                 if (!adev->firmware.smu_load) {
 774                         r = sdma_v3_0_load_microcode(adev);
 775                         if (r)
 776                                 return r;
 777                 } else {
 778                         for (i = 0; i < adev->sdma.num_instances; i++) {
 779                                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 780                                                                                  (i == 0) ?
 781                                                                                  AMDGPU_UCODE_ID_SDMA0 :
 782                                                                                  AMDGPU_UCODE_ID_SDMA1);
 783                                 if (r)
 784                                         return -EINVAL;
 785                         }
 786                 }
 787         }
 788
 789         /* disble sdma engine before programing it */
 790         sdma_v3_0_ctx_switch_enable(adev, false);
 791         sdma_v3_0_enable(adev, false);
 792
 793         /* start the gfx rings and rlc compute queues */
 794         r = sdma_v3_0_gfx_resume(adev);
 795         if (r)
 796                 return r;
 797         r = sdma_v3_0_rlc_resume(adev);
 798         if (r)
 799                 return r;
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * sdma_v3_0_ring_test_ring - simple async dma engine test
 806  *
 807  * @ring: amdgpu_ring structure holding ring information
 808  *
 809  * Test the DMA engine by writing using it to write an
 810  * value to memory. (VI).
 811  * Returns 0 for success, error for failure.
 812  */
 813 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 814 {
 815         struct amdgpu_device *adev = ring->adev;
 816         unsigned i;
 817         unsigned index;
 818         int r;
 819         u32 tmp;
 820         u64 gpu_addr;
 821
 822         r = amdgpu_wb_get(adev, &index);
 823         if (r) {
 824                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 825                 return r;
 826         }
 827
 828         gpu_addr = adev->wb.gpu_addr + (index * 4);
 829         tmp = 0xCAFEDEAD;
 830         adev->wb.wb[index] = cpu_to_le32(tmp);
 831
 832         r = amdgpu_ring_alloc(ring, 5);
 833         if (r) {
 834                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 835                 amdgpu_wb_free(adev, index);
 836                 return r;
 837         }
 838
 839         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 840                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 841         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 842         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 843         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 844         amdgpu_ring_write(ring, 0xDEADBEEF);
 845         amdgpu_ring_commit(ring);
 846
 847         for (i = 0; i < adev->usec_timeout; i++) {
 848                 tmp = le32_to_cpu(adev->wb.wb[index]);
 849                 if (tmp == 0xDEADBEEF)
 850                         break;
 851                 DRM_UDELAY(1);
 852         }
 853
 854         if (i < adev->usec_timeout) {
 855                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 856         } else {
 857                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 858                           ring->idx, tmp);
 859                 r = -EINVAL;
 860         }
 861         amdgpu_wb_free(adev, index);
 862
 863         return r;
 864 }
 865
 866 /**
 867  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 868  *
 869  * @ring: amdgpu_ring structure holding ring information
 870  *
 871  * Test a simple IB in the DMA ring (VI).
 872  * Returns 0 on success, error on failure.
 873  */
 874 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 875 {
 876         struct amdgpu_device *adev = ring->adev;
 877         struct amdgpu_ib ib;
 878         struct fence *f = NULL;
 879         unsigned index;
 880         u32 tmp = 0;
 881         u64 gpu_addr;
 882         long r;
 883
 884         r = amdgpu_wb_get(adev, &index);
 885         if (r) {
 886                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 887                 return r;
 888         }
 889
 890         gpu_addr = adev->wb.gpu_addr + (index * 4);
 891         tmp = 0xCAFEDEAD;
 892         adev->wb.wb[index] = cpu_to_le32(tmp);
 893         memset(&ib, 0, sizeof(ib));
 894         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 895         if (r) {
 896                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 897                 goto err0;
 898         }
 899
 900         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 901                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 902         ib.ptr[1] = lower_32_bits(gpu_addr);
 903         ib.ptr[2] = upper_32_bits(gpu_addr);
 904         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 905         ib.ptr[4] = 0xDEADBEEF;
 906         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 907         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 908         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 909         ib.length_dw = 8;
 910
 911         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 912         if (r)
 913                 goto err1;
 914
 915         r = fence_wait_timeout(f, false, timeout);
 916         if (r == 0) {
 917                 DRM_ERROR("amdgpu: IB test timed out\n");
 918                 r = -ETIMEDOUT;
 919                 goto err1;
 920         } else if (r < 0) {
 921                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 922                 goto err1;
 923         }
 924         tmp = le32_to_cpu(adev->wb.wb[index]);
 925         if (tmp == 0xDEADBEEF) {
 926                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 927                 r = 0;
 928         } else {
 929                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 930                 r = -EINVAL;
 931         }
 932 err1:
 933         amdgpu_ib_free(adev, &ib, NULL);
 934         fence_put(f);
 935 err0:
 936         amdgpu_wb_free(adev, index);
 937         return r;
 938 }
 939
 940 /**
 941  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 942  *
 943  * @ib: indirect buffer to fill with commands
 944  * @pe: addr of the page entry
 945  * @src: src addr to copy from
 946  * @count: number of page entries to update
 947  *
 948  * Update PTEs by copying them from the GART using sDMA (CIK).
 949  */
 950 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 951                                   uint64_t pe, uint64_t src,
 952                                   unsigned count)
 953 {
 954         unsigned bytes = count * 8;
 955
 956         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 957                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 958         ib->ptr[ib->length_dw++] = bytes;
 959         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 960         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 961         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 962         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 963         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 964 }
 965
 966 /**
 967  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 968  *
 969  * @ib: indirect buffer to fill with commands
 970  * @pe: addr of the page entry
 971  * @value: dst addr to write into pe
 972  * @count: number of page entries to update
 973  * @incr: increase next addr by incr bytes
 974  *
 975  * Update PTEs by writing them manually using sDMA (CIK).
 976  */
 977 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 978                                    uint64_t value, unsigned count,
 979                                    uint32_t incr)
 980 {
 981         unsigned ndw = count * 2;
 982
 983         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 984                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 985         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 986         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 987         ib->ptr[ib->length_dw++] = ndw;
 988         for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 989                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 990                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 991                 value += incr;
 992         }
 993 }
 994
 995 /**
 996  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 997  *
 998  * @ib: indirect buffer to fill with commands
 999  * @pe: addr of the page entry
1000  * @addr: dst addr to write into pe
1001  * @count: number of page entries to update
1002  * @incr: increase next addr by incr bytes
1003  * @flags: access flags
1004  *
1005  * Update the page tables using sDMA (CIK).
1006  */
1007 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1008                                      uint64_t addr, unsigned count,
1009                                      uint32_t incr, uint32_t flags)
1010 {
1011         /* for physically contiguous pages (vram) */
1012         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1013         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1014         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1015         ib->ptr[ib->length_dw++] = flags; /* mask */
1016         ib->ptr[ib->length_dw++] = 0;
1017         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1018         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1019         ib->ptr[ib->length_dw++] = incr; /* increment size */
1020         ib->ptr[ib->length_dw++] = 0;
1021         ib->ptr[ib->length_dw++] = count; /* number of entries */
1022 }
1023
1024 /**
1025  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1026  *
1027  * @ib: indirect buffer to fill with padding
1028  *
1029  */
1030 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1031 {
1032         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1033         u32 pad_count;
1034         int i;
1035
1036         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1037         for (i = 0; i < pad_count; i++)
1038                 if (sdma && sdma->burst_nop && (i == 0))
1039                         ib->ptr[ib->length_dw++] =
1040                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1041                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1042                 else
1043                         ib->ptr[ib->length_dw++] =
1044                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1045 }
1046
1047 /**
1048  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1049  *
1050  * @ring: amdgpu_ring pointer
1051  *
1052  * Make sure all previous operations are completed (CIK).
1053  */
1054 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1055 {
1056         uint32_t seq = ring->fence_drv.sync_seq;
1057         uint64_t addr = ring->fence_drv.gpu_addr;
1058
1059         /* wait for idle */
1060         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1061                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1062                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1063                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1064         amdgpu_ring_write(ring, addr & 0xfffffffc);
1065         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1066         amdgpu_ring_write(ring, seq); /* reference */
1067         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1068         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1069                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1070 }
1071
1072 /**
1073  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1074  *
1075  * @ring: amdgpu_ring pointer
1076  * @vm: amdgpu_vm pointer
1077  *
1078  * Update the page table base and flush the VM TLB
1079  * using sDMA (VI).
1080  */
1081 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1082                                          unsigned vm_id, uint64_t pd_addr)
1083 {
1084         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1085                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1086         if (vm_id < 8) {
1087                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1088         } else {
1089                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1090         }
1091         amdgpu_ring_write(ring, pd_addr >> 12);
1092
1093         /* flush TLB */
1094         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1095                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1096         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1097         amdgpu_ring_write(ring, 1 << vm_id);
1098
1099         /* wait for flush */
1100         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1101                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1102                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1103         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1104         amdgpu_ring_write(ring, 0);
1105         amdgpu_ring_write(ring, 0); /* reference */
1106         amdgpu_ring_write(ring, 0); /* mask */
1107         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1108                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1109 }
1110
1111 static int sdma_v3_0_early_init(void *handle)
1112 {
1113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115         switch (adev->asic_type) {
1116         case CHIP_STONEY:
1117                 adev->sdma.num_instances = 1;
1118                 break;
1119         default:
1120                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1121                 break;
1122         }
1123
1124         sdma_v3_0_set_ring_funcs(adev);
1125         sdma_v3_0_set_buffer_funcs(adev);
1126         sdma_v3_0_set_vm_pte_funcs(adev);
1127         sdma_v3_0_set_irq_funcs(adev);
1128
1129         return 0;
1130 }
1131
1132 static int sdma_v3_0_sw_init(void *handle)
1133 {
1134         struct amdgpu_ring *ring;
1135         int r, i;
1136         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1137
1138         /* SDMA trap event */
1139         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1140         if (r)
1141                 return r;
1142
1143         /* SDMA Privileged inst */
1144         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1145         if (r)
1146                 return r;
1147
1148         /* SDMA Privileged inst */
1149         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1150         if (r)
1151                 return r;
1152
1153         r = sdma_v3_0_init_microcode(adev);
1154         if (r) {
1155                 DRM_ERROR("Failed to load sdma firmware!\n");
1156                 return r;
1157         }
1158
1159         for (i = 0; i < adev->sdma.num_instances; i++) {
1160                 ring = &adev->sdma.instance[i].ring;
1161                 ring->ring_obj = NULL;
1162                 ring->use_doorbell = true;
1163                 ring->doorbell_index = (i == 0) ?
1164                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1165
1166                 sprintf(ring->name, "sdma%d", i);
1167                 r = amdgpu_ring_init(adev, ring, 1024,
1168                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1169                                      &adev->sdma.trap_irq,
1170                                      (i == 0) ?
1171                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1172                                      AMDGPU_RING_TYPE_SDMA);
1173                 if (r)
1174                         return r;
1175         }
1176
1177         return r;
1178 }
1179
1180 static int sdma_v3_0_sw_fini(void *handle)
1181 {
1182         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183         int i;
1184
1185         for (i = 0; i < adev->sdma.num_instances; i++)
1186                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1187
1188         sdma_v3_0_free_microcode(adev);
1189         return 0;
1190 }
1191
1192 static int sdma_v3_0_hw_init(void *handle)
1193 {
1194         int r;
1195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197         sdma_v3_0_init_golden_registers(adev);
1198
1199         r = sdma_v3_0_start(adev);
1200         if (r)
1201                 return r;
1202
1203         return r;
1204 }
1205
1206 static int sdma_v3_0_hw_fini(void *handle)
1207 {
1208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209
1210         sdma_v3_0_ctx_switch_enable(adev, false);
1211         sdma_v3_0_enable(adev, false);
1212
1213         return 0;
1214 }
1215
1216 static int sdma_v3_0_suspend(void *handle)
1217 {
1218         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1219
1220         return sdma_v3_0_hw_fini(adev);
1221 }
1222
1223 static int sdma_v3_0_resume(void *handle)
1224 {
1225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1226
1227         return sdma_v3_0_hw_init(adev);
1228 }
1229
1230 static bool sdma_v3_0_is_idle(void *handle)
1231 {
1232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233         u32 tmp = RREG32(mmSRBM_STATUS2);
1234
1235         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1236                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1237             return false;
1238
1239         return true;
1240 }
1241
1242 static int sdma_v3_0_wait_for_idle(void *handle)
1243 {
1244         unsigned i;
1245         u32 tmp;
1246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247
1248         for (i = 0; i < adev->usec_timeout; i++) {
1249                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1250                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1251
1252                 if (!tmp)
1253                         return 0;
1254                 udelay(1);
1255         }
1256         return -ETIMEDOUT;
1257 }
1258
1259 static int sdma_v3_0_check_soft_reset(void *handle)
1260 {
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262         u32 srbm_soft_reset = 0;
1263         u32 tmp = RREG32(mmSRBM_STATUS2);
1264
1265         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1266             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1267                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1268                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1269         }
1270
1271         if (srbm_soft_reset) {
1272                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = true;
1273                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1274         } else {
1275                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang = false;
1276                 adev->sdma.srbm_soft_reset = 0;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int sdma_v3_0_pre_soft_reset(void *handle)
1283 {
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285         u32 srbm_soft_reset = 0;
1286
1287         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1288                 return 0;
1289
1290         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1291
1292         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1293             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1294                 sdma_v3_0_ctx_switch_enable(adev, false);
1295                 sdma_v3_0_enable(adev, false);
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int sdma_v3_0_post_soft_reset(void *handle)
1302 {
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304         u32 srbm_soft_reset = 0;
1305
1306         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1307                 return 0;
1308
1309         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1310
1311         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1312             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1313                 sdma_v3_0_gfx_resume(adev);
1314                 sdma_v3_0_rlc_resume(adev);
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int sdma_v3_0_soft_reset(void *handle)
1321 {
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323         u32 srbm_soft_reset = 0;
1324         u32 tmp;
1325
1326         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_SDMA].hang)
1327                 return 0;
1328
1329         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1330
1331         if (srbm_soft_reset) {
1332                 tmp = RREG32(mmSRBM_SOFT_RESET);
1333                 tmp |= srbm_soft_reset;
1334                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1335                 WREG32(mmSRBM_SOFT_RESET, tmp);
1336                 tmp = RREG32(mmSRBM_SOFT_RESET);
1337
1338                 udelay(50);
1339
1340                 tmp &= ~srbm_soft_reset;
1341                 WREG32(mmSRBM_SOFT_RESET, tmp);
1342                 tmp = RREG32(mmSRBM_SOFT_RESET);
1343
1344                 /* Wait a little for things to settle down */
1345                 udelay(50);
1346         }
1347
1348         return 0;
1349 }
1350
1351 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1352                                         struct amdgpu_irq_src *source,
1353                                         unsigned type,
1354                                         enum amdgpu_interrupt_state state)
1355 {
1356         u32 sdma_cntl;
1357
1358         switch (type) {
1359         case AMDGPU_SDMA_IRQ_TRAP0:
1360                 switch (state) {
1361                 case AMDGPU_IRQ_STATE_DISABLE:
1362                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1363                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1364                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1365                         break;
1366                 case AMDGPU_IRQ_STATE_ENABLE:
1367                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1368                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1369                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1370                         break;
1371                 default:
1372                         break;
1373                 }
1374                 break;
1375         case AMDGPU_SDMA_IRQ_TRAP1:
1376                 switch (state) {
1377                 case AMDGPU_IRQ_STATE_DISABLE:
1378                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1379                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1380                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1381                         break;
1382                 case AMDGPU_IRQ_STATE_ENABLE:
1383                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1384                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1385                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1386                         break;
1387                 default:
1388                         break;
1389                 }
1390                 break;
1391         default:
1392                 break;
1393         }
1394         return 0;
1395 }
1396
1397 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1398                                       struct amdgpu_irq_src *source,
1399                                       struct amdgpu_iv_entry *entry)
1400 {
1401         u8 instance_id, queue_id;
1402
1403         instance_id = (entry->ring_id & 0x3) >> 0;
1404         queue_id = (entry->ring_id & 0xc) >> 2;
1405         DRM_DEBUG("IH: SDMA trap\n");
1406         switch (instance_id) {
1407         case 0:
1408                 switch (queue_id) {
1409                 case 0:
1410                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1411                         break;
1412                 case 1:
1413                         /* XXX compute */
1414                         break;
1415                 case 2:
1416                         /* XXX compute */
1417                         break;
1418                 }
1419                 break;
1420         case 1:
1421                 switch (queue_id) {
1422                 case 0:
1423                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1424                         break;
1425                 case 1:
1426                         /* XXX compute */
1427                         break;
1428                 case 2:
1429                         /* XXX compute */
1430                         break;
1431                 }
1432                 break;
1433         }
1434         return 0;
1435 }
1436
1437 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1438                                               struct amdgpu_irq_src *source,
1439                                               struct amdgpu_iv_entry *entry)
1440 {
1441         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1442         schedule_work(&adev->reset_work);
1443         return 0;
1444 }
1445
1446 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1447                 struct amdgpu_device *adev,
1448                 bool enable)
1449 {
1450         uint32_t temp, data;
1451         int i;
1452
1453         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1454                 for (i = 0; i < adev->sdma.num_instances; i++) {
1455                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1456                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1457                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1458                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1459                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1460                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1461                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1462                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1463                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1464                         if (data != temp)
1465                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1466                 }
1467         } else {
1468                 for (i = 0; i < adev->sdma.num_instances; i++) {
1469                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1470                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1471                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1472                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1473                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1474                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1475                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1476                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1477                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1478
1479                         if (data != temp)
1480                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1481                 }
1482         }
1483 }
1484
1485 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1486                 struct amdgpu_device *adev,
1487                 bool enable)
1488 {
1489         uint32_t temp, data;
1490         int i;
1491
1492         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1493                 for (i = 0; i < adev->sdma.num_instances; i++) {
1494                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1495                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1496
1497                         if (temp != data)
1498                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1499                 }
1500         } else {
1501                 for (i = 0; i < adev->sdma.num_instances; i++) {
1502                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1503                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1504
1505                         if (temp != data)
1506                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1507                 }
1508         }
1509 }
1510
1511 static int sdma_v3_0_set_clockgating_state(void *handle,
1512                                           enum amd_clockgating_state state)
1513 {
1514         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1515
1516         switch (adev->asic_type) {
1517         case CHIP_FIJI:
1518         case CHIP_CARRIZO:
1519         case CHIP_STONEY:
1520                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1521                                 state == AMD_CG_STATE_GATE ? true : false);
1522                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1523                                 state == AMD_CG_STATE_GATE ? true : false);
1524                 break;
1525         default:
1526                 break;
1527         }
1528         return 0;
1529 }
1530
1531 static int sdma_v3_0_set_powergating_state(void *handle,
1532                                           enum amd_powergating_state state)
1533 {
1534         return 0;
1535 }
1536
1537 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1538         .name = "sdma_v3_0",
1539         .early_init = sdma_v3_0_early_init,
1540         .late_init = NULL,
1541         .sw_init = sdma_v3_0_sw_init,
1542         .sw_fini = sdma_v3_0_sw_fini,
1543         .hw_init = sdma_v3_0_hw_init,
1544         .hw_fini = sdma_v3_0_hw_fini,
1545         .suspend = sdma_v3_0_suspend,
1546         .resume = sdma_v3_0_resume,
1547         .is_idle = sdma_v3_0_is_idle,
1548         .wait_for_idle = sdma_v3_0_wait_for_idle,
1549         .check_soft_reset = sdma_v3_0_check_soft_reset,
1550         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1551         .post_soft_reset = sdma_v3_0_post_soft_reset,
1552         .soft_reset = sdma_v3_0_soft_reset,
1553         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1554         .set_powergating_state = sdma_v3_0_set_powergating_state,
1555 };
1556
1557 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1558         .get_rptr = sdma_v3_0_ring_get_rptr,
1559         .get_wptr = sdma_v3_0_ring_get_wptr,
1560         .set_wptr = sdma_v3_0_ring_set_wptr,
1561         .parse_cs = NULL,
1562         .emit_ib = sdma_v3_0_ring_emit_ib,
1563         .emit_fence = sdma_v3_0_ring_emit_fence,
1564         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1565         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1566         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1567         .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1568         .test_ring = sdma_v3_0_ring_test_ring,
1569         .test_ib = sdma_v3_0_ring_test_ib,
1570         .insert_nop = sdma_v3_0_ring_insert_nop,
1571         .pad_ib = sdma_v3_0_ring_pad_ib,
1572 };
1573
1574 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1575 {
1576         int i;
1577
1578         for (i = 0; i < adev->sdma.num_instances; i++)
1579                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1580 }
1581
1582 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1583         .set = sdma_v3_0_set_trap_irq_state,
1584         .process = sdma_v3_0_process_trap_irq,
1585 };
1586
1587 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1588         .process = sdma_v3_0_process_illegal_inst_irq,
1589 };
1590
1591 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1592 {
1593         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1594         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1595         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1596 }
1597
1598 /**
1599  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1600  *
1601  * @ring: amdgpu_ring structure holding ring information
1602  * @src_offset: src GPU address
1603  * @dst_offset: dst GPU address
1604  * @byte_count: number of bytes to xfer
1605  *
1606  * Copy GPU buffers using the DMA engine (VI).
1607  * Used by the amdgpu ttm implementation to move pages if
1608  * registered as the asic copy callback.
1609  */
1610 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1611                                        uint64_t src_offset,
1612                                        uint64_t dst_offset,
1613                                        uint32_t byte_count)
1614 {
1615         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1616                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1617         ib->ptr[ib->length_dw++] = byte_count;
1618         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1619         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1620         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1621         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1622         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1623 }
1624
1625 /**
1626  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1627  *
1628  * @ring: amdgpu_ring structure holding ring information
1629  * @src_data: value to write to buffer
1630  * @dst_offset: dst GPU address
1631  * @byte_count: number of bytes to xfer
1632  *
1633  * Fill GPU buffers using the DMA engine (VI).
1634  */
1635 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1636                                        uint32_t src_data,
1637                                        uint64_t dst_offset,
1638                                        uint32_t byte_count)
1639 {
1640         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1641         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1642         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1643         ib->ptr[ib->length_dw++] = src_data;
1644         ib->ptr[ib->length_dw++] = byte_count;
1645 }
1646
1647 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1648         .copy_max_bytes = 0x1fffff,
1649         .copy_num_dw = 7,
1650         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1651
1652         .fill_max_bytes = 0x1fffff,
1653         .fill_num_dw = 5,
1654         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1655 };
1656
1657 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1658 {
1659         if (adev->mman.buffer_funcs == NULL) {
1660                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1661                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1662         }
1663 }
1664
1665 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1666         .copy_pte = sdma_v3_0_vm_copy_pte,
1667         .write_pte = sdma_v3_0_vm_write_pte,
1668         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1669 };
1670
1671 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1672 {
1673         unsigned i;
1674
1675         if (adev->vm_manager.vm_pte_funcs == NULL) {
1676                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1677                 for (i = 0; i < adev->sdma.num_instances; i++)
1678                         adev->vm_manager.vm_pte_rings[i] =
1679                                 &adev->sdma.instance[i].ring;
1680
1681                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1682         }
1683 }