2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
67 SDMA0_REGISTER_OFFSET,
71 static const u32 golden_settings_tonga_a11[] =
73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
85 static const u32 tonga_mgcg_cgcg_init[] =
87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
91 static const u32 golden_settings_fiji_a10[] =
93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
103 static const u32 fiji_mgcg_cgcg_init[] =
105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
109 static const u32 golden_settings_polaris11_a11[] =
111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
112 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
113 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
114 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
115 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
116 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
117 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
118 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
121 static const u32 golden_settings_polaris10_a11[] =
123 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
124 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
125 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
126 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
127 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
129 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
130 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
131 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
132 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
135 static const u32 cz_golden_settings_a11[] =
137 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
138 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
139 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
140 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
141 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
142 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
143 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
144 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
145 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
146 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
147 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
148 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
151 static const u32 cz_mgcg_cgcg_init[] =
153 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
154 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
157 static const u32 stoney_golden_settings_a11[] =
159 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
160 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
161 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
162 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
165 static const u32 stoney_mgcg_cgcg_init[] =
167 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
172 * Starting with CIK, the GPU has new asynchronous
173 * DMA engines. These engines are used for compute
174 * and gfx. There are two DMA engines (SDMA0, SDMA1)
175 * and each one supports 1 ring buffer used for gfx
176 * and 2 queues used for compute.
178 * The programming model is very similar to the CP
179 * (ring buffer, IBs, etc.), but sDMA has it's own
180 * packet format that is different from the PM4 format
181 * used by the CP. sDMA supports copying data, writing
182 * embedded data, solid fills, and a number of other
183 * things. It also has support for tiling/detiling of
187 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
189 switch (adev->asic_type) {
191 amdgpu_program_register_sequence(adev,
193 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
194 amdgpu_program_register_sequence(adev,
195 golden_settings_fiji_a10,
196 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
199 amdgpu_program_register_sequence(adev,
200 tonga_mgcg_cgcg_init,
201 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
202 amdgpu_program_register_sequence(adev,
203 golden_settings_tonga_a11,
204 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
207 amdgpu_program_register_sequence(adev,
208 golden_settings_polaris11_a11,
209 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
212 amdgpu_program_register_sequence(adev,
213 golden_settings_polaris10_a11,
214 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
217 amdgpu_program_register_sequence(adev,
219 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
220 amdgpu_program_register_sequence(adev,
221 cz_golden_settings_a11,
222 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
225 amdgpu_program_register_sequence(adev,
226 stoney_mgcg_cgcg_init,
227 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
228 amdgpu_program_register_sequence(adev,
229 stoney_golden_settings_a11,
230 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
238 * sdma_v3_0_init_microcode - load ucode images from disk
240 * @adev: amdgpu_device pointer
242 * Use the firmware interface to load the ucode images into
243 * the driver (not loaded into hw).
244 * Returns 0 on success, error on failure.
246 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
248 const char *chip_name;
251 struct amdgpu_firmware_info *info = NULL;
252 const struct common_firmware_header *header = NULL;
253 const struct sdma_firmware_header_v1_0 *hdr;
257 switch (adev->asic_type) {
265 chip_name = "polaris11";
268 chip_name = "polaris10";
271 chip_name = "carrizo";
274 chip_name = "stoney";
279 for (i = 0; i < adev->sdma.num_instances; i++) {
281 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
283 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
284 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
287 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
290 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
291 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
292 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
293 if (adev->sdma.instance[i].feature_version >= 20)
294 adev->sdma.instance[i].burst_nop = true;
296 if (adev->firmware.smu_load) {
297 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
298 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
299 info->fw = adev->sdma.instance[i].fw;
300 header = (const struct common_firmware_header *)info->fw->data;
301 adev->firmware.fw_size +=
302 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
308 "sdma_v3_0: Failed to load firmware \"%s\"\n",
310 for (i = 0; i < adev->sdma.num_instances; i++) {
311 release_firmware(adev->sdma.instance[i].fw);
312 adev->sdma.instance[i].fw = NULL;
319 * sdma_v3_0_ring_get_rptr - get the current read pointer
321 * @ring: amdgpu ring pointer
323 * Get the current rptr from the hardware (VI+).
325 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
329 /* XXX check if swapping is necessary on BE */
330 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
336 * sdma_v3_0_ring_get_wptr - get the current write pointer
338 * @ring: amdgpu ring pointer
340 * Get the current wptr from the hardware (VI+).
342 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
344 struct amdgpu_device *adev = ring->adev;
347 if (ring->use_doorbell) {
348 /* XXX check if swapping is necessary on BE */
349 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
351 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
353 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
360 * sdma_v3_0_ring_set_wptr - commit the write pointer
362 * @ring: amdgpu ring pointer
364 * Write the wptr back to the hardware (VI+).
366 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
368 struct amdgpu_device *adev = ring->adev;
370 if (ring->use_doorbell) {
371 /* XXX check if swapping is necessary on BE */
372 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
373 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
375 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
377 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
381 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
383 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
386 for (i = 0; i < count; i++)
387 if (sdma && sdma->burst_nop && (i == 0))
388 amdgpu_ring_write(ring, ring->nop |
389 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
391 amdgpu_ring_write(ring, ring->nop);
395 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
397 * @ring: amdgpu ring pointer
398 * @ib: IB object to schedule
400 * Schedule an IB in the DMA ring (VI).
402 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
403 struct amdgpu_ib *ib,
404 unsigned vm_id, bool ctx_switch)
406 u32 vmid = vm_id & 0xf;
407 u32 next_rptr = ring->wptr + 5;
409 while ((next_rptr & 7) != 2)
413 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
414 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
415 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
416 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
417 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
418 amdgpu_ring_write(ring, next_rptr);
420 /* IB packet must end on a 8 DW boundary */
421 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
423 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
424 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
425 /* base must be 32 byte aligned */
426 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
427 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
428 amdgpu_ring_write(ring, ib->length_dw);
429 amdgpu_ring_write(ring, 0);
430 amdgpu_ring_write(ring, 0);
435 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
437 * @ring: amdgpu ring pointer
439 * Emit an hdp flush packet on the requested DMA ring.
441 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
443 u32 ref_and_mask = 0;
445 if (ring == &ring->adev->sdma.instance[0].ring)
446 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
448 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
450 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
451 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
452 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
453 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
454 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
455 amdgpu_ring_write(ring, ref_and_mask); /* reference */
456 amdgpu_ring_write(ring, ref_and_mask); /* mask */
457 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
458 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
461 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
463 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
464 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
465 amdgpu_ring_write(ring, mmHDP_DEBUG0);
466 amdgpu_ring_write(ring, 1);
470 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
472 * @ring: amdgpu ring pointer
473 * @fence: amdgpu fence object
475 * Add a DMA fence packet to the ring to write
476 * the fence seq number and DMA trap packet to generate
477 * an interrupt if needed (VI).
479 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
482 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
483 /* write the fence */
484 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
485 amdgpu_ring_write(ring, lower_32_bits(addr));
486 amdgpu_ring_write(ring, upper_32_bits(addr));
487 amdgpu_ring_write(ring, lower_32_bits(seq));
489 /* optionally write high bits as well */
492 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
493 amdgpu_ring_write(ring, lower_32_bits(addr));
494 amdgpu_ring_write(ring, upper_32_bits(addr));
495 amdgpu_ring_write(ring, upper_32_bits(seq));
498 /* generate an interrupt */
499 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
500 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
503 unsigned init_cond_exec(struct amdgpu_ring *ring)
506 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
507 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
508 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
509 amdgpu_ring_write(ring, 1);
510 ret = ring->wptr;/* this is the offset we need patch later */
511 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
515 void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
518 BUG_ON(ring->ring[offset] != 0x55aa55aa);
520 cur = ring->wptr - 1;
521 if (likely(cur > offset))
522 ring->ring[offset] = cur - offset;
524 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
529 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
531 * @adev: amdgpu_device pointer
533 * Stop the gfx async dma ring buffers (VI).
535 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
537 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
538 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
539 u32 rb_cntl, ib_cntl;
542 if ((adev->mman.buffer_funcs_ring == sdma0) ||
543 (adev->mman.buffer_funcs_ring == sdma1))
544 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
546 for (i = 0; i < adev->sdma.num_instances; i++) {
547 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
548 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
549 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
550 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
551 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
552 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
554 sdma0->ready = false;
555 sdma1->ready = false;
559 * sdma_v3_0_rlc_stop - stop the compute async dma engines
561 * @adev: amdgpu_device pointer
563 * Stop the compute async dma queues (VI).
565 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
571 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
573 * @adev: amdgpu_device pointer
574 * @enable: enable/disable the DMA MEs context switch.
576 * Halt or unhalt the async dma engines context switch (VI).
578 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
583 for (i = 0; i < adev->sdma.num_instances; i++) {
584 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
586 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
587 AUTO_CTXSW_ENABLE, 1);
589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
590 AUTO_CTXSW_ENABLE, 0);
591 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
596 * sdma_v3_0_enable - stop the async dma engines
598 * @adev: amdgpu_device pointer
599 * @enable: enable/disable the DMA MEs.
601 * Halt or unhalt the async dma engines (VI).
603 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
608 if (enable == false) {
609 sdma_v3_0_gfx_stop(adev);
610 sdma_v3_0_rlc_stop(adev);
613 for (i = 0; i < adev->sdma.num_instances; i++) {
614 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
616 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
618 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
619 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
624 * sdma_v3_0_gfx_resume - setup and start the async dma engines
626 * @adev: amdgpu_device pointer
628 * Set up the gfx DMA ring buffers and enable them (VI).
629 * Returns 0 for success, error for failure.
631 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
633 struct amdgpu_ring *ring;
634 u32 rb_cntl, ib_cntl;
640 for (i = 0; i < adev->sdma.num_instances; i++) {
641 ring = &adev->sdma.instance[i].ring;
642 wb_offset = (ring->rptr_offs * 4);
644 mutex_lock(&adev->srbm_mutex);
645 for (j = 0; j < 16; j++) {
646 vi_srbm_select(adev, 0, 0, 0, j);
648 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
649 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
651 vi_srbm_select(adev, 0, 0, 0, 0);
652 mutex_unlock(&adev->srbm_mutex);
654 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
655 adev->gfx.config.gb_addr_config & 0x70);
657 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
659 /* Set ring buffer size in dwords */
660 rb_bufsz = order_base_2(ring->ring_size / 4);
661 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
665 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
666 RPTR_WRITEBACK_SWAP_ENABLE, 1);
668 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
670 /* Initialize the ring buffer's read and write pointers */
671 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
672 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
674 /* set the wb address whether it's enabled or not */
675 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
676 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
677 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
678 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
682 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
683 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
686 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
688 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
690 if (ring->use_doorbell) {
691 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
692 OFFSET, ring->doorbell_index);
693 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
695 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
697 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
700 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
701 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
703 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
704 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
706 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
709 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
713 r = amdgpu_ring_test_ring(ring);
719 if (adev->mman.buffer_funcs_ring == ring)
720 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
727 * sdma_v3_0_rlc_resume - setup and start the async dma engines
729 * @adev: amdgpu_device pointer
731 * Set up the compute DMA queues and enable them (VI).
732 * Returns 0 for success, error for failure.
734 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
741 * sdma_v3_0_load_microcode - load the sDMA ME ucode
743 * @adev: amdgpu_device pointer
745 * Loads the sDMA0/1 ucode.
746 * Returns 0 for success, -EINVAL if the ucode is not available.
748 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
750 const struct sdma_firmware_header_v1_0 *hdr;
751 const __le32 *fw_data;
756 sdma_v3_0_enable(adev, false);
758 for (i = 0; i < adev->sdma.num_instances; i++) {
759 if (!adev->sdma.instance[i].fw)
761 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
762 amdgpu_ucode_print_sdma_hdr(&hdr->header);
763 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
764 fw_data = (const __le32 *)
765 (adev->sdma.instance[i].fw->data +
766 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
767 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
768 for (j = 0; j < fw_size; j++)
769 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
770 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
777 * sdma_v3_0_start - setup and start the async dma engines
779 * @adev: amdgpu_device pointer
781 * Set up the DMA engines and enable them (VI).
782 * Returns 0 for success, error for failure.
784 static int sdma_v3_0_start(struct amdgpu_device *adev)
788 if (!adev->pp_enabled) {
789 if (!adev->firmware.smu_load) {
790 r = sdma_v3_0_load_microcode(adev);
794 for (i = 0; i < adev->sdma.num_instances; i++) {
795 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
797 AMDGPU_UCODE_ID_SDMA0 :
798 AMDGPU_UCODE_ID_SDMA1);
806 sdma_v3_0_enable(adev, true);
807 /* enable sdma ring preemption */
808 sdma_v3_0_ctx_switch_enable(adev, true);
810 /* start the gfx rings and rlc compute queues */
811 r = sdma_v3_0_gfx_resume(adev);
814 r = sdma_v3_0_rlc_resume(adev);
822 * sdma_v3_0_ring_test_ring - simple async dma engine test
824 * @ring: amdgpu_ring structure holding ring information
826 * Test the DMA engine by writing using it to write an
827 * value to memory. (VI).
828 * Returns 0 for success, error for failure.
830 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
832 struct amdgpu_device *adev = ring->adev;
839 r = amdgpu_wb_get(adev, &index);
841 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
845 gpu_addr = adev->wb.gpu_addr + (index * 4);
847 adev->wb.wb[index] = cpu_to_le32(tmp);
849 r = amdgpu_ring_alloc(ring, 5);
851 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
852 amdgpu_wb_free(adev, index);
856 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
857 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
858 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
859 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
860 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
861 amdgpu_ring_write(ring, 0xDEADBEEF);
862 amdgpu_ring_commit(ring);
864 for (i = 0; i < adev->usec_timeout; i++) {
865 tmp = le32_to_cpu(adev->wb.wb[index]);
866 if (tmp == 0xDEADBEEF)
871 if (i < adev->usec_timeout) {
872 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
874 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
878 amdgpu_wb_free(adev, index);
884 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
886 * @ring: amdgpu_ring structure holding ring information
888 * Test a simple IB in the DMA ring (VI).
889 * Returns 0 on success, error on failure.
891 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
893 struct amdgpu_device *adev = ring->adev;
895 struct fence *f = NULL;
902 r = amdgpu_wb_get(adev, &index);
904 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
908 gpu_addr = adev->wb.gpu_addr + (index * 4);
910 adev->wb.wb[index] = cpu_to_le32(tmp);
911 memset(&ib, 0, sizeof(ib));
912 r = amdgpu_ib_get(adev, NULL, 256, &ib);
914 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
918 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
919 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
920 ib.ptr[1] = lower_32_bits(gpu_addr);
921 ib.ptr[2] = upper_32_bits(gpu_addr);
922 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
923 ib.ptr[4] = 0xDEADBEEF;
924 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
925 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
926 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
929 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
933 r = fence_wait(f, false);
935 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
938 for (i = 0; i < adev->usec_timeout; i++) {
939 tmp = le32_to_cpu(adev->wb.wb[index]);
940 if (tmp == 0xDEADBEEF)
944 if (i < adev->usec_timeout) {
945 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
949 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
954 amdgpu_ib_free(adev, &ib, NULL);
957 amdgpu_wb_free(adev, index);
962 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
964 * @ib: indirect buffer to fill with commands
965 * @pe: addr of the page entry
966 * @src: src addr to copy from
967 * @count: number of page entries to update
969 * Update PTEs by copying them from the GART using sDMA (CIK).
971 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
972 uint64_t pe, uint64_t src,
976 unsigned bytes = count * 8;
977 if (bytes > 0x1FFFF8)
980 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
981 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
982 ib->ptr[ib->length_dw++] = bytes;
983 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
984 ib->ptr[ib->length_dw++] = lower_32_bits(src);
985 ib->ptr[ib->length_dw++] = upper_32_bits(src);
986 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
987 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
996 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
998 * @ib: indirect buffer to fill with commands
999 * @pe: addr of the page entry
1000 * @addr: dst addr to write into pe
1001 * @count: number of page entries to update
1002 * @incr: increase next addr by incr bytes
1003 * @flags: access flags
1005 * Update PTEs by writing them manually using sDMA (CIK).
1007 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
1008 const dma_addr_t *pages_addr, uint64_t pe,
1009 uint64_t addr, unsigned count,
1010 uint32_t incr, uint32_t flags)
1020 /* for non-physically contiguous pages (system) */
1021 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1022 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1023 ib->ptr[ib->length_dw++] = pe;
1024 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1025 ib->ptr[ib->length_dw++] = ndw;
1026 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1027 value = amdgpu_vm_map_gart(pages_addr, addr);
1030 ib->ptr[ib->length_dw++] = value;
1031 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1037 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1039 * @ib: indirect buffer to fill with commands
1040 * @pe: addr of the page entry
1041 * @addr: dst addr to write into pe
1042 * @count: number of page entries to update
1043 * @incr: increase next addr by incr bytes
1044 * @flags: access flags
1046 * Update the page tables using sDMA (CIK).
1048 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1050 uint64_t addr, unsigned count,
1051 uint32_t incr, uint32_t flags)
1061 if (flags & AMDGPU_PTE_VALID)
1066 /* for physically contiguous pages (vram) */
1067 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1068 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1069 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1070 ib->ptr[ib->length_dw++] = flags; /* mask */
1071 ib->ptr[ib->length_dw++] = 0;
1072 ib->ptr[ib->length_dw++] = value; /* value */
1073 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1074 ib->ptr[ib->length_dw++] = incr; /* increment size */
1075 ib->ptr[ib->length_dw++] = 0;
1076 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1085 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1087 * @ib: indirect buffer to fill with padding
1090 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1092 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1096 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1097 for (i = 0; i < pad_count; i++)
1098 if (sdma && sdma->burst_nop && (i == 0))
1099 ib->ptr[ib->length_dw++] =
1100 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1101 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1103 ib->ptr[ib->length_dw++] =
1104 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1108 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1110 * @ring: amdgpu_ring pointer
1112 * Make sure all previous operations are completed (CIK).
1114 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1116 uint32_t seq = ring->fence_drv.sync_seq;
1117 uint64_t addr = ring->fence_drv.gpu_addr;
1120 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1121 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1122 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1123 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1124 amdgpu_ring_write(ring, addr & 0xfffffffc);
1125 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1126 amdgpu_ring_write(ring, seq); /* reference */
1127 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1128 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1129 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1133 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1135 * @ring: amdgpu_ring pointer
1136 * @vm: amdgpu_vm pointer
1138 * Update the page table base and flush the VM TLB
1141 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1142 unsigned vm_id, uint64_t pd_addr)
1144 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1145 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1147 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1149 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1151 amdgpu_ring_write(ring, pd_addr >> 12);
1154 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1155 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1156 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1157 amdgpu_ring_write(ring, 1 << vm_id);
1159 /* wait for flush */
1160 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1161 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1162 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1163 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1164 amdgpu_ring_write(ring, 0);
1165 amdgpu_ring_write(ring, 0); /* reference */
1166 amdgpu_ring_write(ring, 0); /* mask */
1167 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1168 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1171 static int sdma_v3_0_early_init(void *handle)
1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175 switch (adev->asic_type) {
1177 adev->sdma.num_instances = 1;
1180 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1184 sdma_v3_0_set_ring_funcs(adev);
1185 sdma_v3_0_set_buffer_funcs(adev);
1186 sdma_v3_0_set_vm_pte_funcs(adev);
1187 sdma_v3_0_set_irq_funcs(adev);
1192 static int sdma_v3_0_sw_init(void *handle)
1194 struct amdgpu_ring *ring;
1196 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1198 /* SDMA trap event */
1199 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1203 /* SDMA Privileged inst */
1204 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1208 /* SDMA Privileged inst */
1209 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1213 r = sdma_v3_0_init_microcode(adev);
1215 DRM_ERROR("Failed to load sdma firmware!\n");
1219 for (i = 0; i < adev->sdma.num_instances; i++) {
1220 ring = &adev->sdma.instance[i].ring;
1221 ring->ring_obj = NULL;
1222 ring->use_doorbell = true;
1223 ring->doorbell_index = (i == 0) ?
1224 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1226 sprintf(ring->name, "sdma%d", i);
1227 r = amdgpu_ring_init(adev, ring, 1024,
1228 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1229 &adev->sdma.trap_irq,
1231 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1232 AMDGPU_RING_TYPE_SDMA);
1240 static int sdma_v3_0_sw_fini(void *handle)
1242 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1245 for (i = 0; i < adev->sdma.num_instances; i++)
1246 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1251 static int sdma_v3_0_hw_init(void *handle)
1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256 sdma_v3_0_init_golden_registers(adev);
1258 r = sdma_v3_0_start(adev);
1265 static int sdma_v3_0_hw_fini(void *handle)
1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1269 sdma_v3_0_ctx_switch_enable(adev, false);
1270 sdma_v3_0_enable(adev, false);
1275 static int sdma_v3_0_suspend(void *handle)
1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279 return sdma_v3_0_hw_fini(adev);
1282 static int sdma_v3_0_resume(void *handle)
1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286 return sdma_v3_0_hw_init(adev);
1289 static bool sdma_v3_0_is_idle(void *handle)
1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292 u32 tmp = RREG32(mmSRBM_STATUS2);
1294 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1295 SRBM_STATUS2__SDMA1_BUSY_MASK))
1301 static int sdma_v3_0_wait_for_idle(void *handle)
1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307 for (i = 0; i < adev->usec_timeout; i++) {
1308 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1309 SRBM_STATUS2__SDMA1_BUSY_MASK);
1318 static int sdma_v3_0_soft_reset(void *handle)
1320 u32 srbm_soft_reset = 0;
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322 u32 tmp = RREG32(mmSRBM_STATUS2);
1324 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1326 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1327 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1328 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1329 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1331 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1333 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1334 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1335 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1336 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1339 if (srbm_soft_reset) {
1340 tmp = RREG32(mmSRBM_SOFT_RESET);
1341 tmp |= srbm_soft_reset;
1342 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1343 WREG32(mmSRBM_SOFT_RESET, tmp);
1344 tmp = RREG32(mmSRBM_SOFT_RESET);
1348 tmp &= ~srbm_soft_reset;
1349 WREG32(mmSRBM_SOFT_RESET, tmp);
1350 tmp = RREG32(mmSRBM_SOFT_RESET);
1352 /* Wait a little for things to settle down */
1359 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1360 struct amdgpu_irq_src *source,
1362 enum amdgpu_interrupt_state state)
1367 case AMDGPU_SDMA_IRQ_TRAP0:
1369 case AMDGPU_IRQ_STATE_DISABLE:
1370 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1371 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1372 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1374 case AMDGPU_IRQ_STATE_ENABLE:
1375 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1376 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1377 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1383 case AMDGPU_SDMA_IRQ_TRAP1:
1385 case AMDGPU_IRQ_STATE_DISABLE:
1386 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1387 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1388 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1390 case AMDGPU_IRQ_STATE_ENABLE:
1391 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1392 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1393 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1405 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1406 struct amdgpu_irq_src *source,
1407 struct amdgpu_iv_entry *entry)
1409 u8 instance_id, queue_id;
1411 instance_id = (entry->ring_id & 0x3) >> 0;
1412 queue_id = (entry->ring_id & 0xc) >> 2;
1413 DRM_DEBUG("IH: SDMA trap\n");
1414 switch (instance_id) {
1418 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1431 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1445 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1446 struct amdgpu_irq_src *source,
1447 struct amdgpu_iv_entry *entry)
1449 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1450 schedule_work(&adev->reset_work);
1454 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1455 struct amdgpu_device *adev,
1458 uint32_t temp, data;
1461 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1462 for (i = 0; i < adev->sdma.num_instances; i++) {
1463 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1464 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1466 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1473 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1476 for (i = 0; i < adev->sdma.num_instances; i++) {
1477 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1478 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1488 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1493 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1494 struct amdgpu_device *adev,
1497 uint32_t temp, data;
1500 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1501 for (i = 0; i < adev->sdma.num_instances; i++) {
1502 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1503 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1506 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1509 for (i = 0; i < adev->sdma.num_instances; i++) {
1510 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1511 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1514 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1519 static int sdma_v3_0_set_clockgating_state(void *handle,
1520 enum amd_clockgating_state state)
1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1524 switch (adev->asic_type) {
1528 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1529 state == AMD_CG_STATE_GATE ? true : false);
1530 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1531 state == AMD_CG_STATE_GATE ? true : false);
1539 static int sdma_v3_0_set_powergating_state(void *handle,
1540 enum amd_powergating_state state)
1545 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1546 .name = "sdma_v3_0",
1547 .early_init = sdma_v3_0_early_init,
1549 .sw_init = sdma_v3_0_sw_init,
1550 .sw_fini = sdma_v3_0_sw_fini,
1551 .hw_init = sdma_v3_0_hw_init,
1552 .hw_fini = sdma_v3_0_hw_fini,
1553 .suspend = sdma_v3_0_suspend,
1554 .resume = sdma_v3_0_resume,
1555 .is_idle = sdma_v3_0_is_idle,
1556 .wait_for_idle = sdma_v3_0_wait_for_idle,
1557 .soft_reset = sdma_v3_0_soft_reset,
1558 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1559 .set_powergating_state = sdma_v3_0_set_powergating_state,
1562 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1563 .get_rptr = sdma_v3_0_ring_get_rptr,
1564 .get_wptr = sdma_v3_0_ring_get_wptr,
1565 .set_wptr = sdma_v3_0_ring_set_wptr,
1567 .emit_ib = sdma_v3_0_ring_emit_ib,
1568 .emit_fence = sdma_v3_0_ring_emit_fence,
1569 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1570 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1571 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1572 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1573 .test_ring = sdma_v3_0_ring_test_ring,
1574 .test_ib = sdma_v3_0_ring_test_ib,
1575 .insert_nop = sdma_v3_0_ring_insert_nop,
1576 .pad_ib = sdma_v3_0_ring_pad_ib,
1579 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1583 for (i = 0; i < adev->sdma.num_instances; i++)
1584 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1587 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1588 .set = sdma_v3_0_set_trap_irq_state,
1589 .process = sdma_v3_0_process_trap_irq,
1592 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1593 .process = sdma_v3_0_process_illegal_inst_irq,
1596 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1598 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1599 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1600 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1604 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1606 * @ring: amdgpu_ring structure holding ring information
1607 * @src_offset: src GPU address
1608 * @dst_offset: dst GPU address
1609 * @byte_count: number of bytes to xfer
1611 * Copy GPU buffers using the DMA engine (VI).
1612 * Used by the amdgpu ttm implementation to move pages if
1613 * registered as the asic copy callback.
1615 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1616 uint64_t src_offset,
1617 uint64_t dst_offset,
1618 uint32_t byte_count)
1620 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1621 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1622 ib->ptr[ib->length_dw++] = byte_count;
1623 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1624 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1625 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1626 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1627 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1631 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1633 * @ring: amdgpu_ring structure holding ring information
1634 * @src_data: value to write to buffer
1635 * @dst_offset: dst GPU address
1636 * @byte_count: number of bytes to xfer
1638 * Fill GPU buffers using the DMA engine (VI).
1640 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1642 uint64_t dst_offset,
1643 uint32_t byte_count)
1645 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1646 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1647 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1648 ib->ptr[ib->length_dw++] = src_data;
1649 ib->ptr[ib->length_dw++] = byte_count;
1652 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1653 .copy_max_bytes = 0x1fffff,
1655 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1657 .fill_max_bytes = 0x1fffff,
1659 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1662 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1664 if (adev->mman.buffer_funcs == NULL) {
1665 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1666 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1670 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1671 .copy_pte = sdma_v3_0_vm_copy_pte,
1672 .write_pte = sdma_v3_0_vm_write_pte,
1673 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1676 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1680 if (adev->vm_manager.vm_pte_funcs == NULL) {
1681 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1682 for (i = 0; i < adev->sdma.num_instances; i++)
1683 adev->vm_manager.vm_pte_rings[i] =
1684 &adev->sdma.instance[i].ring;
1686 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;