drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "vi.h"
  38
  39 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  40 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static int uvd_v6_0_start(struct amdgpu_device *adev);
  42 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  43 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  44
  45 /**
  46  * uvd_v6_0_ring_get_rptr - get read pointer
  47  *
  48  * @ring: amdgpu_ring pointer
  49  *
  50  * Returns the current hardware read pointer
  51  */
  52 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  53 {
  54         struct amdgpu_device *adev = ring->adev;
  55
  56         return RREG32(mmUVD_RBC_RB_RPTR);
  57 }
  58
  59 /**
  60  * uvd_v6_0_ring_get_wptr - get write pointer
  61  *
  62  * @ring: amdgpu_ring pointer
  63  *
  64  * Returns the current hardware write pointer
  65  */
  66 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
  67 {
  68         struct amdgpu_device *adev = ring->adev;
  69
  70         return RREG32(mmUVD_RBC_RB_WPTR);
  71 }
  72
  73 /**
  74  * uvd_v6_0_ring_set_wptr - set write pointer
  75  *
  76  * @ring: amdgpu_ring pointer
  77  *
  78  * Commits the write pointer to the hardware
  79  */
  80 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
  81 {
  82         struct amdgpu_device *adev = ring->adev;
  83
  84         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  85 }
  86
  87 static int uvd_v6_0_early_init(void *handle)
  88 {
  89         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  90
  91         uvd_v6_0_set_ring_funcs(adev);
  92         uvd_v6_0_set_irq_funcs(adev);
  93
  94         return 0;
  95 }
  96
  97 static int uvd_v6_0_sw_init(void *handle)
  98 {
  99         struct amdgpu_ring *ring;
 100         int r;
 101         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 102
 103         /* UVD TRAP */
 104         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 105         if (r)
 106                 return r;
 107
 108         r = amdgpu_uvd_sw_init(adev);
 109         if (r)
 110                 return r;
 111
 112         r = amdgpu_uvd_resume(adev);
 113         if (r)
 114                 return r;
 115
 116         ring = &adev->uvd.ring;
 117         sprintf(ring->name, "uvd");
 118         r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
 119                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 120
 121         return r;
 122 }
 123
 124 static int uvd_v6_0_sw_fini(void *handle)
 125 {
 126         int r;
 127         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 128
 129         r = amdgpu_uvd_suspend(adev);
 130         if (r)
 131                 return r;
 132
 133         r = amdgpu_uvd_sw_fini(adev);
 134         if (r)
 135                 return r;
 136
 137         return r;
 138 }
 139
 140 /**
 141  * uvd_v6_0_hw_init - start and test UVD block
 142  *
 143  * @adev: amdgpu_device pointer
 144  *
 145  * Initialize the hardware, boot up the VCPU and do some testing
 146  */
 147 static int uvd_v6_0_hw_init(void *handle)
 148 {
 149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 150         struct amdgpu_ring *ring = &adev->uvd.ring;
 151         uint32_t tmp;
 152         int r;
 153
 154         r = uvd_v6_0_start(adev);
 155         if (r)
 156                 goto done;
 157
 158         ring->ready = true;
 159         r = amdgpu_ring_test_ring(ring);
 160         if (r) {
 161                 ring->ready = false;
 162                 goto done;
 163         }
 164
 165         r = amdgpu_ring_alloc(ring, 10);
 166         if (r) {
 167                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 168                 goto done;
 169         }
 170
 171         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 172         amdgpu_ring_write(ring, tmp);
 173         amdgpu_ring_write(ring, 0xFFFFF);
 174
 175         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 176         amdgpu_ring_write(ring, tmp);
 177         amdgpu_ring_write(ring, 0xFFFFF);
 178
 179         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 180         amdgpu_ring_write(ring, tmp);
 181         amdgpu_ring_write(ring, 0xFFFFF);
 182
 183         /* Clear timeout status bits */
 184         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 185         amdgpu_ring_write(ring, 0x8);
 186
 187         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 188         amdgpu_ring_write(ring, 3);
 189
 190         amdgpu_ring_commit(ring);
 191
 192 done:
 193         if (!r)
 194                 DRM_INFO("UVD initialized successfully.\n");
 195
 196         return r;
 197 }
 198
 199 /**
 200  * uvd_v6_0_hw_fini - stop the hardware block
 201  *
 202  * @adev: amdgpu_device pointer
 203  *
 204  * Stop the UVD block, mark ring as not ready any more
 205  */
 206 static int uvd_v6_0_hw_fini(void *handle)
 207 {
 208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 209         struct amdgpu_ring *ring = &adev->uvd.ring;
 210
 211         uvd_v6_0_stop(adev);
 212         ring->ready = false;
 213
 214         return 0;
 215 }
 216
 217 static int uvd_v6_0_suspend(void *handle)
 218 {
 219         int r;
 220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 221
 222         r = uvd_v6_0_hw_fini(adev);
 223         if (r)
 224                 return r;
 225
 226         /* Skip this for APU for now */
 227         if (!(adev->flags & AMD_IS_APU)) {
 228                 r = amdgpu_uvd_suspend(adev);
 229                 if (r)
 230                         return r;
 231         }
 232
 233         return r;
 234 }
 235
 236 static int uvd_v6_0_resume(void *handle)
 237 {
 238         int r;
 239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 240
 241         /* Skip this for APU for now */
 242         if (!(adev->flags & AMD_IS_APU)) {
 243                 r = amdgpu_uvd_resume(adev);
 244                 if (r)
 245                         return r;
 246         }
 247         r = uvd_v6_0_hw_init(adev);
 248         if (r)
 249                 return r;
 250
 251         return r;
 252 }
 253
 254 /**
 255  * uvd_v6_0_mc_resume - memory controller programming
 256  *
 257  * @adev: amdgpu_device pointer
 258  *
 259  * Let the UVD memory controller know it's offsets
 260  */
 261 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 262 {
 263         uint64_t offset;
 264         uint32_t size;
 265
 266         /* programm memory controller bits 0-27 */
 267         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 268                         lower_32_bits(adev->uvd.gpu_addr));
 269         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 270                         upper_32_bits(adev->uvd.gpu_addr));
 271
 272         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 273         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 274         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 275         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 276
 277         offset += size;
 278         size = AMDGPU_UVD_HEAP_SIZE;
 279         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 280         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 281
 282         offset += size;
 283         size = AMDGPU_UVD_STACK_SIZE +
 284                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 285         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 286         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 287
 288         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 289         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 290         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 291
 292         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 293 }
 294
 295 #if 0
 296 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 297                 bool enable)
 298 {
 299         u32 data, data1;
 300
 301         data = RREG32(mmUVD_CGC_GATE);
 302         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 303         if (enable) {
 304                 data |= UVD_CGC_GATE__SYS_MASK |
 305                                 UVD_CGC_GATE__UDEC_MASK |
 306                                 UVD_CGC_GATE__MPEG2_MASK |
 307                                 UVD_CGC_GATE__RBC_MASK |
 308                                 UVD_CGC_GATE__LMI_MC_MASK |
 309                                 UVD_CGC_GATE__IDCT_MASK |
 310                                 UVD_CGC_GATE__MPRD_MASK |
 311                                 UVD_CGC_GATE__MPC_MASK |
 312                                 UVD_CGC_GATE__LBSI_MASK |
 313                                 UVD_CGC_GATE__LRBBM_MASK |
 314                                 UVD_CGC_GATE__UDEC_RE_MASK |
 315                                 UVD_CGC_GATE__UDEC_CM_MASK |
 316                                 UVD_CGC_GATE__UDEC_IT_MASK |
 317                                 UVD_CGC_GATE__UDEC_DB_MASK |
 318                                 UVD_CGC_GATE__UDEC_MP_MASK |
 319                                 UVD_CGC_GATE__WCB_MASK |
 320                                 UVD_CGC_GATE__VCPU_MASK |
 321                                 UVD_CGC_GATE__SCPU_MASK;
 322                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 323                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 324                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 325                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 326                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 327                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 328                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 329                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 330                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 331                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 332                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 333                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 334                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 335         } else {
 336                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 337                                 UVD_CGC_GATE__UDEC_MASK |
 338                                 UVD_CGC_GATE__MPEG2_MASK |
 339                                 UVD_CGC_GATE__RBC_MASK |
 340                                 UVD_CGC_GATE__LMI_MC_MASK |
 341                                 UVD_CGC_GATE__LMI_UMC_MASK |
 342                                 UVD_CGC_GATE__IDCT_MASK |
 343                                 UVD_CGC_GATE__MPRD_MASK |
 344                                 UVD_CGC_GATE__MPC_MASK |
 345                                 UVD_CGC_GATE__LBSI_MASK |
 346                                 UVD_CGC_GATE__LRBBM_MASK |
 347                                 UVD_CGC_GATE__UDEC_RE_MASK |
 348                                 UVD_CGC_GATE__UDEC_CM_MASK |
 349                                 UVD_CGC_GATE__UDEC_IT_MASK |
 350                                 UVD_CGC_GATE__UDEC_DB_MASK |
 351                                 UVD_CGC_GATE__UDEC_MP_MASK |
 352                                 UVD_CGC_GATE__WCB_MASK |
 353                                 UVD_CGC_GATE__VCPU_MASK |
 354                                 UVD_CGC_GATE__SCPU_MASK);
 355                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 356                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 357                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 358                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 359                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 360                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 361                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 362                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 363                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 364                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 365                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 366                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 367                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 368         }
 369         WREG32(mmUVD_CGC_GATE, data);
 370         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 371 }
 372 #endif
 373
 374 /**
 375  * uvd_v6_0_start - start UVD block
 376  *
 377  * @adev: amdgpu_device pointer
 378  *
 379  * Setup and start the UVD block
 380  */
 381 static int uvd_v6_0_start(struct amdgpu_device *adev)
 382 {
 383         struct amdgpu_ring *ring = &adev->uvd.ring;
 384         uint32_t rb_bufsz, tmp;
 385         uint32_t lmi_swap_cntl;
 386         uint32_t mp_swap_cntl;
 387         int i, j, r;
 388
 389         /* disable DPG */
 390         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 391
 392         /* disable byte swapping */
 393         lmi_swap_cntl = 0;
 394         mp_swap_cntl = 0;
 395
 396         uvd_v6_0_mc_resume(adev);
 397
 398         /* Set dynamic clock gating in S/W control mode */
 399         if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
 400                 uvd_v6_0_set_sw_clock_gating(adev);
 401         } else {
 402                 /* disable clock gating */
 403                 uint32_t data = RREG32(mmUVD_CGC_CTRL);
 404                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 405                 WREG32(mmUVD_CGC_CTRL, data);
 406         }
 407
 408         /* disable interupt */
 409         WREG32_P(mmUVD_MASTINT_EN, 0, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 410
 411         /* stall UMC and register bus before resetting VCPU */
 412         WREG32_P(mmUVD_LMI_CTRL2, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 413         mdelay(1);
 414
 415         /* put LMI, VCPU, RBC etc... into reset */
 416         WREG32(mmUVD_SOFT_RESET,
 417                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 418                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 419                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 420                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 421                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 422                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 423                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 424                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 425         mdelay(5);
 426
 427         /* take UVD block out of reset */
 428         WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 429         mdelay(5);
 430
 431         /* initialize UVD memory controller */
 432         WREG32(mmUVD_LMI_CTRL,
 433                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 434                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 435                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 436                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 437                 UVD_LMI_CTRL__REQ_MODE_MASK |
 438                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 439
 440 #ifdef __BIG_ENDIAN
 441         /* swap (8 in 32) RB and IB */
 442         lmi_swap_cntl = 0xa;
 443         mp_swap_cntl = 0;
 444 #endif
 445         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 446         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 447
 448         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 449         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 450         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 451         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 452         WREG32(mmUVD_MPC_SET_ALU, 0);
 453         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 454
 455         /* take all subblocks out of reset, except VCPU */
 456         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 457         mdelay(5);
 458
 459         /* enable VCPU clock */
 460         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 461
 462         /* enable UMC */
 463         WREG32_P(mmUVD_LMI_CTRL2, 0, ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 464
 465         /* boot up the VCPU */
 466         WREG32(mmUVD_SOFT_RESET, 0);
 467         mdelay(10);
 468
 469         for (i = 0; i < 10; ++i) {
 470                 uint32_t status;
 471
 472                 for (j = 0; j < 100; ++j) {
 473                         status = RREG32(mmUVD_STATUS);
 474                         if (status & 2)
 475                                 break;
 476                         mdelay(10);
 477                 }
 478                 r = 0;
 479                 if (status & 2)
 480                         break;
 481
 482                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 483                 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 484                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 485                 mdelay(10);
 486                 WREG32_P(mmUVD_SOFT_RESET, 0,
 487                          ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 488                 mdelay(10);
 489                 r = -1;
 490         }
 491
 492         if (r) {
 493                 DRM_ERROR("UVD not responding, giving up!!!\n");
 494                 return r;
 495         }
 496         /* enable master interrupt */
 497         WREG32_P(mmUVD_MASTINT_EN,
 498                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 499                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 500
 501         /* clear the bit 4 of UVD_STATUS */
 502         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 503
 504         rb_bufsz = order_base_2(ring->ring_size);
 505         tmp = 0;
 506         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 507         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 508         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 509         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 510         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 511         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 512         /* force RBC into idle state */
 513         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 514
 515         /* set the write pointer delay */
 516         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 517
 518         /* set the wb address */
 519         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 520
 521         /* programm the RB_BASE for ring buffer */
 522         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 523                         lower_32_bits(ring->gpu_addr));
 524         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 525                         upper_32_bits(ring->gpu_addr));
 526
 527         /* Initialize the ring buffer's read and write pointers */
 528         WREG32(mmUVD_RBC_RB_RPTR, 0);
 529
 530         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 531         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 532
 533         WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 534
 535         return 0;
 536 }
 537
 538 /**
 539  * uvd_v6_0_stop - stop UVD block
 540  *
 541  * @adev: amdgpu_device pointer
 542  *
 543  * stop the UVD block
 544  */
 545 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 546 {
 547         /* force RBC into idle state */
 548         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 549
 550         /* Stall UMC and register bus before resetting VCPU */
 551         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 552         mdelay(1);
 553
 554         /* put VCPU into reset */
 555         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 556         mdelay(5);
 557
 558         /* disable VCPU clock */
 559         WREG32(mmUVD_VCPU_CNTL, 0x0);
 560
 561         /* Unstall UMC and register bus */
 562         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 563 }
 564
 565 /**
 566  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 567  *
 568  * @ring: amdgpu_ring pointer
 569  * @fence: fence to emit
 570  *
 571  * Write a fence and a trap command to the ring.
 572  */
 573 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 574                                      unsigned flags)
 575 {
 576         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 577
 578         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 579         amdgpu_ring_write(ring, seq);
 580         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 581         amdgpu_ring_write(ring, addr & 0xffffffff);
 582         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 583         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 584         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 585         amdgpu_ring_write(ring, 0);
 586
 587         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 588         amdgpu_ring_write(ring, 0);
 589         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 590         amdgpu_ring_write(ring, 0);
 591         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 592         amdgpu_ring_write(ring, 2);
 593 }
 594
 595 /**
 596  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 597  *
 598  * @ring: amdgpu_ring pointer
 599  *
 600  * Emits an hdp flush.
 601  */
 602 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 603 {
 604         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 605         amdgpu_ring_write(ring, 0);
 606 }
 607
 608 /**
 609  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 610  *
 611  * @ring: amdgpu_ring pointer
 612  *
 613  * Emits an hdp invalidate.
 614  */
 615 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 616 {
 617         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 618         amdgpu_ring_write(ring, 1);
 619 }
 620
 621 /**
 622  * uvd_v6_0_ring_test_ring - register write test
 623  *
 624  * @ring: amdgpu_ring pointer
 625  *
 626  * Test if we can successfully write to the context register
 627  */
 628 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 629 {
 630         struct amdgpu_device *adev = ring->adev;
 631         uint32_t tmp = 0;
 632         unsigned i;
 633         int r;
 634
 635         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 636         r = amdgpu_ring_alloc(ring, 3);
 637         if (r) {
 638                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 639                           ring->idx, r);
 640                 return r;
 641         }
 642         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 643         amdgpu_ring_write(ring, 0xDEADBEEF);
 644         amdgpu_ring_commit(ring);
 645         for (i = 0; i < adev->usec_timeout; i++) {
 646                 tmp = RREG32(mmUVD_CONTEXT_ID);
 647                 if (tmp == 0xDEADBEEF)
 648                         break;
 649                 DRM_UDELAY(1);
 650         }
 651
 652         if (i < adev->usec_timeout) {
 653                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 654                          ring->idx, i);
 655         } else {
 656                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 657                           ring->idx, tmp);
 658                 r = -EINVAL;
 659         }
 660         return r;
 661 }
 662
 663 /**
 664  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 665  *
 666  * @ring: amdgpu_ring pointer
 667  * @ib: indirect buffer to execute
 668  *
 669  * Write ring commands to execute the indirect buffer
 670  */
 671 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 672                                   struct amdgpu_ib *ib,
 673                                   unsigned vm_id, bool ctx_switch)
 674 {
 675         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 676         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 677         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 678         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 679         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 680         amdgpu_ring_write(ring, ib->length_dw);
 681 }
 682
 683 /**
 684  * uvd_v6_0_ring_test_ib - test ib execution
 685  *
 686  * @ring: amdgpu_ring pointer
 687  *
 688  * Test if we can successfully execute an IB
 689  */
 690 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring)
 691 {
 692         struct fence *fence = NULL;
 693         int r;
 694
 695         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
 696         if (r) {
 697                 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
 698                 goto error;
 699         }
 700
 701         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
 702         if (r) {
 703                 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
 704                 goto error;
 705         }
 706
 707         r = fence_wait(fence, false);
 708         if (r) {
 709                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 710                 goto error;
 711         }
 712         DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
 713 error:
 714         fence_put(fence);
 715         return r;
 716 }
 717
 718 static bool uvd_v6_0_is_idle(void *handle)
 719 {
 720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 721
 722         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 723 }
 724
 725 static int uvd_v6_0_wait_for_idle(void *handle)
 726 {
 727         unsigned i;
 728         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 729
 730         for (i = 0; i < adev->usec_timeout; i++) {
 731                 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
 732                         return 0;
 733         }
 734         return -ETIMEDOUT;
 735 }
 736
 737 static int uvd_v6_0_soft_reset(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740
 741         uvd_v6_0_stop(adev);
 742
 743         WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
 744                         ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
 745         mdelay(5);
 746
 747         return uvd_v6_0_start(adev);
 748 }
 749
 750 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 751                                         struct amdgpu_irq_src *source,
 752                                         unsigned type,
 753                                         enum amdgpu_interrupt_state state)
 754 {
 755         // TODO
 756         return 0;
 757 }
 758
 759 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 760                                       struct amdgpu_irq_src *source,
 761                                       struct amdgpu_iv_entry *entry)
 762 {
 763         DRM_DEBUG("IH: UVD TRAP\n");
 764         amdgpu_fence_process(&adev->uvd.ring);
 765         return 0;
 766 }
 767
 768 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
 769 {
 770         uint32_t data, data1, data2, suvd_flags;
 771
 772         data = RREG32(mmUVD_CGC_CTRL);
 773         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 774         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 775
 776         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 777                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 778
 779         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 780                      UVD_SUVD_CGC_GATE__SIT_MASK |
 781                      UVD_SUVD_CGC_GATE__SMP_MASK |
 782                      UVD_SUVD_CGC_GATE__SCM_MASK |
 783                      UVD_SUVD_CGC_GATE__SDB_MASK;
 784
 785         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 786                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 787                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 788
 789         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 790                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 791                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 792                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 793                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 794                         UVD_CGC_CTRL__SYS_MODE_MASK |
 795                         UVD_CGC_CTRL__UDEC_MODE_MASK |
 796                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
 797                         UVD_CGC_CTRL__REGS_MODE_MASK |
 798                         UVD_CGC_CTRL__RBC_MODE_MASK |
 799                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 800                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 801                         UVD_CGC_CTRL__IDCT_MODE_MASK |
 802                         UVD_CGC_CTRL__MPRD_MODE_MASK |
 803                         UVD_CGC_CTRL__MPC_MODE_MASK |
 804                         UVD_CGC_CTRL__LBSI_MODE_MASK |
 805                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
 806                         UVD_CGC_CTRL__WCB_MODE_MASK |
 807                         UVD_CGC_CTRL__VCPU_MODE_MASK |
 808                         UVD_CGC_CTRL__JPEG_MODE_MASK |
 809                         UVD_CGC_CTRL__SCPU_MODE_MASK |
 810                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
 811         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 812                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 813                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 814                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 815                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 816         data1 |= suvd_flags;
 817
 818         WREG32(mmUVD_CGC_CTRL, data);
 819         WREG32(mmUVD_CGC_GATE, 0);
 820         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 821         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 822 }
 823
 824 #if 0
 825 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
 826 {
 827         uint32_t data, data1, cgc_flags, suvd_flags;
 828
 829         data = RREG32(mmUVD_CGC_GATE);
 830         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 831
 832         cgc_flags = UVD_CGC_GATE__SYS_MASK |
 833                 UVD_CGC_GATE__UDEC_MASK |
 834                 UVD_CGC_GATE__MPEG2_MASK |
 835                 UVD_CGC_GATE__RBC_MASK |
 836                 UVD_CGC_GATE__LMI_MC_MASK |
 837                 UVD_CGC_GATE__IDCT_MASK |
 838                 UVD_CGC_GATE__MPRD_MASK |
 839                 UVD_CGC_GATE__MPC_MASK |
 840                 UVD_CGC_GATE__LBSI_MASK |
 841                 UVD_CGC_GATE__LRBBM_MASK |
 842                 UVD_CGC_GATE__UDEC_RE_MASK |
 843                 UVD_CGC_GATE__UDEC_CM_MASK |
 844                 UVD_CGC_GATE__UDEC_IT_MASK |
 845                 UVD_CGC_GATE__UDEC_DB_MASK |
 846                 UVD_CGC_GATE__UDEC_MP_MASK |
 847                 UVD_CGC_GATE__WCB_MASK |
 848                 UVD_CGC_GATE__VCPU_MASK |
 849                 UVD_CGC_GATE__SCPU_MASK |
 850                 UVD_CGC_GATE__JPEG_MASK |
 851                 UVD_CGC_GATE__JPEG2_MASK;
 852
 853         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 854                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 855                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 856                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 857                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 858
 859         data |= cgc_flags;
 860         data1 |= suvd_flags;
 861
 862         WREG32(mmUVD_CGC_GATE, data);
 863         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 864 }
 865 #endif
 866
 867 static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)
 868 {
 869         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
 870
 871         if (enable)
 872                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
 873                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
 874         else
 875                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
 876                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
 877
 878         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
 879 }
 880
 881 static int uvd_v6_0_set_clockgating_state(void *handle,
 882                                           enum amd_clockgating_state state)
 883 {
 884         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 885         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 886         static int curstate = -1;
 887
 888         if (adev->asic_type == CHIP_FIJI ||
 889                         adev->asic_type == CHIP_POLARIS10)
 890                 uvd_v6_set_bypass_mode(adev, enable);
 891
 892         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
 893                 return 0;
 894
 895         if (curstate == state)
 896                 return 0;
 897
 898         curstate = state;
 899         if (enable) {
 900                 /* disable HW gating and enable Sw gating */
 901                 uvd_v6_0_set_sw_clock_gating(adev);
 902         } else {
 903                 /* wait for STATUS to clear */
 904                 if (uvd_v6_0_wait_for_idle(handle))
 905                         return -EBUSY;
 906
 907                 /* enable HW gates because UVD is idle */
 908 /*              uvd_v6_0_set_hw_clock_gating(adev); */
 909         }
 910
 911         return 0;
 912 }
 913
 914 static int uvd_v6_0_set_powergating_state(void *handle,
 915                                           enum amd_powergating_state state)
 916 {
 917         /* This doesn't actually powergate the UVD block.
 918          * That's done in the dpm code via the SMC.  This
 919          * just re-inits the block as necessary.  The actual
 920          * gating still happens in the dpm code.  We should
 921          * revisit this when there is a cleaner line between
 922          * the smc and the hw blocks
 923          */
 924         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 925
 926         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
 927                 return 0;
 928
 929         if (state == AMD_PG_STATE_GATE) {
 930                 uvd_v6_0_stop(adev);
 931                 return 0;
 932         } else {
 933                 return uvd_v6_0_start(adev);
 934         }
 935 }
 936
 937 const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 938         .name = "uvd_v6_0",
 939         .early_init = uvd_v6_0_early_init,
 940         .late_init = NULL,
 941         .sw_init = uvd_v6_0_sw_init,
 942         .sw_fini = uvd_v6_0_sw_fini,
 943         .hw_init = uvd_v6_0_hw_init,
 944         .hw_fini = uvd_v6_0_hw_fini,
 945         .suspend = uvd_v6_0_suspend,
 946         .resume = uvd_v6_0_resume,
 947         .is_idle = uvd_v6_0_is_idle,
 948         .wait_for_idle = uvd_v6_0_wait_for_idle,
 949         .soft_reset = uvd_v6_0_soft_reset,
 950         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
 951         .set_powergating_state = uvd_v6_0_set_powergating_state,
 952 };
 953
 954 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
 955         .get_rptr = uvd_v6_0_ring_get_rptr,
 956         .get_wptr = uvd_v6_0_ring_get_wptr,
 957         .set_wptr = uvd_v6_0_ring_set_wptr,
 958         .parse_cs = amdgpu_uvd_ring_parse_cs,
 959         .emit_ib = uvd_v6_0_ring_emit_ib,
 960         .emit_fence = uvd_v6_0_ring_emit_fence,
 961         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
 962         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
 963         .test_ring = uvd_v6_0_ring_test_ring,
 964         .test_ib = uvd_v6_0_ring_test_ib,
 965         .insert_nop = amdgpu_ring_insert_nop,
 966         .pad_ib = amdgpu_ring_generic_pad_ib,
 967 };
 968
 969 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
 970 {
 971         adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs;
 972 }
 973
 974 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
 975         .set = uvd_v6_0_set_interrupt_state,
 976         .process = uvd_v6_0_process_interrupt,
 977 };
 978
 979 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
 980 {
 981         adev->uvd.irq.num_types = 1;
 982         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
 983 }