2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/gfp.h>
26 #include <linux/slab.h>
27 #include "amd_shared.h"
28 #include "amd_powerplay.h"
29 #include "pp_instance.h"
30 #include "power_state.h"
31 #include "eventmanager.h"
34 #define PP_CHECK(handle) \
36 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
40 #define PP_CHECK_HW(hwmgr) \
42 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
46 static int pp_early_init(void *handle)
51 static int pp_sw_init(void *handle)
53 struct pp_instance *pp_handle;
54 struct pp_hwmgr *hwmgr;
60 pp_handle = (struct pp_instance *)handle;
61 hwmgr = pp_handle->hwmgr;
65 if (hwmgr->pptable_func == NULL ||
66 hwmgr->pptable_func->pptable_init == NULL ||
67 hwmgr->hwmgr_func->backend_init == NULL)
70 ret = hwmgr->pptable_func->pptable_init(hwmgr);
74 ret = hwmgr->hwmgr_func->backend_init(hwmgr);
78 pr_info("amdgpu: powerplay initialized\n");
82 if (hwmgr->pptable_func->pptable_fini)
83 hwmgr->pptable_func->pptable_fini(hwmgr);
85 pr_err("amdgpu: powerplay initialization failed\n");
89 static int pp_sw_fini(void *handle)
91 struct pp_instance *pp_handle;
92 struct pp_hwmgr *hwmgr;
98 pp_handle = (struct pp_instance *)handle;
99 hwmgr = pp_handle->hwmgr;
103 if (hwmgr->hwmgr_func->backend_fini != NULL)
104 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
106 if (hwmgr->pptable_func->pptable_fini)
107 hwmgr->pptable_func->pptable_fini(hwmgr);
112 static int pp_hw_init(void *handle)
114 struct pp_instance *pp_handle;
115 struct pp_smumgr *smumgr;
116 struct pp_eventmgr *eventmgr;
122 pp_handle = (struct pp_instance *)handle;
123 smumgr = pp_handle->smu_mgr;
125 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
126 smumgr->smumgr_funcs->smu_init == NULL ||
127 smumgr->smumgr_funcs->start_smu == NULL)
130 ret = smumgr->smumgr_funcs->smu_init(smumgr);
132 printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
136 ret = smumgr->smumgr_funcs->start_smu(smumgr);
138 printk(KERN_ERR "[ powerplay ] smc start failed\n");
139 smumgr->smumgr_funcs->smu_fini(smumgr);
143 hw_init_power_state_table(pp_handle->hwmgr);
144 eventmgr = pp_handle->eventmgr;
146 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
149 ret = eventmgr->pp_eventmgr_init(eventmgr);
153 static int pp_hw_fini(void *handle)
155 struct pp_instance *pp_handle;
156 struct pp_smumgr *smumgr;
157 struct pp_eventmgr *eventmgr;
162 pp_handle = (struct pp_instance *)handle;
163 eventmgr = pp_handle->eventmgr;
165 if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL)
166 eventmgr->pp_eventmgr_fini(eventmgr);
168 smumgr = pp_handle->smu_mgr;
170 if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
171 smumgr->smumgr_funcs->smu_fini != NULL)
172 smumgr->smumgr_funcs->smu_fini(smumgr);
177 static bool pp_is_idle(void *handle)
182 static int pp_wait_for_idle(void *handle)
187 static int pp_sw_reset(void *handle)
193 static int pp_set_clockgating_state(void *handle,
194 enum amd_clockgating_state state)
196 struct pp_hwmgr *hwmgr;
197 uint32_t msg_id, pp_state;
202 hwmgr = ((struct pp_instance *)handle)->hwmgr;
206 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
207 printk(KERN_INFO "%s was not implemented.\n", __func__);
211 if (state == AMD_CG_STATE_UNGATE)
214 pp_state = PP_STATE_CG | PP_STATE_LS;
216 /* Enable/disable GFX blocks clock gating through SMU */
217 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
219 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
221 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
222 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
224 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
226 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
227 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
229 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
231 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
232 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
234 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
236 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
237 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
239 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
241 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
243 /* Enable/disable System blocks clock gating through SMU */
244 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
246 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
248 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
249 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
251 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
253 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
254 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
256 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
258 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
259 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
261 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
263 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
264 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
266 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
268 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
269 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
271 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
273 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
274 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
276 PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
278 hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
283 static int pp_set_powergating_state(void *handle,
284 enum amd_powergating_state state)
286 struct pp_hwmgr *hwmgr;
291 hwmgr = ((struct pp_instance *)handle)->hwmgr;
295 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
296 printk(KERN_INFO "%s was not implemented.\n", __func__);
300 /* Enable/disable GFX per cu powergating through SMU */
301 return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
302 state == AMD_PG_STATE_GATE ? true : false);
305 static int pp_suspend(void *handle)
307 struct pp_instance *pp_handle;
308 struct pp_eventmgr *eventmgr;
309 struct pem_event_data event_data = { {0} };
314 pp_handle = (struct pp_instance *)handle;
315 eventmgr = pp_handle->eventmgr;
316 pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
320 static int pp_resume(void *handle)
322 struct pp_instance *pp_handle;
323 struct pp_eventmgr *eventmgr;
324 struct pem_event_data event_data = { {0} };
325 struct pp_smumgr *smumgr;
331 pp_handle = (struct pp_instance *)handle;
332 smumgr = pp_handle->smu_mgr;
334 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
335 smumgr->smumgr_funcs->start_smu == NULL)
338 ret = smumgr->smumgr_funcs->start_smu(smumgr);
340 printk(KERN_ERR "[ powerplay ] smc start failed\n");
341 smumgr->smumgr_funcs->smu_fini(smumgr);
345 eventmgr = pp_handle->eventmgr;
346 pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
351 const struct amd_ip_funcs pp_ip_funcs = {
353 .early_init = pp_early_init,
355 .sw_init = pp_sw_init,
356 .sw_fini = pp_sw_fini,
357 .hw_init = pp_hw_init,
358 .hw_fini = pp_hw_fini,
359 .suspend = pp_suspend,
361 .is_idle = pp_is_idle,
362 .wait_for_idle = pp_wait_for_idle,
363 .soft_reset = pp_sw_reset,
364 .set_clockgating_state = pp_set_clockgating_state,
365 .set_powergating_state = pp_set_powergating_state,
368 static int pp_dpm_load_fw(void *handle)
373 static int pp_dpm_fw_loading_complete(void *handle)
378 static int pp_dpm_force_performance_level(void *handle,
379 enum amd_dpm_forced_level level)
381 struct pp_instance *pp_handle;
382 struct pp_hwmgr *hwmgr;
387 pp_handle = (struct pp_instance *)handle;
389 hwmgr = pp_handle->hwmgr;
393 if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
394 printk(KERN_INFO "%s was not implemented.\n", __func__);
398 hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
403 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
406 struct pp_hwmgr *hwmgr;
411 hwmgr = ((struct pp_instance *)handle)->hwmgr;
416 return (((struct pp_instance *)handle)->hwmgr->dpm_level);
419 static int pp_dpm_get_sclk(void *handle, bool low)
421 struct pp_hwmgr *hwmgr;
426 hwmgr = ((struct pp_instance *)handle)->hwmgr;
430 if (hwmgr->hwmgr_func->get_sclk == NULL) {
431 printk(KERN_INFO "%s was not implemented.\n", __func__);
435 return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
438 static int pp_dpm_get_mclk(void *handle, bool low)
440 struct pp_hwmgr *hwmgr;
445 hwmgr = ((struct pp_instance *)handle)->hwmgr;
449 if (hwmgr->hwmgr_func->get_mclk == NULL) {
450 printk(KERN_INFO "%s was not implemented.\n", __func__);
454 return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
457 static int pp_dpm_powergate_vce(void *handle, bool gate)
459 struct pp_hwmgr *hwmgr;
464 hwmgr = ((struct pp_instance *)handle)->hwmgr;
468 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
469 printk(KERN_INFO "%s was not implemented.\n", __func__);
473 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
476 static int pp_dpm_powergate_uvd(void *handle, bool gate)
478 struct pp_hwmgr *hwmgr;
483 hwmgr = ((struct pp_instance *)handle)->hwmgr;
487 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
488 printk(KERN_INFO "%s was not implemented.\n", __func__);
492 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
495 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
498 case POWER_STATE_TYPE_BATTERY:
499 return PP_StateUILabel_Battery;
500 case POWER_STATE_TYPE_BALANCED:
501 return PP_StateUILabel_Balanced;
502 case POWER_STATE_TYPE_PERFORMANCE:
503 return PP_StateUILabel_Performance;
505 return PP_StateUILabel_None;
509 int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
512 struct pp_instance *pp_handle;
513 struct pem_event_data data = { {0} };
515 pp_handle = (struct pp_instance *)handle;
517 if (pp_handle == NULL)
521 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
522 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
524 case AMD_PP_EVENT_ENABLE_USER_STATE:
526 enum amd_pm_state_type ps;
530 ps = *(unsigned long *)input;
532 data.requested_ui_label = power_state_convert(ps);
533 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
536 case AMD_PP_EVENT_COMPLETE_INIT:
537 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
539 case AMD_PP_EVENT_READJUST_POWER_STATE:
540 pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;
541 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
549 enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
551 struct pp_hwmgr *hwmgr;
552 struct pp_power_state *state;
557 hwmgr = ((struct pp_instance *)handle)->hwmgr;
559 if (hwmgr == NULL || hwmgr->current_ps == NULL)
562 state = hwmgr->current_ps;
564 switch (state->classification.ui_label) {
565 case PP_StateUILabel_Battery:
566 return POWER_STATE_TYPE_BATTERY;
567 case PP_StateUILabel_Balanced:
568 return POWER_STATE_TYPE_BALANCED;
569 case PP_StateUILabel_Performance:
570 return POWER_STATE_TYPE_PERFORMANCE;
572 if (state->classification.flags & PP_StateClassificationFlag_Boot)
573 return POWER_STATE_TYPE_INTERNAL_BOOT;
575 return POWER_STATE_TYPE_DEFAULT;
580 pp_debugfs_print_current_performance_level(void *handle,
583 struct pp_hwmgr *hwmgr;
588 hwmgr = ((struct pp_instance *)handle)->hwmgr;
590 if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
593 if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
594 printk(KERN_INFO "%s was not implemented.\n", __func__);
598 hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
601 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
603 struct pp_hwmgr *hwmgr;
608 hwmgr = ((struct pp_instance *)handle)->hwmgr;
612 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
613 printk(KERN_INFO "%s was not implemented.\n", __func__);
617 return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
620 static int pp_dpm_get_fan_control_mode(void *handle)
622 struct pp_hwmgr *hwmgr;
627 hwmgr = ((struct pp_instance *)handle)->hwmgr;
631 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
632 printk(KERN_INFO "%s was not implemented.\n", __func__);
636 return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
639 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
641 struct pp_hwmgr *hwmgr;
646 hwmgr = ((struct pp_instance *)handle)->hwmgr;
650 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
651 printk(KERN_INFO "%s was not implemented.\n", __func__);
655 return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
658 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
660 struct pp_hwmgr *hwmgr;
665 hwmgr = ((struct pp_instance *)handle)->hwmgr;
669 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
670 printk(KERN_INFO "%s was not implemented.\n", __func__);
674 return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
677 static int pp_dpm_get_temperature(void *handle)
679 struct pp_hwmgr *hwmgr;
684 hwmgr = ((struct pp_instance *)handle)->hwmgr;
688 if (hwmgr->hwmgr_func->get_temperature == NULL) {
689 printk(KERN_INFO "%s was not implemented.\n", __func__);
693 return hwmgr->hwmgr_func->get_temperature(hwmgr);
696 static int pp_dpm_get_pp_num_states(void *handle,
697 struct pp_states_info *data)
699 struct pp_hwmgr *hwmgr;
705 hwmgr = ((struct pp_instance *)handle)->hwmgr;
707 if (hwmgr == NULL || hwmgr->ps == NULL)
710 data->nums = hwmgr->num_ps;
712 for (i = 0; i < hwmgr->num_ps; i++) {
713 struct pp_power_state *state = (struct pp_power_state *)
714 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
715 switch (state->classification.ui_label) {
716 case PP_StateUILabel_Battery:
717 data->states[i] = POWER_STATE_TYPE_BATTERY;
719 case PP_StateUILabel_Balanced:
720 data->states[i] = POWER_STATE_TYPE_BALANCED;
722 case PP_StateUILabel_Performance:
723 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
726 if (state->classification.flags & PP_StateClassificationFlag_Boot)
727 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
729 data->states[i] = POWER_STATE_TYPE_DEFAULT;
736 static int pp_dpm_get_pp_table(void *handle, char **table)
738 struct pp_hwmgr *hwmgr;
743 hwmgr = ((struct pp_instance *)handle)->hwmgr;
747 if (!hwmgr->soft_pp_table)
750 *table = (char *)hwmgr->soft_pp_table;
752 return hwmgr->soft_pp_table_size;
755 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
757 struct pp_hwmgr *hwmgr;
762 hwmgr = ((struct pp_instance *)handle)->hwmgr;
766 if (!hwmgr->hardcode_pp_table) {
767 hwmgr->hardcode_pp_table =
768 kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
770 if (!hwmgr->hardcode_pp_table)
773 /* to avoid powerplay crash when hardcode pptable is empty */
774 memcpy(hwmgr->hardcode_pp_table, hwmgr->soft_pp_table,
775 hwmgr->soft_pp_table_size);
778 memcpy(hwmgr->hardcode_pp_table, buf, size);
780 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
782 return amd_powerplay_reset(handle);
785 static int pp_dpm_force_clock_level(void *handle,
786 enum pp_clock_type type, uint32_t mask)
788 struct pp_hwmgr *hwmgr;
793 hwmgr = ((struct pp_instance *)handle)->hwmgr;
797 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
798 printk(KERN_INFO "%s was not implemented.\n", __func__);
802 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
805 static int pp_dpm_print_clock_levels(void *handle,
806 enum pp_clock_type type, char *buf)
808 struct pp_hwmgr *hwmgr;
813 hwmgr = ((struct pp_instance *)handle)->hwmgr;
817 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
818 printk(KERN_INFO "%s was not implemented.\n", __func__);
821 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
824 static int pp_dpm_get_sclk_od(void *handle)
826 struct pp_hwmgr *hwmgr;
831 hwmgr = ((struct pp_instance *)handle)->hwmgr;
835 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
836 printk(KERN_INFO "%s was not implemented.\n", __func__);
840 return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
843 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
845 struct pp_hwmgr *hwmgr;
850 hwmgr = ((struct pp_instance *)handle)->hwmgr;
854 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
855 printk(KERN_INFO "%s was not implemented.\n", __func__);
859 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
862 static int pp_dpm_get_mclk_od(void *handle)
864 struct pp_hwmgr *hwmgr;
869 hwmgr = ((struct pp_instance *)handle)->hwmgr;
873 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
874 printk(KERN_INFO "%s was not implemented.\n", __func__);
878 return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
881 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
883 struct pp_hwmgr *hwmgr;
888 hwmgr = ((struct pp_instance *)handle)->hwmgr;
892 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
893 printk(KERN_INFO "%s was not implemented.\n", __func__);
897 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
900 const struct amd_powerplay_funcs pp_dpm_funcs = {
901 .get_temperature = pp_dpm_get_temperature,
902 .load_firmware = pp_dpm_load_fw,
903 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
904 .force_performance_level = pp_dpm_force_performance_level,
905 .get_performance_level = pp_dpm_get_performance_level,
906 .get_current_power_state = pp_dpm_get_current_power_state,
907 .get_sclk = pp_dpm_get_sclk,
908 .get_mclk = pp_dpm_get_mclk,
909 .powergate_vce = pp_dpm_powergate_vce,
910 .powergate_uvd = pp_dpm_powergate_uvd,
911 .dispatch_tasks = pp_dpm_dispatch_tasks,
912 .print_current_performance_level = pp_debugfs_print_current_performance_level,
913 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
914 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
915 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
916 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
917 .get_pp_num_states = pp_dpm_get_pp_num_states,
918 .get_pp_table = pp_dpm_get_pp_table,
919 .set_pp_table = pp_dpm_set_pp_table,
920 .force_clock_level = pp_dpm_force_clock_level,
921 .print_clock_levels = pp_dpm_print_clock_levels,
922 .get_sclk_od = pp_dpm_get_sclk_od,
923 .set_sclk_od = pp_dpm_set_sclk_od,
924 .get_mclk_od = pp_dpm_get_mclk_od,
925 .set_mclk_od = pp_dpm_set_mclk_od,
928 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
929 struct amd_powerplay *amd_pp)
932 struct pp_instance *handle;
934 handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
938 handle->pp_valid = PP_VALID;
940 ret = smum_init(pp_init, handle);
944 ret = hwmgr_init(pp_init, handle);
948 ret = eventmgr_init(handle);
952 amd_pp->pp_handle = handle;
956 hwmgr_fini(handle->hwmgr);
958 smum_fini(handle->smu_mgr);
964 static int amd_pp_instance_fini(void *handle)
966 struct pp_instance *instance = (struct pp_instance *)handle;
968 if (instance == NULL)
971 eventmgr_fini(instance->eventmgr);
973 hwmgr_fini(instance->hwmgr);
975 smum_fini(instance->smu_mgr);
981 int amd_powerplay_init(struct amd_pp_init *pp_init,
982 struct amd_powerplay *amd_pp)
986 if (pp_init == NULL || amd_pp == NULL)
989 ret = amd_pp_instance_init(pp_init, amd_pp);
994 amd_pp->ip_funcs = &pp_ip_funcs;
995 amd_pp->pp_funcs = &pp_dpm_funcs;
1000 int amd_powerplay_fini(void *handle)
1002 amd_pp_instance_fini(handle);
1007 int amd_powerplay_reset(void *handle)
1009 struct pp_instance *instance = (struct pp_instance *)handle;
1010 struct pp_eventmgr *eventmgr;
1011 struct pem_event_data event_data = { {0} };
1014 if (instance == NULL)
1017 eventmgr = instance->eventmgr;
1018 if (!eventmgr || !eventmgr->pp_eventmgr_fini)
1021 eventmgr->pp_eventmgr_fini(eventmgr);
1023 ret = pp_sw_fini(handle);
1027 kfree(instance->hwmgr->ps);
1029 ret = pp_sw_init(handle);
1033 hw_init_power_state_table(instance->hwmgr);
1035 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
1038 ret = eventmgr->pp_eventmgr_init(eventmgr);
1042 return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
1045 /* export this function to DAL */
1047 int amd_powerplay_display_configuration_change(void *handle,
1048 const struct amd_pp_display_configuration *display_config)
1050 struct pp_hwmgr *hwmgr;
1052 PP_CHECK((struct pp_instance *)handle);
1054 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1056 phm_store_dal_configuration_data(hwmgr, display_config);
1061 int amd_powerplay_get_display_power_level(void *handle,
1062 struct amd_pp_simple_clock_info *output)
1064 struct pp_hwmgr *hwmgr;
1066 PP_CHECK((struct pp_instance *)handle);
1071 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1073 return phm_get_dal_power_level(hwmgr, output);
1076 int amd_powerplay_get_current_clocks(void *handle,
1077 struct amd_pp_clock_info *clocks)
1079 struct pp_hwmgr *hwmgr;
1080 struct amd_pp_simple_clock_info simple_clocks;
1081 struct pp_clock_info hw_clocks;
1083 PP_CHECK((struct pp_instance *)handle);
1088 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1090 phm_get_dal_power_level(hwmgr, &simple_clocks);
1092 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
1093 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
1094 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
1096 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
1097 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
1100 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1101 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1102 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1103 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1104 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1105 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1107 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1108 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1110 clocks->max_clocks_state = simple_clocks.level;
1112 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1113 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1114 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1121 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1125 struct pp_hwmgr *hwmgr;
1127 PP_CHECK((struct pp_instance *)handle);
1132 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1134 result = phm_get_clock_by_type(hwmgr, type, clocks);
1139 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1140 struct amd_pp_simple_clock_info *clocks)
1143 struct pp_hwmgr *hwmgr;
1145 PP_CHECK((struct pp_instance *)handle);
1150 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1152 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1153 result = phm_get_max_high_clocks(hwmgr, clocks);