drivers/gpu/drm/amd/powerplay/amd_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/gfp.h>
  26 #include <linux/slab.h>
  27 #include "amd_shared.h"
  28 #include "amd_powerplay.h"
  29 #include "pp_instance.h"
  30 #include "power_state.h"
  31 #include "eventmanager.h"
  32 #include "pp_debug.h"
  33
  34 #define PP_CHECK(handle)                                                \
  35         do {                                                            \
  36                 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
  37                         return -EINVAL;                                 \
  38         } while (0)
  39
  40 #define PP_CHECK_HW(hwmgr)                                              \
  41         do {                                                            \
  42                 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL)     \
  43                         return -EINVAL;                                 \
  44         } while (0)
  45
  46 static int pp_early_init(void *handle)
  47 {
  48         return 0;
  49 }
  50
  51 static int pp_sw_init(void *handle)
  52 {
  53         struct pp_instance *pp_handle;
  54         struct pp_hwmgr  *hwmgr;
  55         int ret = 0;
  56
  57         if (handle == NULL)
  58                 return -EINVAL;
  59
  60         pp_handle = (struct pp_instance *)handle;
  61         hwmgr = pp_handle->hwmgr;
  62
  63         PP_CHECK_HW(hwmgr);
  64
  65         if (hwmgr->pptable_func == NULL ||
  66             hwmgr->pptable_func->pptable_init == NULL ||
  67             hwmgr->hwmgr_func->backend_init == NULL)
  68                 return -EINVAL;
  69
  70         ret = hwmgr->pptable_func->pptable_init(hwmgr);
  71         if (ret)
  72                 goto err;
  73
  74         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
  75         if (ret)
  76                 goto err;
  77
  78         pr_info("amdgpu: powerplay initialized\n");
  79
  80         return 0;
  81 err:
  82         pr_err("amdgpu: powerplay initialization failed\n");
  83         return ret;
  84 }
  85
  86 static int pp_sw_fini(void *handle)
  87 {
  88         struct pp_instance *pp_handle;
  89         struct pp_hwmgr  *hwmgr;
  90         int ret = 0;
  91
  92         if (handle == NULL)
  93                 return -EINVAL;
  94
  95         pp_handle = (struct pp_instance *)handle;
  96         hwmgr = pp_handle->hwmgr;
  97
  98         PP_CHECK_HW(hwmgr);
  99
 100         if (hwmgr->hwmgr_func->backend_fini != NULL)
 101                 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
 102
 103         return ret;
 104 }
 105
 106 static int pp_hw_init(void *handle)
 107 {
 108         struct pp_instance *pp_handle;
 109         struct pp_smumgr *smumgr;
 110         struct pp_eventmgr *eventmgr;
 111         int ret = 0;
 112
 113         if (handle == NULL)
 114                 return -EINVAL;
 115
 116         pp_handle = (struct pp_instance *)handle;
 117         smumgr = pp_handle->smu_mgr;
 118
 119         if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
 120                 smumgr->smumgr_funcs->smu_init == NULL ||
 121                 smumgr->smumgr_funcs->start_smu == NULL)
 122                 return -EINVAL;
 123
 124         ret = smumgr->smumgr_funcs->smu_init(smumgr);
 125         if (ret) {
 126                 printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
 127                 return ret;
 128         }
 129
 130         ret = smumgr->smumgr_funcs->start_smu(smumgr);
 131         if (ret) {
 132                 printk(KERN_ERR "[ powerplay ] smc start failed\n");
 133                 smumgr->smumgr_funcs->smu_fini(smumgr);
 134                 return ret;
 135         }
 136
 137         hw_init_power_state_table(pp_handle->hwmgr);
 138         eventmgr = pp_handle->eventmgr;
 139
 140         if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
 141                 return -EINVAL;
 142
 143         ret = eventmgr->pp_eventmgr_init(eventmgr);
 144         return 0;
 145 }
 146
 147 static int pp_hw_fini(void *handle)
 148 {
 149         struct pp_instance *pp_handle;
 150         struct pp_smumgr *smumgr;
 151         struct pp_eventmgr *eventmgr;
 152
 153         if (handle == NULL)
 154                 return -EINVAL;
 155
 156         pp_handle = (struct pp_instance *)handle;
 157         eventmgr = pp_handle->eventmgr;
 158
 159         if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL)
 160                 eventmgr->pp_eventmgr_fini(eventmgr);
 161
 162         smumgr = pp_handle->smu_mgr;
 163
 164         if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
 165                 smumgr->smumgr_funcs->smu_fini != NULL)
 166                 smumgr->smumgr_funcs->smu_fini(smumgr);
 167
 168         return 0;
 169 }
 170
 171 static bool pp_is_idle(void *handle)
 172 {
 173         return 0;
 174 }
 175
 176 static int pp_wait_for_idle(void *handle)
 177 {
 178         return 0;
 179 }
 180
 181 static int pp_sw_reset(void *handle)
 182 {
 183         return 0;
 184 }
 185
 186
 187 static int pp_set_clockgating_state(void *handle,
 188                                     enum amd_clockgating_state state)
 189 {
 190         struct pp_hwmgr  *hwmgr;
 191         uint32_t msg_id, pp_state;
 192
 193         if (handle == NULL)
 194                 return -EINVAL;
 195
 196         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 197
 198         PP_CHECK_HW(hwmgr);
 199
 200         if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
 201                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 202                 return 0;
 203         }
 204
 205         if (state == AMD_CG_STATE_UNGATE)
 206                 pp_state = 0;
 207         else
 208                 pp_state = PP_STATE_CG | PP_STATE_LS;
 209
 210         /* Enable/disable GFX blocks clock gating through SMU */
 211         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 212                         PP_BLOCK_GFX_CG,
 213                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 214                         pp_state);
 215         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 216         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 217                         PP_BLOCK_GFX_3D,
 218                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 219                         pp_state);
 220         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 221         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 222                         PP_BLOCK_GFX_RLC,
 223                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 224                         pp_state);
 225         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 226         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 227                         PP_BLOCK_GFX_CP,
 228                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 229                         pp_state);
 230         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 231         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 232                         PP_BLOCK_GFX_MG,
 233                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 234                         pp_state);
 235         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 236
 237         /* Enable/disable System blocks clock gating through SMU */
 238         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 239                         PP_BLOCK_SYS_BIF,
 240                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 241                         pp_state);
 242         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 243         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 244                         PP_BLOCK_SYS_BIF,
 245                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 246                         pp_state);
 247         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 248         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 249                         PP_BLOCK_SYS_MC,
 250                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 251                         pp_state);
 252         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 253         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 254                         PP_BLOCK_SYS_ROM,
 255                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 256                         pp_state);
 257         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 258         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 259                         PP_BLOCK_SYS_DRM,
 260                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 261                         pp_state);
 262         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 263         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 264                         PP_BLOCK_SYS_HDP,
 265                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 266                         pp_state);
 267         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 268         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 269                         PP_BLOCK_SYS_SDMA,
 270                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 271                         pp_state);
 272         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 273
 274         return 0;
 275 }
 276
 277 static int pp_set_powergating_state(void *handle,
 278                                     enum amd_powergating_state state)
 279 {
 280         struct pp_hwmgr  *hwmgr;
 281
 282         if (handle == NULL)
 283                 return -EINVAL;
 284
 285         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 286
 287         PP_CHECK_HW(hwmgr);
 288
 289         if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
 290                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 291                 return 0;
 292         }
 293
 294         /* Enable/disable GFX per cu powergating through SMU */
 295         return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
 296                         state == AMD_PG_STATE_GATE ? true : false);
 297 }
 298
 299 static int pp_suspend(void *handle)
 300 {
 301         struct pp_instance *pp_handle;
 302         struct pp_eventmgr *eventmgr;
 303         struct pem_event_data event_data = { {0} };
 304
 305         if (handle == NULL)
 306                 return -EINVAL;
 307
 308         pp_handle = (struct pp_instance *)handle;
 309         eventmgr = pp_handle->eventmgr;
 310         pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
 311         return 0;
 312 }
 313
 314 static int pp_resume(void *handle)
 315 {
 316         struct pp_instance *pp_handle;
 317         struct pp_eventmgr *eventmgr;
 318         struct pem_event_data event_data = { {0} };
 319         struct pp_smumgr *smumgr;
 320         int ret;
 321
 322         if (handle == NULL)
 323                 return -EINVAL;
 324
 325         pp_handle = (struct pp_instance *)handle;
 326         smumgr = pp_handle->smu_mgr;
 327
 328         if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
 329                 smumgr->smumgr_funcs->start_smu == NULL)
 330                 return -EINVAL;
 331
 332         ret = smumgr->smumgr_funcs->start_smu(smumgr);
 333         if (ret) {
 334                 printk(KERN_ERR "[ powerplay ] smc start failed\n");
 335                 smumgr->smumgr_funcs->smu_fini(smumgr);
 336                 return ret;
 337         }
 338
 339         eventmgr = pp_handle->eventmgr;
 340         pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
 341
 342         return 0;
 343 }
 344
 345 const struct amd_ip_funcs pp_ip_funcs = {
 346         .name = "powerplay",
 347         .early_init = pp_early_init,
 348         .late_init = NULL,
 349         .sw_init = pp_sw_init,
 350         .sw_fini = pp_sw_fini,
 351         .hw_init = pp_hw_init,
 352         .hw_fini = pp_hw_fini,
 353         .suspend = pp_suspend,
 354         .resume = pp_resume,
 355         .is_idle = pp_is_idle,
 356         .wait_for_idle = pp_wait_for_idle,
 357         .soft_reset = pp_sw_reset,
 358         .set_clockgating_state = pp_set_clockgating_state,
 359         .set_powergating_state = pp_set_powergating_state,
 360 };
 361
 362 static int pp_dpm_load_fw(void *handle)
 363 {
 364         return 0;
 365 }
 366
 367 static int pp_dpm_fw_loading_complete(void *handle)
 368 {
 369         return 0;
 370 }
 371
 372 static int pp_dpm_force_performance_level(void *handle,
 373                                         enum amd_dpm_forced_level level)
 374 {
 375         struct pp_instance *pp_handle;
 376         struct pp_hwmgr  *hwmgr;
 377
 378         if (handle == NULL)
 379                 return -EINVAL;
 380
 381         pp_handle = (struct pp_instance *)handle;
 382
 383         hwmgr = pp_handle->hwmgr;
 384
 385         PP_CHECK_HW(hwmgr);
 386
 387         if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
 388                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 389                 return 0;
 390         }
 391
 392         hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 393
 394         return 0;
 395 }
 396
 397 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
 398                                                                 void *handle)
 399 {
 400         struct pp_hwmgr  *hwmgr;
 401
 402         if (handle == NULL)
 403                 return -EINVAL;
 404
 405         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 406
 407         if (hwmgr == NULL)
 408                 return -EINVAL;
 409
 410         return (((struct pp_instance *)handle)->hwmgr->dpm_level);
 411 }
 412
 413 static int pp_dpm_get_sclk(void *handle, bool low)
 414 {
 415         struct pp_hwmgr  *hwmgr;
 416
 417         if (handle == NULL)
 418                 return -EINVAL;
 419
 420         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 421
 422         PP_CHECK_HW(hwmgr);
 423
 424         if (hwmgr->hwmgr_func->get_sclk == NULL) {
 425                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 426                 return 0;
 427         }
 428
 429         return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
 430 }
 431
 432 static int pp_dpm_get_mclk(void *handle, bool low)
 433 {
 434         struct pp_hwmgr  *hwmgr;
 435
 436         if (handle == NULL)
 437                 return -EINVAL;
 438
 439         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 440
 441         PP_CHECK_HW(hwmgr);
 442
 443         if (hwmgr->hwmgr_func->get_mclk == NULL) {
 444                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 445                 return 0;
 446         }
 447
 448         return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
 449 }
 450
 451 static int pp_dpm_powergate_vce(void *handle, bool gate)
 452 {
 453         struct pp_hwmgr  *hwmgr;
 454
 455         if (handle == NULL)
 456                 return -EINVAL;
 457
 458         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 459
 460         PP_CHECK_HW(hwmgr);
 461
 462         if (hwmgr->hwmgr_func->powergate_vce == NULL) {
 463                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 464                 return 0;
 465         }
 466
 467         return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 468 }
 469
 470 static int pp_dpm_powergate_uvd(void *handle, bool gate)
 471 {
 472         struct pp_hwmgr  *hwmgr;
 473
 474         if (handle == NULL)
 475                 return -EINVAL;
 476
 477         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 478
 479         PP_CHECK_HW(hwmgr);
 480
 481         if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
 482                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 483                 return 0;
 484         }
 485
 486         return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 487 }
 488
 489 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 490 {
 491         switch (state) {
 492         case POWER_STATE_TYPE_BATTERY:
 493                 return PP_StateUILabel_Battery;
 494         case POWER_STATE_TYPE_BALANCED:
 495                 return PP_StateUILabel_Balanced;
 496         case POWER_STATE_TYPE_PERFORMANCE:
 497                 return PP_StateUILabel_Performance;
 498         default:
 499                 return PP_StateUILabel_None;
 500         }
 501 }
 502
 503 int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
 504 {
 505         int ret = 0;
 506         struct pp_instance *pp_handle;
 507         struct pem_event_data data = { {0} };
 508
 509         pp_handle = (struct pp_instance *)handle;
 510
 511         if (pp_handle == NULL)
 512                 return -EINVAL;
 513
 514         switch (event_id) {
 515         case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
 516                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 517                 break;
 518         case AMD_PP_EVENT_ENABLE_USER_STATE:
 519         {
 520                 enum amd_pm_state_type  ps;
 521
 522                 if (input == NULL)
 523                         return -EINVAL;
 524                 ps = *(unsigned long *)input;
 525
 526                 data.requested_ui_label = power_state_convert(ps);
 527                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 528                 break;
 529         }
 530         case AMD_PP_EVENT_COMPLETE_INIT:
 531                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 532                 break;
 533         default:
 534                 break;
 535         }
 536         return ret;
 537 }
 538
 539 enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
 540 {
 541         struct pp_hwmgr *hwmgr;
 542         struct pp_power_state *state;
 543
 544         if (handle == NULL)
 545                 return -EINVAL;
 546
 547         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 548
 549         if (hwmgr == NULL || hwmgr->current_ps == NULL)
 550                 return -EINVAL;
 551
 552         state = hwmgr->current_ps;
 553
 554         switch (state->classification.ui_label) {
 555         case PP_StateUILabel_Battery:
 556                 return POWER_STATE_TYPE_BATTERY;
 557         case PP_StateUILabel_Balanced:
 558                 return POWER_STATE_TYPE_BALANCED;
 559         case PP_StateUILabel_Performance:
 560                 return POWER_STATE_TYPE_PERFORMANCE;
 561         default:
 562                 if (state->classification.flags & PP_StateClassificationFlag_Boot)
 563                         return  POWER_STATE_TYPE_INTERNAL_BOOT;
 564                 else
 565                         return POWER_STATE_TYPE_DEFAULT;
 566         }
 567 }
 568
 569 static void
 570 pp_debugfs_print_current_performance_level(void *handle,
 571                                                struct seq_file *m)
 572 {
 573         struct pp_hwmgr  *hwmgr;
 574
 575         if (handle == NULL)
 576                 return;
 577
 578         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 579
 580         if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
 581                 return;
 582
 583         if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
 584                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 585                 return;
 586         }
 587
 588         hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
 589 }
 590
 591 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
 592 {
 593         struct pp_hwmgr  *hwmgr;
 594
 595         if (handle == NULL)
 596                 return -EINVAL;
 597
 598         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 599
 600         PP_CHECK_HW(hwmgr);
 601
 602         if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
 603                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 604                 return 0;
 605         }
 606
 607         return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
 608 }
 609
 610 static int pp_dpm_get_fan_control_mode(void *handle)
 611 {
 612         struct pp_hwmgr  *hwmgr;
 613
 614         if (handle == NULL)
 615                 return -EINVAL;
 616
 617         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 618
 619         PP_CHECK_HW(hwmgr);
 620
 621         if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
 622                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 623                 return 0;
 624         }
 625
 626         return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
 627 }
 628
 629 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
 630 {
 631         struct pp_hwmgr  *hwmgr;
 632
 633         if (handle == NULL)
 634                 return -EINVAL;
 635
 636         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 637
 638         PP_CHECK_HW(hwmgr);
 639
 640         if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
 641                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 642                 return 0;
 643         }
 644
 645         return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
 646 }
 647
 648 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
 649 {
 650         struct pp_hwmgr  *hwmgr;
 651
 652         if (handle == NULL)
 653                 return -EINVAL;
 654
 655         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 656
 657         PP_CHECK_HW(hwmgr);
 658
 659         if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
 660                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 661                 return 0;
 662         }
 663
 664         return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
 665 }
 666
 667 static int pp_dpm_get_temperature(void *handle)
 668 {
 669         struct pp_hwmgr  *hwmgr;
 670
 671         if (handle == NULL)
 672                 return -EINVAL;
 673
 674         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 675
 676         PP_CHECK_HW(hwmgr);
 677
 678         if (hwmgr->hwmgr_func->get_temperature == NULL) {
 679                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 680                 return 0;
 681         }
 682
 683         return hwmgr->hwmgr_func->get_temperature(hwmgr);
 684 }
 685
 686 static int pp_dpm_get_pp_num_states(void *handle,
 687                 struct pp_states_info *data)
 688 {
 689         struct pp_hwmgr *hwmgr;
 690         int i;
 691
 692         if (!handle)
 693                 return -EINVAL;
 694
 695         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 696
 697         if (hwmgr == NULL || hwmgr->ps == NULL)
 698                 return -EINVAL;
 699
 700         data->nums = hwmgr->num_ps;
 701
 702         for (i = 0; i < hwmgr->num_ps; i++) {
 703                 struct pp_power_state *state = (struct pp_power_state *)
 704                                 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
 705                 switch (state->classification.ui_label) {
 706                 case PP_StateUILabel_Battery:
 707                         data->states[i] = POWER_STATE_TYPE_BATTERY;
 708                         break;
 709                 case PP_StateUILabel_Balanced:
 710                         data->states[i] = POWER_STATE_TYPE_BALANCED;
 711                         break;
 712                 case PP_StateUILabel_Performance:
 713                         data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
 714                         break;
 715                 default:
 716                         if (state->classification.flags & PP_StateClassificationFlag_Boot)
 717                                 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
 718                         else
 719                                 data->states[i] = POWER_STATE_TYPE_DEFAULT;
 720                 }
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int pp_dpm_get_pp_table(void *handle, char **table)
 727 {
 728         struct pp_hwmgr *hwmgr;
 729
 730         if (!handle)
 731                 return -EINVAL;
 732
 733         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 734
 735         PP_CHECK_HW(hwmgr);
 736
 737         if (hwmgr->hwmgr_func->get_pp_table == NULL) {
 738                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 739                 return 0;
 740         }
 741
 742         return hwmgr->hwmgr_func->get_pp_table(hwmgr, table);
 743 }
 744
 745 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
 746 {
 747         struct pp_hwmgr *hwmgr;
 748
 749         if (!handle)
 750                 return -EINVAL;
 751
 752         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 753
 754         PP_CHECK_HW(hwmgr);
 755
 756         if (hwmgr->hwmgr_func->set_pp_table == NULL) {
 757                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 758                 return 0;
 759         }
 760
 761         return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
 762 }
 763
 764 static int pp_dpm_force_clock_level(void *handle,
 765                 enum pp_clock_type type, uint32_t mask)
 766 {
 767         struct pp_hwmgr *hwmgr;
 768
 769         if (!handle)
 770                 return -EINVAL;
 771
 772         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 773
 774         PP_CHECK_HW(hwmgr);
 775
 776         if (hwmgr->hwmgr_func->force_clock_level == NULL) {
 777                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 778                 return 0;
 779         }
 780
 781         return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 782 }
 783
 784 static int pp_dpm_print_clock_levels(void *handle,
 785                 enum pp_clock_type type, char *buf)
 786 {
 787         struct pp_hwmgr *hwmgr;
 788
 789         if (!handle)
 790                 return -EINVAL;
 791
 792         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 793
 794         PP_CHECK_HW(hwmgr);
 795
 796         if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
 797                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 798                 return 0;
 799         }
 800         return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
 801 }
 802
 803 const struct amd_powerplay_funcs pp_dpm_funcs = {
 804         .get_temperature = pp_dpm_get_temperature,
 805         .load_firmware = pp_dpm_load_fw,
 806         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
 807         .force_performance_level = pp_dpm_force_performance_level,
 808         .get_performance_level = pp_dpm_get_performance_level,
 809         .get_current_power_state = pp_dpm_get_current_power_state,
 810         .get_sclk = pp_dpm_get_sclk,
 811         .get_mclk = pp_dpm_get_mclk,
 812         .powergate_vce = pp_dpm_powergate_vce,
 813         .powergate_uvd = pp_dpm_powergate_uvd,
 814         .dispatch_tasks = pp_dpm_dispatch_tasks,
 815         .print_current_performance_level = pp_debugfs_print_current_performance_level,
 816         .set_fan_control_mode = pp_dpm_set_fan_control_mode,
 817         .get_fan_control_mode = pp_dpm_get_fan_control_mode,
 818         .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
 819         .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
 820         .get_pp_num_states = pp_dpm_get_pp_num_states,
 821         .get_pp_table = pp_dpm_get_pp_table,
 822         .set_pp_table = pp_dpm_set_pp_table,
 823         .force_clock_level = pp_dpm_force_clock_level,
 824         .print_clock_levels = pp_dpm_print_clock_levels,
 825 };
 826
 827 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
 828                                 struct amd_powerplay *amd_pp)
 829 {
 830         int ret;
 831         struct pp_instance *handle;
 832
 833         handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
 834         if (handle == NULL)
 835                 return -ENOMEM;
 836
 837         handle->pp_valid = PP_VALID;
 838
 839         ret = smum_init(pp_init, handle);
 840         if (ret)
 841                 goto fail_smum;
 842
 843         ret = hwmgr_init(pp_init, handle);
 844         if (ret)
 845                 goto fail_hwmgr;
 846
 847         ret = eventmgr_init(handle);
 848         if (ret)
 849                 goto fail_eventmgr;
 850
 851         amd_pp->pp_handle = handle;
 852         return 0;
 853
 854 fail_eventmgr:
 855         hwmgr_fini(handle->hwmgr);
 856 fail_hwmgr:
 857         smum_fini(handle->smu_mgr);
 858 fail_smum:
 859         kfree(handle);
 860         return ret;
 861 }
 862
 863 static int amd_pp_instance_fini(void *handle)
 864 {
 865         struct pp_instance *instance = (struct pp_instance *)handle;
 866
 867         if (instance == NULL)
 868                 return -EINVAL;
 869
 870         eventmgr_fini(instance->eventmgr);
 871
 872         hwmgr_fini(instance->hwmgr);
 873
 874         smum_fini(instance->smu_mgr);
 875
 876         kfree(handle);
 877         return 0;
 878 }
 879
 880 int amd_powerplay_init(struct amd_pp_init *pp_init,
 881                        struct amd_powerplay *amd_pp)
 882 {
 883         int ret;
 884
 885         if (pp_init == NULL || amd_pp == NULL)
 886                 return -EINVAL;
 887
 888         ret = amd_pp_instance_init(pp_init, amd_pp);
 889
 890         if (ret)
 891                 return ret;
 892
 893         amd_pp->ip_funcs = &pp_ip_funcs;
 894         amd_pp->pp_funcs = &pp_dpm_funcs;
 895
 896         return 0;
 897 }
 898
 899 int amd_powerplay_fini(void *handle)
 900 {
 901         amd_pp_instance_fini(handle);
 902
 903         return 0;
 904 }
 905
 906 /* export this function to DAL */
 907
 908 int amd_powerplay_display_configuration_change(void *handle,
 909         const struct amd_pp_display_configuration *display_config)
 910 {
 911         struct pp_hwmgr  *hwmgr;
 912
 913         PP_CHECK((struct pp_instance *)handle);
 914
 915         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 916
 917         phm_store_dal_configuration_data(hwmgr, display_config);
 918
 919         return 0;
 920 }
 921
 922 int amd_powerplay_get_display_power_level(void *handle,
 923                 struct amd_pp_simple_clock_info *output)
 924 {
 925         struct pp_hwmgr  *hwmgr;
 926
 927         PP_CHECK((struct pp_instance *)handle);
 928
 929         if (output == NULL)
 930                 return -EINVAL;
 931
 932         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 933
 934         return phm_get_dal_power_level(hwmgr, output);
 935 }
 936
 937 int amd_powerplay_get_current_clocks(void *handle,
 938                 struct amd_pp_clock_info *clocks)
 939 {
 940         struct pp_hwmgr  *hwmgr;
 941         struct amd_pp_simple_clock_info simple_clocks;
 942         struct pp_clock_info hw_clocks;
 943
 944         PP_CHECK((struct pp_instance *)handle);
 945
 946         if (clocks == NULL)
 947                 return -EINVAL;
 948
 949         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 950
 951         phm_get_dal_power_level(hwmgr, &simple_clocks);
 952
 953         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
 954                 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
 955                         PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
 956         } else {
 957                 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
 958                         PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
 959         }
 960
 961         clocks->min_engine_clock = hw_clocks.min_eng_clk;
 962         clocks->max_engine_clock = hw_clocks.max_eng_clk;
 963         clocks->min_memory_clock = hw_clocks.min_mem_clk;
 964         clocks->max_memory_clock = hw_clocks.max_mem_clk;
 965         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
 966         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
 967
 968         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
 969         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
 970
 971         clocks->max_clocks_state = simple_clocks.level;
 972
 973         if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
 974                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
 975                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
 976         }
 977
 978         return 0;
 979
 980 }
 981
 982 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
 983 {
 984         int result = -1;
 985
 986         struct pp_hwmgr *hwmgr;
 987
 988         PP_CHECK((struct pp_instance *)handle);
 989
 990         if (clocks == NULL)
 991                 return -EINVAL;
 992
 993         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 994
 995         result = phm_get_clock_by_type(hwmgr, type, clocks);
 996
 997         return result;
 998 }
 999
1000 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1001                 struct amd_pp_simple_clock_info *clocks)
1002 {
1003         int result = -1;
1004         struct pp_hwmgr  *hwmgr;
1005
1006         PP_CHECK((struct pp_instance *)handle);
1007
1008         if (clocks == NULL)
1009                 return -EINVAL;
1010
1011         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1012
1013         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1014                 result = phm_get_max_high_clocks(hwmgr, clocks);
1015
1016         return result;
1017 }
1018