drivers/gpu/drm/amd/powerplay/amd_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/gfp.h>
  26 #include <linux/slab.h>
  27 #include "amd_shared.h"
  28 #include "amd_powerplay.h"
  29 #include "pp_instance.h"
  30 #include "power_state.h"
  31 #include "eventmanager.h"
  32 #include "pp_debug.h"
  33
  34 #define PP_CHECK(handle)                                                \
  35         do {                                                            \
  36                 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
  37                         return -EINVAL;                                 \
  38         } while (0)
  39
  40 #define PP_CHECK_HW(hwmgr)                                              \
  41         do {                                                            \
  42                 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL)     \
  43                         return -EINVAL;                                 \
  44         } while (0)
  45
  46 static int pp_early_init(void *handle)
  47 {
  48         return 0;
  49 }
  50
  51 static int pp_sw_init(void *handle)
  52 {
  53         struct pp_instance *pp_handle;
  54         struct pp_hwmgr  *hwmgr;
  55         int ret = 0;
  56
  57         if (handle == NULL)
  58                 return -EINVAL;
  59
  60         pp_handle = (struct pp_instance *)handle;
  61         hwmgr = pp_handle->hwmgr;
  62
  63         PP_CHECK_HW(hwmgr);
  64
  65         if (hwmgr->pptable_func == NULL ||
  66             hwmgr->pptable_func->pptable_init == NULL ||
  67             hwmgr->hwmgr_func->backend_init == NULL)
  68                 return -EINVAL;
  69
  70         ret = hwmgr->pptable_func->pptable_init(hwmgr);
  71         if (ret)
  72                 goto err;
  73
  74         ret = hwmgr->hwmgr_func->backend_init(hwmgr);
  75         if (ret)
  76                 goto err1;
  77
  78         pr_info("amdgpu: powerplay initialized\n");
  79
  80         return 0;
  81 err1:
  82         if (hwmgr->pptable_func->pptable_fini)
  83                 hwmgr->pptable_func->pptable_fini(hwmgr);
  84 err:
  85         pr_err("amdgpu: powerplay initialization failed\n");
  86         return ret;
  87 }
  88
  89 static int pp_sw_fini(void *handle)
  90 {
  91         struct pp_instance *pp_handle;
  92         struct pp_hwmgr  *hwmgr;
  93         int ret = 0;
  94
  95         if (handle == NULL)
  96                 return -EINVAL;
  97
  98         pp_handle = (struct pp_instance *)handle;
  99         hwmgr = pp_handle->hwmgr;
 100
 101         PP_CHECK_HW(hwmgr);
 102
 103         if (hwmgr->hwmgr_func->backend_fini != NULL)
 104                 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
 105
 106         if (hwmgr->pptable_func->pptable_fini)
 107                 hwmgr->pptable_func->pptable_fini(hwmgr);
 108
 109         return ret;
 110 }
 111
 112 static int pp_hw_init(void *handle)
 113 {
 114         struct pp_instance *pp_handle;
 115         struct pp_smumgr *smumgr;
 116         struct pp_eventmgr *eventmgr;
 117         int ret = 0;
 118
 119         if (handle == NULL)
 120                 return -EINVAL;
 121
 122         pp_handle = (struct pp_instance *)handle;
 123         smumgr = pp_handle->smu_mgr;
 124
 125         if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
 126                 smumgr->smumgr_funcs->smu_init == NULL ||
 127                 smumgr->smumgr_funcs->start_smu == NULL)
 128                 return -EINVAL;
 129
 130         ret = smumgr->smumgr_funcs->smu_init(smumgr);
 131         if (ret) {
 132                 printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
 133                 return ret;
 134         }
 135
 136         ret = smumgr->smumgr_funcs->start_smu(smumgr);
 137         if (ret) {
 138                 printk(KERN_ERR "[ powerplay ] smc start failed\n");
 139                 smumgr->smumgr_funcs->smu_fini(smumgr);
 140                 return ret;
 141         }
 142
 143         hw_init_power_state_table(pp_handle->hwmgr);
 144         eventmgr = pp_handle->eventmgr;
 145
 146         if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
 147                 return -EINVAL;
 148
 149         ret = eventmgr->pp_eventmgr_init(eventmgr);
 150         return 0;
 151 }
 152
 153 static int pp_hw_fini(void *handle)
 154 {
 155         struct pp_instance *pp_handle;
 156         struct pp_smumgr *smumgr;
 157         struct pp_eventmgr *eventmgr;
 158
 159         if (handle == NULL)
 160                 return -EINVAL;
 161
 162         pp_handle = (struct pp_instance *)handle;
 163         eventmgr = pp_handle->eventmgr;
 164
 165         if (eventmgr != NULL || eventmgr->pp_eventmgr_fini != NULL)
 166                 eventmgr->pp_eventmgr_fini(eventmgr);
 167
 168         smumgr = pp_handle->smu_mgr;
 169
 170         if (smumgr != NULL || smumgr->smumgr_funcs != NULL ||
 171                 smumgr->smumgr_funcs->smu_fini != NULL)
 172                 smumgr->smumgr_funcs->smu_fini(smumgr);
 173
 174         return 0;
 175 }
 176
 177 static bool pp_is_idle(void *handle)
 178 {
 179         return false;
 180 }
 181
 182 static int pp_wait_for_idle(void *handle)
 183 {
 184         return 0;
 185 }
 186
 187 static int pp_sw_reset(void *handle)
 188 {
 189         return 0;
 190 }
 191
 192
 193 static int pp_set_clockgating_state(void *handle,
 194                                     enum amd_clockgating_state state)
 195 {
 196         struct pp_hwmgr  *hwmgr;
 197         uint32_t msg_id, pp_state;
 198
 199         if (handle == NULL)
 200                 return -EINVAL;
 201
 202         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 203
 204         PP_CHECK_HW(hwmgr);
 205
 206         if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
 207                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 208                 return 0;
 209         }
 210
 211         if (state == AMD_CG_STATE_UNGATE)
 212                 pp_state = 0;
 213         else
 214                 pp_state = PP_STATE_CG | PP_STATE_LS;
 215
 216         /* Enable/disable GFX blocks clock gating through SMU */
 217         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 218                         PP_BLOCK_GFX_CG,
 219                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 220                         pp_state);
 221         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 222         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 223                         PP_BLOCK_GFX_3D,
 224                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 225                         pp_state);
 226         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 227         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 228                         PP_BLOCK_GFX_RLC,
 229                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 230                         pp_state);
 231         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 232         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 233                         PP_BLOCK_GFX_CP,
 234                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 235                         pp_state);
 236         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 237         msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
 238                         PP_BLOCK_GFX_MG,
 239                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 240                         pp_state);
 241         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 242
 243         /* Enable/disable System blocks clock gating through SMU */
 244         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 245                         PP_BLOCK_SYS_BIF,
 246                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 247                         pp_state);
 248         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 249         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 250                         PP_BLOCK_SYS_BIF,
 251                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 252                         pp_state);
 253         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 254         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 255                         PP_BLOCK_SYS_MC,
 256                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 257                         pp_state);
 258         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 259         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 260                         PP_BLOCK_SYS_ROM,
 261                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 262                         pp_state);
 263         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 264         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 265                         PP_BLOCK_SYS_DRM,
 266                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 267                         pp_state);
 268         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 269         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 270                         PP_BLOCK_SYS_HDP,
 271                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 272                         pp_state);
 273         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 274         msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
 275                         PP_BLOCK_SYS_SDMA,
 276                         PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
 277                         pp_state);
 278         hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
 279
 280         return 0;
 281 }
 282
 283 static int pp_set_powergating_state(void *handle,
 284                                     enum amd_powergating_state state)
 285 {
 286         struct pp_hwmgr  *hwmgr;
 287
 288         if (handle == NULL)
 289                 return -EINVAL;
 290
 291         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 292
 293         PP_CHECK_HW(hwmgr);
 294
 295         if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
 296                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 297                 return 0;
 298         }
 299
 300         /* Enable/disable GFX per cu powergating through SMU */
 301         return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
 302                         state == AMD_PG_STATE_GATE ? true : false);
 303 }
 304
 305 static int pp_suspend(void *handle)
 306 {
 307         struct pp_instance *pp_handle;
 308         struct pp_eventmgr *eventmgr;
 309         struct pem_event_data event_data = { {0} };
 310
 311         if (handle == NULL)
 312                 return -EINVAL;
 313
 314         pp_handle = (struct pp_instance *)handle;
 315         eventmgr = pp_handle->eventmgr;
 316         pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
 317         return 0;
 318 }
 319
 320 static int pp_resume(void *handle)
 321 {
 322         struct pp_instance *pp_handle;
 323         struct pp_eventmgr *eventmgr;
 324         struct pem_event_data event_data = { {0} };
 325         struct pp_smumgr *smumgr;
 326         int ret;
 327
 328         if (handle == NULL)
 329                 return -EINVAL;
 330
 331         pp_handle = (struct pp_instance *)handle;
 332         smumgr = pp_handle->smu_mgr;
 333
 334         if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
 335                 smumgr->smumgr_funcs->start_smu == NULL)
 336                 return -EINVAL;
 337
 338         ret = smumgr->smumgr_funcs->start_smu(smumgr);
 339         if (ret) {
 340                 printk(KERN_ERR "[ powerplay ] smc start failed\n");
 341                 smumgr->smumgr_funcs->smu_fini(smumgr);
 342                 return ret;
 343         }
 344
 345         eventmgr = pp_handle->eventmgr;
 346         pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
 347
 348         return 0;
 349 }
 350
 351 const struct amd_ip_funcs pp_ip_funcs = {
 352         .name = "powerplay",
 353         .early_init = pp_early_init,
 354         .late_init = NULL,
 355         .sw_init = pp_sw_init,
 356         .sw_fini = pp_sw_fini,
 357         .hw_init = pp_hw_init,
 358         .hw_fini = pp_hw_fini,
 359         .suspend = pp_suspend,
 360         .resume = pp_resume,
 361         .is_idle = pp_is_idle,
 362         .wait_for_idle = pp_wait_for_idle,
 363         .soft_reset = pp_sw_reset,
 364         .set_clockgating_state = pp_set_clockgating_state,
 365         .set_powergating_state = pp_set_powergating_state,
 366 };
 367
 368 static int pp_dpm_load_fw(void *handle)
 369 {
 370         return 0;
 371 }
 372
 373 static int pp_dpm_fw_loading_complete(void *handle)
 374 {
 375         return 0;
 376 }
 377
 378 static int pp_dpm_force_performance_level(void *handle,
 379                                         enum amd_dpm_forced_level level)
 380 {
 381         struct pp_instance *pp_handle;
 382         struct pp_hwmgr  *hwmgr;
 383
 384         if (handle == NULL)
 385                 return -EINVAL;
 386
 387         pp_handle = (struct pp_instance *)handle;
 388
 389         hwmgr = pp_handle->hwmgr;
 390
 391         PP_CHECK_HW(hwmgr);
 392
 393         if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
 394                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 395                 return 0;
 396         }
 397
 398         hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 399
 400         return 0;
 401 }
 402
 403 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
 404                                                                 void *handle)
 405 {
 406         struct pp_hwmgr  *hwmgr;
 407
 408         if (handle == NULL)
 409                 return -EINVAL;
 410
 411         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 412
 413         if (hwmgr == NULL)
 414                 return -EINVAL;
 415
 416         return (((struct pp_instance *)handle)->hwmgr->dpm_level);
 417 }
 418
 419 static int pp_dpm_get_sclk(void *handle, bool low)
 420 {
 421         struct pp_hwmgr  *hwmgr;
 422
 423         if (handle == NULL)
 424                 return -EINVAL;
 425
 426         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 427
 428         PP_CHECK_HW(hwmgr);
 429
 430         if (hwmgr->hwmgr_func->get_sclk == NULL) {
 431                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 432                 return 0;
 433         }
 434
 435         return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
 436 }
 437
 438 static int pp_dpm_get_mclk(void *handle, bool low)
 439 {
 440         struct pp_hwmgr  *hwmgr;
 441
 442         if (handle == NULL)
 443                 return -EINVAL;
 444
 445         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 446
 447         PP_CHECK_HW(hwmgr);
 448
 449         if (hwmgr->hwmgr_func->get_mclk == NULL) {
 450                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 451                 return 0;
 452         }
 453
 454         return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
 455 }
 456
 457 static int pp_dpm_powergate_vce(void *handle, bool gate)
 458 {
 459         struct pp_hwmgr  *hwmgr;
 460
 461         if (handle == NULL)
 462                 return -EINVAL;
 463
 464         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 465
 466         PP_CHECK_HW(hwmgr);
 467
 468         if (hwmgr->hwmgr_func->powergate_vce == NULL) {
 469                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 470                 return 0;
 471         }
 472
 473         return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 474 }
 475
 476 static int pp_dpm_powergate_uvd(void *handle, bool gate)
 477 {
 478         struct pp_hwmgr  *hwmgr;
 479
 480         if (handle == NULL)
 481                 return -EINVAL;
 482
 483         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 484
 485         PP_CHECK_HW(hwmgr);
 486
 487         if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
 488                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 489                 return 0;
 490         }
 491
 492         return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 493 }
 494
 495 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
 496 {
 497         switch (state) {
 498         case POWER_STATE_TYPE_BATTERY:
 499                 return PP_StateUILabel_Battery;
 500         case POWER_STATE_TYPE_BALANCED:
 501                 return PP_StateUILabel_Balanced;
 502         case POWER_STATE_TYPE_PERFORMANCE:
 503                 return PP_StateUILabel_Performance;
 504         default:
 505                 return PP_StateUILabel_None;
 506         }
 507 }
 508
 509 int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
 510 {
 511         int ret = 0;
 512         struct pp_instance *pp_handle;
 513         struct pem_event_data data = { {0} };
 514
 515         pp_handle = (struct pp_instance *)handle;
 516
 517         if (pp_handle == NULL)
 518                 return -EINVAL;
 519
 520         switch (event_id) {
 521         case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
 522                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 523                 break;
 524         case AMD_PP_EVENT_ENABLE_USER_STATE:
 525         {
 526                 enum amd_pm_state_type  ps;
 527
 528                 if (input == NULL)
 529                         return -EINVAL;
 530                 ps = *(unsigned long *)input;
 531
 532                 data.requested_ui_label = power_state_convert(ps);
 533                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 534                 break;
 535         }
 536         case AMD_PP_EVENT_COMPLETE_INIT:
 537                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 538                 break;
 539         case AMD_PP_EVENT_READJUST_POWER_STATE:
 540                 pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;
 541                 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
 542                 break;
 543         default:
 544                 break;
 545         }
 546         return ret;
 547 }
 548
 549 enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
 550 {
 551         struct pp_hwmgr *hwmgr;
 552         struct pp_power_state *state;
 553
 554         if (handle == NULL)
 555                 return -EINVAL;
 556
 557         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 558
 559         if (hwmgr == NULL || hwmgr->current_ps == NULL)
 560                 return -EINVAL;
 561
 562         state = hwmgr->current_ps;
 563
 564         switch (state->classification.ui_label) {
 565         case PP_StateUILabel_Battery:
 566                 return POWER_STATE_TYPE_BATTERY;
 567         case PP_StateUILabel_Balanced:
 568                 return POWER_STATE_TYPE_BALANCED;
 569         case PP_StateUILabel_Performance:
 570                 return POWER_STATE_TYPE_PERFORMANCE;
 571         default:
 572                 if (state->classification.flags & PP_StateClassificationFlag_Boot)
 573                         return  POWER_STATE_TYPE_INTERNAL_BOOT;
 574                 else
 575                         return POWER_STATE_TYPE_DEFAULT;
 576         }
 577 }
 578
 579 static void
 580 pp_debugfs_print_current_performance_level(void *handle,
 581                                                struct seq_file *m)
 582 {
 583         struct pp_hwmgr  *hwmgr;
 584
 585         if (handle == NULL)
 586                 return;
 587
 588         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 589
 590         if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
 591                 return;
 592
 593         if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
 594                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 595                 return;
 596         }
 597
 598         hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
 599 }
 600
 601 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
 602 {
 603         struct pp_hwmgr  *hwmgr;
 604
 605         if (handle == NULL)
 606                 return -EINVAL;
 607
 608         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 609
 610         PP_CHECK_HW(hwmgr);
 611
 612         if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
 613                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 614                 return 0;
 615         }
 616
 617         return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
 618 }
 619
 620 static int pp_dpm_get_fan_control_mode(void *handle)
 621 {
 622         struct pp_hwmgr  *hwmgr;
 623
 624         if (handle == NULL)
 625                 return -EINVAL;
 626
 627         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 628
 629         PP_CHECK_HW(hwmgr);
 630
 631         if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
 632                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 633                 return 0;
 634         }
 635
 636         return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
 637 }
 638
 639 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
 640 {
 641         struct pp_hwmgr  *hwmgr;
 642
 643         if (handle == NULL)
 644                 return -EINVAL;
 645
 646         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 647
 648         PP_CHECK_HW(hwmgr);
 649
 650         if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
 651                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 652                 return 0;
 653         }
 654
 655         return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
 656 }
 657
 658 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
 659 {
 660         struct pp_hwmgr  *hwmgr;
 661
 662         if (handle == NULL)
 663                 return -EINVAL;
 664
 665         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 666
 667         PP_CHECK_HW(hwmgr);
 668
 669         if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
 670                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 671                 return 0;
 672         }
 673
 674         return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
 675 }
 676
 677 static int pp_dpm_get_temperature(void *handle)
 678 {
 679         struct pp_hwmgr  *hwmgr;
 680
 681         if (handle == NULL)
 682                 return -EINVAL;
 683
 684         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 685
 686         PP_CHECK_HW(hwmgr);
 687
 688         if (hwmgr->hwmgr_func->get_temperature == NULL) {
 689                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 690                 return 0;
 691         }
 692
 693         return hwmgr->hwmgr_func->get_temperature(hwmgr);
 694 }
 695
 696 static int pp_dpm_get_pp_num_states(void *handle,
 697                 struct pp_states_info *data)
 698 {
 699         struct pp_hwmgr *hwmgr;
 700         int i;
 701
 702         if (!handle)
 703                 return -EINVAL;
 704
 705         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 706
 707         if (hwmgr == NULL || hwmgr->ps == NULL)
 708                 return -EINVAL;
 709
 710         data->nums = hwmgr->num_ps;
 711
 712         for (i = 0; i < hwmgr->num_ps; i++) {
 713                 struct pp_power_state *state = (struct pp_power_state *)
 714                                 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
 715                 switch (state->classification.ui_label) {
 716                 case PP_StateUILabel_Battery:
 717                         data->states[i] = POWER_STATE_TYPE_BATTERY;
 718                         break;
 719                 case PP_StateUILabel_Balanced:
 720                         data->states[i] = POWER_STATE_TYPE_BALANCED;
 721                         break;
 722                 case PP_StateUILabel_Performance:
 723                         data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
 724                         break;
 725                 default:
 726                         if (state->classification.flags & PP_StateClassificationFlag_Boot)
 727                                 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
 728                         else
 729                                 data->states[i] = POWER_STATE_TYPE_DEFAULT;
 730                 }
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int pp_dpm_get_pp_table(void *handle, char **table)
 737 {
 738         struct pp_hwmgr *hwmgr;
 739
 740         if (!handle)
 741                 return -EINVAL;
 742
 743         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 744
 745         PP_CHECK_HW(hwmgr);
 746
 747         if (!hwmgr->soft_pp_table)
 748                 return -EINVAL;
 749
 750         *table = (char *)hwmgr->soft_pp_table;
 751
 752         return hwmgr->soft_pp_table_size;
 753 }
 754
 755 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
 756 {
 757         struct pp_hwmgr *hwmgr;
 758
 759         if (!handle)
 760                 return -EINVAL;
 761
 762         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 763
 764         PP_CHECK_HW(hwmgr);
 765
 766         if (!hwmgr->hardcode_pp_table) {
 767                 hwmgr->hardcode_pp_table =
 768                                 kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
 769
 770                 if (!hwmgr->hardcode_pp_table)
 771                         return -ENOMEM;
 772
 773                 /* to avoid powerplay crash when hardcode pptable is empty */
 774                 memcpy(hwmgr->hardcode_pp_table, hwmgr->soft_pp_table,
 775                                 hwmgr->soft_pp_table_size);
 776         }
 777
 778         memcpy(hwmgr->hardcode_pp_table, buf, size);
 779
 780         hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
 781
 782         return amd_powerplay_reset(handle);
 783 }
 784
 785 static int pp_dpm_force_clock_level(void *handle,
 786                 enum pp_clock_type type, uint32_t mask)
 787 {
 788         struct pp_hwmgr *hwmgr;
 789
 790         if (!handle)
 791                 return -EINVAL;
 792
 793         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 794
 795         PP_CHECK_HW(hwmgr);
 796
 797         if (hwmgr->hwmgr_func->force_clock_level == NULL) {
 798                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 799                 return 0;
 800         }
 801
 802         return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
 803 }
 804
 805 static int pp_dpm_print_clock_levels(void *handle,
 806                 enum pp_clock_type type, char *buf)
 807 {
 808         struct pp_hwmgr *hwmgr;
 809
 810         if (!handle)
 811                 return -EINVAL;
 812
 813         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 814
 815         PP_CHECK_HW(hwmgr);
 816
 817         if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
 818                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 819                 return 0;
 820         }
 821         return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
 822 }
 823
 824 static int pp_dpm_get_sclk_od(void *handle)
 825 {
 826         struct pp_hwmgr *hwmgr;
 827
 828         if (!handle)
 829                 return -EINVAL;
 830
 831         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 832
 833         PP_CHECK_HW(hwmgr);
 834
 835         if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
 836                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 837                 return 0;
 838         }
 839
 840         return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
 841 }
 842
 843 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
 844 {
 845         struct pp_hwmgr *hwmgr;
 846
 847         if (!handle)
 848                 return -EINVAL;
 849
 850         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 851
 852         PP_CHECK_HW(hwmgr);
 853
 854         if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
 855                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 856                 return 0;
 857         }
 858
 859         return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
 860 }
 861
 862 static int pp_dpm_get_mclk_od(void *handle)
 863 {
 864         struct pp_hwmgr *hwmgr;
 865
 866         if (!handle)
 867                 return -EINVAL;
 868
 869         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 870
 871         PP_CHECK_HW(hwmgr);
 872
 873         if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
 874                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 875                 return 0;
 876         }
 877
 878         return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
 879 }
 880
 881 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
 882 {
 883         struct pp_hwmgr *hwmgr;
 884
 885         if (!handle)
 886                 return -EINVAL;
 887
 888         hwmgr = ((struct pp_instance *)handle)->hwmgr;
 889
 890         PP_CHECK_HW(hwmgr);
 891
 892         if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
 893                 printk(KERN_INFO "%s was not implemented.\n", __func__);
 894                 return 0;
 895         }
 896
 897         return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 898 }
 899
 900 const struct amd_powerplay_funcs pp_dpm_funcs = {
 901         .get_temperature = pp_dpm_get_temperature,
 902         .load_firmware = pp_dpm_load_fw,
 903         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
 904         .force_performance_level = pp_dpm_force_performance_level,
 905         .get_performance_level = pp_dpm_get_performance_level,
 906         .get_current_power_state = pp_dpm_get_current_power_state,
 907         .get_sclk = pp_dpm_get_sclk,
 908         .get_mclk = pp_dpm_get_mclk,
 909         .powergate_vce = pp_dpm_powergate_vce,
 910         .powergate_uvd = pp_dpm_powergate_uvd,
 911         .dispatch_tasks = pp_dpm_dispatch_tasks,
 912         .print_current_performance_level = pp_debugfs_print_current_performance_level,
 913         .set_fan_control_mode = pp_dpm_set_fan_control_mode,
 914         .get_fan_control_mode = pp_dpm_get_fan_control_mode,
 915         .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
 916         .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
 917         .get_pp_num_states = pp_dpm_get_pp_num_states,
 918         .get_pp_table = pp_dpm_get_pp_table,
 919         .set_pp_table = pp_dpm_set_pp_table,
 920         .force_clock_level = pp_dpm_force_clock_level,
 921         .print_clock_levels = pp_dpm_print_clock_levels,
 922         .get_sclk_od = pp_dpm_get_sclk_od,
 923         .set_sclk_od = pp_dpm_set_sclk_od,
 924         .get_mclk_od = pp_dpm_get_mclk_od,
 925         .set_mclk_od = pp_dpm_set_mclk_od,
 926 };
 927
 928 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
 929                                 struct amd_powerplay *amd_pp)
 930 {
 931         int ret;
 932         struct pp_instance *handle;
 933
 934         handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
 935         if (handle == NULL)
 936                 return -ENOMEM;
 937
 938         handle->pp_valid = PP_VALID;
 939
 940         ret = smum_init(pp_init, handle);
 941         if (ret)
 942                 goto fail_smum;
 943
 944         ret = hwmgr_init(pp_init, handle);
 945         if (ret)
 946                 goto fail_hwmgr;
 947
 948         ret = eventmgr_init(handle);
 949         if (ret)
 950                 goto fail_eventmgr;
 951
 952         amd_pp->pp_handle = handle;
 953         return 0;
 954
 955 fail_eventmgr:
 956         hwmgr_fini(handle->hwmgr);
 957 fail_hwmgr:
 958         smum_fini(handle->smu_mgr);
 959 fail_smum:
 960         kfree(handle);
 961         return ret;
 962 }
 963
 964 static int amd_pp_instance_fini(void *handle)
 965 {
 966         struct pp_instance *instance = (struct pp_instance *)handle;
 967
 968         if (instance == NULL)
 969                 return -EINVAL;
 970
 971         eventmgr_fini(instance->eventmgr);
 972
 973         hwmgr_fini(instance->hwmgr);
 974
 975         smum_fini(instance->smu_mgr);
 976
 977         kfree(handle);
 978         return 0;
 979 }
 980
 981 int amd_powerplay_init(struct amd_pp_init *pp_init,
 982                        struct amd_powerplay *amd_pp)
 983 {
 984         int ret;
 985
 986         if (pp_init == NULL || amd_pp == NULL)
 987                 return -EINVAL;
 988
 989         ret = amd_pp_instance_init(pp_init, amd_pp);
 990
 991         if (ret)
 992                 return ret;
 993
 994         amd_pp->ip_funcs = &pp_ip_funcs;
 995         amd_pp->pp_funcs = &pp_dpm_funcs;
 996
 997         return 0;
 998 }
 999
1000 int amd_powerplay_fini(void *handle)
1001 {
1002         amd_pp_instance_fini(handle);
1003
1004         return 0;
1005 }
1006
1007 int amd_powerplay_reset(void *handle)
1008 {
1009         struct pp_instance *instance = (struct pp_instance *)handle;
1010         struct pp_eventmgr *eventmgr;
1011         struct pem_event_data event_data = { {0} };
1012         int ret;
1013
1014         if (instance == NULL)
1015                 return -EINVAL;
1016
1017         eventmgr = instance->eventmgr;
1018         if (!eventmgr || !eventmgr->pp_eventmgr_fini)
1019                 return -EINVAL;
1020
1021         eventmgr->pp_eventmgr_fini(eventmgr);
1022
1023         ret = pp_sw_fini(handle);
1024         if (ret)
1025                 return ret;
1026
1027         kfree(instance->hwmgr->ps);
1028
1029         ret = pp_sw_init(handle);
1030         if (ret)
1031                 return ret;
1032
1033         hw_init_power_state_table(instance->hwmgr);
1034
1035         if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
1036                 return -EINVAL;
1037
1038         ret = eventmgr->pp_eventmgr_init(eventmgr);
1039         if (ret)
1040                 return ret;
1041
1042         return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
1043 }
1044
1045 /* export this function to DAL */
1046
1047 int amd_powerplay_display_configuration_change(void *handle,
1048         const struct amd_pp_display_configuration *display_config)
1049 {
1050         struct pp_hwmgr  *hwmgr;
1051
1052         PP_CHECK((struct pp_instance *)handle);
1053
1054         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1055
1056         phm_store_dal_configuration_data(hwmgr, display_config);
1057
1058         return 0;
1059 }
1060
1061 int amd_powerplay_get_display_power_level(void *handle,
1062                 struct amd_pp_simple_clock_info *output)
1063 {
1064         struct pp_hwmgr  *hwmgr;
1065
1066         PP_CHECK((struct pp_instance *)handle);
1067
1068         if (output == NULL)
1069                 return -EINVAL;
1070
1071         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1072
1073         return phm_get_dal_power_level(hwmgr, output);
1074 }
1075
1076 int amd_powerplay_get_current_clocks(void *handle,
1077                 struct amd_pp_clock_info *clocks)
1078 {
1079         struct pp_hwmgr  *hwmgr;
1080         struct amd_pp_simple_clock_info simple_clocks;
1081         struct pp_clock_info hw_clocks;
1082
1083         PP_CHECK((struct pp_instance *)handle);
1084
1085         if (clocks == NULL)
1086                 return -EINVAL;
1087
1088         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1089
1090         phm_get_dal_power_level(hwmgr, &simple_clocks);
1091
1092         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
1093                 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
1094                         PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
1095         } else {
1096                 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
1097                         PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
1098         }
1099
1100         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1101         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1102         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1103         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1104         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1105         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1106
1107         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1108         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1109
1110         clocks->max_clocks_state = simple_clocks.level;
1111
1112         if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1113                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1114                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1115         }
1116
1117         return 0;
1118
1119 }
1120
1121 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1122 {
1123         int result = -1;
1124
1125         struct pp_hwmgr *hwmgr;
1126
1127         PP_CHECK((struct pp_instance *)handle);
1128
1129         if (clocks == NULL)
1130                 return -EINVAL;
1131
1132         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1133
1134         result = phm_get_clock_by_type(hwmgr, type, clocks);
1135
1136         return result;
1137 }
1138
1139 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1140                 struct amd_pp_simple_clock_info *clocks)
1141 {
1142         int result = -1;
1143         struct pp_hwmgr  *hwmgr;
1144
1145         PP_CHECK((struct pp_instance *)handle);
1146
1147         if (clocks == NULL)
1148                 return -EINVAL;
1149
1150         hwmgr = ((struct pp_instance *)handle)->hwmgr;
1151
1152         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1153                 result = phm_get_max_high_clocks(hwmgr, clocks);
1154
1155         return result;
1156 }
1157