drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include "linux/delay.h"
  27
  28 #include "hwmgr.h"
  29 #include "fiji_smumgr.h"
  30 #include "atombios.h"
  31 #include "hardwaremanager.h"
  32 #include "ppatomctrl.h"
  33 #include "atombios.h"
  34 #include "cgs_common.h"
  35 #include "fiji_dyn_defaults.h"
  36 #include "fiji_powertune.h"
  37 #include "smu73.h"
  38 #include "smu/smu_7_1_3_d.h"
  39 #include "smu/smu_7_1_3_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44 #include "dce/dce_10_0_d.h"
  45 #include "dce/dce_10_0_sh_mask.h"
  46 #include "pppcielanes.h"
  47 #include "fiji_hwmgr.h"
  48 #include "tonga_processpptables.h"
  49 #include "tonga_pptable.h"
  50 #include "pp_debug.h"
  51 #include "pp_acpi.h"
  52 #include "amd_pcie_helpers.h"
  53 #include "cgs_linux.h"
  54 #include "ppinterrupt.h"
  55
  56 #include "fiji_clockpowergating.h"
  57 #include "fiji_thermal.h"
  58
  59 #define VOLTAGE_SCALE   4
  60 #define SMC_RAM_END             0x40000
  61 #define VDDC_VDDCI_DELTA        300
  62
  63 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  64 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  65 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  66
  67 #define MC_CG_ARB_FREQ_F0           0x0a /* boot-up default */
  68 #define MC_CG_ARB_FREQ_F1           0x0b
  69 #define MC_CG_ARB_FREQ_F2           0x0c
  70 #define MC_CG_ARB_FREQ_F3           0x0d
  71
  72 /* From smc_reg.h */
  73 #define SMC_CG_IND_START            0xc0030000
  74 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND */
  75
  76 #define VOLTAGE_SCALE               4
  77 #define VOLTAGE_VID_OFFSET_SCALE1   625
  78 #define VOLTAGE_VID_OFFSET_SCALE2   100
  79
  80 #define VDDC_VDDCI_DELTA            300
  81
  82 #define ixSWRST_COMMAND_1           0x1400103
  83 #define MC_SEQ_CNTL__CAC_EN_MASK    0x40000000
  84
  85 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
  86 enum DPM_EVENT_SRC {
  87     DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
  88     DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
  89     DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
  90     DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
  91     DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
  92 };
  93
  94
  95 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
  96  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
  97  */
  98 static const uint16_t fiji_clock_stretcher_lookup_table[2][4] =
  99 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 100
 101 /* [FF, SS] type, [] 4 voltage ranges, and
 102  * [Floor Freq, Boundary Freq, VID min , VID max]
 103  */
 104 static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
 105 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 106   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 107
 108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
 109  * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
 110  */
 111 static const uint8_t fiji_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 static const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
 115
 116 struct fiji_power_state *cast_phw_fiji_power_state(
 117                                   struct pp_hw_power_state *hw_ps)
 118 {
 119         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 120                                 "Invalid Powerstate Type!",
 121                                  return NULL;);
 122
 123         return (struct fiji_power_state *)hw_ps;
 124 }
 125
 126 const struct fiji_power_state *cast_const_phw_fiji_power_state(
 127                                  const struct pp_hw_power_state *hw_ps)
 128 {
 129         PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
 130                                 "Invalid Powerstate Type!",
 131                                  return NULL;);
 132
 133         return (const struct fiji_power_state *)hw_ps;
 134 }
 135
 136 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
 137 {
 138         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 139                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 140                         ? true : false;
 141 }
 142
 143 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 144 {
 145         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 146         struct fiji_ulv_parm *ulv = &data->ulv;
 147
 148         ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
 149         data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
 150         data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
 151         data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
 152         data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
 153         data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
 154         data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
 155         data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
 156         data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
 157
 158         data->static_screen_threshold_unit =
 159                         PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
 160         data->static_screen_threshold =
 161                         PPFIJI_STATICSCREENTHRESHOLD_DFLT;
 162
 163         /* Unset ABM cap as it moved to DAL.
 164          * Add PHM_PlatformCaps_NonABMSupportInPPLib
 165          * for re-direct ABM related request to DAL
 166          */
 167         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 168                         PHM_PlatformCaps_ABM);
 169         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 170                         PHM_PlatformCaps_NonABMSupportInPPLib);
 171
 172         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 173                         PHM_PlatformCaps_DynamicACTiming);
 174
 175         fiji_initialize_power_tune_defaults(hwmgr);
 176
 177         data->mclk_stutter_mode_threshold = 60000;
 178         data->pcie_gen_performance.max = PP_PCIEGen1;
 179         data->pcie_gen_performance.min = PP_PCIEGen3;
 180         data->pcie_gen_power_saving.max = PP_PCIEGen1;
 181         data->pcie_gen_power_saving.min = PP_PCIEGen3;
 182         data->pcie_lane_performance.max = 0;
 183         data->pcie_lane_performance.min = 16;
 184         data->pcie_lane_power_saving.max = 0;
 185         data->pcie_lane_power_saving.min = 16;
 186
 187         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 188                         PHM_PlatformCaps_DynamicUVDState);
 189 }
 190
 191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 192         phm_ppt_v1_voltage_lookup_table *lookup_table,
 193         uint16_t virtual_voltage_id, int32_t *sclk)
 194 {
 195         uint8_t entryId;
 196         uint8_t voltageId;
 197         struct phm_ppt_v1_information *table_info =
 198                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 199
 200         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
 201
 202         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 203         for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
 204                 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
 205                 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
 206                         break;
 207         }
 208
 209         PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
 210                         "Can't find requested voltage id in vdd_dep_on_sclk table!",
 211                         return -EINVAL;
 212                         );
 213
 214         *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
 215
 216         return 0;
 217 }
 218
 219 /**
 220 * Get Leakage VDDC based on leakage ID.
 221 *
 222 * @param    hwmgr  the address of the powerplay hardware manager.
 223 * @return   always 0
 224 */
 225 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
 226 {
 227         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 228         uint16_t    vv_id;
 229         uint16_t    vddc = 0;
 230         uint16_t    evv_default = 1150;
 231         uint16_t    i, j;
 232         uint32_t  sclk = 0;
 233         struct phm_ppt_v1_information *table_info =
 234                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 235         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 236                         table_info->vdd_dep_on_sclk;
 237         int result;
 238
 239         for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
 240                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 241                 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
 242                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
 243                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 244                                         PHM_PlatformCaps_ClockStretcher)) {
 245                                 for (j = 1; j < sclk_table->count; j++) {
 246                                         if (sclk_table->entries[j].clk == sclk &&
 247                                                         sclk_table->entries[j].cks_enable == 0) {
 248                                                 sclk += 5000;
 249                                                 break;
 250                                         }
 251                                 }
 252                         }
 253
 254                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 255                                         PHM_PlatformCaps_EnableDriverEVV))
 256                                 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
 257                                                 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
 258                         else
 259                                 result = -EINVAL;
 260
 261                         if (result)
 262                                 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
 263                                                 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
 264
 265                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 266                         PP_ASSERT_WITH_CODE((vddc < 2000),
 267                                         "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
 268
 269                         if (result)
 270                                 /* 1.15V is the default safe value for Fiji */
 271                                 vddc = evv_default;
 272
 273                         /* the voltage should not be zero nor equal to leakage ID */
 274                         if (vddc != 0 && vddc != vv_id) {
 275                                 data->vddc_leakage.actual_voltage
 276                                 [data->vddc_leakage.count] = vddc;
 277                                 data->vddc_leakage.leakage_id
 278                                 [data->vddc_leakage.count] = vv_id;
 279                                 data->vddc_leakage.count++;
 280                         }
 281                 }
 282         }
 283         return 0;
 284 }
 285
 286 /**
 287  * Change virtual leakage voltage to actual value.
 288  *
 289  * @param     hwmgr  the address of the powerplay hardware manager.
 290  * @param     pointer to changing voltage
 291  * @param     pointer to leakage table
 292  */
 293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
 294                 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
 295 {
 296         uint32_t index;
 297
 298         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
 299         for (index = 0; index < leakage_table->count; index++) {
 300                 /* if this voltage matches a leakage voltage ID */
 301                 /* patch with actual leakage voltage */
 302                 if (leakage_table->leakage_id[index] == *voltage) {
 303                         *voltage = leakage_table->actual_voltage[index];
 304                         break;
 305                 }
 306         }
 307
 308         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
 309                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
 310 }
 311
 312 /**
 313 * Patch voltage lookup table by EVV leakages.
 314 *
 315 * @param     hwmgr  the address of the powerplay hardware manager.
 316 * @param     pointer to voltage lookup table
 317 * @param     pointer to leakage table
 318 * @return     always 0
 319 */
 320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
 321                 phm_ppt_v1_voltage_lookup_table *lookup_table,
 322                 struct fiji_leakage_voltage *leakage_table)
 323 {
 324         uint32_t i;
 325
 326         for (i = 0; i < lookup_table->count; i++)
 327                 fiji_patch_with_vdd_leakage(hwmgr,
 328                                 &lookup_table->entries[i].us_vdd, leakage_table);
 329
 330         return 0;
 331 }
 332
 333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
 334                 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
 335                 uint16_t *vddc)
 336 {
 337         struct phm_ppt_v1_information *table_info =
 338                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 339         fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
 340         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
 341                         table_info->max_clock_voltage_on_dc.vddc;
 342         return 0;
 343 }
 344
 345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
 346                 struct pp_hwmgr *hwmgr)
 347 {
 348         uint8_t entryId;
 349         uint8_t voltageId;
 350         struct phm_ppt_v1_information *table_info =
 351                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 352
 353         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 354                         table_info->vdd_dep_on_sclk;
 355         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
 356                         table_info->vdd_dep_on_mclk;
 357         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
 358                         table_info->mm_dep_table;
 359
 360         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
 361                 voltageId = sclk_table->entries[entryId].vddInd;
 362                 sclk_table->entries[entryId].vddc =
 363                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 364         }
 365
 366         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
 367                 voltageId = mclk_table->entries[entryId].vddInd;
 368                 mclk_table->entries[entryId].vddc =
 369                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 370         }
 371
 372         for (entryId = 0; entryId < mm_table->count; ++entryId) {
 373                 voltageId = mm_table->entries[entryId].vddcInd;
 374                 mm_table->entries[entryId].vddc =
 375                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
 376         }
 377
 378         return 0;
 379
 380 }
 381
 382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
 383 {
 384         /* Need to determine if we need calculated voltage. */
 385         return 0;
 386 }
 387
 388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
 389 {
 390         /* Need to determine if we need calculated voltage from mm table. */
 391         return 0;
 392 }
 393
 394 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
 395                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
 396 {
 397         uint32_t table_size, i, j;
 398         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
 399         table_size = lookup_table->count;
 400
 401         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
 402                 "Lookup table is empty", return -EINVAL);
 403
 404         /* Sorting voltages */
 405         for (i = 0; i < table_size - 1; i++) {
 406                 for (j = i + 1; j > 0; j--) {
 407                         if (lookup_table->entries[j].us_vdd <
 408                                         lookup_table->entries[j - 1].us_vdd) {
 409                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
 410                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
 411                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
 412                         }
 413                 }
 414         }
 415
 416         return 0;
 417 }
 418
 419 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 420 {
 421         int result = 0;
 422         int tmp_result;
 423         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 424         struct phm_ppt_v1_information *table_info =
 425                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 426
 427         tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
 428                         table_info->vddc_lookup_table, &(data->vddc_leakage));
 429         if (tmp_result)
 430                 result = tmp_result;
 431
 432         tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
 433                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
 434         if (tmp_result)
 435                 result = tmp_result;
 436
 437         tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
 438         if (tmp_result)
 439                 result = tmp_result;
 440
 441         tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
 442         if (tmp_result)
 443                 result = tmp_result;
 444
 445         tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
 446         if (tmp_result)
 447                 result = tmp_result;
 448
 449         tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
 450         if(tmp_result)
 451                 result = tmp_result;
 452
 453         return result;
 454 }
 455
 456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 457 {
 458         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 459         struct phm_ppt_v1_information *table_info =
 460                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 461
 462         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
 463                         table_info->vdd_dep_on_sclk;
 464         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
 465                         table_info->vdd_dep_on_mclk;
 466
 467         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
 468                 "VDD dependency on SCLK table is missing.       \
 469                 This table is mandatory", return -EINVAL);
 470         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
 471                 "VDD dependency on SCLK table has to have is missing.   \
 472                 This table is mandatory", return -EINVAL);
 473
 474         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
 475                 "VDD dependency on MCLK table is missing.       \
 476                 This table is mandatory", return -EINVAL);
 477         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
 478                 "VDD dependency on MCLK table has to have is missing.    \
 479                 This table is mandatory", return -EINVAL);
 480
 481         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
 482         data->max_vddc_in_pptable =     (uint16_t)allowed_sclk_vdd_table->
 483                         entries[allowed_sclk_vdd_table->count - 1].vddc;
 484
 485         table_info->max_clock_voltage_on_ac.sclk =
 486                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 487         table_info->max_clock_voltage_on_ac.mclk =
 488                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
 489         table_info->max_clock_voltage_on_ac.vddc =
 490                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 491         table_info->max_clock_voltage_on_ac.vddci =
 492                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 493
 494         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
 495                 table_info->max_clock_voltage_on_ac.sclk;
 496         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
 497                 table_info->max_clock_voltage_on_ac.mclk;
 498         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
 499                 table_info->max_clock_voltage_on_ac.vddc;
 500         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
 501                 table_info->max_clock_voltage_on_ac.vddci;
 502
 503         return 0;
 504 }
 505
 506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 507 {
 508         uint32_t speedCntl = 0;
 509
 510         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 511         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 512                         ixPCIE_LC_SPEED_CNTL);
 513         return((uint16_t)PHM_GET_FIELD(speedCntl,
 514                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 515 }
 516
 517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 518 {
 519         uint32_t link_width;
 520
 521         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 522         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 523                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 524
 525         PP_ASSERT_WITH_CODE((7 >= link_width),
 526                         "Invalid PCIe lane width!", return 0);
 527
 528         return decode_pcie_lane_width(link_width);
 529 }
 530
 531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
 532 *
 533 * @param hwmgr Pointer to the hardware manager.
 534 * @param pPowerState The address of the PowerState instance being created.
 535 *
 536 */
 537 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
 538                 struct pp_hw_power_state *hw_ps)
 539 {
 540         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 541         struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
 542         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
 543         uint16_t size;
 544         uint8_t frev, crev;
 545         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 546
 547         /* First retrieve the Boot clocks and VDDC from the firmware info table.
 548          * We assume here that fw_info is unchanged if this call fails.
 549          */
 550         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
 551                         hwmgr->device, index,
 552                         &size, &frev, &crev);
 553         if (!fw_info)
 554                 /* During a test, there is no firmware info table. */
 555                 return 0;
 556
 557         /* Patch the state. */
 558         data->vbios_boot_state.sclk_bootup_value =
 559                         le32_to_cpu(fw_info->ulDefaultEngineClock);
 560         data->vbios_boot_state.mclk_bootup_value =
 561                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
 562         data->vbios_boot_state.mvdd_bootup_value =
 563                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
 564         data->vbios_boot_state.vddc_bootup_value =
 565                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
 566         data->vbios_boot_state.vddci_bootup_value =
 567                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
 568         data->vbios_boot_state.pcie_gen_bootup_value =
 569                         fiji_get_current_pcie_speed(hwmgr);
 570         data->vbios_boot_state.pcie_lane_bootup_value =
 571                         (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
 572
 573         /* set boot power state */
 574         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
 575         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
 576         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
 577         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
 578
 579         return 0;
 580 }
 581
 582 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 583 {
 584         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 585         uint32_t i;
 586         struct phm_ppt_v1_information *table_info =
 587                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 588         bool stay_in_boot;
 589         int result;
 590
 591         data->dll_default_on = false;
 592         data->sram_end = SMC_RAM_END;
 593
 594         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
 595                 data->activity_target[i] = FIJI_AT_DFLT;
 596
 597         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
 598
 599         data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
 600         data->mclk_dpm0_activity_target = 0xa;
 601
 602         data->sclk_dpm_key_disabled = 0;
 603         data->mclk_dpm_key_disabled = 0;
 604         data->pcie_dpm_key_disabled = 0;
 605
 606         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 607                         PHM_PlatformCaps_UnTabledHardwareInterface);
 608         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 609                         PHM_PlatformCaps_TablelessHardwareInterface);
 610
 611         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 612                         PHM_PlatformCaps_SclkDeepSleep);
 613
 614         data->gpio_debug = 0;
 615
 616         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 617                         PHM_PlatformCaps_DynamicPatchPowerState);
 618
 619         /* need to set voltage control types before EVV patching */
 620         data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
 621         data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
 622         data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
 623
 624         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 625                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
 626                 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 627
 628         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 629                         PHM_PlatformCaps_EnableMVDDControl))
 630                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 631                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
 632                         data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 633
 634         if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
 635                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 636                         PHM_PlatformCaps_EnableMVDDControl);
 637
 638         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 639                         PHM_PlatformCaps_ControlVDDCI)) {
 640                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 641                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
 642                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
 643                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
 644                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
 645                         data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
 646         }
 647
 648         if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
 649                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 650                                 PHM_PlatformCaps_ControlVDDCI);
 651
 652         if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
 653                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 654                                 PHM_PlatformCaps_ClockStretcher);
 655
 656         fiji_init_dpm_defaults(hwmgr);
 657
 658         /* Get leakage voltage based on leakage ID. */
 659         fiji_get_evv_voltages(hwmgr);
 660
 661         /* Patch our voltage dependency table with actual leakage voltage
 662          * We need to perform leakage translation before it's used by other functions
 663          */
 664         fiji_complete_dependency_tables(hwmgr);
 665
 666         /* Parse pptable data read from VBIOS */
 667         fiji_set_private_data_based_on_pptable(hwmgr);
 668
 669         /* ULV Support */
 670         data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
 671
 672         /* Initalize Dynamic State Adjustment Rule Settings */
 673         result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
 674
 675         if (!result) {
 676                 data->uvd_enabled = false;
 677                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 678                                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
 679                 data->vddc_phase_shed_control = false;
 680         }
 681
 682         stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 683                         PHM_PlatformCaps_StayInBootState);
 684
 685         if (0 == result) {
 686                 struct cgs_system_info sys_info = {0};
 687
 688                 data->is_tlu_enabled = 0;
 689                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 690                                 FIJI_MAX_HARDWARE_POWERLEVELS;
 691                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 692                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
 693
 694                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 695                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
 696
 697                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
 698                                 hwmgr->thermal_controller.
 699                                 advanceFanControlParameters.ucFanControlMode) {
 700                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
 701                                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
 702                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
 703                                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
 704                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
 705                                         table_info->cac_dtp_table->usOperatingTempMinLimit;
 706                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
 707                                         table_info->cac_dtp_table->usOperatingTempMaxLimit;
 708                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
 709                                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
 710                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
 711                                         table_info->cac_dtp_table->usOperatingTempStep;
 712                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
 713                                         table_info->cac_dtp_table->usTargetOperatingTemp;
 714
 715                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 716                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
 717                 }
 718
 719                 sys_info.size = sizeof(struct cgs_system_info);
 720                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
 721                 result = cgs_query_system_info(hwmgr->device, &sys_info);
 722                 if (result)
 723                         data->pcie_gen_cap = 0x30007;
 724                 else
 725                         data->pcie_gen_cap = (uint32_t)sys_info.value;
 726                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 727                         data->pcie_spc_cap = 20;
 728                 sys_info.size = sizeof(struct cgs_system_info);
 729                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
 730                 result = cgs_query_system_info(hwmgr->device, &sys_info);
 731                 if (result)
 732                         data->pcie_lane_cap = 0x2f0000;
 733                 else
 734                         data->pcie_lane_cap = (uint32_t)sys_info.value;
 735         } else {
 736                 /* Ignore return value in here, we are cleaning up a mess. */
 737                 tonga_hwmgr_backend_fini(hwmgr);
 738         }
 739
 740         return 0;
 741 }
 742
 743 /**
 744  * Read clock related registers.
 745  *
 746  * @param    hwmgr  the address of the powerplay hardware manager.
 747  * @return   always 0
 748  */
 749 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
 750 {
 751         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 752
 753         data->clock_registers.vCG_SPLL_FUNC_CNTL =
 754                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 755                                 ixCG_SPLL_FUNC_CNTL);
 756         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
 757                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 758                                 ixCG_SPLL_FUNC_CNTL_2);
 759         data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
 760                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 761                                 ixCG_SPLL_FUNC_CNTL_3);
 762         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
 763                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 764                                 ixCG_SPLL_FUNC_CNTL_4);
 765         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
 766                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 767                                 ixCG_SPLL_SPREAD_SPECTRUM);
 768         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 769                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 770                                 ixCG_SPLL_SPREAD_SPECTRUM_2);
 771
 772         return 0;
 773 }
 774
 775 /**
 776  * Find out if memory is GDDR5.
 777  *
 778  * @param    hwmgr  the address of the powerplay hardware manager.
 779  * @return   always 0
 780  */
 781 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
 782 {
 783         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 784         uint32_t temp;
 785
 786         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 787
 788         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 789                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 790                          MC_SEQ_MISC0_GDDR5_SHIFT));
 791
 792         return 0;
 793 }
 794
 795 /**
 796  * Enables Dynamic Power Management by SMC
 797  *
 798  * @param    hwmgr  the address of the powerplay hardware manager.
 799  * @return   always 0
 800  */
 801 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 802 {
 803         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 804                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * Initialize PowerGating States for different engines
 811  *
 812  * @param    hwmgr  the address of the powerplay hardware manager.
 813  * @return   always 0
 814  */
 815 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
 816 {
 817         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 818
 819         data->uvd_power_gated = false;
 820         data->vce_power_gated = false;
 821         data->samu_power_gated = false;
 822         data->acp_power_gated = false;
 823         data->pg_acp_init = true;
 824
 825         return 0;
 826 }
 827
 828 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 829 {
 830         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 831         data->low_sclk_interrupt_threshold = 0;
 832
 833         return 0;
 834 }
 835
 836 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
 837 {
 838         int tmp_result, result = 0;
 839
 840         tmp_result = fiji_read_clock_registers(hwmgr);
 841         PP_ASSERT_WITH_CODE((0 == tmp_result),
 842                         "Failed to read clock registers!", result = tmp_result);
 843
 844         tmp_result = fiji_get_memory_type(hwmgr);
 845         PP_ASSERT_WITH_CODE((0 == tmp_result),
 846                         "Failed to get memory type!", result = tmp_result);
 847
 848         tmp_result = fiji_enable_acpi_power_management(hwmgr);
 849         PP_ASSERT_WITH_CODE((0 == tmp_result),
 850                         "Failed to enable ACPI power management!", result = tmp_result);
 851
 852         tmp_result = fiji_init_power_gate_state(hwmgr);
 853         PP_ASSERT_WITH_CODE((0 == tmp_result),
 854                         "Failed to init power gate state!", result = tmp_result);
 855
 856         tmp_result = tonga_get_mc_microcode_version(hwmgr);
 857         PP_ASSERT_WITH_CODE((0 == tmp_result),
 858                         "Failed to get MC microcode version!", result = tmp_result);
 859
 860         tmp_result = fiji_init_sclk_threshold(hwmgr);
 861         PP_ASSERT_WITH_CODE((0 == tmp_result),
 862                         "Failed to init sclk threshold!", result = tmp_result);
 863
 864         return result;
 865 }
 866
 867 /**
 868 * Checks if we want to support voltage control
 869 *
 870 * @param    hwmgr  the address of the powerplay hardware manager.
 871 */
 872 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
 873 {
 874         const struct fiji_hwmgr *data =
 875                         (const struct fiji_hwmgr *)(hwmgr->backend);
 876
 877         return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
 878 }
 879
 880 /**
 881 * Enable voltage control
 882 *
 883 * @param    hwmgr  the address of the powerplay hardware manager.
 884 * @return   always 0
 885 */
 886 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
 887 {
 888         /* enable voltage control */
 889         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 890                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 891
 892         return 0;
 893 }
 894
 895 /**
 896 * Remove repeated voltage values and create table with unique values.
 897 *
 898 * @param    hwmgr  the address of the powerplay hardware manager.
 899 * @param    vol_table  the pointer to changing voltage table
 900 * @return    0 in success
 901 */
 902
 903 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
 904                 struct pp_atomctrl_voltage_table *vol_table)
 905 {
 906         uint32_t i, j;
 907         uint16_t vvalue;
 908         bool found = false;
 909         struct pp_atomctrl_voltage_table *table;
 910
 911         PP_ASSERT_WITH_CODE((NULL != vol_table),
 912                         "Voltage Table empty.", return -EINVAL);
 913         table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
 914                         GFP_KERNEL);
 915
 916         if (NULL == table)
 917                 return -ENOMEM;
 918
 919         table->mask_low = vol_table->mask_low;
 920         table->phase_delay = vol_table->phase_delay;
 921
 922         for (i = 0; i < vol_table->count; i++) {
 923                 vvalue = vol_table->entries[i].value;
 924                 found = false;
 925
 926                 for (j = 0; j < table->count; j++) {
 927                         if (vvalue == table->entries[j].value) {
 928                                 found = true;
 929                                 break;
 930                         }
 931                 }
 932
 933                 if (!found) {
 934                         table->entries[table->count].value = vvalue;
 935                         table->entries[table->count].smio_low =
 936                                         vol_table->entries[i].smio_low;
 937                         table->count++;
 938                 }
 939         }
 940
 941         memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
 942         kfree(table);
 943
 944         return 0;
 945 }
 946
 947 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
 948                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 949 {
 950         uint32_t i;
 951         int result;
 952         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 953         struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
 954
 955         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 956                         "Voltage Dependency Table empty.", return -EINVAL);
 957
 958         vol_table->mask_low = 0;
 959         vol_table->phase_delay = 0;
 960         vol_table->count = dep_table->count;
 961
 962         for (i = 0; i < dep_table->count; i++) {
 963                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
 964                 vol_table->entries[i].smio_low = 0;
 965         }
 966
 967         result = fiji_trim_voltage_table(hwmgr, vol_table);
 968         PP_ASSERT_WITH_CODE((0 == result),
 969                         "Failed to trim MVDD table.", return result);
 970
 971         return 0;
 972 }
 973
 974 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
 975                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 976 {
 977         uint32_t i;
 978         int result;
 979         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 980         struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
 981
 982         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 983                         "Voltage Dependency Table empty.", return -EINVAL);
 984
 985         vol_table->mask_low = 0;
 986         vol_table->phase_delay = 0;
 987         vol_table->count = dep_table->count;
 988
 989         for (i = 0; i < dep_table->count; i++) {
 990                 vol_table->entries[i].value = dep_table->entries[i].vddci;
 991                 vol_table->entries[i].smio_low = 0;
 992         }
 993
 994         result = fiji_trim_voltage_table(hwmgr, vol_table);
 995         PP_ASSERT_WITH_CODE((0 == result),
 996                         "Failed to trim VDDCI table.", return result);
 997
 998         return 0;
 999 }
1000
1001 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1002                 phm_ppt_v1_voltage_lookup_table *lookup_table)
1003 {
1004         int i = 0;
1005         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1006         struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
1007
1008         PP_ASSERT_WITH_CODE((0 != lookup_table->count),
1009                         "Voltage Lookup Table empty.", return -EINVAL);
1010
1011         vol_table->mask_low = 0;
1012         vol_table->phase_delay = 0;
1013
1014         vol_table->count = lookup_table->count;
1015
1016         for (i = 0; i < vol_table->count; i++) {
1017                 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
1018                 vol_table->entries[i].smio_low = 0;
1019         }
1020
1021         return 0;
1022 }
1023
1024 /* ---- Voltage Tables ----
1025  * If the voltage table would be bigger than
1026  * what will fit into the state table on
1027  * the SMC keep only the higher entries.
1028  */
1029 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
1030                 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
1031 {
1032         unsigned int i, diff;
1033
1034         if (vol_table->count <= max_vol_steps)
1035                 return;
1036
1037         diff = vol_table->count - max_vol_steps;
1038
1039         for (i = 0; i < max_vol_steps; i++)
1040                 vol_table->entries[i] = vol_table->entries[i + diff];
1041
1042         vol_table->count = max_vol_steps;
1043
1044         return;
1045 }
1046
1047 /**
1048 * Create Voltage Tables.
1049 *
1050 * @param    hwmgr  the address of the powerplay hardware manager.
1051 * @return   always 0
1052 */
1053 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1054 {
1055         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1056         struct phm_ppt_v1_information *table_info =
1057                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1058         int result;
1059
1060         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1061                 result = atomctrl_get_voltage_table_v3(hwmgr,
1062                                 VOLTAGE_TYPE_MVDDC,     VOLTAGE_OBJ_GPIO_LUT,
1063                                 &(data->mvdd_voltage_table));
1064                 PP_ASSERT_WITH_CODE((0 == result),
1065                                 "Failed to retrieve MVDD table.",
1066                                 return result);
1067         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1068                 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1069                                 table_info->vdd_dep_on_mclk);
1070                 PP_ASSERT_WITH_CODE((0 == result),
1071                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1072                                 return result;);
1073         }
1074
1075         if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1076                 result = atomctrl_get_voltage_table_v3(hwmgr,
1077                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1078                                 &(data->vddci_voltage_table));
1079                 PP_ASSERT_WITH_CODE((0 == result),
1080                                 "Failed to retrieve VDDCI table.",
1081                                 return result);
1082         } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1083                 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1084                                 table_info->vdd_dep_on_mclk);
1085                 PP_ASSERT_WITH_CODE((0 == result),
1086                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1087                                 return result);
1088         }
1089
1090         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1091                 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1092                                 table_info->vddc_lookup_table);
1093                 PP_ASSERT_WITH_CODE((0 == result),
1094                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
1095                                 return result);
1096         }
1097
1098         PP_ASSERT_WITH_CODE(
1099                         (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1100                         "Too many voltage values for VDDC. Trimming to fit state table.",
1101                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1102                                         SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1103
1104         PP_ASSERT_WITH_CODE(
1105                         (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1106                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1107                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1108                                         SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1109
1110         PP_ASSERT_WITH_CODE(
1111                         (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1112                         "Too many voltage values for MVDD. Trimming to fit state table.",
1113                         fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1114                                         SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1115
1116         return 0;
1117 }
1118
1119 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1120 {
1121         /* Program additional LP registers
1122          * that are no longer programmed by VBIOS
1123          */
1124         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1125                         cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1126         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1127                         cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1128         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1129                         cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1130         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1131                         cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1132         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1133                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1134         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1135                         cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1136         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1137                         cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1138
1139         return 0;
1140 }
1141
1142 /**
1143 * Programs static screed detection parameters
1144 *
1145 * @param    hwmgr  the address of the powerplay hardware manager.
1146 * @return   always 0
1147 */
1148 static int fiji_program_static_screen_threshold_parameters(
1149                 struct pp_hwmgr *hwmgr)
1150 {
1151         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1152
1153         /* Set static screen threshold unit */
1154         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1155                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1156                         data->static_screen_threshold_unit);
1157         /* Set static screen threshold */
1158         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1159                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1160                         data->static_screen_threshold);
1161
1162         return 0;
1163 }
1164
1165 /**
1166 * Setup display gap for glitch free memory clock switching.
1167 *
1168 * @param    hwmgr  the address of the powerplay hardware manager.
1169 * @return   always  0
1170 */
1171 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1172 {
1173         uint32_t displayGap =
1174                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1175                                         ixCG_DISPLAY_GAP_CNTL);
1176
1177         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1178                         DISP_GAP, DISPLAY_GAP_IGNORE);
1179
1180         displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1181                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1182
1183         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1184                         ixCG_DISPLAY_GAP_CNTL, displayGap);
1185
1186         return 0;
1187 }
1188
1189 /**
1190 * Programs activity state transition voting clients
1191 *
1192 * @param    hwmgr  the address of the powerplay hardware manager.
1193 * @return   always  0
1194 */
1195 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1196 {
1197         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1198
1199         /* Clear reset for voting clients before enabling DPM */
1200         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1201                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1202         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1203                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1204
1205         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1206                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1207         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1208                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1209         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1210                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1211         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1212                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1213         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1214                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1215         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1216                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1217         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1218                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1219         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1220                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1221
1222         return 0;
1223 }
1224
1225 /**
1226 * Get the location of various tables inside the FW image.
1227 *
1228 * @param    hwmgr  the address of the powerplay hardware manager.
1229 * @return   always  0
1230 */
1231 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1232 {
1233         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1234         struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1235         uint32_t tmp;
1236         int result;
1237         bool error = false;
1238
1239         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1240                         SMU7_FIRMWARE_HEADER_LOCATION +
1241                         offsetof(SMU73_Firmware_Header, DpmTable),
1242                         &tmp, data->sram_end);
1243
1244         if (0 == result)
1245                 data->dpm_table_start = tmp;
1246
1247         error |= (0 != result);
1248
1249         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1250                         SMU7_FIRMWARE_HEADER_LOCATION +
1251                         offsetof(SMU73_Firmware_Header, SoftRegisters),
1252                         &tmp, data->sram_end);
1253
1254         if (!result) {
1255                 data->soft_regs_start = tmp;
1256                 smu_data->soft_regs_start = tmp;
1257         }
1258
1259         error |= (0 != result);
1260
1261         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1262                         SMU7_FIRMWARE_HEADER_LOCATION +
1263                         offsetof(SMU73_Firmware_Header, mcRegisterTable),
1264                         &tmp, data->sram_end);
1265
1266         if (!result)
1267                 data->mc_reg_table_start = tmp;
1268
1269         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1270                         SMU7_FIRMWARE_HEADER_LOCATION +
1271                         offsetof(SMU73_Firmware_Header, FanTable),
1272                         &tmp, data->sram_end);
1273
1274         if (!result)
1275                 data->fan_table_start = tmp;
1276
1277         error |= (0 != result);
1278
1279         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1280                         SMU7_FIRMWARE_HEADER_LOCATION +
1281                         offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1282                         &tmp, data->sram_end);
1283
1284         if (!result)
1285                 data->arb_table_start = tmp;
1286
1287         error |= (0 != result);
1288
1289         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1290                         SMU7_FIRMWARE_HEADER_LOCATION +
1291                         offsetof(SMU73_Firmware_Header, Version),
1292                         &tmp, data->sram_end);
1293
1294         if (!result)
1295                 hwmgr->microcode_version_info.SMC = tmp;
1296
1297         error |= (0 != result);
1298
1299         return error ? -1 : 0;
1300 }
1301
1302 /* Copy one arb setting to another and then switch the active set.
1303  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1304  */
1305 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1306                 uint32_t arb_src, uint32_t arb_dest)
1307 {
1308         uint32_t mc_arb_dram_timing;
1309         uint32_t mc_arb_dram_timing2;
1310         uint32_t burst_time;
1311         uint32_t mc_cg_config;
1312
1313         switch (arb_src) {
1314         case MC_CG_ARB_FREQ_F0:
1315                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1316                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1317                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1318                 break;
1319         case MC_CG_ARB_FREQ_F1:
1320                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1321                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1322                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1323                 break;
1324         default:
1325                 return -EINVAL;
1326         }
1327
1328         switch (arb_dest) {
1329         case MC_CG_ARB_FREQ_F0:
1330                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1331                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1332                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1333                 break;
1334         case MC_CG_ARB_FREQ_F1:
1335                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1336                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1337                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1338                 break;
1339         default:
1340                 return -EINVAL;
1341         }
1342
1343         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1344         mc_cg_config |= 0x0000000F;
1345         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1346         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1347
1348         return 0;
1349 }
1350
1351 /**
1352 * Initial switch from ARB F0->F1
1353 *
1354 * @param    hwmgr  the address of the powerplay hardware manager.
1355 * @return   always 0
1356 * This function is to be called from the SetPowerState table.
1357 */
1358 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1359 {
1360         return fiji_copy_and_switch_arb_sets(hwmgr,
1361                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1362 }
1363
1364 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1365                 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1366 {
1367         int i;
1368         PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1369                         "Fatal error, can not set up single DPM table entries "
1370                         "to exceed max number!",);
1371
1372         dpm_table->count = count;
1373         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1374                 dpm_table->dpm_levels[i].enabled = false;
1375
1376         return 0;
1377 }
1378
1379 static void fiji_setup_pcie_table_entry(
1380         struct fiji_single_dpm_table *dpm_table,
1381         uint32_t index, uint32_t pcie_gen,
1382         uint32_t pcie_lanes)
1383 {
1384         dpm_table->dpm_levels[index].value = pcie_gen;
1385         dpm_table->dpm_levels[index].param1 = pcie_lanes;
1386         dpm_table->dpm_levels[index].enabled = 1;
1387 }
1388
1389 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1390 {
1391         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1392         struct phm_ppt_v1_information *table_info =
1393                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1394         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1395         uint32_t i, max_entry;
1396
1397         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1398                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
1399                         return -EINVAL);
1400
1401         if (data->use_pcie_performance_levels &&
1402                         !data->use_pcie_power_saving_levels) {
1403                 data->pcie_gen_power_saving = data->pcie_gen_performance;
1404                 data->pcie_lane_power_saving = data->pcie_lane_performance;
1405         } else if (!data->use_pcie_performance_levels &&
1406                         data->use_pcie_power_saving_levels) {
1407                 data->pcie_gen_performance = data->pcie_gen_power_saving;
1408                 data->pcie_lane_performance = data->pcie_lane_power_saving;
1409         }
1410
1411         fiji_reset_single_dpm_table(hwmgr,
1412                         &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1413
1414         if (pcie_table != NULL) {
1415                 /* max_entry is used to make sure we reserve one PCIE level
1416                  * for boot level (fix for A+A PSPP issue).
1417                  * If PCIE table from PPTable have ULV entry + 8 entries,
1418                  * then ignore the last entry.*/
1419                 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1420                                 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1421                 for (i = 1; i < max_entry; i++) {
1422                         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1423                                         get_pcie_gen_support(data->pcie_gen_cap,
1424                                                         pcie_table->entries[i].gen_speed),
1425                                         get_pcie_lane_support(data->pcie_lane_cap,
1426                                                         pcie_table->entries[i].lane_width));
1427                 }
1428                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1429         } else {
1430                 /* Hardcode Pcie Table */
1431                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1432                                 get_pcie_gen_support(data->pcie_gen_cap,
1433                                                 PP_Min_PCIEGen),
1434                                 get_pcie_lane_support(data->pcie_lane_cap,
1435                                                 PP_Max_PCIELane));
1436                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1437                                 get_pcie_gen_support(data->pcie_gen_cap,
1438                                                 PP_Min_PCIEGen),
1439                                 get_pcie_lane_support(data->pcie_lane_cap,
1440                                                 PP_Max_PCIELane));
1441                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1442                                 get_pcie_gen_support(data->pcie_gen_cap,
1443                                                 PP_Max_PCIEGen),
1444                                 get_pcie_lane_support(data->pcie_lane_cap,
1445                                                 PP_Max_PCIELane));
1446                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1447                                 get_pcie_gen_support(data->pcie_gen_cap,
1448                                                 PP_Max_PCIEGen),
1449                                 get_pcie_lane_support(data->pcie_lane_cap,
1450                                                 PP_Max_PCIELane));
1451                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1452                                 get_pcie_gen_support(data->pcie_gen_cap,
1453                                                 PP_Max_PCIEGen),
1454                                 get_pcie_lane_support(data->pcie_lane_cap,
1455                                                 PP_Max_PCIELane));
1456                 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1457                                 get_pcie_gen_support(data->pcie_gen_cap,
1458                                                 PP_Max_PCIEGen),
1459                                 get_pcie_lane_support(data->pcie_lane_cap,
1460                                                 PP_Max_PCIELane));
1461
1462                 data->dpm_table.pcie_speed_table.count = 6;
1463         }
1464         /* Populate last level for boot PCIE level, but do not increment count. */
1465         fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1466                         data->dpm_table.pcie_speed_table.count,
1467                         get_pcie_gen_support(data->pcie_gen_cap,
1468                                         PP_Min_PCIEGen),
1469                         get_pcie_lane_support(data->pcie_lane_cap,
1470                                         PP_Max_PCIELane));
1471
1472         return 0;
1473 }
1474
1475 /*
1476  * This function is to initalize all DPM state tables
1477  * for SMU7 based on the dependency table.
1478  * Dynamic state patching function will then trim these
1479  * state tables to the allowed range based
1480  * on the power policy or external client requests,
1481  * such as UVD request, etc.
1482  */
1483 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1484 {
1485         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1486         struct phm_ppt_v1_information *table_info =
1487                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1488         uint32_t i;
1489
1490         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1491                         table_info->vdd_dep_on_sclk;
1492         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1493                         table_info->vdd_dep_on_mclk;
1494
1495         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1496                         "SCLK dependency table is missing. This table is mandatory",
1497                         return -EINVAL);
1498         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1499                         "SCLK dependency table has to have is missing. "
1500                         "This table is mandatory",
1501                         return -EINVAL);
1502
1503         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1504                         "MCLK dependency table is missing. This table is mandatory",
1505                         return -EINVAL);
1506         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1507                         "MCLK dependency table has to have is missing. "
1508                         "This table is mandatory",
1509                         return -EINVAL);
1510
1511         /* clear the state table to reset everything to default */
1512         fiji_reset_single_dpm_table(hwmgr,
1513                         &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1514         fiji_reset_single_dpm_table(hwmgr,
1515                         &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1516
1517         /* Initialize Sclk DPM table based on allow Sclk values */
1518         data->dpm_table.sclk_table.count = 0;
1519         for (i = 0; i < dep_sclk_table->count; i++) {
1520                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1521                                 [data->dpm_table.sclk_table.count - 1].value !=
1522                                                 dep_sclk_table->entries[i].clk) {
1523                         data->dpm_table.sclk_table.dpm_levels
1524                         [data->dpm_table.sclk_table.count].value =
1525                                         dep_sclk_table->entries[i].clk;
1526                         data->dpm_table.sclk_table.dpm_levels
1527                         [data->dpm_table.sclk_table.count].enabled =
1528                                         (i == 0) ? true : false;
1529                         data->dpm_table.sclk_table.count++;
1530                 }
1531         }
1532
1533         /* Initialize Mclk DPM table based on allow Mclk values */
1534         data->dpm_table.mclk_table.count = 0;
1535         for (i=0; i<dep_mclk_table->count; i++) {
1536                 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1537                                 [data->dpm_table.mclk_table.count - 1].value !=
1538                                                 dep_mclk_table->entries[i].clk) {
1539                         data->dpm_table.mclk_table.dpm_levels
1540                         [data->dpm_table.mclk_table.count].value =
1541                                         dep_mclk_table->entries[i].clk;
1542                         data->dpm_table.mclk_table.dpm_levels
1543                         [data->dpm_table.mclk_table.count].enabled =
1544                                         (i == 0) ? true : false;
1545                         data->dpm_table.mclk_table.count++;
1546                 }
1547         }
1548
1549         /* setup PCIE gen speed levels */
1550         fiji_setup_default_pcie_table(hwmgr);
1551
1552         /* save a copy of the default DPM table */
1553         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1554                         sizeof(struct fiji_dpm_table));
1555
1556         return 0;
1557 }
1558
1559 /**
1560  * @brief PhwFiji_GetVoltageOrder
1561  *  Returns index of requested voltage record in lookup(table)
1562  * @param lookup_table - lookup list to search in
1563  * @param voltage - voltage to look for
1564  * @return 0 on success
1565  */
1566 uint8_t fiji_get_voltage_index(
1567                 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1568 {
1569         uint8_t count = (uint8_t) (lookup_table->count);
1570         uint8_t i;
1571
1572         PP_ASSERT_WITH_CODE((NULL != lookup_table),
1573                         "Lookup Table empty.", return 0);
1574         PP_ASSERT_WITH_CODE((0 != count),
1575                         "Lookup Table empty.", return 0);
1576
1577         for (i = 0; i < lookup_table->count; i++) {
1578                 /* find first voltage equal or bigger than requested */
1579                 if (lookup_table->entries[i].us_vdd >= voltage)
1580                         return i;
1581         }
1582         /* voltage is bigger than max voltage in the table */
1583         return i - 1;
1584 }
1585
1586 /**
1587 * Preparation of vddc and vddgfx CAC tables for SMC.
1588 *
1589 * @param    hwmgr  the address of the hardware manager
1590 * @param    table  the SMC DPM table structure to be populated
1591 * @return   always 0
1592 */
1593 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1594                 struct SMU73_Discrete_DpmTable *table)
1595 {
1596         uint32_t count;
1597         uint8_t index;
1598         int result = 0;
1599         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1600         struct phm_ppt_v1_information *table_info =
1601                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1602         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1603                         table_info->vddc_lookup_table;
1604         /* tables is already swapped, so in order to use the value from it,
1605          * we need to swap it back.
1606          * We are populating vddc CAC data to BapmVddc table
1607          * in split and merged mode
1608          */
1609         for( count = 0; count<lookup_table->count; count++) {
1610                 index = fiji_get_voltage_index(lookup_table,
1611                                 data->vddc_voltage_table.entries[count].value);
1612                 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1613                                 (lookup_table->entries[index].us_cac_low *
1614                                                 VOLTAGE_SCALE)) / 25);
1615                 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1616                                 (lookup_table->entries[index].us_cac_high *
1617                                                 VOLTAGE_SCALE)) / 25);
1618         }
1619
1620         return result;
1621 }
1622
1623 /**
1624 * Preparation of voltage tables for SMC.
1625 *
1626 * @param    hwmgr   the address of the hardware manager
1627 * @param    table   the SMC DPM table structure to be populated
1628 * @return   always  0
1629 */
1630
1631 int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1632                 struct SMU73_Discrete_DpmTable *table)
1633 {
1634         int result;
1635
1636         result = fiji_populate_cac_table(hwmgr, table);
1637         PP_ASSERT_WITH_CODE(0 == result,
1638                         "can not populate CAC voltage tables to SMC",
1639                         return -EINVAL);
1640
1641         return 0;
1642 }
1643
1644 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1645                 struct SMU73_Discrete_Ulv *state)
1646 {
1647         int result = 0;
1648         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1649         struct phm_ppt_v1_information *table_info =
1650                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1651
1652         state->CcPwrDynRm = 0;
1653         state->CcPwrDynRm1 = 0;
1654
1655         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1656         state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1657                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1658
1659         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1660
1661         if (!result) {
1662                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1663                 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1664                 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1665         }
1666         return result;
1667 }
1668
1669 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1670                 struct SMU73_Discrete_DpmTable *table)
1671 {
1672         return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1673 }
1674
1675 static int32_t fiji_get_dpm_level_enable_mask_value(
1676                 struct fiji_single_dpm_table* dpm_table)
1677 {
1678         int32_t i;
1679         int32_t mask = 0;
1680
1681         for (i = dpm_table->count; i > 0; i--) {
1682                 mask = mask << 1;
1683                 if (dpm_table->dpm_levels[i - 1].enabled)
1684                         mask |= 0x1;
1685                 else
1686                         mask &= 0xFFFFFFFE;
1687         }
1688         return mask;
1689 }
1690
1691 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1692                 struct SMU73_Discrete_DpmTable *table)
1693 {
1694         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1695         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1696         int i;
1697
1698         /* Index (dpm_table->pcie_speed_table.count)
1699          * is reserved for PCIE boot level. */
1700         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1701                 table->LinkLevel[i].PcieGenSpeed  =
1702                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1703                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1704                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1705                 table->LinkLevel[i].EnabledForActivity = 1;
1706                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1707                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1708                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1709         }
1710
1711         data->smc_state_table.LinkLevelCount =
1712                         (uint8_t)dpm_table->pcie_speed_table.count;
1713         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1714                         fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1715
1716         return 0;
1717 }
1718
1719 /**
1720 * Calculates the SCLK dividers using the provided engine clock
1721 *
1722 * @param    hwmgr  the address of the hardware manager
1723 * @param    clock  the engine clock to use to populate the structure
1724 * @param    sclk   the SMC SCLK structure to be populated
1725 */
1726 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1727                 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1728 {
1729         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1730         struct pp_atomctrl_clock_dividers_vi dividers;
1731         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1732         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1733         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1734         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1735         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1736         uint32_t ref_clock;
1737         uint32_t ref_divider;
1738         uint32_t fbdiv;
1739         int result;
1740
1741         /* get the engine clock dividers for this clock value */
1742         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
1743
1744         PP_ASSERT_WITH_CODE(result == 0,
1745                         "Error retrieving Engine Clock dividers from VBIOS.",
1746                         return result);
1747
1748         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1749         ref_clock = atomctrl_get_reference_clock(hwmgr);
1750         ref_divider = 1 + dividers.uc_pll_ref_div;
1751
1752         /* low 14 bits is fraction and high 12 bits is divider */
1753         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1754
1755         /* SPLL_FUNC_CNTL setup */
1756         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1757                         SPLL_REF_DIV, dividers.uc_pll_ref_div);
1758         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1759                         SPLL_PDIV_A,  dividers.uc_pll_post_div);
1760
1761         /* SPLL_FUNC_CNTL_3 setup*/
1762         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1763                         SPLL_FB_DIV, fbdiv);
1764
1765         /* set to use fractional accumulation*/
1766         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1767                         SPLL_DITHEN, 1);
1768
1769         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1770                                 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1771                 struct pp_atomctrl_internal_ss_info ssInfo;
1772
1773                 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1774                 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1775                                 vco_freq, &ssInfo)) {
1776                         /*
1777                          * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1778                          * ss_info.speed_spectrum_rate -- in unit of khz
1779                          *
1780                          * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1781                          */
1782                         uint32_t clk_s = ref_clock * 5 /
1783                                         (ref_divider * ssInfo.speed_spectrum_rate);
1784                         /* clkv = 2 * D * fbdiv / NS */
1785                         uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1786                                         fbdiv / (clk_s * 10000);
1787
1788                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1789                                         CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1790                         cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1791                                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1792                         cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1793                                         CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1794                 }
1795         }
1796
1797         sclk->SclkFrequency        = clock;
1798         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
1799         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
1800         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
1801         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
1802         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
1803
1804         return 0;
1805 }
1806
1807 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1808 {
1809         uint32_t  i;
1810         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1811         struct pp_atomctrl_voltage_table *vddci_table =
1812                         &(data->vddci_voltage_table);
1813
1814         for (i = 0; i < vddci_table->count; i++) {
1815                 if (vddci_table->entries[i].value >= vddci)
1816                         return vddci_table->entries[i].value;
1817         }
1818
1819         PP_ASSERT_WITH_CODE(false,
1820                         "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1821                         return vddci_table->entries[i].value);
1822 }
1823
1824 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1825                 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1826                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1827 {
1828         uint32_t i;
1829         uint16_t vddci;
1830         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1831
1832         *voltage = *mvdd = 0;
1833
1834         /* clock - voltage dependency table is empty table */
1835         if (dep_table->count == 0)
1836                 return -EINVAL;
1837
1838         for (i = 0; i < dep_table->count; i++) {
1839                 /* find first sclk bigger than request */
1840                 if (dep_table->entries[i].clk >= clock) {
1841                         *voltage |= (dep_table->entries[i].vddc *
1842                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1843                         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1844                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1845                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1846                         else if (dep_table->entries[i].vddci)
1847                                 *voltage |= (dep_table->entries[i].vddci *
1848                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1849                         else {
1850                                 vddci = fiji_find_closest_vddci(hwmgr,
1851                                                 (dep_table->entries[i].vddc -
1852                                                                 (uint16_t)data->vddc_vddci_delta));
1853                                 *voltage |= (vddci * VOLTAGE_SCALE) <<  VDDCI_SHIFT;
1854                         }
1855
1856                         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1857                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1858                                         VOLTAGE_SCALE;
1859                         else if (dep_table->entries[i].mvdd)
1860                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1861                                         VOLTAGE_SCALE;
1862
1863                         *voltage |= 1 << PHASES_SHIFT;
1864                         return 0;
1865                 }
1866         }
1867
1868         /* sclk is bigger than max sclk in the dependence table */
1869         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1870
1871         if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1872                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1873                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1874         else if (dep_table->entries[i-1].vddci) {
1875                 vddci = fiji_find_closest_vddci(hwmgr,
1876                                 (dep_table->entries[i].vddc -
1877                                                 (uint16_t)data->vddc_vddci_delta));
1878                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1879         }
1880
1881         if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1882                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1883         else if (dep_table->entries[i].mvdd)
1884                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1885
1886         return 0;
1887 }
1888
1889 static uint8_t fiji_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
1890                                                 uint32_t clock, uint32_t clock_insr)
1891 {
1892         uint8_t i;
1893         uint32_t temp;
1894         uint32_t min = clock_insr > 2500 ? clock_insr : 2500;
1895
1896         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
1897         for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1898                 temp = clock / (1UL << i);
1899
1900                 if (temp >= min || i == 0)
1901                         break;
1902         }
1903         return i;
1904 }
1905 /**
1906 * Populates single SMC SCLK structure using the provided engine clock
1907 *
1908 * @param    hwmgr      the address of the hardware manager
1909 * @param    clock the engine clock to use to populate the structure
1910 * @param    sclk        the SMC SCLK structure to be populated
1911 */
1912
1913 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1914                 uint32_t clock, uint16_t sclk_al_threshold,
1915                 struct SMU73_Discrete_GraphicsLevel *level)
1916 {
1917         int result;
1918         /* PP_Clocks minClocks; */
1919         uint32_t threshold, mvdd;
1920         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1921         struct phm_ppt_v1_information *table_info =
1922                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1923
1924         result = fiji_calculate_sclk_params(hwmgr, clock, level);
1925
1926         /* populate graphics levels */
1927         result = fiji_get_dependency_volt_by_clk(hwmgr,
1928                         table_info->vdd_dep_on_sclk, clock,
1929                         &level->MinVoltage, &mvdd);
1930         PP_ASSERT_WITH_CODE((0 == result),
1931                         "can not find VDDC voltage value for "
1932                         "VDDC engine clock dependency table",
1933                         return result);
1934
1935         level->SclkFrequency = clock;
1936         level->ActivityLevel = sclk_al_threshold;
1937         level->CcPwrDynRm = 0;
1938         level->CcPwrDynRm1 = 0;
1939         level->EnabledForActivity = 0;
1940         level->EnabledForThrottle = 1;
1941         level->UpHyst = 10;
1942         level->DownHyst = 0;
1943         level->VoltageDownHyst = 0;
1944         level->PowerThrottle = 0;
1945
1946         threshold = clock * data->fast_watermark_threshold / 100;
1947
1948
1949         data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
1950
1951         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1952                 level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(hwmgr, clock,
1953                                                                 hwmgr->display_config.min_core_set_clock_in_sr);
1954
1955
1956         /* Default to slow, highest DPM level will be
1957          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1958          */
1959         level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1960
1961         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1962         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1963         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1964         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1965         CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1966         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1967         CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1968         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1969         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1970
1971         return 0;
1972 }
1973 /**
1974 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1975 *
1976 * @param    hwmgr      the address of the hardware manager
1977 */
1978 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1979 {
1980         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1981         struct fiji_dpm_table *dpm_table = &data->dpm_table;
1982         struct phm_ppt_v1_information *table_info =
1983                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1984         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1985         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1986         int result = 0;
1987         uint32_t array = data->dpm_table_start +
1988                         offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1989         uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1990                         SMU73_MAX_LEVELS_GRAPHICS;
1991         struct SMU73_Discrete_GraphicsLevel *levels =
1992                         data->smc_state_table.GraphicsLevel;
1993         uint32_t i, max_entry;
1994         uint8_t hightest_pcie_level_enabled = 0,
1995                         lowest_pcie_level_enabled = 0,
1996                         mid_pcie_level_enabled = 0,
1997                         count = 0;
1998
1999         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2000                 result = fiji_populate_single_graphic_level(hwmgr,
2001                                 dpm_table->sclk_table.dpm_levels[i].value,
2002                                 (uint16_t)data->activity_target[i],
2003                                 &levels[i]);
2004                 if (result)
2005                         return result;
2006
2007                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2008                 if (i > 1)
2009                         levels[i].DeepSleepDivId = 0;
2010         }
2011
2012         /* Only enable level 0 for now.*/
2013         levels[0].EnabledForActivity = 1;
2014
2015         /* set highest level watermark to high */
2016         levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
2017                         PPSMC_DISPLAY_WATERMARK_HIGH;
2018
2019         data->smc_state_table.GraphicsDpmLevelCount =
2020                         (uint8_t)dpm_table->sclk_table.count;
2021         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2022                         fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2023
2024         if (pcie_table != NULL) {
2025                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
2026                                 "There must be 1 or more PCIE levels defined in PPTable.",
2027                                 return -EINVAL);
2028                 max_entry = pcie_entry_cnt - 1;
2029                 for (i = 0; i < dpm_table->sclk_table.count; i++)
2030                         levels[i].pcieDpmLevel =
2031                                         (uint8_t) ((i < max_entry)? i : max_entry);
2032         } else {
2033                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2034                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2035                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
2036                         hightest_pcie_level_enabled++;
2037
2038                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2039                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2040                                                 (1 << lowest_pcie_level_enabled)) == 0 ))
2041                         lowest_pcie_level_enabled++;
2042
2043                 while ((count < hightest_pcie_level_enabled) &&
2044                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2045                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
2046                         count++;
2047
2048                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
2049                                 hightest_pcie_level_enabled?
2050                                                 (lowest_pcie_level_enabled + 1 + count) :
2051                                                 hightest_pcie_level_enabled;
2052
2053                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2054                 for(i = 2; i < dpm_table->sclk_table.count; i++)
2055                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2056
2057                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2058                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2059
2060                 /* set pcieDpmLevel to mid_pcie_level_enabled */
2061                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2062         }
2063         /* level count will send to smc once at init smc table and never change */
2064         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2065                         (uint32_t)array_size, data->sram_end);
2066
2067         return result;
2068 }
2069
2070 /**
2071  * MCLK Frequency Ratio
2072  * SEQ_CG_RESP  Bit[31:24] - 0x0
2073  * Bit[27:24] \96 DDR3 Frequency ratio
2074  * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
2075  * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
2076  * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
2077  * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
2078  * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
2079  * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
2080  * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
2081  * 400 < 0x7 <= 450MHz,       800 < 0xF
2082  */
2083 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2084 {
2085         if (mem_clock <= 10000) return 0x0;
2086         if (mem_clock <= 15000) return 0x1;
2087         if (mem_clock <= 20000) return 0x2;
2088         if (mem_clock <= 25000) return 0x3;
2089         if (mem_clock <= 30000) return 0x4;
2090         if (mem_clock <= 35000) return 0x5;
2091         if (mem_clock <= 40000) return 0x6;
2092         if (mem_clock <= 45000) return 0x7;
2093         if (mem_clock <= 50000) return 0x8;
2094         if (mem_clock <= 55000) return 0x9;
2095         if (mem_clock <= 60000) return 0xa;
2096         if (mem_clock <= 65000) return 0xb;
2097         if (mem_clock <= 70000) return 0xc;
2098         if (mem_clock <= 75000) return 0xd;
2099         if (mem_clock <= 80000) return 0xe;
2100         /* mem_clock > 800MHz */
2101         return 0xf;
2102 }
2103
2104 /**
2105 * Populates the SMC MCLK structure using the provided memory clock
2106 *
2107 * @param    hwmgr   the address of the hardware manager
2108 * @param    clock   the memory clock to use to populate the structure
2109 * @param    sclk    the SMC SCLK structure to be populated
2110 */
2111 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2112     uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2113 {
2114         struct pp_atomctrl_memory_clock_param mem_param;
2115         int result;
2116
2117         result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2118         PP_ASSERT_WITH_CODE((0 == result),
2119                         "Failed to get Memory PLL Dividers.",);
2120
2121         /* Save the result data to outpupt memory level structure */
2122         mclk->MclkFrequency   = clock;
2123         mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
2124         mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
2125
2126         return result;
2127 }
2128
2129 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2130                 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2131 {
2132         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2133         struct phm_ppt_v1_information *table_info =
2134                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2135         int result = 0;
2136
2137         if (table_info->vdd_dep_on_mclk) {
2138                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2139                                 table_info->vdd_dep_on_mclk, clock,
2140                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
2141                 PP_ASSERT_WITH_CODE((0 == result),
2142                                 "can not find MinVddc voltage value from memory "
2143                                 "VDDC voltage dependency table", return result);
2144         }
2145
2146         mem_level->EnabledForThrottle = 1;
2147         mem_level->EnabledForActivity = 0;
2148         mem_level->UpHyst = 0;
2149         mem_level->DownHyst = 100;
2150         mem_level->VoltageDownHyst = 0;
2151         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2152         mem_level->StutterEnable = false;
2153
2154         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2155
2156         /* enable stutter mode if all the follow condition applied
2157          * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2158          * &(data->DisplayTiming.numExistingDisplays));
2159          */
2160         data->display_timing.num_existing_displays = 1;
2161
2162         if ((data->mclk_stutter_mode_threshold) &&
2163                 (clock <= data->mclk_stutter_mode_threshold) &&
2164                 (!data->is_uvd_enabled) &&
2165                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2166                                 STUTTER_ENABLE) & 0x1))
2167                 mem_level->StutterEnable = true;
2168
2169         result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2170         if (!result) {
2171                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2172                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2173                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2174                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2175         }
2176         return result;
2177 }
2178
2179 /**
2180 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2181 *
2182 * @param    hwmgr      the address of the hardware manager
2183 */
2184 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2185 {
2186         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2187         struct fiji_dpm_table *dpm_table = &data->dpm_table;
2188         int result;
2189         /* populate MCLK dpm table to SMU7 */
2190         uint32_t array = data->dpm_table_start +
2191                         offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2192         uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2193                         SMU73_MAX_LEVELS_MEMORY;
2194         struct SMU73_Discrete_MemoryLevel *levels =
2195                         data->smc_state_table.MemoryLevel;
2196         uint32_t i;
2197
2198         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2199                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2200                                 "can not populate memory level as memory clock is zero",
2201                                 return -EINVAL);
2202                 result = fiji_populate_single_memory_level(hwmgr,
2203                                 dpm_table->mclk_table.dpm_levels[i].value,
2204                                 &levels[i]);
2205                 if (result)
2206                         return result;
2207         }
2208
2209         /* Only enable level 0 for now. */
2210         levels[0].EnabledForActivity = 1;
2211
2212         /* in order to prevent MC activity from stutter mode to push DPM up.
2213          * the UVD change complements this by putting the MCLK in
2214          * a higher state by default such that we are not effected by
2215          * up threshold or and MCLK DPM latency.
2216          */
2217         levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2218         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2219
2220         data->smc_state_table.MemoryDpmLevelCount =
2221                         (uint8_t)dpm_table->mclk_table.count;
2222         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2223                         fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2224         /* set highest level watermark to high */
2225         levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2226                         PPSMC_DISPLAY_WATERMARK_HIGH;
2227
2228         /* level count will send to smc once at init smc table and never change */
2229         result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2230                         (uint32_t)array_size, data->sram_end);
2231
2232         return result;
2233 }
2234
2235 /**
2236 * Populates the SMC MVDD structure using the provided memory clock.
2237 *
2238 * @param    hwmgr      the address of the hardware manager
2239 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2240 * @param    voltage     the SMC VOLTAGE structure to be populated
2241 */
2242 int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2243                 uint32_t mclk, SMIO_Pattern *smio_pat)
2244 {
2245         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2246         struct phm_ppt_v1_information *table_info =
2247                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2248         uint32_t i = 0;
2249
2250         if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2251                 /* find mvdd value which clock is more than request */
2252                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2253                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2254                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2255                                 break;
2256                         }
2257                 }
2258                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2259                                 "MVDD Voltage is outside the supported range.",
2260                                 return -EINVAL);
2261         } else
2262                 return -EINVAL;
2263
2264         return 0;
2265 }
2266
2267 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2268                 SMU73_Discrete_DpmTable *table)
2269 {
2270         int result = 0;
2271         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2272         struct phm_ppt_v1_information *table_info =
2273                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2274         struct pp_atomctrl_clock_dividers_vi dividers;
2275         SMIO_Pattern vol_level;
2276         uint32_t mvdd;
2277         uint16_t us_mvdd;
2278         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2279         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2280
2281         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2282
2283         if (!data->sclk_dpm_key_disabled) {
2284                 /* Get MinVoltage and Frequency from DPM0,
2285                  * already converted to SMC_UL */
2286                 table->ACPILevel.SclkFrequency =
2287                                 data->dpm_table.sclk_table.dpm_levels[0].value;
2288                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2289                                 table_info->vdd_dep_on_sclk,
2290                                 table->ACPILevel.SclkFrequency,
2291                                 &table->ACPILevel.MinVoltage, &mvdd);
2292                 PP_ASSERT_WITH_CODE((0 == result),
2293                                 "Cannot find ACPI VDDC voltage value "
2294                                 "in Clock Dependency Table",);
2295         } else {
2296                 table->ACPILevel.SclkFrequency =
2297                                 data->vbios_boot_state.sclk_bootup_value;
2298                 table->ACPILevel.MinVoltage =
2299                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2300         }
2301
2302         /* get the engine clock dividers for this clock value */
2303         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2304                         table->ACPILevel.SclkFrequency,  &dividers);
2305         PP_ASSERT_WITH_CODE(result == 0,
2306                         "Error retrieving Engine Clock dividers from VBIOS.",
2307                         return result);
2308
2309         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2310         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2311         table->ACPILevel.DeepSleepDivId = 0;
2312
2313         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2314                         SPLL_PWRON, 0);
2315         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2316                         SPLL_RESET, 1);
2317         spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2318                         SCLK_MUX_SEL, 4);
2319
2320         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2321         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2322         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2323         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2324         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2325         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2326         table->ACPILevel.CcPwrDynRm = 0;
2327         table->ACPILevel.CcPwrDynRm1 = 0;
2328
2329         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2330         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2331         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2332         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2333         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2334         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2335         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2336         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2337         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2338         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2339         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2340
2341         if (!data->mclk_dpm_key_disabled) {
2342                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2343                 table->MemoryACPILevel.MclkFrequency =
2344                                 data->dpm_table.mclk_table.dpm_levels[0].value;
2345                 result = fiji_get_dependency_volt_by_clk(hwmgr,
2346                                 table_info->vdd_dep_on_mclk,
2347                                 table->MemoryACPILevel.MclkFrequency,
2348                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
2349                 PP_ASSERT_WITH_CODE((0 == result),
2350                                 "Cannot find ACPI VDDCI voltage value "
2351                                 "in Clock Dependency Table",);
2352         } else {
2353                 table->MemoryACPILevel.MclkFrequency =
2354                                 data->vbios_boot_state.mclk_bootup_value;
2355                 table->MemoryACPILevel.MinVoltage =
2356                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2357         }
2358
2359         us_mvdd = 0;
2360         if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2361                         (data->mclk_dpm_key_disabled))
2362                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2363         else {
2364                 if (!fiji_populate_mvdd_value(hwmgr,
2365                                 data->dpm_table.mclk_table.dpm_levels[0].value,
2366                                 &vol_level))
2367                         us_mvdd = vol_level.Voltage;
2368         }
2369
2370         table->MemoryACPILevel.MinMvdd =
2371                         PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2372
2373         table->MemoryACPILevel.EnabledForThrottle = 0;
2374         table->MemoryACPILevel.EnabledForActivity = 0;
2375         table->MemoryACPILevel.UpHyst = 0;
2376         table->MemoryACPILevel.DownHyst = 100;
2377         table->MemoryACPILevel.VoltageDownHyst = 0;
2378         table->MemoryACPILevel.ActivityLevel =
2379                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2380
2381         table->MemoryACPILevel.StutterEnable = false;
2382         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2383         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2384
2385         return result;
2386 }
2387
2388 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2389                 SMU73_Discrete_DpmTable *table)
2390 {
2391         int result = -EINVAL;
2392         uint8_t count;
2393         struct pp_atomctrl_clock_dividers_vi dividers;
2394         struct phm_ppt_v1_information *table_info =
2395                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2396         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2397                         table_info->mm_dep_table;
2398         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2399
2400         table->VceLevelCount = (uint8_t)(mm_table->count);
2401         table->VceBootLevel = 0;
2402
2403         for(count = 0; count < table->VceLevelCount; count++) {
2404                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2405                 table->VceLevel[count].MinVoltage = 0;
2406                 table->VceLevel[count].MinVoltage |=
2407                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2408                 table->VceLevel[count].MinVoltage |=
2409                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2410                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
2411                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2412
2413                 /*retrieve divider value for VBIOS */
2414                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2415                                 table->VceLevel[count].Frequency, &dividers);
2416                 PP_ASSERT_WITH_CODE((0 == result),
2417                                 "can not find divide id for VCE engine clock",
2418                                 return result);
2419
2420                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2421
2422                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2423                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2424         }
2425         return result;
2426 }
2427
2428 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2429                 SMU73_Discrete_DpmTable *table)
2430 {
2431         int result = -EINVAL;
2432         uint8_t count;
2433         struct pp_atomctrl_clock_dividers_vi dividers;
2434         struct phm_ppt_v1_information *table_info =
2435                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2436         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2437                         table_info->mm_dep_table;
2438         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2439
2440         table->AcpLevelCount = (uint8_t)(mm_table->count);
2441         table->AcpBootLevel = 0;
2442
2443         for (count = 0; count < table->AcpLevelCount; count++) {
2444                 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2445                 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2446                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2447                 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2448                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2449                 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2450
2451                 /* retrieve divider value for VBIOS */
2452                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2453                                 table->AcpLevel[count].Frequency, &dividers);
2454                 PP_ASSERT_WITH_CODE((0 == result),
2455                                 "can not find divide id for engine clock", return result);
2456
2457                 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2458
2459                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2460                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2461         }
2462         return result;
2463 }
2464
2465 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2466                 SMU73_Discrete_DpmTable *table)
2467 {
2468         int result = -EINVAL;
2469         uint8_t count;
2470         struct pp_atomctrl_clock_dividers_vi dividers;
2471         struct phm_ppt_v1_information *table_info =
2472                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2473         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2474                         table_info->mm_dep_table;
2475         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2476
2477         table->SamuBootLevel = 0;
2478         table->SamuLevelCount = (uint8_t)(mm_table->count);
2479
2480         for (count = 0; count < table->SamuLevelCount; count++) {
2481                 /* not sure whether we need evclk or not */
2482                 table->SamuLevel[count].MinVoltage = 0;
2483                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2484                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2485                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2486                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2487                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2488                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2489
2490                 /* retrieve divider value for VBIOS */
2491                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2492                                 table->SamuLevel[count].Frequency, &dividers);
2493                 PP_ASSERT_WITH_CODE((0 == result),
2494                                 "can not find divide id for samu clock", return result);
2495
2496                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2497
2498                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2499                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2500         }
2501         return result;
2502 }
2503
2504 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2505                 int32_t eng_clock, int32_t mem_clock,
2506                 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2507 {
2508         uint32_t dram_timing;
2509         uint32_t dram_timing2;
2510         uint32_t burstTime;
2511         ULONG state, trrds, trrdl;
2512         int result;
2513
2514         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2515                         eng_clock, mem_clock);
2516         PP_ASSERT_WITH_CODE(result == 0,
2517                         "Error calling VBIOS to set DRAM_TIMING.", return result);
2518
2519         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2520         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2521         burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2522
2523         state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2524         trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2525         trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2526
2527         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
2528         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2529         arb_regs->McArbBurstTime   = (uint8_t)burstTime;
2530         arb_regs->TRRDS            = (uint8_t)trrds;
2531         arb_regs->TRRDL            = (uint8_t)trrdl;
2532
2533         return 0;
2534 }
2535
2536 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2537 {
2538         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2539         struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2540         uint32_t i, j;
2541         int result = 0;
2542
2543         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2544                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2545                         result = fiji_populate_memory_timing_parameters(hwmgr,
2546                                         data->dpm_table.sclk_table.dpm_levels[i].value,
2547                                         data->dpm_table.mclk_table.dpm_levels[j].value,
2548                                         &arb_regs.entries[i][j]);
2549                         if (result)
2550                                 break;
2551                 }
2552         }
2553
2554         if (!result)
2555                 result = fiji_copy_bytes_to_smc(
2556                                 hwmgr->smumgr,
2557                                 data->arb_table_start,
2558                                 (uint8_t *)&arb_regs,
2559                                 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2560                                 data->sram_end);
2561         return result;
2562 }
2563
2564 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2565                 struct SMU73_Discrete_DpmTable *table)
2566 {
2567         int result = -EINVAL;
2568         uint8_t count;
2569         struct pp_atomctrl_clock_dividers_vi dividers;
2570         struct phm_ppt_v1_information *table_info =
2571                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2572         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2573                         table_info->mm_dep_table;
2574         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2575
2576         table->UvdLevelCount = (uint8_t)(mm_table->count);
2577         table->UvdBootLevel = 0;
2578
2579         for (count = 0; count < table->UvdLevelCount; count++) {
2580                 table->UvdLevel[count].MinVoltage = 0;
2581                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2582                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2583                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2584                                 VOLTAGE_SCALE) << VDDC_SHIFT;
2585                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2586                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2587                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2588
2589                 /* retrieve divider value for VBIOS */
2590                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2591                                 table->UvdLevel[count].VclkFrequency, &dividers);
2592                 PP_ASSERT_WITH_CODE((0 == result),
2593                                 "can not find divide id for Vclk clock", return result);
2594
2595                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2596
2597                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2598                                 table->UvdLevel[count].DclkFrequency, &dividers);
2599                 PP_ASSERT_WITH_CODE((0 == result),
2600                                 "can not find divide id for Dclk clock", return result);
2601
2602                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2603
2604                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2605                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2606                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2607
2608         }
2609         return result;
2610 }
2611
2612 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2613                 uint32_t value, uint32_t *boot_level)
2614 {
2615         int result = -EINVAL;
2616         uint32_t i;
2617
2618         for (i = 0; i < table->count; i++) {
2619                 if (value == table->dpm_levels[i].value) {
2620                         *boot_level = i;
2621                         result = 0;
2622                 }
2623         }
2624         return result;
2625 }
2626
2627 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2628                 struct SMU73_Discrete_DpmTable *table)
2629 {
2630         int result = 0;
2631         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2632
2633         table->GraphicsBootLevel = 0;
2634         table->MemoryBootLevel = 0;
2635
2636         /* find boot level from dpm table */
2637         result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2638                         data->vbios_boot_state.sclk_bootup_value,
2639                         (uint32_t *)&(table->GraphicsBootLevel));
2640
2641         result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2642                         data->vbios_boot_state.mclk_bootup_value,
2643                         (uint32_t *)&(table->MemoryBootLevel));
2644
2645         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
2646                         VOLTAGE_SCALE;
2647         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2648                         VOLTAGE_SCALE;
2649         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
2650                         VOLTAGE_SCALE;
2651
2652         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2653         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2654         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2655
2656         return 0;
2657 }
2658
2659 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2660 {
2661         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2662         struct phm_ppt_v1_information *table_info =
2663                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2664         uint8_t count, level;
2665
2666         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2667         for (level = 0; level < count; level++) {
2668                 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2669                                 data->vbios_boot_state.sclk_bootup_value) {
2670                         data->smc_state_table.GraphicsBootLevel = level;
2671                         break;
2672                 }
2673         }
2674
2675         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2676         for (level = 0; level < count; level++) {
2677                 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2678                                 data->vbios_boot_state.mclk_bootup_value) {
2679                         data->smc_state_table.MemoryBootLevel = level;
2680                         break;
2681                 }
2682         }
2683
2684         return 0;
2685 }
2686
2687 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2688 {
2689         uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2690                         volt_with_cks, value;
2691         uint16_t clock_freq_u16;
2692         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2693         uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2694                         volt_offset = 0;
2695         struct phm_ppt_v1_information *table_info =
2696                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2697         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2698                         table_info->vdd_dep_on_sclk;
2699
2700         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2701
2702         /* Read SMU_Eefuse to read and calculate RO and determine
2703          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2704          */
2705         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2706                         ixSMU_EFUSE_0 + (146 * 4));
2707         efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2708                         ixSMU_EFUSE_0 + (148 * 4));
2709         efuse &= 0xFF000000;
2710         efuse = efuse >> 24;
2711         efuse2 &= 0xF;
2712
2713         if (efuse2 == 1)
2714                 ro = (2300 - 1350) * efuse / 255 + 1350;
2715         else
2716                 ro = (2500 - 1000) * efuse / 255 + 1000;
2717
2718         if (ro >= 1660)
2719                 type = 0;
2720         else
2721                 type = 1;
2722
2723         /* Populate Stretch amount */
2724         data->smc_state_table.ClockStretcherAmount = stretch_amount;
2725
2726         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2727         for (i = 0; i < sclk_table->count; i++) {
2728                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2729                                 sclk_table->entries[i].cks_enable << i;
2730                 volt_without_cks = (uint32_t)((14041 *
2731                         (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2732                         (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2733                 volt_with_cks = (uint32_t)((13946 *
2734                         (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2735                         (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2736                 if (volt_without_cks >= volt_with_cks)
2737                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2738                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2739                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2740         }
2741
2742         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2743                         STRETCH_ENABLE, 0x0);
2744         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2745                         masterReset, 0x1);
2746         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2747                         staticEnable, 0x1);
2748         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2749                         masterReset, 0x0);
2750
2751         /* Populate CKS Lookup Table */
2752         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2753                 stretch_amount2 = 0;
2754         else if (stretch_amount == 3 || stretch_amount == 4)
2755                 stretch_amount2 = 1;
2756         else {
2757                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2758                                 PHM_PlatformCaps_ClockStretcher);
2759                 PP_ASSERT_WITH_CODE(false,
2760                                 "Stretch Amount in PPTable not supported\n",
2761                                 return -EINVAL);
2762         }
2763
2764         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2765                         ixPWR_CKS_CNTL);
2766         value &= 0xFFC2FF87;
2767         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2768                         fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2769         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2770                         fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2771         clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2772                         GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2773                         SclkFrequency) / 100);
2774         if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2775                         clock_freq_u16 &&
2776             fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2777                         clock_freq_u16) {
2778                 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2779                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2780                 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2781                 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2782                 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2783                 value |= (fiji_clock_stretch_amount_conversion
2784                                 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2785                                  [stretch_amount]) << 3;
2786         }
2787         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2788                         CKS_LOOKUPTableEntry[0].minFreq);
2789         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2790                         CKS_LOOKUPTableEntry[0].maxFreq);
2791         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2792                         fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2793         data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2794                         (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2795
2796         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2797                         ixPWR_CKS_CNTL, value);
2798
2799         /* Populate DDT Lookup Table */
2800         for (i = 0; i < 4; i++) {
2801                 /* Assign the minimum and maximum VID stored
2802                  * in the last row of Clock Stretcher Voltage Table.
2803                  */
2804                 data->smc_state_table.ClockStretcherDataTable.
2805                 ClockStretcherDataTableEntry[i].minVID =
2806                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2807                 data->smc_state_table.ClockStretcherDataTable.
2808                 ClockStretcherDataTableEntry[i].maxVID =
2809                                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2810                 /* Loop through each SCLK and check the frequency
2811                  * to see if it lies within the frequency for clock stretcher.
2812                  */
2813                 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2814                         cks_setting = 0;
2815                         clock_freq = PP_SMC_TO_HOST_UL(
2816                                         data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2817                         /* Check the allowed frequency against the sclk level[j].
2818                          *  Sclk's endianness has already been converted,
2819                          *  and it's in 10Khz unit,
2820                          *  as opposed to Data table, which is in Mhz unit.
2821                          */
2822                         if (clock_freq >=
2823                                         (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2824                                 cks_setting |= 0x2;
2825                                 if (clock_freq <
2826                                                 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2827                                         cks_setting |= 0x1;
2828                         }
2829                         data->smc_state_table.ClockStretcherDataTable.
2830                         ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2831                 }
2832                 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2833                                 ClockStretcherDataTable.
2834                                 ClockStretcherDataTableEntry[i].setting);
2835         }
2836
2837         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2838         value &= 0xFFFFFFFE;
2839         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2840
2841         return 0;
2842 }
2843
2844 /**
2845 * Populates the SMC VRConfig field in DPM table.
2846 *
2847 * @param    hwmgr   the address of the hardware manager
2848 * @param    table   the SMC DPM table structure to be populated
2849 * @return   always 0
2850 */
2851 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2852                 struct SMU73_Discrete_DpmTable *table)
2853 {
2854         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2855         uint16_t config;
2856
2857         config = VR_MERGED_WITH_VDDC;
2858         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2859
2860         /* Set Vddc Voltage Controller */
2861         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2862                 config = VR_SVI2_PLANE_1;
2863                 table->VRConfig |= config;
2864         } else {
2865                 PP_ASSERT_WITH_CODE(false,
2866                                 "VDDC should be on SVI2 control in merged mode!",);
2867         }
2868         /* Set Vddci Voltage Controller */
2869         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2870                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
2871                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2872         } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2873                 config = VR_SMIO_PATTERN_1;
2874                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2875         } else {
2876                 config = VR_STATIC_VOLTAGE;
2877                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2878         }
2879         /* Set Mvdd Voltage Controller */
2880         if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2881                 config = VR_SVI2_PLANE_2;
2882                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2883         } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2884                 config = VR_SMIO_PATTERN_2;
2885                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2886         } else {
2887                 config = VR_STATIC_VOLTAGE;
2888                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2889         }
2890
2891         return 0;
2892 }
2893
2894 /**
2895 * Initializes the SMC table and uploads it
2896 *
2897 * @param    hwmgr  the address of the powerplay hardware manager.
2898 * @param    pInput  the pointer to input data (PowerState)
2899 * @return   always 0
2900 */
2901 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2902 {
2903         int result;
2904         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2905         struct phm_ppt_v1_information *table_info =
2906                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2907         struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2908         const struct fiji_ulv_parm *ulv = &(data->ulv);
2909         uint8_t i;
2910         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2911
2912         result = fiji_setup_default_dpm_tables(hwmgr);
2913         PP_ASSERT_WITH_CODE(0 == result,
2914                         "Failed to setup default DPM tables!", return result);
2915
2916         if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2917                 fiji_populate_smc_voltage_tables(hwmgr, table);
2918
2919         table->SystemFlags = 0;
2920
2921         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2922                         PHM_PlatformCaps_AutomaticDCTransition))
2923                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2924
2925         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2926                         PHM_PlatformCaps_StepVddc))
2927                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2928
2929         if (data->is_memory_gddr5)
2930                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2931
2932         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2933                 result = fiji_populate_ulv_state(hwmgr, table);
2934                 PP_ASSERT_WITH_CODE(0 == result,
2935                                 "Failed to initialize ULV state!", return result);
2936                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2937                                 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2938         }
2939
2940         result = fiji_populate_smc_link_level(hwmgr, table);
2941         PP_ASSERT_WITH_CODE(0 == result,
2942                         "Failed to initialize Link Level!", return result);
2943
2944         result = fiji_populate_all_graphic_levels(hwmgr);
2945         PP_ASSERT_WITH_CODE(0 == result,
2946                         "Failed to initialize Graphics Level!", return result);
2947
2948         result = fiji_populate_all_memory_levels(hwmgr);
2949         PP_ASSERT_WITH_CODE(0 == result,
2950                         "Failed to initialize Memory Level!", return result);
2951
2952         result = fiji_populate_smc_acpi_level(hwmgr, table);
2953         PP_ASSERT_WITH_CODE(0 == result,
2954                         "Failed to initialize ACPI Level!", return result);
2955
2956         result = fiji_populate_smc_vce_level(hwmgr, table);
2957         PP_ASSERT_WITH_CODE(0 == result,
2958                         "Failed to initialize VCE Level!", return result);
2959
2960         result = fiji_populate_smc_acp_level(hwmgr, table);
2961         PP_ASSERT_WITH_CODE(0 == result,
2962                         "Failed to initialize ACP Level!", return result);
2963
2964         result = fiji_populate_smc_samu_level(hwmgr, table);
2965         PP_ASSERT_WITH_CODE(0 == result,
2966                         "Failed to initialize SAMU Level!", return result);
2967
2968         /* Since only the initial state is completely set up at this point
2969          * (the other states are just copies of the boot state) we only
2970          * need to populate the  ARB settings for the initial state.
2971          */
2972         result = fiji_program_memory_timing_parameters(hwmgr);
2973         PP_ASSERT_WITH_CODE(0 == result,
2974                         "Failed to Write ARB settings for the initial state.", return result);
2975
2976         result = fiji_populate_smc_uvd_level(hwmgr, table);
2977         PP_ASSERT_WITH_CODE(0 == result,
2978                         "Failed to initialize UVD Level!", return result);
2979
2980         result = fiji_populate_smc_boot_level(hwmgr, table);
2981         PP_ASSERT_WITH_CODE(0 == result,
2982                         "Failed to initialize Boot Level!", return result);
2983
2984         result = fiji_populate_smc_initailial_state(hwmgr);
2985         PP_ASSERT_WITH_CODE(0 == result,
2986                         "Failed to initialize Boot State!", return result);
2987
2988         result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2989         PP_ASSERT_WITH_CODE(0 == result,
2990                         "Failed to populate BAPM Parameters!", return result);
2991
2992         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2993                         PHM_PlatformCaps_ClockStretcher)) {
2994                 result = fiji_populate_clock_stretcher_data_table(hwmgr);
2995                 PP_ASSERT_WITH_CODE(0 == result,
2996                                 "Failed to populate Clock Stretcher Data Table!",
2997                                 return result);
2998         }
2999
3000         table->GraphicsVoltageChangeEnable  = 1;
3001         table->GraphicsThermThrottleEnable  = 1;
3002         table->GraphicsInterval = 1;
3003         table->VoltageInterval  = 1;
3004         table->ThermalInterval  = 1;
3005         table->TemperatureLimitHigh =
3006                         table_info->cac_dtp_table->usTargetOperatingTemp *
3007                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
3008         table->TemperatureLimitLow  =
3009                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3010                         FIJI_Q88_FORMAT_CONVERSION_UNIT;
3011         table->MemoryVoltageChangeEnable = 1;
3012         table->MemoryInterval = 1;
3013         table->VoltageResponseTime = 0;
3014         table->PhaseResponseTime = 0;
3015         table->MemoryThermThrottleEnable = 1;
3016         table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
3017         table->PCIeGenInterval = 1;
3018         table->VRConfig = 0;
3019
3020         result = fiji_populate_vr_config(hwmgr, table);
3021         PP_ASSERT_WITH_CODE(0 == result,
3022                         "Failed to populate VRConfig setting!", return result);
3023
3024         table->ThermGpio = 17;
3025         table->SclkStepSize = 0x4000;
3026
3027         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
3028                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
3029                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3030                                 PHM_PlatformCaps_RegulatorHot);
3031         } else {
3032                 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
3033                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3034                                 PHM_PlatformCaps_RegulatorHot);
3035         }
3036
3037         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3038                         &gpio_pin)) {
3039                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
3040                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3041                                 PHM_PlatformCaps_AutomaticDCTransition);
3042         } else {
3043                 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
3044                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3045                                 PHM_PlatformCaps_AutomaticDCTransition);
3046         }
3047
3048         /* Thermal Output GPIO */
3049         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
3050                         &gpio_pin)) {
3051                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3052                                 PHM_PlatformCaps_ThermalOutGPIO);
3053
3054                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
3055
3056                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3057                  * since VBIOS will program this register to set 'inactive state',
3058                  * driver can then determine 'active state' from this and
3059                  * program SMU with correct polarity
3060                  */
3061                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3062                                 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3063                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3064
3065                 /* if required, combine VRHot/PCC with thermal out GPIO */
3066                 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3067                                 PHM_PlatformCaps_RegulatorHot) &&
3068                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3069                                         PHM_PlatformCaps_CombinePCCWithThermalSignal))
3070                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3071         } else {
3072                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3073                                 PHM_PlatformCaps_ThermalOutGPIO);
3074                 table->ThermOutGpio = 17;
3075                 table->ThermOutPolarity = 1;
3076                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3077         }
3078
3079         for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3080                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3081
3082         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3083         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3084         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3085         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3086         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3087         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3088         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3089         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3090         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3091
3092         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3093         result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3094                         data->dpm_table_start +
3095                         offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3096                         (uint8_t *)&(table->SystemFlags),
3097                         sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3098                         data->sram_end);
3099         PP_ASSERT_WITH_CODE(0 == result,
3100                         "Failed to upload dpm data to SMC memory!", return result);
3101
3102         return 0;
3103 }
3104
3105 /**
3106 * Initialize the ARB DRAM timing table's index field.
3107 *
3108 * @param    hwmgr  the address of the powerplay hardware manager.
3109 * @return   always 0
3110 */
3111 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3112 {
3113         const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3114         uint32_t tmp;
3115         int result;
3116
3117         /* This is a read-modify-write on the first byte of the ARB table.
3118          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3119          * is the field 'current'.
3120          * This solution is ugly, but we never write the whole table only
3121          * individual fields in it.
3122          * In reality this field should not be in that structure
3123          * but in a soft register.
3124          */
3125         result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3126                         data->arb_table_start, &tmp, data->sram_end);
3127
3128         if (result)
3129                 return result;
3130
3131         tmp &= 0x00FFFFFF;
3132         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3133
3134         return fiji_write_smc_sram_dword(hwmgr->smumgr,
3135                         data->arb_table_start,  tmp, data->sram_end);
3136 }
3137
3138 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3139 {
3140         if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3141                         PHM_PlatformCaps_RegulatorHot))
3142                 return smum_send_msg_to_smc(hwmgr->smumgr,
3143                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3144
3145         return 0;
3146 }
3147
3148 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3149 {
3150         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3151                         SCLK_PWRMGT_OFF, 0);
3152         return 0;
3153 }
3154
3155 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3156 {
3157         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3158         struct fiji_ulv_parm *ulv = &(data->ulv);
3159
3160         if (ulv->ulv_supported)
3161                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3162
3163         return 0;
3164 }
3165
3166 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3167 {
3168         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3169                         PHM_PlatformCaps_SclkDeepSleep)) {
3170                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3171                         PP_ASSERT_WITH_CODE(false,
3172                                         "Attempt to enable Master Deep Sleep switch failed!",
3173                                         return -1);
3174         } else {
3175                 if (smum_send_msg_to_smc(hwmgr->smumgr,
3176                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3177                         PP_ASSERT_WITH_CODE(false,
3178                                         "Attempt to disable Master Deep Sleep switch failed!",
3179                                         return -1);
3180                 }
3181         }
3182
3183         return 0;
3184 }
3185
3186 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3187 {
3188         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3189         uint32_t   val, val0, val2;
3190         uint32_t   i, cpl_cntl, cpl_threshold, mc_threshold;
3191
3192         /* enable SCLK dpm */
3193         if(!data->sclk_dpm_key_disabled)
3194                 PP_ASSERT_WITH_CODE(
3195                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3196                 "Failed to enable SCLK DPM during DPM Start Function!",
3197                 return -1);
3198
3199         /* enable MCLK dpm */
3200         if(0 == data->mclk_dpm_key_disabled) {
3201                 cpl_threshold = 0;
3202                 mc_threshold = 0;
3203
3204                 /* Read per MCD tile (0 - 7) */
3205                 for (i = 0; i < 8; i++) {
3206                         PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3207                         val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3208                         if (0xf0000000 != val) {
3209                                 /* count number of MCQ that has channel(s) enabled */
3210                                 cpl_threshold++;
3211                                 /* only harvest 3 or full 4 supported */
3212                                 mc_threshold = val ? 3 : 4;
3213                         }
3214                 }
3215                 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3216                                 "Number of MCQ is zero!", return -EINVAL;);
3217
3218                 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3219                                 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3220                                                 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3221                 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3222                                 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3223                                                 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3224                 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3225                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3226                                 ixLCAC_MC0_CNTL, mc_threshold);
3227                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3228                                 ixLCAC_MC1_CNTL, mc_threshold);
3229                 if (8 == cpl_threshold) {
3230                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3231                                         ixLCAC_MC2_CNTL, mc_threshold);
3232                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3233                                         ixLCAC_MC3_CNTL, mc_threshold);
3234                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3235                                         ixLCAC_MC4_CNTL, mc_threshold);
3236                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3237                                         ixLCAC_MC5_CNTL, mc_threshold);
3238                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3239                                         ixLCAC_MC6_CNTL, mc_threshold);
3240                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3241                                         ixLCAC_MC7_CNTL, mc_threshold);
3242                 }
3243                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3244                                 ixLCAC_CPL_CNTL, cpl_cntl);
3245
3246                 udelay(5);
3247
3248                 mc_threshold = mc_threshold |
3249                                 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3250                 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3251                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3252                                 ixLCAC_MC0_CNTL, mc_threshold);
3253                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3254                                 ixLCAC_MC1_CNTL, mc_threshold);
3255                 if (8 == cpl_threshold) {
3256                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3257                                         ixLCAC_MC2_CNTL, mc_threshold);
3258                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3259                                         ixLCAC_MC3_CNTL, mc_threshold);
3260                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3261                                         ixLCAC_MC4_CNTL, mc_threshold);
3262                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3263                                         ixLCAC_MC5_CNTL, mc_threshold);
3264                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3265                                         ixLCAC_MC6_CNTL, mc_threshold);
3266                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3267                                         ixLCAC_MC7_CNTL, mc_threshold);
3268                 }
3269                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3270                                 ixLCAC_CPL_CNTL, cpl_cntl);
3271
3272                 /* Program CAC_EN per MCD (0-7) Tile */
3273                 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3274                 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3275                                 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3276                                 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3277                                 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3278                                 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3279                                 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3280                                 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3281                                 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3282                                 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3283
3284                 for (i = 0; i < 8; i++) {
3285                         /* Enable MCD i Tile read & write */
3286                         val2  = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3287                                         (1 << i));
3288                         cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3289                         /* Enbale CAC_ON MCD i Tile */
3290                         val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3291                         val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3292                         cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3293                 }
3294                 /* Set MC_CONFIG_MCD back to its default setting val0 */
3295                 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3296
3297                 PP_ASSERT_WITH_CODE(
3298                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3299                                                 PPSMC_MSG_MCLKDPM_Enable)),
3300                                 "Failed to enable MCLK DPM during DPM Start Function!",
3301                                 return -1);
3302         }
3303         return 0;
3304 }
3305
3306 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3307 {
3308         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3309
3310         /*enable general power management */
3311         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3312                         GLOBAL_PWRMGT_EN, 1);
3313         /* enable sclk deep sleep */
3314         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3315                         DYNAMIC_PM_EN, 1);
3316         /* prepare for PCIE DPM */
3317         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3318                         data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3319                                         VoltageChangeTimeout), 0x1000);
3320         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3321                         SWRST_COMMAND_1, RESETLC, 0x0);
3322
3323         PP_ASSERT_WITH_CODE(
3324                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3325                                         PPSMC_MSG_Voltage_Cntl_Enable)),
3326                         "Failed to enable voltage DPM during DPM Start Function!",
3327                         return -1);
3328
3329         if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3330                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3331                 return -1;
3332         }
3333
3334         /* enable PCIE dpm */
3335         if(!data->pcie_dpm_key_disabled) {
3336                 PP_ASSERT_WITH_CODE(
3337                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3338                                                 PPSMC_MSG_PCIeDPM_Enable)),
3339                                 "Failed to enable pcie DPM during DPM Start Function!",
3340                                 return -1);
3341         }
3342
3343         return 0;
3344 }
3345
3346 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3347                 uint32_t sources)
3348 {
3349         bool protection;
3350         enum DPM_EVENT_SRC src;
3351
3352         switch (sources) {
3353         default:
3354                 printk(KERN_ERR "Unknown throttling event sources.");
3355                 /* fall through */
3356         case 0:
3357                 protection = false;
3358                 /* src is unused */
3359                 break;
3360         case (1 << PHM_AutoThrottleSource_Thermal):
3361                 protection = true;
3362                 src = DPM_EVENT_SRC_DIGITAL;
3363                 break;
3364         case (1 << PHM_AutoThrottleSource_External):
3365                 protection = true;
3366                 src = DPM_EVENT_SRC_EXTERNAL;
3367                 break;
3368         case (1 << PHM_AutoThrottleSource_External) |
3369                         (1 << PHM_AutoThrottleSource_Thermal):
3370                 protection = true;
3371                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3372                 break;
3373         }
3374         /* Order matters - don't enable thermal protection for the wrong source. */
3375         if (protection) {
3376                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3377                                 DPM_EVENT_SRC, src);
3378                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3379                                 THERMAL_PROTECTION_DIS,
3380                                 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3381                                                 PHM_PlatformCaps_ThermalController));
3382         } else
3383                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3384                                 THERMAL_PROTECTION_DIS, 1);
3385 }
3386
3387 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3388                 PHM_AutoThrottleSource source)
3389 {
3390         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3391
3392         if (!(data->active_auto_throttle_sources & (1 << source))) {
3393                 data->active_auto_throttle_sources |= 1 << source;
3394                 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3395         }
3396         return 0;
3397 }
3398
3399 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3400 {
3401         return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3402 }
3403
3404 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3405 {
3406         int tmp_result, result = 0;
3407
3408         tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3409         PP_ASSERT_WITH_CODE(result == 0,
3410                         "DPM is already running right now, no need to enable DPM!",
3411                         return 0);
3412
3413         if (fiji_voltage_control(hwmgr)) {
3414                 tmp_result = fiji_enable_voltage_control(hwmgr);
3415                 PP_ASSERT_WITH_CODE(tmp_result == 0,
3416                                 "Failed to enable voltage control!",
3417                                 result = tmp_result);
3418         }
3419
3420         if (fiji_voltage_control(hwmgr)) {
3421                 tmp_result = fiji_construct_voltage_tables(hwmgr);
3422                 PP_ASSERT_WITH_CODE((0 == tmp_result),
3423                                 "Failed to contruct voltage tables!",
3424                                 result = tmp_result);
3425         }
3426
3427         tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3428         PP_ASSERT_WITH_CODE((0 == tmp_result),
3429                         "Failed to initialize MC reg table!", result = tmp_result);
3430
3431         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3432                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3433                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3434                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3435
3436         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3437                         PHM_PlatformCaps_ThermalController))
3438                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3439                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3440
3441         tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3442         PP_ASSERT_WITH_CODE((0 == tmp_result),
3443                         "Failed to program static screen threshold parameters!",
3444                         result = tmp_result);
3445
3446         tmp_result = fiji_enable_display_gap(hwmgr);
3447         PP_ASSERT_WITH_CODE((0 == tmp_result),
3448                         "Failed to enable display gap!", result = tmp_result);
3449
3450         tmp_result = fiji_program_voting_clients(hwmgr);
3451         PP_ASSERT_WITH_CODE((0 == tmp_result),
3452                         "Failed to program voting clients!", result = tmp_result);
3453
3454         tmp_result = fiji_process_firmware_header(hwmgr);
3455         PP_ASSERT_WITH_CODE((0 == tmp_result),
3456                         "Failed to process firmware header!", result = tmp_result);
3457
3458         tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3459         PP_ASSERT_WITH_CODE((0 == tmp_result),
3460                         "Failed to initialize switch from ArbF0 to F1!",
3461                         result = tmp_result);
3462
3463         tmp_result = fiji_init_smc_table(hwmgr);
3464         PP_ASSERT_WITH_CODE((0 == tmp_result),
3465                         "Failed to initialize SMC table!", result = tmp_result);
3466
3467         tmp_result = fiji_init_arb_table_index(hwmgr);
3468         PP_ASSERT_WITH_CODE((0 == tmp_result),
3469                         "Failed to initialize ARB table index!", result = tmp_result);
3470
3471         tmp_result = fiji_populate_pm_fuses(hwmgr);
3472         PP_ASSERT_WITH_CODE((0 == tmp_result),
3473                         "Failed to populate PM fuses!", result = tmp_result);
3474
3475         tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3476         PP_ASSERT_WITH_CODE((0 == tmp_result),
3477                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3478
3479         tmp_result = tonga_notify_smc_display_change(hwmgr, false);
3480         PP_ASSERT_WITH_CODE((0 == tmp_result),
3481                         "Failed to notify no display!", result = tmp_result);
3482
3483         tmp_result = fiji_enable_sclk_control(hwmgr);
3484         PP_ASSERT_WITH_CODE((0 == tmp_result),
3485                         "Failed to enable SCLK control!", result = tmp_result);
3486
3487         tmp_result = fiji_enable_ulv(hwmgr);
3488         PP_ASSERT_WITH_CODE((0 == tmp_result),
3489                         "Failed to enable ULV!", result = tmp_result);
3490
3491         tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3492         PP_ASSERT_WITH_CODE((0 == tmp_result),
3493                         "Failed to enable deep sleep master switch!", result = tmp_result);
3494
3495         tmp_result = fiji_start_dpm(hwmgr);
3496         PP_ASSERT_WITH_CODE((0 == tmp_result),
3497                         "Failed to start DPM!", result = tmp_result);
3498
3499         tmp_result = fiji_enable_smc_cac(hwmgr);
3500         PP_ASSERT_WITH_CODE((0 == tmp_result),
3501                         "Failed to enable SMC CAC!", result = tmp_result);
3502
3503         tmp_result = fiji_enable_power_containment(hwmgr);
3504         PP_ASSERT_WITH_CODE((0 == tmp_result),
3505                         "Failed to enable power containment!", result = tmp_result);
3506
3507         tmp_result = fiji_power_control_set_level(hwmgr);
3508         PP_ASSERT_WITH_CODE((0 == tmp_result),
3509                         "Failed to power control set level!", result = tmp_result);
3510
3511         tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3512         PP_ASSERT_WITH_CODE((0 == tmp_result),
3513                         "Failed to enable thermal auto throttle!", result = tmp_result);
3514
3515         return result;
3516 }
3517
3518 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3519 {
3520         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3521         uint32_t level, tmp;
3522
3523         if (!data->sclk_dpm_key_disabled) {
3524                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3525                         level = 0;
3526                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3527                         while (tmp >>= 1)
3528                                 level++;
3529                         if (level)
3530                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3531                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3532                                                 (1 << level));
3533                 }
3534         }
3535
3536         if (!data->mclk_dpm_key_disabled) {
3537                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3538                         level = 0;
3539                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3540                         while (tmp >>= 1)
3541                                 level++;
3542                         if (level)
3543                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3544                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3545                                                 (1 << level));
3546                 }
3547         }
3548
3549         if (!data->pcie_dpm_key_disabled) {
3550                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3551                         level = 0;
3552                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3553                         while (tmp >>= 1)
3554                                 level++;
3555                         if (level)
3556                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3557                                                 PPSMC_MSG_PCIeDPM_ForceLevel,
3558                                                 (1 << level));
3559                 }
3560         }
3561         return 0;
3562 }
3563
3564 static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
3565 {
3566         struct phm_ppt_v1_information *table_info =
3567                         (struct phm_ppt_v1_information *)hwmgr->pptable;
3568         struct phm_clock_voltage_dependency_table *table =
3569                                 table_info->vddc_dep_on_dal_pwrl;
3570         struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
3571         enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
3572         uint32_t req_vddc = 0, req_volt, i;
3573
3574         if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
3575                         dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
3576                 return;
3577
3578         for (i= 0; i < table->count; i++) {
3579                 if (dal_power_level == table->entries[i].clk) {
3580                         req_vddc = table->entries[i].v;
3581                         break;
3582                 }
3583         }
3584
3585         vddc_table = table_info->vdd_dep_on_sclk;
3586         for (i= 0; i < vddc_table->count; i++) {
3587                 if (req_vddc <= vddc_table->entries[i].vddc) {
3588                         req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
3589                                         << VDDC_SHIFT;
3590                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3591                                         PPSMC_MSG_VddC_Request, req_volt);
3592                         return;
3593                 }
3594         }
3595         printk(KERN_ERR "DAL requested level can not"
3596                         " found a available voltage in VDDC DPM Table \n");
3597 }
3598
3599 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3600 {
3601         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3602
3603         fiji_apply_dal_min_voltage_request(hwmgr);
3604
3605         if (!data->sclk_dpm_key_disabled) {
3606                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3607                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3608                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3609                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3610         }
3611         return 0;
3612 }
3613
3614 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3615 {
3616         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3617
3618         if (!fiji_is_dpm_running(hwmgr))
3619                 return -EINVAL;
3620
3621         if (!data->pcie_dpm_key_disabled) {
3622                 smum_send_msg_to_smc(hwmgr->smumgr,
3623                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3624         }
3625
3626         return fiji_upload_dpmlevel_enable_mask(hwmgr);
3627 }
3628
3629 static uint32_t fiji_get_lowest_enabled_level(
3630                 struct pp_hwmgr *hwmgr, uint32_t mask)
3631 {
3632         uint32_t level = 0;
3633
3634         while(0 == (mask & (1 << level)))
3635                 level++;
3636
3637         return level;
3638 }
3639
3640 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3641 {
3642         struct fiji_hwmgr *data =
3643                         (struct fiji_hwmgr *)(hwmgr->backend);
3644         uint32_t level;
3645
3646         if (!data->sclk_dpm_key_disabled)
3647                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3648                         level = fiji_get_lowest_enabled_level(hwmgr,
3649                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3650                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3651                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3652                                                             (1 << level));
3653
3654         }
3655
3656         if (!data->mclk_dpm_key_disabled) {
3657                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3658                         level = fiji_get_lowest_enabled_level(hwmgr,
3659                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3660                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3661                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3662                                                             (1 << level));
3663                 }
3664         }
3665
3666         if (!data->pcie_dpm_key_disabled) {
3667                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3668                         level = fiji_get_lowest_enabled_level(hwmgr,
3669                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3670                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3671                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3672                                                             (1 << level));
3673                 }
3674         }
3675
3676         return 0;
3677
3678 }
3679 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3680                                 enum amd_dpm_forced_level level)
3681 {
3682         int ret = 0;
3683
3684         switch (level) {
3685         case AMD_DPM_FORCED_LEVEL_HIGH:
3686                 ret = fiji_force_dpm_highest(hwmgr);
3687                 if (ret)
3688                         return ret;
3689                 break;
3690         case AMD_DPM_FORCED_LEVEL_LOW:
3691                 ret = fiji_force_dpm_lowest(hwmgr);
3692                 if (ret)
3693                         return ret;
3694                 break;
3695         case AMD_DPM_FORCED_LEVEL_AUTO:
3696                 ret = fiji_unforce_dpm_levels(hwmgr);
3697                 if (ret)
3698                         return ret;
3699                 break;
3700         default:
3701                 break;
3702         }
3703
3704         hwmgr->dpm_level = level;
3705
3706         return ret;
3707 }
3708
3709 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3710 {
3711         return sizeof(struct fiji_power_state);
3712 }
3713
3714 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3715                 void *state, struct pp_power_state *power_state,
3716                 void *pp_table, uint32_t classification_flag)
3717 {
3718         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3719         struct fiji_power_state  *fiji_power_state =
3720                         (struct fiji_power_state *)(&(power_state->hardware));
3721         struct fiji_performance_level *performance_level;
3722         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3723         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3724                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3725         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3726                         (ATOM_Tonga_SCLK_Dependency_Table *)
3727                         (((unsigned long)powerplay_table) +
3728                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3729         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3730                         (ATOM_Tonga_MCLK_Dependency_Table *)
3731                         (((unsigned long)powerplay_table) +
3732                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3733
3734         /* The following fields are not initialized here: id orderedList allStatesList */
3735         power_state->classification.ui_label =
3736                         (le16_to_cpu(state_entry->usClassification) &
3737                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3738                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3739         power_state->classification.flags = classification_flag;
3740         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3741
3742         power_state->classification.temporary_state = false;
3743         power_state->classification.to_be_deleted = false;
3744
3745         power_state->validation.disallowOnDC =
3746                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3747                                         ATOM_Tonga_DISALLOW_ON_DC));
3748
3749         power_state->pcie.lanes = 0;
3750
3751         power_state->display.disableFrameModulation = false;
3752         power_state->display.limitRefreshrate = false;
3753         power_state->display.enableVariBright =
3754                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3755                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3756
3757         power_state->validation.supportedPowerLevels = 0;
3758         power_state->uvd_clocks.VCLK = 0;
3759         power_state->uvd_clocks.DCLK = 0;
3760         power_state->temperatures.min = 0;
3761         power_state->temperatures.max = 0;
3762
3763         performance_level = &(fiji_power_state->performance_levels
3764                         [fiji_power_state->performance_level_count++]);
3765
3766         PP_ASSERT_WITH_CODE(
3767                         (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3768                         "Performance levels exceeds SMC limit!",
3769                         return -1);
3770
3771         PP_ASSERT_WITH_CODE(
3772                         (fiji_power_state->performance_level_count <=
3773                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3774                         "Performance levels exceeds Driver limit!",
3775                         return -1);
3776
3777         /* Performance levels are arranged from low to high. */
3778         performance_level->memory_clock = mclk_dep_table->entries
3779                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3780         performance_level->engine_clock = sclk_dep_table->entries
3781                         [state_entry->ucEngineClockIndexLow].ulSclk;
3782         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3783                         state_entry->ucPCIEGenLow);
3784         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3785                         state_entry->ucPCIELaneHigh);
3786
3787         performance_level = &(fiji_power_state->performance_levels
3788                         [fiji_power_state->performance_level_count++]);
3789         performance_level->memory_clock = mclk_dep_table->entries
3790                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3791         performance_level->engine_clock = sclk_dep_table->entries
3792                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3793         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3794                         state_entry->ucPCIEGenHigh);
3795         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3796                         state_entry->ucPCIELaneHigh);
3797
3798         return 0;
3799 }
3800
3801 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3802                 unsigned long entry_index, struct pp_power_state *state)
3803 {
3804         int result;
3805         struct fiji_power_state *ps;
3806         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3807         struct phm_ppt_v1_information *table_info =
3808                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3809         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3810                         table_info->vdd_dep_on_mclk;
3811
3812         state->hardware.magic = PHM_VIslands_Magic;
3813
3814         ps = (struct fiji_power_state *)(&state->hardware);
3815
3816         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3817                         fiji_get_pp_table_entry_callback_func);
3818
3819         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3820          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3821          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3822          */
3823         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3824                 if (dep_mclk_table->entries[0].clk !=
3825                                 data->vbios_boot_state.mclk_bootup_value)
3826                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3827                                         "does not match VBIOS boot MCLK level");
3828                 if (dep_mclk_table->entries[0].vddci !=
3829                                 data->vbios_boot_state.vddci_bootup_value)
3830                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3831                                         "does not match VBIOS boot VDDCI level");
3832         }
3833
3834         /* set DC compatible flag if this state supports DC */
3835         if (!state->validation.disallowOnDC)
3836                 ps->dc_compatible = true;
3837
3838         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3839                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3840
3841         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3842         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3843
3844         if (!result) {
3845                 uint32_t i;
3846
3847                 switch (state->classification.ui_label) {
3848                 case PP_StateUILabel_Performance:
3849                         data->use_pcie_performance_levels = true;
3850
3851                         for (i = 0; i < ps->performance_level_count; i++) {
3852                                 if (data->pcie_gen_performance.max <
3853                                                 ps->performance_levels[i].pcie_gen)
3854                                         data->pcie_gen_performance.max =
3855                                                         ps->performance_levels[i].pcie_gen;
3856
3857                                 if (data->pcie_gen_performance.min >
3858                                                 ps->performance_levels[i].pcie_gen)
3859                                         data->pcie_gen_performance.min =
3860                                                         ps->performance_levels[i].pcie_gen;
3861
3862                                 if (data->pcie_lane_performance.max <
3863                                                 ps->performance_levels[i].pcie_lane)
3864                                         data->pcie_lane_performance.max =
3865                                                         ps->performance_levels[i].pcie_lane;
3866
3867                                 if (data->pcie_lane_performance.min >
3868                                                 ps->performance_levels[i].pcie_lane)
3869                                         data->pcie_lane_performance.min =
3870                                                         ps->performance_levels[i].pcie_lane;
3871                         }
3872                         break;
3873                 case PP_StateUILabel_Battery:
3874                         data->use_pcie_power_saving_levels = true;
3875
3876                         for (i = 0; i < ps->performance_level_count; i++) {
3877                                 if (data->pcie_gen_power_saving.max <
3878                                                 ps->performance_levels[i].pcie_gen)
3879                                         data->pcie_gen_power_saving.max =
3880                                                         ps->performance_levels[i].pcie_gen;
3881
3882                                 if (data->pcie_gen_power_saving.min >
3883                                                 ps->performance_levels[i].pcie_gen)
3884                                         data->pcie_gen_power_saving.min =
3885                                                         ps->performance_levels[i].pcie_gen;
3886
3887                                 if (data->pcie_lane_power_saving.max <
3888                                                 ps->performance_levels[i].pcie_lane)
3889                                         data->pcie_lane_power_saving.max =
3890                                                         ps->performance_levels[i].pcie_lane;
3891
3892                                 if (data->pcie_lane_power_saving.min >
3893                                                 ps->performance_levels[i].pcie_lane)
3894                                         data->pcie_lane_power_saving.min =
3895                                                         ps->performance_levels[i].pcie_lane;
3896                         }
3897                         break;
3898                 default:
3899                         break;
3900                 }
3901         }
3902         return 0;
3903 }
3904
3905 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3906                                 struct pp_power_state  *request_ps,
3907                         const struct pp_power_state *current_ps)
3908 {
3909         struct fiji_power_state *fiji_ps =
3910                                 cast_phw_fiji_power_state(&request_ps->hardware);
3911         uint32_t sclk;
3912         uint32_t mclk;
3913         struct PP_Clocks minimum_clocks = {0};
3914         bool disable_mclk_switching;
3915         bool disable_mclk_switching_for_frame_lock;
3916         struct cgs_display_info info = {0};
3917         const struct phm_clock_and_voltage_limits *max_limits;
3918         uint32_t i;
3919         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3920         struct phm_ppt_v1_information *table_info =
3921                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3922         int32_t count;
3923         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3924
3925         data->battery_state = (PP_StateUILabel_Battery ==
3926                         request_ps->classification.ui_label);
3927
3928         PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3929                                  "VI should always have 2 performance levels",);
3930
3931         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3932                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3933                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3934
3935         /* Cap clock DPM tables at DC MAX if it is in DC. */
3936         if (PP_PowerSource_DC == hwmgr->power_source) {
3937                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3938                         if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3939                                 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3940                         if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3941                                 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3942                 }
3943         }
3944
3945         fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3946         fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3947
3948         fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3949
3950         cgs_get_active_displays_info(hwmgr->device, &info);
3951
3952         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3953
3954         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3955
3956         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3957                         PHM_PlatformCaps_StablePState)) {
3958                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3959                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3960
3961                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3962                                 count >= 0; count--) {
3963                         if (stable_pstate_sclk >=
3964                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3965                                 stable_pstate_sclk =
3966                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3967                                 break;
3968                         }
3969                 }
3970
3971                 if (count < 0)
3972                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3973
3974                 stable_pstate_mclk = max_limits->mclk;
3975
3976                 minimum_clocks.engineClock = stable_pstate_sclk;
3977                 minimum_clocks.memoryClock = stable_pstate_mclk;
3978         }
3979
3980         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3981                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3982
3983         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3984                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3985
3986         fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3987
3988         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3989                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3990                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3991                                 "Overdrive sclk exceeds limit",
3992                                 hwmgr->gfx_arbiter.sclk_over_drive =
3993                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3994
3995                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3996                         fiji_ps->performance_levels[1].engine_clock =
3997                                         hwmgr->gfx_arbiter.sclk_over_drive;
3998         }
3999
4000         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4001                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
4002                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4003                                 "Overdrive mclk exceeds limit",
4004                                 hwmgr->gfx_arbiter.mclk_over_drive =
4005                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4006
4007                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4008                         fiji_ps->performance_levels[1].memory_clock =
4009                                         hwmgr->gfx_arbiter.mclk_over_drive;
4010         }
4011
4012         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4013                                     hwmgr->platform_descriptor.platformCaps,
4014                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4015
4016         disable_mclk_switching = (1 < info.display_count) ||
4017                                     disable_mclk_switching_for_frame_lock;
4018
4019         sclk = fiji_ps->performance_levels[0].engine_clock;
4020         mclk = fiji_ps->performance_levels[0].memory_clock;
4021
4022         if (disable_mclk_switching)
4023                 mclk = fiji_ps->performance_levels
4024                 [fiji_ps->performance_level_count - 1].memory_clock;
4025
4026         if (sclk < minimum_clocks.engineClock)
4027                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
4028                                 max_limits->sclk : minimum_clocks.engineClock;
4029
4030         if (mclk < minimum_clocks.memoryClock)
4031                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
4032                                 max_limits->mclk : minimum_clocks.memoryClock;
4033
4034         fiji_ps->performance_levels[0].engine_clock = sclk;
4035         fiji_ps->performance_levels[0].memory_clock = mclk;
4036
4037         fiji_ps->performance_levels[1].engine_clock =
4038                 (fiji_ps->performance_levels[1].engine_clock >=
4039                                 fiji_ps->performance_levels[0].engine_clock) ?
4040                                                 fiji_ps->performance_levels[1].engine_clock :
4041                                                 fiji_ps->performance_levels[0].engine_clock;
4042
4043         if (disable_mclk_switching) {
4044                 if (mclk < fiji_ps->performance_levels[1].memory_clock)
4045                         mclk = fiji_ps->performance_levels[1].memory_clock;
4046
4047                 fiji_ps->performance_levels[0].memory_clock = mclk;
4048                 fiji_ps->performance_levels[1].memory_clock = mclk;
4049         } else {
4050                 if (fiji_ps->performance_levels[1].memory_clock <
4051                                 fiji_ps->performance_levels[0].memory_clock)
4052                         fiji_ps->performance_levels[1].memory_clock =
4053                                         fiji_ps->performance_levels[0].memory_clock;
4054         }
4055
4056         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4057                         PHM_PlatformCaps_StablePState)) {
4058                 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4059                         fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4060                         fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4061                         fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4062                         fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4063                 }
4064         }
4065
4066         return 0;
4067 }
4068
4069 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4070 {
4071         const struct phm_set_power_state_input *states =
4072                         (const struct phm_set_power_state_input *)input;
4073         const struct fiji_power_state *fiji_ps =
4074                         cast_const_phw_fiji_power_state(states->pnew_state);
4075         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4076         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4077         uint32_t sclk = fiji_ps->performance_levels
4078                         [fiji_ps->performance_level_count - 1].engine_clock;
4079         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4080         uint32_t mclk = fiji_ps->performance_levels
4081                         [fiji_ps->performance_level_count - 1].memory_clock;
4082         uint32_t i;
4083         struct cgs_display_info info = {0};
4084
4085         data->need_update_smu7_dpm_table = 0;
4086
4087         for (i = 0; i < sclk_table->count; i++) {
4088                 if (sclk == sclk_table->dpm_levels[i].value)
4089                         break;
4090         }
4091
4092         if (i >= sclk_table->count)
4093                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4094         else {
4095                 if(data->display_timing.min_clock_in_sr !=
4096                         hwmgr->display_config.min_core_set_clock_in_sr)
4097                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4098         }
4099
4100         for (i = 0; i < mclk_table->count; i++) {
4101                 if (mclk == mclk_table->dpm_levels[i].value)
4102                         break;
4103         }
4104
4105         if (i >= mclk_table->count)
4106                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4107
4108         cgs_get_active_displays_info(hwmgr->device, &info);
4109
4110         if (data->display_timing.num_existing_displays != info.display_count)
4111                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4112
4113         return 0;
4114 }
4115
4116 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4117                 const struct fiji_power_state *fiji_ps)
4118 {
4119         uint32_t i;
4120         uint32_t sclk, max_sclk = 0;
4121         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4122         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4123
4124         for (i = 0; i < fiji_ps->performance_level_count; i++) {
4125                 sclk = fiji_ps->performance_levels[i].engine_clock;
4126                 if (max_sclk < sclk)
4127                         max_sclk = sclk;
4128         }
4129
4130         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4131                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4132                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4133                                         dpm_table->pcie_speed_table.dpm_levels
4134                                         [dpm_table->pcie_speed_table.count - 1].value :
4135                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4136         }
4137
4138         return 0;
4139 }
4140
4141 static int fiji_request_link_speed_change_before_state_change(
4142                 struct pp_hwmgr *hwmgr, const void *input)
4143 {
4144         const struct phm_set_power_state_input *states =
4145                         (const struct phm_set_power_state_input *)input;
4146         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4147         const struct fiji_power_state *fiji_nps =
4148                         cast_const_phw_fiji_power_state(states->pnew_state);
4149         const struct fiji_power_state *fiji_cps =
4150                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4151
4152         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4153         uint16_t current_link_speed;
4154
4155         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4156                 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4157         else
4158                 current_link_speed = data->force_pcie_gen;
4159
4160         data->force_pcie_gen = PP_PCIEGenInvalid;
4161         data->pspp_notify_required = false;
4162         if (target_link_speed > current_link_speed) {
4163                 switch(target_link_speed) {
4164                 case PP_PCIEGen3:
4165                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4166                                 break;
4167                         data->force_pcie_gen = PP_PCIEGen2;
4168                         if (current_link_speed == PP_PCIEGen2)
4169                                 break;
4170                 case PP_PCIEGen2:
4171                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4172                                 break;
4173                 default:
4174                         data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4175                         break;
4176                 }
4177         } else {
4178                 if (target_link_speed < current_link_speed)
4179                         data->pspp_notify_required = true;
4180         }
4181
4182         return 0;
4183 }
4184
4185 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4186 {
4187         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4188
4189         if (0 == data->need_update_smu7_dpm_table)
4190                 return 0;
4191
4192         if ((0 == data->sclk_dpm_key_disabled) &&
4193                 (data->need_update_smu7_dpm_table &
4194                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4195                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4196                                 "Trying to freeze SCLK DPM when DPM is disabled",);
4197                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4198                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4199                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4200                                 return -1);
4201         }
4202
4203         if ((0 == data->mclk_dpm_key_disabled) &&
4204                 (data->need_update_smu7_dpm_table &
4205                  DPMTABLE_OD_UPDATE_MCLK)) {
4206                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4207                                 "Trying to freeze MCLK DPM when DPM is disabled",);
4208                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4209                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4210                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4211                                 return -1);
4212         }
4213
4214         return 0;
4215 }
4216
4217 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4218                 struct pp_hwmgr *hwmgr, const void *input)
4219 {
4220         int result = 0;
4221         const struct phm_set_power_state_input *states =
4222                         (const struct phm_set_power_state_input *)input;
4223         const struct fiji_power_state *fiji_ps =
4224                         cast_const_phw_fiji_power_state(states->pnew_state);
4225         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4226         uint32_t sclk = fiji_ps->performance_levels
4227                         [fiji_ps->performance_level_count - 1].engine_clock;
4228         uint32_t mclk = fiji_ps->performance_levels
4229                         [fiji_ps->performance_level_count - 1].memory_clock;
4230         struct fiji_dpm_table *dpm_table = &data->dpm_table;
4231
4232         struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4233         uint32_t dpm_count, clock_percent;
4234         uint32_t i;
4235
4236         if (0 == data->need_update_smu7_dpm_table)
4237                 return 0;
4238
4239         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4240                 dpm_table->sclk_table.dpm_levels
4241                 [dpm_table->sclk_table.count - 1].value = sclk;
4242
4243                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4244                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4245                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4246                                         PHM_PlatformCaps_OD6PlusinDCSupport)) {
4247                 /* Need to do calculation based on the golden DPM table
4248                  * as the Heatmap GPU Clock axis is also based on the default values
4249                  */
4250                         PP_ASSERT_WITH_CODE(
4251                                 (golden_dpm_table->sclk_table.dpm_levels
4252                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4253                                 "Divide by 0!",
4254                                 return -1);
4255                         dpm_count = dpm_table->sclk_table.count < 2 ?
4256                                         0 : dpm_table->sclk_table.count - 2;
4257                         for (i = dpm_count; i > 1; i--) {
4258                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4259                                                 [golden_dpm_table->sclk_table.count-1].value) {
4260                                         clock_percent =
4261                                                 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4262                                                         [golden_dpm_table->sclk_table.count-1].value) * 100) /
4263                                                 golden_dpm_table->sclk_table.dpm_levels
4264                                                         [golden_dpm_table->sclk_table.count-1].value;
4265
4266                                         dpm_table->sclk_table.dpm_levels[i].value =
4267                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4268                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4269                                                                 clock_percent)/100;
4270
4271                                 } else if (golden_dpm_table->sclk_table.dpm_levels
4272                                                 [dpm_table->sclk_table.count-1].value > sclk) {
4273                                         clock_percent =
4274                                                 ((golden_dpm_table->sclk_table.dpm_levels
4275                                                 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4276                                                                 100) /
4277                                                 golden_dpm_table->sclk_table.dpm_levels
4278                                                         [golden_dpm_table->sclk_table.count-1].value;
4279
4280                                         dpm_table->sclk_table.dpm_levels[i].value =
4281                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4282                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4283                                                                         clock_percent) / 100;
4284                                 } else
4285                                         dpm_table->sclk_table.dpm_levels[i].value =
4286                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4287                         }
4288                 }
4289         }
4290
4291         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4292                 dpm_table->mclk_table.dpm_levels
4293                         [dpm_table->mclk_table.count - 1].value = mclk;
4294                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4295                                 PHM_PlatformCaps_OD6PlusinACSupport) ||
4296                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4297                                 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4298
4299                         PP_ASSERT_WITH_CODE(
4300                                         (golden_dpm_table->mclk_table.dpm_levels
4301                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4302                                         "Divide by 0!",
4303                                         return -1);
4304                         dpm_count = dpm_table->mclk_table.count < 2 ?
4305                                         0 : dpm_table->mclk_table.count - 2;
4306                         for (i = dpm_count; i > 1; i--) {
4307                                 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4308                                                 [golden_dpm_table->mclk_table.count-1].value) {
4309                                         clock_percent = ((mclk -
4310                                                         golden_dpm_table->mclk_table.dpm_levels
4311                                                         [golden_dpm_table->mclk_table.count-1].value) * 100) /
4312                                                         golden_dpm_table->mclk_table.dpm_levels
4313                                                         [golden_dpm_table->mclk_table.count-1].value;
4314
4315                                         dpm_table->mclk_table.dpm_levels[i].value =
4316                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4317                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4318                                                                         clock_percent) / 100;
4319
4320                                 } else if (golden_dpm_table->mclk_table.dpm_levels
4321                                                 [dpm_table->mclk_table.count-1].value > mclk) {
4322                                         clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4323                                                         [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4324                                                                         golden_dpm_table->mclk_table.dpm_levels
4325                                                                         [golden_dpm_table->mclk_table.count-1].value;
4326
4327                                         dpm_table->mclk_table.dpm_levels[i].value =
4328                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4329                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4330                                                                         clock_percent) / 100;
4331                                 } else
4332                                         dpm_table->mclk_table.dpm_levels[i].value =
4333                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4334                         }
4335                 }
4336         }
4337
4338         if (data->need_update_smu7_dpm_table &
4339                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4340                 result = fiji_populate_all_memory_levels(hwmgr);
4341                 PP_ASSERT_WITH_CODE((0 == result),
4342                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4343                                 return result);
4344         }
4345
4346         if (data->need_update_smu7_dpm_table &
4347                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4348                 /*populate MCLK dpm table to SMU7 */
4349                 result = fiji_populate_all_memory_levels(hwmgr);
4350                 PP_ASSERT_WITH_CODE((0 == result),
4351                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4352                                 return result);
4353         }
4354
4355         return result;
4356 }
4357
4358 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4359                           struct fiji_single_dpm_table * dpm_table,
4360                              uint32_t low_limit, uint32_t high_limit)
4361 {
4362         uint32_t i;
4363
4364         for (i = 0; i < dpm_table->count; i++) {
4365                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4366                     (dpm_table->dpm_levels[i].value > high_limit))
4367                         dpm_table->dpm_levels[i].enabled = false;
4368                 else
4369                         dpm_table->dpm_levels[i].enabled = true;
4370         }
4371         return 0;
4372 }
4373
4374 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4375                 const struct fiji_power_state *fiji_ps)
4376 {
4377         int result = 0;
4378         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4379         uint32_t high_limit_count;
4380
4381         PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4382                         "power state did not have any performance level",
4383                         return -1);
4384
4385         high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4386
4387         fiji_trim_single_dpm_states(hwmgr,
4388                         &(data->dpm_table.sclk_table),
4389                         fiji_ps->performance_levels[0].engine_clock,
4390                         fiji_ps->performance_levels[high_limit_count].engine_clock);
4391
4392         fiji_trim_single_dpm_states(hwmgr,
4393                         &(data->dpm_table.mclk_table),
4394                         fiji_ps->performance_levels[0].memory_clock,
4395                         fiji_ps->performance_levels[high_limit_count].memory_clock);
4396
4397         return result;
4398 }
4399
4400 static int fiji_generate_dpm_level_enable_mask(
4401                 struct pp_hwmgr *hwmgr, const void *input)
4402 {
4403         int result;
4404         const struct phm_set_power_state_input *states =
4405                         (const struct phm_set_power_state_input *)input;
4406         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4407         const struct fiji_power_state *fiji_ps =
4408                         cast_const_phw_fiji_power_state(states->pnew_state);
4409
4410         result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4411         if (result)
4412                 return result;
4413
4414         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4415                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4416         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4417                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4418         data->last_mclk_dpm_enable_mask =
4419                         data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4420
4421         if (data->uvd_enabled) {
4422                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4423                         data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4424         }
4425
4426         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4427                         fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4428
4429         return 0;
4430 }
4431
4432 int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4433 {
4434         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4435                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
4436                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
4437 }
4438
4439 int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4440 {
4441         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4442                         PPSMC_MSG_VCEDPM_Enable :
4443                         PPSMC_MSG_VCEDPM_Disable);
4444 }
4445
4446 int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4447 {
4448         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4449                         PPSMC_MSG_SAMUDPM_Enable :
4450                         PPSMC_MSG_SAMUDPM_Disable);
4451 }
4452
4453 int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
4454 {
4455         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4456                         PPSMC_MSG_ACPDPM_Enable :
4457                         PPSMC_MSG_ACPDPM_Disable);
4458 }
4459
4460 int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4461 {
4462         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4463         uint32_t mm_boot_level_offset, mm_boot_level_value;
4464         struct phm_ppt_v1_information *table_info =
4465                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4466
4467         if (!bgate) {
4468                 data->smc_state_table.UvdBootLevel = 0;
4469                 if (table_info->mm_dep_table->count > 0)
4470                         data->smc_state_table.UvdBootLevel =
4471                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4472                 mm_boot_level_offset = data->dpm_table_start +
4473                                 offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
4474                 mm_boot_level_offset /= 4;
4475                 mm_boot_level_offset *= 4;
4476                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4477                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4478                 mm_boot_level_value &= 0x00FFFFFF;
4479                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4480                 cgs_write_ind_register(hwmgr->device,
4481                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4482
4483                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4484                                 PHM_PlatformCaps_UVDDPM) ||
4485                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4486                                 PHM_PlatformCaps_StablePState))
4487                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4488                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4489                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4490         }
4491
4492         return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
4493 }
4494
4495 int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4496 {
4497         const struct phm_set_power_state_input *states =
4498                         (const struct phm_set_power_state_input *)input;
4499         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4500         const struct fiji_power_state *fiji_nps =
4501                         cast_const_phw_fiji_power_state(states->pnew_state);
4502         const struct fiji_power_state *fiji_cps =
4503                         cast_const_phw_fiji_power_state(states->pcurrent_state);
4504
4505         uint32_t mm_boot_level_offset, mm_boot_level_value;
4506         struct phm_ppt_v1_information *table_info =
4507                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4508
4509         if (fiji_nps->vce_clks.evclk >0 &&
4510         (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4511                 data->smc_state_table.VceBootLevel =
4512                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4513
4514                 mm_boot_level_offset = data->dpm_table_start +
4515                                 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4516                 mm_boot_level_offset /= 4;
4517                 mm_boot_level_offset *= 4;
4518                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4519                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4520                 mm_boot_level_value &= 0xFF00FFFF;
4521                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4522                 cgs_write_ind_register(hwmgr->device,
4523                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4524
4525                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4526                                 PHM_PlatformCaps_StablePState)) {
4527                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4528                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4529                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4530
4531                         fiji_enable_disable_vce_dpm(hwmgr, true);
4532                 } else if (fiji_nps->vce_clks.evclk == 0 &&
4533                                 fiji_cps != NULL &&
4534                                 fiji_cps->vce_clks.evclk > 0)
4535                         fiji_enable_disable_vce_dpm(hwmgr, false);
4536         }
4537
4538         return 0;
4539 }
4540
4541 int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4542 {
4543         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4544         uint32_t mm_boot_level_offset, mm_boot_level_value;
4545         struct phm_ppt_v1_information *table_info =
4546                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4547
4548         if (!bgate) {
4549                 data->smc_state_table.SamuBootLevel =
4550                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4551                 mm_boot_level_offset = data->dpm_table_start +
4552                                 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
4553                 mm_boot_level_offset /= 4;
4554                 mm_boot_level_offset *= 4;
4555                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4556                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4557                 mm_boot_level_value &= 0xFFFFFF00;
4558                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4559                 cgs_write_ind_register(hwmgr->device,
4560                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4561
4562                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4563                                 PHM_PlatformCaps_StablePState))
4564                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4565                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4566                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4567         }
4568
4569         return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
4570 }
4571
4572 int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4573 {
4574         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4575         uint32_t mm_boot_level_offset, mm_boot_level_value;
4576         struct phm_ppt_v1_information *table_info =
4577                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4578
4579         if (!bgate) {
4580                 data->smc_state_table.AcpBootLevel =
4581                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4582                 mm_boot_level_offset = data->dpm_table_start +
4583                                 offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
4584                 mm_boot_level_offset /= 4;
4585                 mm_boot_level_offset *= 4;
4586                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4587                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4588                 mm_boot_level_value &= 0xFFFF00FF;
4589                 mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
4590                 cgs_write_ind_register(hwmgr->device,
4591                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4592
4593                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4594                                 PHM_PlatformCaps_StablePState))
4595                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4596                                                 PPSMC_MSG_ACPDPM_SetEnabledMask,
4597                                                 (uint32_t)(1 << data->smc_state_table.AcpBootLevel));
4598         }
4599
4600         return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
4601 }
4602
4603 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4604 {
4605         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4606
4607         int result = 0;
4608         uint32_t low_sclk_interrupt_threshold = 0;
4609
4610         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4611                         PHM_PlatformCaps_SclkThrottleLowNotification)
4612                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4613                                 data->low_sclk_interrupt_threshold)) {
4614                 data->low_sclk_interrupt_threshold =
4615                                 hwmgr->gfx_arbiter.sclk_threshold;
4616                 low_sclk_interrupt_threshold =
4617                                 data->low_sclk_interrupt_threshold;
4618
4619                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4620
4621                 result = fiji_copy_bytes_to_smc(
4622                                 hwmgr->smumgr,
4623                                 data->dpm_table_start +
4624                                 offsetof(SMU73_Discrete_DpmTable,
4625                                         LowSclkInterruptThreshold),
4626                                 (uint8_t *)&low_sclk_interrupt_threshold,
4627                                 sizeof(uint32_t),
4628                                 data->sram_end);
4629         }
4630
4631         return result;
4632 }
4633
4634 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4635 {
4636         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4637
4638         if (data->need_update_smu7_dpm_table &
4639                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4640                 return fiji_program_memory_timing_parameters(hwmgr);
4641
4642         return 0;
4643 }
4644
4645 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4646 {
4647         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4648
4649         if (0 == data->need_update_smu7_dpm_table)
4650                 return 0;
4651
4652         if ((0 == data->sclk_dpm_key_disabled) &&
4653                 (data->need_update_smu7_dpm_table &
4654                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4655
4656                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4657                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4658                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4659                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4660                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4661                         return -1);
4662         }
4663
4664         if ((0 == data->mclk_dpm_key_disabled) &&
4665                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4666
4667                 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4668                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4669                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4670                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4671                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4672                     return -1);
4673         }
4674
4675         data->need_update_smu7_dpm_table = 0;
4676
4677         return 0;
4678 }
4679
4680 /* Look up the voltaged based on DAL's requested level.
4681  * and then send the requested VDDC voltage to SMC
4682  */
4683 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4684 {
4685         return;
4686 }
4687
4688 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4689 {
4690         int result;
4691         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4692
4693         /* Apply minimum voltage based on DAL's request level */
4694         fiji_apply_dal_minimum_voltage_request(hwmgr);
4695
4696         if (0 == data->sclk_dpm_key_disabled) {
4697                 /* Checking if DPM is running.  If we discover hang because of this,
4698                  *  we should skip this message.
4699                  */
4700                 if (!fiji_is_dpm_running(hwmgr))
4701                         printk(KERN_ERR "[ powerplay ] "
4702                                         "Trying to set Enable Mask when DPM is disabled \n");
4703
4704                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4705                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4706                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4707                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4708                         PP_ASSERT_WITH_CODE((0 == result),
4709                                 "Set Sclk Dpm enable Mask failed", return -1);
4710                 }
4711         }
4712
4713         if (0 == data->mclk_dpm_key_disabled) {
4714                 /* Checking if DPM is running.  If we discover hang because of this,
4715                  *  we should skip this message.
4716                  */
4717                 if (!fiji_is_dpm_running(hwmgr))
4718                         printk(KERN_ERR "[ powerplay ]"
4719                                         " Trying to set Enable Mask when DPM is disabled \n");
4720
4721                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4722                         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4723                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4724                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4725                         PP_ASSERT_WITH_CODE((0 == result),
4726                                 "Set Mclk Dpm enable Mask failed", return -1);
4727                 }
4728         }
4729
4730         return 0;
4731 }
4732
4733 static int fiji_notify_link_speed_change_after_state_change(
4734                 struct pp_hwmgr *hwmgr, const void *input)
4735 {
4736         const struct phm_set_power_state_input *states =
4737                         (const struct phm_set_power_state_input *)input;
4738         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4739         const struct fiji_power_state *fiji_ps =
4740                         cast_const_phw_fiji_power_state(states->pnew_state);
4741         uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4742         uint8_t  request;
4743
4744         if (data->pspp_notify_required) {
4745                 if (target_link_speed == PP_PCIEGen3)
4746                         request = PCIE_PERF_REQ_GEN3;
4747                 else if (target_link_speed == PP_PCIEGen2)
4748                         request = PCIE_PERF_REQ_GEN2;
4749                 else
4750                         request = PCIE_PERF_REQ_GEN1;
4751
4752                 if(request == PCIE_PERF_REQ_GEN1 &&
4753                                 fiji_get_current_pcie_speed(hwmgr) > 0)
4754                         return 0;
4755
4756                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4757                         if (PP_PCIEGen2 == target_link_speed)
4758                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4759                         else
4760                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4761                 }
4762         }
4763
4764         return 0;
4765 }
4766
4767 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4768                 const void *input)
4769 {
4770         int tmp_result, result = 0;
4771
4772         tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4773         PP_ASSERT_WITH_CODE((0 == tmp_result),
4774                         "Failed to find DPM states clocks in DPM table!",
4775                         result = tmp_result);
4776
4777         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4778                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4779                 tmp_result =
4780                         fiji_request_link_speed_change_before_state_change(hwmgr, input);
4781                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4782                                 "Failed to request link speed change before state change!",
4783                                 result = tmp_result);
4784         }
4785
4786         tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4787         PP_ASSERT_WITH_CODE((0 == tmp_result),
4788                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4789
4790         tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4791         PP_ASSERT_WITH_CODE((0 == tmp_result),
4792                         "Failed to populate and upload SCLK MCLK DPM levels!",
4793                         result = tmp_result);
4794
4795         tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4796         PP_ASSERT_WITH_CODE((0 == tmp_result),
4797                         "Failed to generate DPM level enabled mask!",
4798                         result = tmp_result);
4799
4800         tmp_result = fiji_update_vce_dpm(hwmgr, input);
4801         PP_ASSERT_WITH_CODE((0 == tmp_result),
4802                         "Failed to update VCE DPM!",
4803                         result = tmp_result);
4804
4805         tmp_result = fiji_update_sclk_threshold(hwmgr);
4806         PP_ASSERT_WITH_CODE((0 == tmp_result),
4807                         "Failed to update SCLK threshold!",
4808                         result = tmp_result);
4809
4810         tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4811         PP_ASSERT_WITH_CODE((0 == tmp_result),
4812                         "Failed to program memory timing parameters!",
4813                         result = tmp_result);
4814
4815         tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4816         PP_ASSERT_WITH_CODE((0 == tmp_result),
4817                         "Failed to unfreeze SCLK MCLK DPM!",
4818                         result = tmp_result);
4819
4820         tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4821         PP_ASSERT_WITH_CODE((0 == tmp_result),
4822                         "Failed to upload DPM level enabled mask!",
4823                         result = tmp_result);
4824
4825         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4826                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4827                 tmp_result =
4828                         fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4829                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4830                                 "Failed to notify link speed change after state change!",
4831                                 result = tmp_result);
4832         }
4833
4834         return result;
4835 }
4836
4837 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4838 {
4839         struct pp_power_state  *ps;
4840         struct fiji_power_state  *fiji_ps;
4841
4842         if (hwmgr == NULL)
4843                 return -EINVAL;
4844
4845         ps = hwmgr->request_ps;
4846
4847         if (ps == NULL)
4848                 return -EINVAL;
4849
4850         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4851
4852         if (low)
4853                 return fiji_ps->performance_levels[0].engine_clock;
4854         else
4855                 return fiji_ps->performance_levels
4856                                 [fiji_ps->performance_level_count-1].engine_clock;
4857 }
4858
4859 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4860 {
4861         struct pp_power_state  *ps;
4862         struct fiji_power_state  *fiji_ps;
4863
4864         if (hwmgr == NULL)
4865                 return -EINVAL;
4866
4867         ps = hwmgr->request_ps;
4868
4869         if (ps == NULL)
4870                 return -EINVAL;
4871
4872         fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4873
4874         if (low)
4875                 return fiji_ps->performance_levels[0].memory_clock;
4876         else
4877                 return fiji_ps->performance_levels
4878                                 [fiji_ps->performance_level_count-1].memory_clock;
4879 }
4880
4881 static void fiji_print_current_perforce_level(
4882                 struct pp_hwmgr *hwmgr, struct seq_file *m)
4883 {
4884         uint32_t sclk, mclk, activity_percent = 0;
4885         uint32_t offset;
4886         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4887
4888         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4889
4890         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4891
4892         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4893
4894         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4895         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
4896                         mclk / 100, sclk / 100);
4897
4898         offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
4899         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4900         activity_percent += 0x80;
4901         activity_percent >>= 8;
4902
4903         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4904
4905         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
4906
4907         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
4908 }
4909
4910 static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
4911 {
4912         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4913         uint32_t num_active_displays = 0;
4914         uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4915                         CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4916         uint32_t display_gap2;
4917         uint32_t pre_vbi_time_in_us;
4918         uint32_t frame_time_in_us;
4919         uint32_t ref_clock;
4920         uint32_t refresh_rate = 0;
4921         struct cgs_display_info info = {0};
4922         struct cgs_mode_info mode_info;
4923
4924         info.mode_info = &mode_info;
4925
4926         cgs_get_active_displays_info(hwmgr->device, &info);
4927         num_active_displays = info.display_count;
4928
4929         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
4930                         DISP_GAP, (num_active_displays > 0)?
4931                         DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4932         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4933                         ixCG_DISPLAY_GAP_CNTL, display_gap);
4934
4935         ref_clock = mode_info.ref_clock;
4936         refresh_rate = mode_info.refresh_rate;
4937
4938         if (refresh_rate == 0)
4939                 refresh_rate = 60;
4940
4941         frame_time_in_us = 1000000 / refresh_rate;
4942
4943         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4944         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4945
4946         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4947                         ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4948
4949         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4950                         data->soft_regs_start +
4951                         offsetof(SMU73_SoftRegisters, PreVBlankGap), 0x64);
4952
4953         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4954                         data->soft_regs_start +
4955                         offsetof(SMU73_SoftRegisters, VBlankTimeout),
4956                         (frame_time_in_us - pre_vbi_time_in_us));
4957
4958         if (num_active_displays == 1)
4959                 tonga_notify_smc_display_change(hwmgr, true);
4960
4961         return 0;
4962 }
4963
4964 int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4965 {
4966         return fiji_program_display_gap(hwmgr);
4967 }
4968
4969 static int fiji_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr,
4970                 uint16_t us_max_fan_pwm)
4971 {
4972         hwmgr->thermal_controller.
4973         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4974
4975         if (phm_is_hw_access_blocked(hwmgr))
4976                 return 0;
4977
4978         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4979                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4980 }
4981
4982 static int fiji_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr,
4983                 uint16_t us_max_fan_rpm)
4984 {
4985         hwmgr->thermal_controller.
4986         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4987
4988         if (phm_is_hw_access_blocked(hwmgr))
4989                 return 0;
4990
4991         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4992                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4993 }
4994
4995 int fiji_dpm_set_interrupt_state(void *private_data,
4996                                          unsigned src_id, unsigned type,
4997                                          int enabled)
4998 {
4999         uint32_t cg_thermal_int;
5000         struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5001
5002         if (hwmgr == NULL)
5003                 return -EINVAL;
5004
5005         switch (type) {
5006         case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5007                 if (enabled) {
5008                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5009                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5010                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5011                         cgs_write_ind_register(hwmgr->device,
5012                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5013                 } else {
5014                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5015                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5016                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5017                         cgs_write_ind_register(hwmgr->device,
5018                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5019                 }
5020                 break;
5021
5022         case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5023                 if (enabled) {
5024                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5025                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5026                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5027                         cgs_write_ind_register(hwmgr->device,
5028                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5029                 } else {
5030                         cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5031                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5032                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5033                         cgs_write_ind_register(hwmgr->device,
5034                                         CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5035                 }
5036                 break;
5037         default:
5038                 break;
5039         }
5040         return 0;
5041 }
5042
5043 int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5044                                         const void *thermal_interrupt_info)
5045 {
5046         int result;
5047         const struct pp_interrupt_registration_info *info =
5048                         (const struct pp_interrupt_registration_info *)
5049                         thermal_interrupt_info;
5050
5051         if (info == NULL)
5052                 return -EINVAL;
5053
5054         result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5055                                 fiji_dpm_set_interrupt_state,
5056                                 info->call_back, info->context);
5057
5058         if (result)
5059                 return -EINVAL;
5060
5061         result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5062                                 fiji_dpm_set_interrupt_state,
5063                                 info->call_back, info->context);
5064
5065         if (result)
5066                 return -EINVAL;
5067
5068         return 0;
5069 }
5070
5071 static int fiji_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5072 {
5073         if (mode) {
5074                 /* stop auto-manage */
5075                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5076                                 PHM_PlatformCaps_MicrocodeFanControl))
5077                         fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
5078                 fiji_fan_ctrl_set_static_mode(hwmgr, mode);
5079         } else
5080                 /* restart auto-manage */
5081                 fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5082
5083         return 0;
5084 }
5085
5086 static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5087 {
5088         if (hwmgr->fan_ctrl_is_in_default_mode)
5089                 return hwmgr->fan_ctrl_default_mode;
5090         else
5091                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5092                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5093 }
5094
5095 static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
5096 {
5097         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5098
5099         *table = (char *)&data->smc_state_table;
5100
5101         return sizeof(struct SMU73_Discrete_DpmTable);
5102 }
5103
5104 static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
5105 {
5106         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5107
5108         void *table = (void *)&data->smc_state_table;
5109
5110         memcpy(table, buf, size);
5111
5112         return 0;
5113 }
5114
5115 static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
5116                 enum pp_clock_type type, int level)
5117 {
5118         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5119
5120         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5121                 return -EINVAL;
5122
5123         switch (type) {
5124         case PP_SCLK:
5125                 if (!data->sclk_dpm_key_disabled)
5126                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5127                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
5128                                         (1 << level));
5129                 break;
5130         case PP_MCLK:
5131                 if (!data->mclk_dpm_key_disabled)
5132                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5133                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
5134                                         (1 << level));
5135                 break;
5136         case PP_PCIE:
5137                 if (!data->pcie_dpm_key_disabled)
5138                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5139                                         PPSMC_MSG_PCIeDPM_ForceLevel,
5140                                         (1 << level));
5141                 break;
5142         default:
5143                 break;
5144         }
5145
5146         return 0;
5147 }
5148
5149 static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5150                 enum pp_clock_type type, char *buf)
5151 {
5152         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5153         struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5154         struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5155         struct fiji_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5156         int i, now, size = 0;
5157         uint32_t clock, pcie_speed;
5158
5159         switch (type) {
5160         case PP_SCLK:
5161                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5162                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5163
5164                 for (i = 0; i < sclk_table->count; i++) {
5165                         if (clock > sclk_table->dpm_levels[i].value)
5166                                 continue;
5167                         break;
5168                 }
5169                 now = i;
5170
5171                 for (i = 0; i < sclk_table->count; i++)
5172                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5173                                         i, sclk_table->dpm_levels[i].value / 100,
5174                                         (i == now) ? "*" : "");
5175                 break;
5176         case PP_MCLK:
5177                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5178                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5179
5180                 for (i = 0; i < mclk_table->count; i++) {
5181                         if (clock > mclk_table->dpm_levels[i].value)
5182                                 continue;
5183                         break;
5184                 }
5185                 now = i;
5186
5187                 for (i = 0; i < mclk_table->count; i++)
5188                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5189                                         i, mclk_table->dpm_levels[i].value / 100,
5190                                         (i == now) ? "*" : "");
5191                 break;
5192         case PP_PCIE:
5193                 pcie_speed = fiji_get_current_pcie_speed(hwmgr);
5194                 for (i = 0; i < pcie_table->count; i++) {
5195                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5196                                 continue;
5197                         break;
5198                 }
5199                 now = i;
5200
5201                 for (i = 0; i < pcie_table->count; i++)
5202                         size += sprintf(buf + size, "%d: %s %s\n", i,
5203                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
5204                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5205                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5206                                         (i == now) ? "*" : "");
5207                 break;
5208         default:
5209                 break;
5210         }
5211         return size;
5212 }
5213
5214 static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5215                                                            const struct fiji_performance_level *pl2)
5216 {
5217         return ((pl1->memory_clock == pl2->memory_clock) &&
5218                   (pl1->engine_clock == pl2->engine_clock) &&
5219                   (pl1->pcie_gen == pl2->pcie_gen) &&
5220                   (pl1->pcie_lane == pl2->pcie_lane));
5221 }
5222
5223 int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5224 {
5225         const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5226         const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5227         int i;
5228
5229         if (equal == NULL || psa == NULL || psb == NULL)
5230                 return -EINVAL;
5231
5232         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5233         if (psa->performance_level_count != psb->performance_level_count) {
5234                 *equal = false;
5235                 return 0;
5236         }
5237
5238         for (i = 0; i < psa->performance_level_count; i++) {
5239                 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5240                         /* If we have found even one performance level pair that is different the states are different. */
5241                         *equal = false;
5242                         return 0;
5243                 }
5244         }
5245
5246         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5247         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5248         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5249         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5250         *equal &= (psa->acp_clk == psb->acp_clk);
5251
5252         return 0;
5253 }
5254
5255 bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5256 {
5257         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5258         bool is_update_required = false;
5259         struct cgs_display_info info = {0,0,NULL};
5260
5261         cgs_get_active_displays_info(hwmgr->device, &info);
5262
5263         if (data->display_timing.num_existing_displays != info.display_count)
5264                 is_update_required = true;
5265
5266         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5267                 if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr)
5268                         is_update_required = true;
5269         }
5270
5271         return is_update_required;
5272 }
5273
5274
5275 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5276         .backend_init = &fiji_hwmgr_backend_init,
5277         .backend_fini = &tonga_hwmgr_backend_fini,
5278         .asic_setup = &fiji_setup_asic_task,
5279         .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
5280         .force_dpm_level = &fiji_dpm_force_dpm_level,
5281         .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
5282         .get_power_state_size = &fiji_get_power_state_size,
5283         .get_pp_table_entry = &fiji_get_pp_table_entry,
5284         .patch_boot_state = &fiji_patch_boot_state,
5285         .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
5286         .power_state_set = &fiji_set_power_state_tasks,
5287         .get_sclk = &fiji_dpm_get_sclk,
5288         .get_mclk = &fiji_dpm_get_mclk,
5289         .print_current_perforce_level = &fiji_print_current_perforce_level,
5290         .powergate_uvd = &fiji_phm_powergate_uvd,
5291         .powergate_vce = &fiji_phm_powergate_vce,
5292         .disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
5293         .notify_smc_display_config_after_ps_adjustment =
5294                         &tonga_notify_smc_display_config_after_ps_adjustment,
5295         .display_config_changed = &fiji_display_configuration_changed_task,
5296         .set_max_fan_pwm_output = fiji_set_max_fan_pwm_output,
5297         .set_max_fan_rpm_output = fiji_set_max_fan_rpm_output,
5298         .get_temperature = fiji_thermal_get_temperature,
5299         .stop_thermal_controller = fiji_thermal_stop_thermal_controller,
5300         .get_fan_speed_info = fiji_fan_ctrl_get_fan_speed_info,
5301         .get_fan_speed_percent = fiji_fan_ctrl_get_fan_speed_percent,
5302         .set_fan_speed_percent = fiji_fan_ctrl_set_fan_speed_percent,
5303         .reset_fan_speed_to_default = fiji_fan_ctrl_reset_fan_speed_to_default,
5304         .get_fan_speed_rpm = fiji_fan_ctrl_get_fan_speed_rpm,
5305         .set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
5306         .uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
5307         .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5308         .set_fan_control_mode = fiji_set_fan_control_mode,
5309         .get_fan_control_mode = fiji_get_fan_control_mode,
5310         .check_states_equal = fiji_check_states_equal,
5311         .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5312         .get_pp_table = fiji_get_pp_table,
5313         .set_pp_table = fiji_set_pp_table,
5314         .force_clock_level = fiji_force_clock_level,
5315         .print_clock_levels = fiji_print_clock_levels,
5316 };
5317
5318 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
5319 {
5320         struct fiji_hwmgr  *data;
5321         int ret = 0;
5322
5323         data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
5324         if (data == NULL)
5325                 return -ENOMEM;
5326
5327         hwmgr->backend = data;
5328         hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
5329         hwmgr->pptable_func = &tonga_pptable_funcs;
5330         pp_fiji_thermal_initialize(hwmgr);
5331         return ret;
5332 }