drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <drm/amdgpu_drm.h>
  27 #include "pp_instance.h"
  28 #include "smumgr.h"
  29 #include "cgs_common.h"
  30 #include "linux/delay.h"
  31 #include "cz_smumgr.h"
  32 #include "tonga_smumgr.h"
  33 #include "fiji_smumgr.h"
  34 #include "polaris10_smumgr.h"
  35
  36 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  37 {
  38         struct pp_smumgr *smumgr;
  39
  40         if ((handle == NULL) || (pp_init == NULL))
  41                 return -EINVAL;
  42
  43         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  44         if (smumgr == NULL)
  45                 return -ENOMEM;
  46
  47         smumgr->device = pp_init->device;
  48         smumgr->chip_family = pp_init->chip_family;
  49         smumgr->chip_id = pp_init->chip_id;
  50         smumgr->hw_revision = pp_init->rev_id;
  51         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  52         smumgr->reload_fw = 1;
  53         handle->smu_mgr = smumgr;
  54
  55         switch (smumgr->chip_family) {
  56         case AMDGPU_FAMILY_CZ:
  57                 cz_smum_init(smumgr);
  58                 break;
  59         case AMDGPU_FAMILY_VI:
  60                 switch (smumgr->chip_id) {
  61                 case CHIP_TONGA:
  62                         tonga_smum_init(smumgr);
  63                         break;
  64                 case CHIP_FIJI:
  65                         fiji_smum_init(smumgr);
  66                         break;
  67                 case CHIP_POLARIS11:
  68                 case CHIP_POLARIS10:
  69                         polaris10_smum_init(smumgr);
  70                         break;
  71                 default:
  72                         return -EINVAL;
  73                 }
  74                 break;
  75         default:
  76                 kfree(smumgr);
  77                 return -EINVAL;
  78         }
  79
  80         return 0;
  81 }
  82
  83 int smum_fini(struct pp_smumgr *smumgr)
  84 {
  85         kfree(smumgr->device);
  86         kfree(smumgr);
  87         return 0;
  88 }
  89
  90 int smum_get_argument(struct pp_smumgr *smumgr)
  91 {
  92         if (NULL != smumgr->smumgr_funcs->get_argument)
  93                 return smumgr->smumgr_funcs->get_argument(smumgr);
  94
  95         return 0;
  96 }
  97
  98 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
  99                                                                 void **table)
 100 {
 101         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
 102                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
 103                                                                         table);
 104
 105         return 0;
 106 }
 107
 108 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
 109 {
 110         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
 111                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
 112
 113         return 0;
 114 }
 115
 116 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 117 {
 118         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 119                 return -EINVAL;
 120
 121         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 122 }
 123
 124 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 125                                         uint16_t msg, uint32_t parameter)
 126 {
 127         if (smumgr == NULL ||
 128                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 129                 return -EINVAL;
 130         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 131                                                 smumgr, msg, parameter);
 132 }
 133
 134 /*
 135  * Returns once the part of the register indicated by the mask has
 136  * reached the given value.
 137  */
 138 int smum_wait_on_register(struct pp_smumgr *smumgr,
 139                                 uint32_t index,
 140                                 uint32_t value, uint32_t mask)
 141 {
 142         uint32_t i;
 143         uint32_t cur_value;
 144
 145         if (smumgr == NULL || smumgr->device == NULL)
 146                 return -EINVAL;
 147
 148         for (i = 0; i < smumgr->usec_timeout; i++) {
 149                 cur_value = cgs_read_register(smumgr->device, index);
 150                 if ((cur_value & mask) == (value & mask))
 151                         break;
 152                 udelay(1);
 153         }
 154
 155         /* timeout means wrong logic*/
 156         if (i == smumgr->usec_timeout)
 157                 return -1;
 158
 159         return 0;
 160 }
 161
 162 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 163                                         uint32_t index,
 164                                         uint32_t value, uint32_t mask)
 165 {
 166         uint32_t i;
 167         uint32_t cur_value;
 168
 169         if (smumgr == NULL)
 170                 return -EINVAL;
 171
 172         for (i = 0; i < smumgr->usec_timeout; i++) {
 173                 cur_value = cgs_read_register(smumgr->device,
 174                                                                         index);
 175                 if ((cur_value & mask) != (value & mask))
 176                         break;
 177                 udelay(1);
 178         }
 179
 180         /* timeout means wrong logic */
 181         if (i == smumgr->usec_timeout)
 182                 return -1;
 183
 184         return 0;
 185 }
 186
 187
 188 /*
 189  * Returns once the part of the register indicated by the mask
 190  * has reached the given value.The indirect space is described by
 191  * giving the memory-mapped index of the indirect index register.
 192  */
 193 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 194                                         uint32_t indirect_port,
 195                                         uint32_t index,
 196                                         uint32_t value,
 197                                         uint32_t mask)
 198 {
 199         if (smumgr == NULL || smumgr->device == NULL)
 200                 return -EINVAL;
 201
 202         cgs_write_register(smumgr->device, indirect_port, index);
 203         return smum_wait_on_register(smumgr, indirect_port + 1,
 204                                                 mask, value);
 205 }
 206
 207 void smum_wait_for_indirect_register_unequal(
 208                                                 struct pp_smumgr *smumgr,
 209                                                 uint32_t indirect_port,
 210                                                 uint32_t index,
 211                                                 uint32_t value,
 212                                                 uint32_t mask)
 213 {
 214         if (smumgr == NULL || smumgr->device == NULL)
 215                 return;
 216         cgs_write_register(smumgr->device, indirect_port, index);
 217         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 218                                                 value, mask);
 219 }
 220
 221 int smu_allocate_memory(void *device, uint32_t size,
 222                          enum cgs_gpu_mem_type type,
 223                          uint32_t byte_align, uint64_t *mc_addr,
 224                          void **kptr, void *handle)
 225 {
 226         int ret = 0;
 227         cgs_handle_t cgs_handle;
 228
 229         if (device == NULL || handle == NULL ||
 230             mc_addr == NULL || kptr == NULL)
 231                 return -EINVAL;
 232
 233         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 234                                 0, 0, (cgs_handle_t *)handle);
 235         if (ret)
 236                 return -ENOMEM;
 237
 238         cgs_handle = *(cgs_handle_t *)handle;
 239
 240         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 241         if (ret)
 242                 goto error_gmap;
 243
 244         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 245         if (ret)
 246                 goto error_kmap;
 247
 248         return 0;
 249
 250 error_kmap:
 251         cgs_gunmap_gpu_mem(device, cgs_handle);
 252
 253 error_gmap:
 254         cgs_free_gpu_mem(device, cgs_handle);
 255         return ret;
 256 }
 257
 258 int smu_free_memory(void *device, void *handle)
 259 {
 260         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 261
 262         if (device == NULL || handle == NULL)
 263                 return -EINVAL;
 264
 265         cgs_kunmap_gpu_mem(device, cgs_handle);
 266         cgs_gunmap_gpu_mem(device, cgs_handle);
 267         cgs_free_gpu_mem(device, cgs_handle);
 268
 269         return 0;
 270 }