2 * Analogix DP (Display port) core register interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
18 #include <drm/bridge/analogix_dp.h>
20 #include "analogix_dp_core.h"
21 #include "analogix_dp_reg.h"
23 #define COMMON_INT_MASK_1 0
24 #define COMMON_INT_MASK_2 0
25 #define COMMON_INT_MASK_3 0
26 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
27 #define INT_STA_MASK INT_HPD
29 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
34 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
35 reg |= HDCP_VIDEO_MUTE;
36 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
38 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
39 reg &= ~HDCP_VIDEO_MUTE;
40 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
44 void analogix_dp_stop_video(struct analogix_dp_device *dp)
48 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
50 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
53 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
58 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
59 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
61 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
62 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
64 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
67 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
71 reg = TX_TERMINAL_CTRL_50_OHM;
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
74 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
75 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
77 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
79 if (dp->plat_data->dev_type == RK3288_DP)
82 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
83 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
84 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
85 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
86 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
89 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
90 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
92 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
93 TX_CUR1_2X | TX_CUR_16_MA;
94 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
96 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
97 CH1_AMP_400_MV | CH0_AMP_400_MV;
98 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
101 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
103 /* Set interrupt pin assertion polarity as high */
104 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
106 /* Clear pending regisers */
107 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
108 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
109 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
110 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
111 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
113 /* 0:mask,1: unmask */
114 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
115 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
116 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
117 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
118 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
121 void analogix_dp_reset(struct analogix_dp_device *dp)
125 analogix_dp_stop_video(dp);
126 analogix_dp_enable_video_mute(dp, 0);
128 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
129 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
130 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
131 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
133 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
134 SERDES_FIFO_FUNC_EN_N |
135 LS_CLK_DOMAIN_FUNC_EN_N;
136 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
138 usleep_range(20, 30);
140 analogix_dp_lane_swap(dp, 0);
142 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
143 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
144 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
145 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
147 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
148 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
150 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
151 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
153 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
155 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
157 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
158 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
160 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
161 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
163 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
166 void analogix_dp_swreset(struct analogix_dp_device *dp)
168 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
171 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
175 /* 0: mask, 1: unmask */
176 reg = COMMON_INT_MASK_1;
177 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
179 reg = COMMON_INT_MASK_2;
180 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
182 reg = COMMON_INT_MASK_3;
183 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
185 reg = COMMON_INT_MASK_4;
186 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
189 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
192 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
196 /* 0: mask, 1: unmask */
197 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
198 reg &= ~COMMON_INT_MASK_4;
199 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
201 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
202 reg &= ~INT_STA_MASK;
203 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
206 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
210 /* 0: mask, 1: unmask */
211 reg = COMMON_INT_MASK_4;
212 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
215 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
218 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
222 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
229 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
234 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
236 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
238 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
240 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
244 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
245 enum analog_power_block block,
249 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
251 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
252 phy_pd_addr = ANALOGIX_DP_PD;
257 reg = readl(dp->reg_base + phy_pd_addr);
259 writel(reg, dp->reg_base + phy_pd_addr);
261 reg = readl(dp->reg_base + phy_pd_addr);
263 writel(reg, dp->reg_base + phy_pd_addr);
268 reg = readl(dp->reg_base + phy_pd_addr);
270 writel(reg, dp->reg_base + phy_pd_addr);
272 reg = readl(dp->reg_base + phy_pd_addr);
274 writel(reg, dp->reg_base + phy_pd_addr);
279 reg = readl(dp->reg_base + phy_pd_addr);
281 writel(reg, dp->reg_base + phy_pd_addr);
283 reg = readl(dp->reg_base + phy_pd_addr);
285 writel(reg, dp->reg_base + phy_pd_addr);
290 reg = readl(dp->reg_base + phy_pd_addr);
292 writel(reg, dp->reg_base + phy_pd_addr);
294 reg = readl(dp->reg_base + phy_pd_addr);
296 writel(reg, dp->reg_base + phy_pd_addr);
301 reg = readl(dp->reg_base + phy_pd_addr);
303 writel(reg, dp->reg_base + phy_pd_addr);
305 reg = readl(dp->reg_base + phy_pd_addr);
307 writel(reg, dp->reg_base + phy_pd_addr);
312 reg = readl(dp->reg_base + phy_pd_addr);
314 writel(reg, dp->reg_base + phy_pd_addr);
316 reg = readl(dp->reg_base + phy_pd_addr);
318 writel(reg, dp->reg_base + phy_pd_addr);
323 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
325 writel(reg, dp->reg_base + phy_pd_addr);
327 writel(0x00, dp->reg_base + phy_pd_addr);
335 void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
338 int timeout_loop = 0;
340 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
343 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
345 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
346 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
347 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
350 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
351 analogix_dp_set_pll_power_down(dp, 0);
353 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
355 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
356 dev_err(dp->dev, "failed to get pll lock status\n");
359 usleep_range(10, 20);
363 /* Enable Serdes FIFO function and Link symbol clock domain module */
364 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
365 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
367 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
370 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
374 if (gpio_is_valid(dp->hpd_gpio))
377 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
378 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
381 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
384 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
388 if (gpio_is_valid(dp->hpd_gpio))
391 analogix_dp_clear_hotplug_interrupts(dp);
393 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
394 reg &= ~(F_HPD | HPD_CTRL);
395 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
398 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
402 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
403 reg = (F_HPD | HPD_CTRL);
404 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
407 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
411 if (gpio_is_valid(dp->hpd_gpio)) {
412 reg = gpio_get_value(dp->hpd_gpio);
414 return DP_IRQ_TYPE_HP_CABLE_IN;
416 return DP_IRQ_TYPE_HP_CABLE_OUT;
418 /* Parse hotplug interrupt status register */
419 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
422 return DP_IRQ_TYPE_HP_CABLE_IN;
425 return DP_IRQ_TYPE_HP_CABLE_OUT;
427 if (reg & HOTPLUG_CHG)
428 return DP_IRQ_TYPE_HP_CHANGE;
430 return DP_IRQ_TYPE_UNKNOWN;
434 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
438 /* Disable AUX channel module */
439 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
440 reg |= AUX_FUNC_EN_N;
441 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
444 void analogix_dp_init_aux(struct analogix_dp_device *dp)
448 /* Clear inerrupts related to AUX channel */
449 reg = RPLY_RECEIV | AUX_ERR;
450 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
452 analogix_dp_reset_aux(dp);
454 /* Disable AUX transaction H/W retry */
455 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
456 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
457 AUX_HW_RETRY_COUNT_SEL(3) |
458 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
460 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
461 AUX_HW_RETRY_COUNT_SEL(0) |
462 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
463 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
465 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
466 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
467 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
469 /* Enable AUX channel module */
470 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
471 reg &= ~AUX_FUNC_EN_N;
472 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
475 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
479 if (gpio_is_valid(dp->hpd_gpio)) {
480 if (gpio_get_value(dp->hpd_gpio))
483 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
484 if (reg & HPD_STATUS)
491 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
495 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
496 reg &= ~SW_FUNC_EN_N;
497 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
500 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
504 int timeout_loop = 0;
506 /* Enable AUX CH operation */
507 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
509 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
511 /* Is AUX CH command reply received? */
512 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
513 while (!(reg & RPLY_RECEIV)) {
515 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
516 dev_err(dp->dev, "AUX CH command reply failed!\n");
519 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
520 usleep_range(10, 11);
523 /* Clear interrupt source for AUX CH command reply */
524 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
526 /* Clear interrupt source for AUX CH access error */
527 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
529 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
533 /* Check AUX CH error access status */
534 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
535 if ((reg & AUX_STATUS_MASK) != 0) {
536 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
537 reg & AUX_STATUS_MASK);
544 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
545 unsigned int reg_addr,
552 for (i = 0; i < 3; i++) {
553 /* Clear AUX CH data buffer */
555 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
557 /* Select DPCD device address */
558 reg = AUX_ADDR_7_0(reg_addr);
559 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
560 reg = AUX_ADDR_15_8(reg_addr);
561 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
562 reg = AUX_ADDR_19_16(reg_addr);
563 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
565 /* Write data buffer */
566 reg = (unsigned int)data;
567 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
570 * Set DisplayPort transaction and write 1 byte
571 * If bit 3 is 1, DisplayPort transaction.
572 * If Bit 3 is 0, I2C transaction.
574 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
575 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
577 /* Start AUX transaction */
578 retval = analogix_dp_start_aux_transaction(dp);
582 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
588 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
589 unsigned int reg_addr,
596 for (i = 0; i < 3; i++) {
597 /* Clear AUX CH data buffer */
599 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
601 /* Select DPCD device address */
602 reg = AUX_ADDR_7_0(reg_addr);
603 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
604 reg = AUX_ADDR_15_8(reg_addr);
605 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
606 reg = AUX_ADDR_19_16(reg_addr);
607 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
610 * Set DisplayPort transaction and read 1 byte
611 * If bit 3 is 1, DisplayPort transaction.
612 * If Bit 3 is 0, I2C transaction.
614 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
615 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
617 /* Start AUX transaction */
618 retval = analogix_dp_start_aux_transaction(dp);
622 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
625 /* Read data buffer */
626 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
627 *data = (unsigned char)(reg & 0xff);
632 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
633 unsigned int reg_addr,
635 unsigned char data[])
638 unsigned int start_offset;
639 unsigned int cur_data_count;
640 unsigned int cur_data_idx;
644 /* Clear AUX CH data buffer */
646 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
649 while (start_offset < count) {
650 /* Buffer size of AUX CH is 16 * 4bytes */
651 if ((count - start_offset) > 16)
654 cur_data_count = count - start_offset;
656 for (i = 0; i < 3; i++) {
657 /* Select DPCD device address */
658 reg = AUX_ADDR_7_0(reg_addr + start_offset);
659 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
660 reg = AUX_ADDR_15_8(reg_addr + start_offset);
661 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
662 reg = AUX_ADDR_19_16(reg_addr + start_offset);
663 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
665 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
667 reg = data[start_offset + cur_data_idx];
668 writel(reg, dp->reg_base +
669 ANALOGIX_DP_BUF_DATA_0 +
674 * Set DisplayPort transaction and write
675 * If bit 3 is 1, DisplayPort transaction.
676 * If Bit 3 is 0, I2C transaction.
678 reg = AUX_LENGTH(cur_data_count) |
679 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
680 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
682 /* Start AUX transaction */
683 retval = analogix_dp_start_aux_transaction(dp);
687 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
691 start_offset += cur_data_count;
697 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
698 unsigned int reg_addr,
700 unsigned char data[])
703 unsigned int start_offset;
704 unsigned int cur_data_count;
705 unsigned int cur_data_idx;
709 /* Clear AUX CH data buffer */
711 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
714 while (start_offset < count) {
715 /* Buffer size of AUX CH is 16 * 4bytes */
716 if ((count - start_offset) > 16)
719 cur_data_count = count - start_offset;
721 /* AUX CH Request Transaction process */
722 for (i = 0; i < 3; i++) {
723 /* Select DPCD device address */
724 reg = AUX_ADDR_7_0(reg_addr + start_offset);
725 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
726 reg = AUX_ADDR_15_8(reg_addr + start_offset);
727 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
728 reg = AUX_ADDR_19_16(reg_addr + start_offset);
729 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
732 * Set DisplayPort transaction and read
733 * If bit 3 is 1, DisplayPort transaction.
734 * If Bit 3 is 0, I2C transaction.
736 reg = AUX_LENGTH(cur_data_count) |
737 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
738 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
740 /* Start AUX transaction */
741 retval = analogix_dp_start_aux_transaction(dp);
745 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
749 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
751 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
753 data[start_offset + cur_data_idx] =
757 start_offset += cur_data_count;
763 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
764 unsigned int device_addr,
765 unsigned int reg_addr)
770 /* Set EDID device address */
772 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
773 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
774 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
776 /* Set offset from base address of EDID device */
777 writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
780 * Set I2C transaction and write address
781 * If bit 3 is 1, DisplayPort transaction.
782 * If Bit 3 is 0, I2C transaction.
784 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
786 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
788 /* Start AUX transaction */
789 retval = analogix_dp_start_aux_transaction(dp);
791 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
796 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
797 unsigned int device_addr,
798 unsigned int reg_addr,
805 for (i = 0; i < 3; i++) {
806 /* Clear AUX CH data buffer */
808 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
810 /* Select EDID device */
811 retval = analogix_dp_select_i2c_device(dp, device_addr,
817 * Set I2C transaction and read data
818 * If bit 3 is 1, DisplayPort transaction.
819 * If Bit 3 is 0, I2C transaction.
821 reg = AUX_TX_COMM_I2C_TRANSACTION |
823 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
825 /* Start AUX transaction */
826 retval = analogix_dp_start_aux_transaction(dp);
830 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
835 *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
840 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
841 unsigned int device_addr,
842 unsigned int reg_addr,
844 unsigned char edid[])
848 unsigned int cur_data_idx;
849 unsigned int defer = 0;
852 for (i = 0; i < count; i += 16) {
853 for (j = 0; j < 3; j++) {
854 /* Clear AUX CH data buffer */
856 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
858 /* Set normal AUX CH command */
859 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
861 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
864 * If Rx sends defer, Tx sends only reads
865 * request without sending address
868 retval = analogix_dp_select_i2c_device(dp,
869 device_addr, reg_addr + i);
875 * Set I2C transaction and write data
876 * If bit 3 is 1, DisplayPort transaction.
877 * If Bit 3 is 0, I2C transaction.
879 reg = AUX_LENGTH(16) |
880 AUX_TX_COMM_I2C_TRANSACTION |
882 writel(reg, dp->reg_base +
883 ANALOGIX_DP_AUX_CH_CTL_1);
885 /* Start AUX transaction */
886 retval = analogix_dp_start_aux_transaction(dp);
890 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
893 /* Check if Rx sends defer */
894 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
895 if (reg == AUX_RX_COMM_AUX_DEFER ||
896 reg == AUX_RX_COMM_I2C_DEFER) {
897 dev_err(dp->dev, "Defer: %d\n\n", reg);
902 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
903 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
905 edid[i + cur_data_idx] = (unsigned char)reg;
912 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
917 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
918 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
921 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
925 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
929 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
934 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
937 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
941 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
945 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
951 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
953 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
955 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
957 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
961 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
962 enum pattern_set pattern)
968 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
969 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
972 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
973 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
976 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
977 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
980 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
981 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
984 reg = SCRAMBLING_ENABLE |
985 LINK_QUAL_PATTERN_SET_DISABLE |
986 SW_TRAINING_PATTERN_SET_NORMAL;
987 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
994 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
999 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1000 reg &= ~PRE_EMPHASIS_SET_MASK;
1001 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1002 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1005 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
1010 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1011 reg &= ~PRE_EMPHASIS_SET_MASK;
1012 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1013 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1016 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
1021 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1022 reg &= ~PRE_EMPHASIS_SET_MASK;
1023 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1024 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1027 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
1032 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1033 reg &= ~PRE_EMPHASIS_SET_MASK;
1034 reg |= level << PRE_EMPHASIS_SET_SHIFT;
1035 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1038 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
1043 reg = training_lane;
1044 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1047 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
1052 reg = training_lane;
1053 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1056 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
1061 reg = training_lane;
1062 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1065 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
1070 reg = training_lane;
1071 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1074 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
1078 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1082 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
1086 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1090 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
1094 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1098 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
1102 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1106 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
1110 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
1112 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
1114 /* 10 us is the minimum reset time. */
1115 usleep_range(10, 20);
1118 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
1121 void analogix_dp_init_video(struct analogix_dp_device *dp)
1125 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1126 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
1129 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1131 reg = CHA_CRI(4) | CHA_CTRL;
1132 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1135 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1137 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1138 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
1141 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
1145 /* Configure the input color depth, color space, dynamic range */
1146 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
1147 (dp->video_info.color_depth << IN_BPC_SHIFT) |
1148 (dp->video_info.color_space << IN_COLOR_F_SHIFT);
1149 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
1151 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1152 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1153 reg &= ~IN_YC_COEFFI_MASK;
1154 if (dp->video_info.ycbcr_coeff)
1155 reg |= IN_YC_COEFFI_ITU709;
1157 reg |= IN_YC_COEFFI_ITU601;
1158 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1161 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
1165 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1166 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1168 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1170 if (!(reg & DET_STA)) {
1171 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1175 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1176 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1178 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1179 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1181 if (reg & CHA_STA) {
1182 dev_dbg(dp->dev, "Input stream clk is changing\n");
1189 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
1190 enum clock_recovery_m_value_type type,
1191 u32 m_value, u32 n_value)
1195 if (type == REGISTER_M) {
1196 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1198 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1199 reg = m_value & 0xff;
1200 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
1201 reg = (m_value >> 8) & 0xff;
1202 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
1203 reg = (m_value >> 16) & 0xff;
1204 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
1206 reg = n_value & 0xff;
1207 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
1208 reg = (n_value >> 8) & 0xff;
1209 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
1210 reg = (n_value >> 16) & 0xff;
1211 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
1213 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1215 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1217 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
1218 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
1219 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
1223 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
1227 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1228 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1230 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1232 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1234 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1238 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
1243 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1244 reg &= ~VIDEO_MODE_MASK;
1245 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1246 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1248 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1249 reg &= ~VIDEO_MODE_MASK;
1250 reg |= VIDEO_MODE_SLAVE_MODE;
1251 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1255 void analogix_dp_start_video(struct analogix_dp_device *dp)
1259 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
1261 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
1264 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
1268 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1269 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1271 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1272 if (!(reg & STRM_VALID)) {
1273 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1280 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
1284 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
1285 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
1286 reg |= MASTER_VID_FUNC_EN_N;
1287 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
1289 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1290 reg &= ~INTERACE_SCAN_CFG;
1291 reg |= (dp->video_info.interlaced << 2);
1292 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1294 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1295 reg &= ~VSYNC_POLARITY_CFG;
1296 reg |= (dp->video_info.v_sync_polarity << 1);
1297 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1299 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1300 reg &= ~HSYNC_POLARITY_CFG;
1301 reg |= (dp->video_info.h_sync_polarity << 0);
1302 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1304 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1305 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1308 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
1312 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1313 reg &= ~SCRAMBLING_DISABLE;
1314 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1317 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
1321 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1322 reg |= SCRAMBLING_DISABLE;
1323 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);