drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/clk.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/io.h>
  37 #include <linux/of_gpio.h>
  38 #include <plat/gpio-cfg.h>
  39
  40 #include <drm/exynos_drm.h>
  41
  42 #include "exynos_drm_drv.h"
  43 #include "exynos_drm_display.h"
  44
  45 #include "exynos_hdmi.h"
  46
  47 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  48
  49 struct hdmi_resources {
  50         struct clk                      *hdmi;
  51         struct clk                      *sclk_hdmi;
  52         struct clk                      *sclk_pixel;
  53         struct clk                      *sclk_hdmiphy;
  54         struct clk                      *hdmiphy;
  55         struct regulator_bulk_data      *regul_bulk;
  56         int                             regul_count;
  57 };
  58
  59 struct hdmi_tg_regs {
  60         u8 cmd[1];
  61         u8 h_fsz[2];
  62         u8 hact_st[2];
  63         u8 hact_sz[2];
  64         u8 v_fsz[2];
  65         u8 vsync[2];
  66         u8 vsync2[2];
  67         u8 vact_st[2];
  68         u8 vact_sz[2];
  69         u8 field_chg[2];
  70         u8 vact_st2[2];
  71         u8 vact_st3[2];
  72         u8 vact_st4[2];
  73         u8 vsync_top_hdmi[2];
  74         u8 vsync_bot_hdmi[2];
  75         u8 field_top_hdmi[2];
  76         u8 field_bot_hdmi[2];
  77         u8 tg_3d[1];
  78 };
  79
  80 struct hdmi_core_regs {
  81         u8 h_blank[2];
  82         u8 v2_blank[2];
  83         u8 v1_blank[2];
  84         u8 v_line[2];
  85         u8 h_line[2];
  86         u8 hsync_pol[1];
  87         u8 vsync_pol[1];
  88         u8 int_pro_mode[1];
  89         u8 v_blank_f0[2];
  90         u8 v_blank_f1[2];
  91         u8 h_sync_start[2];
  92         u8 h_sync_end[2];
  93         u8 v_sync_line_bef_2[2];
  94         u8 v_sync_line_bef_1[2];
  95         u8 v_sync_line_aft_2[2];
  96         u8 v_sync_line_aft_1[2];
  97         u8 v_sync_line_aft_pxl_2[2];
  98         u8 v_sync_line_aft_pxl_1[2];
  99         u8 v_blank_f2[2]; /* for 3D mode */
 100         u8 v_blank_f3[2]; /* for 3D mode */
 101         u8 v_blank_f4[2]; /* for 3D mode */
 102         u8 v_blank_f5[2]; /* for 3D mode */
 103         u8 v_sync_line_aft_3[2];
 104         u8 v_sync_line_aft_4[2];
 105         u8 v_sync_line_aft_5[2];
 106         u8 v_sync_line_aft_6[2];
 107         u8 v_sync_line_aft_pxl_3[2];
 108         u8 v_sync_line_aft_pxl_4[2];
 109         u8 v_sync_line_aft_pxl_5[2];
 110         u8 v_sync_line_aft_pxl_6[2];
 111         u8 vact_space_1[2];
 112         u8 vact_space_2[2];
 113         u8 vact_space_3[2];
 114         u8 vact_space_4[2];
 115         u8 vact_space_5[2];
 116         u8 vact_space_6[2];
 117 };
 118
 119 struct hdmi_mode_conf {
 120         int pixel_clock;
 121         struct hdmi_core_regs core;
 122         struct hdmi_tg_regs tg;
 123         u8 vic;
 124 };
 125
 126 struct hdmi_context {
 127         struct device                   *dev;
 128         struct drm_device               *drm_dev;
 129         struct fb_videomode             *default_timing;
 130         struct hdmi_mode_conf           mode_conf;
 131         unsigned int                    is_v13:1;
 132         unsigned int                    default_win;
 133         unsigned int                    default_bpp;
 134         bool                            hpd_handle;
 135         bool                            enabled;
 136         bool                            has_hdmi_sink;
 137         bool                            has_hdmi_audio;
 138         bool                            is_soc_exynos5;
 139         bool                            is_hdmi_powered_on;
 140
 141         struct resource                 *regs_res;
 142         void __iomem                    *regs;
 143         unsigned int                    external_irq;
 144         unsigned int                    internal_irq;
 145         unsigned int                    curr_irq;
 146         struct workqueue_struct         *wq;
 147         struct work_struct              hotplug_work;
 148
 149         struct i2c_client               *ddc_port;
 150         struct i2c_client               *hdmiphy_port;
 151         int                             hpd_gpio;
 152         /* current hdmiphy conf index */
 153         int cur_conf;
 154
 155         struct hdmi_resources           res;
 156 };
 157
 158 /* HDMI Version 1.3 */
 159 static const u8 hdmiphy_v13_conf27[32] = {
 160         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 161         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 162         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 163         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 164 };
 165
 166 static const u8 hdmiphy_v13_conf27_027[32] = {
 167         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 168         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 169         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 170         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 171 };
 172
 173 static const u8 hdmiphy_v13_conf74_175[32] = {
 174         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 175         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 176         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 177         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 178 };
 179
 180 static const u8 hdmiphy_v13_conf74_25[32] = {
 181         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 182         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 183         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 184         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 185 };
 186
 187 static const u8 hdmiphy_v13_conf148_5[32] = {
 188         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 189         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 190         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 191         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 192 };
 193
 194 struct hdmi_v13_tg_regs {
 195         u8 cmd;
 196         u8 h_fsz_l;
 197         u8 h_fsz_h;
 198         u8 hact_st_l;
 199         u8 hact_st_h;
 200         u8 hact_sz_l;
 201         u8 hact_sz_h;
 202         u8 v_fsz_l;
 203         u8 v_fsz_h;
 204         u8 vsync_l;
 205         u8 vsync_h;
 206         u8 vsync2_l;
 207         u8 vsync2_h;
 208         u8 vact_st_l;
 209         u8 vact_st_h;
 210         u8 vact_sz_l;
 211         u8 vact_sz_h;
 212         u8 field_chg_l;
 213         u8 field_chg_h;
 214         u8 vact_st2_l;
 215         u8 vact_st2_h;
 216         u8 vsync_top_hdmi_l;
 217         u8 vsync_top_hdmi_h;
 218         u8 vsync_bot_hdmi_l;
 219         u8 vsync_bot_hdmi_h;
 220         u8 field_top_hdmi_l;
 221         u8 field_top_hdmi_h;
 222         u8 field_bot_hdmi_l;
 223         u8 field_bot_hdmi_h;
 224 };
 225
 226 struct hdmi_v13_core_regs {
 227         u8 h_blank[2];
 228         u8 v_blank[3];
 229         u8 h_v_line[3];
 230         u8 vsync_pol[1];
 231         u8 int_pro_mode[1];
 232         u8 v_blank_f[3];
 233         u8 h_sync_gen[3];
 234         u8 v_sync_gen1[3];
 235         u8 v_sync_gen2[3];
 236         u8 v_sync_gen3[3];
 237 };
 238
 239 struct hdmi_v13_preset_conf {
 240         struct hdmi_v13_core_regs core;
 241         struct hdmi_v13_tg_regs tg;
 242 };
 243
 244 struct hdmi_v13_conf {
 245         int width;
 246         int height;
 247         int vrefresh;
 248         bool interlace;
 249         const u8 *hdmiphy_data;
 250         const struct hdmi_v13_preset_conf *conf;
 251 };
 252
 253 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 254         .core = {
 255                 .h_blank = {0x8a, 0x00},
 256                 .v_blank = {0x0d, 0x6a, 0x01},
 257                 .h_v_line = {0x0d, 0xa2, 0x35},
 258                 .vsync_pol = {0x01},
 259                 .int_pro_mode = {0x00},
 260                 .v_blank_f = {0x00, 0x00, 0x00},
 261                 .h_sync_gen = {0x0e, 0x30, 0x11},
 262                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 263                 /* other don't care */
 264         },
 265         .tg = {
 266                 0x00, /* cmd */
 267                 0x5a, 0x03, /* h_fsz */
 268                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 269                 0x0d, 0x02, /* v_fsz */
 270                 0x01, 0x00, 0x33, 0x02, /* vsync */
 271                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 272                 0x33, 0x02, /* field_chg */
 273                 0x49, 0x02, /* vact_st2 */
 274                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 275                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 276         },
 277 };
 278
 279 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 280         .core = {
 281                 .h_blank = {0x72, 0x01},
 282                 .v_blank = {0xee, 0xf2, 0x00},
 283                 .h_v_line = {0xee, 0x22, 0x67},
 284                 .vsync_pol = {0x00},
 285                 .int_pro_mode = {0x00},
 286                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 287                 .h_sync_gen = {0x6c, 0x50, 0x02},
 288                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 289                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 290                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 291                 /* other don't care */
 292         },
 293         .tg = {
 294                 0x00, /* cmd */
 295                 0x72, 0x06, /* h_fsz */
 296                 0x71, 0x01, 0x01, 0x05, /* hact */
 297                 0xee, 0x02, /* v_fsz */
 298                 0x01, 0x00, 0x33, 0x02, /* vsync */
 299                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 300                 0x33, 0x02, /* field_chg */
 301                 0x49, 0x02, /* vact_st2 */
 302                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 303                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 304         },
 305 };
 306
 307 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 308         .core = {
 309                 .h_blank = {0xd0, 0x02},
 310                 .v_blank = {0x32, 0xB2, 0x00},
 311                 .h_v_line = {0x65, 0x04, 0xa5},
 312                 .vsync_pol = {0x00},
 313                 .int_pro_mode = {0x01},
 314                 .v_blank_f = {0x49, 0x2A, 0x23},
 315                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 316                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 317                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 318                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 319                 /* other don't care */
 320         },
 321         .tg = {
 322                 0x00, /* cmd */
 323                 0x50, 0x0A, /* h_fsz */
 324                 0xCF, 0x02, 0x81, 0x07, /* hact */
 325                 0x65, 0x04, /* v_fsz */
 326                 0x01, 0x00, 0x33, 0x02, /* vsync */
 327                 0x16, 0x00, 0x1c, 0x02, /* vact */
 328                 0x33, 0x02, /* field_chg */
 329                 0x49, 0x02, /* vact_st2 */
 330                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 331                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 332         },
 333 };
 334
 335 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 336         .core = {
 337                 .h_blank = {0xd0, 0x02},
 338                 .v_blank = {0x65, 0x6c, 0x01},
 339                 .h_v_line = {0x65, 0x04, 0xa5},
 340                 .vsync_pol = {0x00},
 341                 .int_pro_mode = {0x00},
 342                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 343                 .h_sync_gen = {0x0e, 0xea, 0x08},
 344                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 345                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 346                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 347                 /* other don't care */
 348         },
 349         .tg = {
 350                 0x00, /* cmd */
 351                 0x50, 0x0A, /* h_fsz */
 352                 0xCF, 0x02, 0x81, 0x07, /* hact */
 353                 0x65, 0x04, /* v_fsz */
 354                 0x01, 0x00, 0x33, 0x02, /* vsync */
 355                 0x2d, 0x00, 0x38, 0x04, /* vact */
 356                 0x33, 0x02, /* field_chg */
 357                 0x48, 0x02, /* vact_st2 */
 358                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 359                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 360         },
 361 };
 362
 363 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 364         .core = {
 365                 .h_blank = {0x18, 0x01},
 366                 .v_blank = {0x32, 0xB2, 0x00},
 367                 .h_v_line = {0x65, 0x84, 0x89},
 368                 .vsync_pol = {0x00},
 369                 .int_pro_mode = {0x01},
 370                 .v_blank_f = {0x49, 0x2A, 0x23},
 371                 .h_sync_gen = {0x56, 0x08, 0x02},
 372                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 373                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 374                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 375                 /* other don't care */
 376         },
 377         .tg = {
 378                 0x00, /* cmd */
 379                 0x98, 0x08, /* h_fsz */
 380                 0x17, 0x01, 0x81, 0x07, /* hact */
 381                 0x65, 0x04, /* v_fsz */
 382                 0x01, 0x00, 0x33, 0x02, /* vsync */
 383                 0x16, 0x00, 0x1c, 0x02, /* vact */
 384                 0x33, 0x02, /* field_chg */
 385                 0x49, 0x02, /* vact_st2 */
 386                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 387                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 388         },
 389 };
 390
 391 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 392         .core = {
 393                 .h_blank = {0x18, 0x01},
 394                 .v_blank = {0x65, 0x6c, 0x01},
 395                 .h_v_line = {0x65, 0x84, 0x89},
 396                 .vsync_pol = {0x00},
 397                 .int_pro_mode = {0x00},
 398                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 399                 .h_sync_gen = {0x56, 0x08, 0x02},
 400                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 401                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 402                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 403                 /* other don't care */
 404         },
 405         .tg = {
 406                 0x00, /* cmd */
 407                 0x98, 0x08, /* h_fsz */
 408                 0x17, 0x01, 0x81, 0x07, /* hact */
 409                 0x65, 0x04, /* v_fsz */
 410                 0x01, 0x00, 0x33, 0x02, /* vsync */
 411                 0x2d, 0x00, 0x38, 0x04, /* vact */
 412                 0x33, 0x02, /* field_chg */
 413                 0x48, 0x02, /* vact_st2 */
 414                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 415                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 416         },
 417 };
 418
 419 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 420         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 421         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 422         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 423         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 424         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 425                                  &hdmi_v13_conf_1080p50 },
 426         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 427         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 428                                  &hdmi_v13_conf_1080p60 },
 429 };
 430
 431 struct hdmiphy_config {
 432         int pixel_clock;
 433         u8 conf[32];
 434 };
 435
 436 static const struct hdmiphy_config phy_configs[] = {
 437         {
 438                 .pixel_clock = 25200000,
 439                 .conf = {
 440                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 441                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 442                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 443                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 444                 },
 445         },
 446         {
 447                 .pixel_clock = 27000000,
 448                 .conf = {
 449                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 450                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 451                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 452                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 453                 },
 454         },
 455         {
 456                 .pixel_clock = 27027000,
 457                 .conf = {
 458                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 459                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 460                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 461                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 462                 },
 463         },
 464         {
 465                 .pixel_clock = 36000000,
 466                 .conf = {
 467                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 468                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 469                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 470                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 471                 },
 472         },
 473         {
 474                 .pixel_clock = 40000000,
 475                 .conf = {
 476                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 477                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 478                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 479                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 480                 },
 481         },
 482         {
 483                 .pixel_clock = 65000000,
 484                 .conf = {
 485                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 486                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 487                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 488                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 489                 },
 490         },
 491         {
 492                 .pixel_clock = 74176000,
 493                 .conf = {
 494                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 495                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 496                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 497                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 498                 },
 499         },
 500         {
 501                 .pixel_clock = 74250000,
 502                 .conf = {
 503                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 504                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 505                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 506                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 507                 },
 508         },
 509         {
 510                 .pixel_clock = 83500000,
 511                 .conf = {
 512                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 513                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 514                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 515                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 516                 },
 517         },
 518         {
 519                 .pixel_clock = 106500000,
 520                 .conf = {
 521                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 522                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 523                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 524                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 525                 },
 526         },
 527         {
 528                 .pixel_clock = 108000000,
 529                 .conf = {
 530                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 531                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 532                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 533                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 534                 },
 535         },
 536         {
 537                 .pixel_clock = 146250000,
 538                 .conf = {
 539                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 540                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 541                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 542                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 543                 },
 544         },
 545         {
 546                 .pixel_clock = 148500000,
 547                 .conf = {
 548                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 549                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 550                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 551                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 552                 },
 553         },
 554 };
 555
 556 struct hdmi_infoframe {
 557         enum HDMI_PACKET_TYPE type;
 558         u8 ver;
 559         u8 len;
 560 };
 561
 562 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 563 {
 564         return readl(hdata->regs + reg_id);
 565 }
 566
 567 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 568                                  u32 reg_id, u8 value)
 569 {
 570         writeb(value, hdata->regs + reg_id);
 571 }
 572
 573 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 574                                  u32 reg_id, u32 value, u32 mask)
 575 {
 576         u32 old = readl(hdata->regs + reg_id);
 577         value = (value & mask) | (old & ~mask);
 578         writel(value, hdata->regs + reg_id);
 579 }
 580
 581 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 582 {
 583         if (external) {
 584                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 585                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 586         } else {
 587                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 588                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 589         }
 590 }
 591
 592 static int hdmi_get_hpd(struct hdmi_context *hdata)
 593 {
 594         return gpio_get_value(hdata->hpd_gpio);
 595 }
 596
 597 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 598 {
 599 #define DUMPREG(reg_id) \
 600         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 601         readl(hdata->regs + reg_id))
 602         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 603         DUMPREG(HDMI_INTC_FLAG);
 604         DUMPREG(HDMI_INTC_CON);
 605         DUMPREG(HDMI_HPD_STATUS);
 606         DUMPREG(HDMI_V13_PHY_RSTOUT);
 607         DUMPREG(HDMI_V13_PHY_VPLL);
 608         DUMPREG(HDMI_V13_PHY_CMU);
 609         DUMPREG(HDMI_V13_CORE_RSTOUT);
 610
 611         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 612         DUMPREG(HDMI_CON_0);
 613         DUMPREG(HDMI_CON_1);
 614         DUMPREG(HDMI_CON_2);
 615         DUMPREG(HDMI_SYS_STATUS);
 616         DUMPREG(HDMI_V13_PHY_STATUS);
 617         DUMPREG(HDMI_STATUS_EN);
 618         DUMPREG(HDMI_HPD);
 619         DUMPREG(HDMI_MODE_SEL);
 620         DUMPREG(HDMI_V13_HPD_GEN);
 621         DUMPREG(HDMI_V13_DC_CONTROL);
 622         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 623
 624         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 625         DUMPREG(HDMI_H_BLANK_0);
 626         DUMPREG(HDMI_H_BLANK_1);
 627         DUMPREG(HDMI_V13_V_BLANK_0);
 628         DUMPREG(HDMI_V13_V_BLANK_1);
 629         DUMPREG(HDMI_V13_V_BLANK_2);
 630         DUMPREG(HDMI_V13_H_V_LINE_0);
 631         DUMPREG(HDMI_V13_H_V_LINE_1);
 632         DUMPREG(HDMI_V13_H_V_LINE_2);
 633         DUMPREG(HDMI_VSYNC_POL);
 634         DUMPREG(HDMI_INT_PRO_MODE);
 635         DUMPREG(HDMI_V13_V_BLANK_F_0);
 636         DUMPREG(HDMI_V13_V_BLANK_F_1);
 637         DUMPREG(HDMI_V13_V_BLANK_F_2);
 638         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 639         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 640         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 641         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 642         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 643         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 644         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 645         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 646         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 647         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 648         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 649         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 650
 651         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 652         DUMPREG(HDMI_TG_CMD);
 653         DUMPREG(HDMI_TG_H_FSZ_L);
 654         DUMPREG(HDMI_TG_H_FSZ_H);
 655         DUMPREG(HDMI_TG_HACT_ST_L);
 656         DUMPREG(HDMI_TG_HACT_ST_H);
 657         DUMPREG(HDMI_TG_HACT_SZ_L);
 658         DUMPREG(HDMI_TG_HACT_SZ_H);
 659         DUMPREG(HDMI_TG_V_FSZ_L);
 660         DUMPREG(HDMI_TG_V_FSZ_H);
 661         DUMPREG(HDMI_TG_VSYNC_L);
 662         DUMPREG(HDMI_TG_VSYNC_H);
 663         DUMPREG(HDMI_TG_VSYNC2_L);
 664         DUMPREG(HDMI_TG_VSYNC2_H);
 665         DUMPREG(HDMI_TG_VACT_ST_L);
 666         DUMPREG(HDMI_TG_VACT_ST_H);
 667         DUMPREG(HDMI_TG_VACT_SZ_L);
 668         DUMPREG(HDMI_TG_VACT_SZ_H);
 669         DUMPREG(HDMI_TG_FIELD_CHG_L);
 670         DUMPREG(HDMI_TG_FIELD_CHG_H);
 671         DUMPREG(HDMI_TG_VACT_ST2_L);
 672         DUMPREG(HDMI_TG_VACT_ST2_H);
 673         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 674         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 675         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 676         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 677         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 678         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 679         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 680         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 681 #undef DUMPREG
 682 }
 683
 684 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 685 {
 686         int i;
 687
 688 #define DUMPREG(reg_id) \
 689         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 690         readl(hdata->regs + reg_id))
 691
 692         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 693         DUMPREG(HDMI_INTC_CON);
 694         DUMPREG(HDMI_INTC_FLAG);
 695         DUMPREG(HDMI_HPD_STATUS);
 696         DUMPREG(HDMI_INTC_CON_1);
 697         DUMPREG(HDMI_INTC_FLAG_1);
 698         DUMPREG(HDMI_PHY_STATUS_0);
 699         DUMPREG(HDMI_PHY_STATUS_PLL);
 700         DUMPREG(HDMI_PHY_CON_0);
 701         DUMPREG(HDMI_PHY_RSTOUT);
 702         DUMPREG(HDMI_PHY_VPLL);
 703         DUMPREG(HDMI_PHY_CMU);
 704         DUMPREG(HDMI_CORE_RSTOUT);
 705
 706         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 707         DUMPREG(HDMI_CON_0);
 708         DUMPREG(HDMI_CON_1);
 709         DUMPREG(HDMI_CON_2);
 710         DUMPREG(HDMI_SYS_STATUS);
 711         DUMPREG(HDMI_PHY_STATUS_0);
 712         DUMPREG(HDMI_STATUS_EN);
 713         DUMPREG(HDMI_HPD);
 714         DUMPREG(HDMI_MODE_SEL);
 715         DUMPREG(HDMI_ENC_EN);
 716         DUMPREG(HDMI_DC_CONTROL);
 717         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 718
 719         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 720         DUMPREG(HDMI_H_BLANK_0);
 721         DUMPREG(HDMI_H_BLANK_1);
 722         DUMPREG(HDMI_V2_BLANK_0);
 723         DUMPREG(HDMI_V2_BLANK_1);
 724         DUMPREG(HDMI_V1_BLANK_0);
 725         DUMPREG(HDMI_V1_BLANK_1);
 726         DUMPREG(HDMI_V_LINE_0);
 727         DUMPREG(HDMI_V_LINE_1);
 728         DUMPREG(HDMI_H_LINE_0);
 729         DUMPREG(HDMI_H_LINE_1);
 730         DUMPREG(HDMI_HSYNC_POL);
 731
 732         DUMPREG(HDMI_VSYNC_POL);
 733         DUMPREG(HDMI_INT_PRO_MODE);
 734         DUMPREG(HDMI_V_BLANK_F0_0);
 735         DUMPREG(HDMI_V_BLANK_F0_1);
 736         DUMPREG(HDMI_V_BLANK_F1_0);
 737         DUMPREG(HDMI_V_BLANK_F1_1);
 738
 739         DUMPREG(HDMI_H_SYNC_START_0);
 740         DUMPREG(HDMI_H_SYNC_START_1);
 741         DUMPREG(HDMI_H_SYNC_END_0);
 742         DUMPREG(HDMI_H_SYNC_END_1);
 743
 744         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 745         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 746         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 747         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 748
 749         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 750         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 751         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 752         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 753
 754         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 755         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 756         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 757         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 758
 759         DUMPREG(HDMI_V_BLANK_F2_0);
 760         DUMPREG(HDMI_V_BLANK_F2_1);
 761         DUMPREG(HDMI_V_BLANK_F3_0);
 762         DUMPREG(HDMI_V_BLANK_F3_1);
 763         DUMPREG(HDMI_V_BLANK_F4_0);
 764         DUMPREG(HDMI_V_BLANK_F4_1);
 765         DUMPREG(HDMI_V_BLANK_F5_0);
 766         DUMPREG(HDMI_V_BLANK_F5_1);
 767
 768         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 769         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 776
 777         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 778         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 779         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 780         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 781         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 782         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 783         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 784         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 785
 786         DUMPREG(HDMI_VACT_SPACE_1_0);
 787         DUMPREG(HDMI_VACT_SPACE_1_1);
 788         DUMPREG(HDMI_VACT_SPACE_2_0);
 789         DUMPREG(HDMI_VACT_SPACE_2_1);
 790         DUMPREG(HDMI_VACT_SPACE_3_0);
 791         DUMPREG(HDMI_VACT_SPACE_3_1);
 792         DUMPREG(HDMI_VACT_SPACE_4_0);
 793         DUMPREG(HDMI_VACT_SPACE_4_1);
 794         DUMPREG(HDMI_VACT_SPACE_5_0);
 795         DUMPREG(HDMI_VACT_SPACE_5_1);
 796         DUMPREG(HDMI_VACT_SPACE_6_0);
 797         DUMPREG(HDMI_VACT_SPACE_6_1);
 798
 799         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 800         DUMPREG(HDMI_TG_CMD);
 801         DUMPREG(HDMI_TG_H_FSZ_L);
 802         DUMPREG(HDMI_TG_H_FSZ_H);
 803         DUMPREG(HDMI_TG_HACT_ST_L);
 804         DUMPREG(HDMI_TG_HACT_ST_H);
 805         DUMPREG(HDMI_TG_HACT_SZ_L);
 806         DUMPREG(HDMI_TG_HACT_SZ_H);
 807         DUMPREG(HDMI_TG_V_FSZ_L);
 808         DUMPREG(HDMI_TG_V_FSZ_H);
 809         DUMPREG(HDMI_TG_VSYNC_L);
 810         DUMPREG(HDMI_TG_VSYNC_H);
 811         DUMPREG(HDMI_TG_VSYNC2_L);
 812         DUMPREG(HDMI_TG_VSYNC2_H);
 813         DUMPREG(HDMI_TG_VACT_ST_L);
 814         DUMPREG(HDMI_TG_VACT_ST_H);
 815         DUMPREG(HDMI_TG_VACT_SZ_L);
 816         DUMPREG(HDMI_TG_VACT_SZ_H);
 817         DUMPREG(HDMI_TG_FIELD_CHG_L);
 818         DUMPREG(HDMI_TG_FIELD_CHG_H);
 819         DUMPREG(HDMI_TG_VACT_ST2_L);
 820         DUMPREG(HDMI_TG_VACT_ST2_H);
 821         DUMPREG(HDMI_TG_VACT_ST3_L);
 822         DUMPREG(HDMI_TG_VACT_ST3_H);
 823         DUMPREG(HDMI_TG_VACT_ST4_L);
 824         DUMPREG(HDMI_TG_VACT_ST4_H);
 825         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 826         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 827         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 828         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 829         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 830         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 831         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 832         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 833         DUMPREG(HDMI_TG_3D);
 834
 835         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 836         DUMPREG(HDMI_AVI_CON);
 837         DUMPREG(HDMI_AVI_HEADER0);
 838         DUMPREG(HDMI_AVI_HEADER1);
 839         DUMPREG(HDMI_AVI_HEADER2);
 840         DUMPREG(HDMI_AVI_CHECK_SUM);
 841         DUMPREG(HDMI_VSI_CON);
 842         DUMPREG(HDMI_VSI_HEADER0);
 843         DUMPREG(HDMI_VSI_HEADER1);
 844         DUMPREG(HDMI_VSI_HEADER2);
 845         for (i = 0; i < 7; ++i)
 846                 DUMPREG(HDMI_VSI_DATA(i));
 847
 848 #undef DUMPREG
 849 }
 850
 851 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 852 {
 853         if (hdata->is_v13)
 854                 hdmi_v13_regs_dump(hdata, prefix);
 855         else
 856                 hdmi_v14_regs_dump(hdata, prefix);
 857 }
 858
 859 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 860 {
 861         int i;
 862
 863         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 864                 if (hdmi_v13_confs[i].width == mode->hdisplay &&
 865                                 hdmi_v13_confs[i].height == mode->vdisplay &&
 866                                 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 867                                 hdmi_v13_confs[i].interlace ==
 868                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 869                                  true : false))
 870                         return i;
 871
 872         return -EINVAL;
 873 }
 874
 875 static bool hdmi_is_connected(void *ctx)
 876 {
 877         struct hdmi_context *hdata = ctx;
 878         if (hdata->is_hdmi_powered_on) {
 879                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 880                         DRM_DEBUG_KMS("hdmi is not connected\n");
 881                         return false;
 882                 }
 883         } else if (!hdmi_get_hpd(hdata)) {
 884                         DRM_DEBUG_KMS("hdmi is not connected\n");
 885                         return false;
 886         }
 887
 888         return true;
 889 }
 890
 891 static int hdmi_get_edid(void *ctx, struct drm_connector *connector,
 892                                 u8 *edid, int len)
 893 {
 894         struct edid *raw_edid;
 895         struct hdmi_context *hdata = ctx;
 896
 897         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 898
 899         if (!hdata->ddc_port)
 900                 return -ENODEV;
 901
 902         raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 903         if (raw_edid) {
 904         /* TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 905          * to get the edid and then call drm_detect_hdmi_monitor.
 906          */
 907                 hdata->has_hdmi_sink = drm_detect_hdmi_monitor(raw_edid);
 908                 hdata->has_hdmi_audio = drm_detect_monitor_audio(raw_edid);
 909                 memcpy(edid, raw_edid, min((1 + raw_edid->extensions)
 910                                         * EDID_LENGTH, len));
 911                 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
 912                         (hdata->has_hdmi_sink ? "hdmi monitor" : "dvi monitor"),
 913                         raw_edid->width_cm, raw_edid->height_cm);
 914         } else {
 915                 return -ENODEV;
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 922 {
 923         int i;
 924
 925         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 926                         check_timing->xres, check_timing->yres,
 927                         check_timing->refresh, (check_timing->vmode &
 928                         FB_VMODE_INTERLACED) ? true : false);
 929
 930         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 931                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 932                         hdmi_v13_confs[i].height == check_timing->yres &&
 933                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 934                         hdmi_v13_confs[i].interlace ==
 935                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 936                          true : false))
 937                                 return 0;
 938
 939         /* TODO */
 940
 941         return -EINVAL;
 942 }
 943
 944 static int find_hdmiphy_conf(int pixel_clock)
 945 {
 946         int i;
 947
 948         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 949                 if (phy_configs[i].pixel_clock == pixel_clock)
 950                         return i;
 951         }
 952         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 953         return -EINVAL;
 954 }
 955
 956 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 957 {
 958         int ret;
 959         enum exynos_mixer_mode_type mode_type;
 960
 961         /* Make sure the mixer can generate this mode */
 962         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 963         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 964                 return -EINVAL;
 965
 966         ret = find_hdmiphy_conf(mode->pixclock);
 967         return ret < 0 ? ret : 0;
 968 }
 969
 970 static u8 hdmi_chksum(struct hdmi_context *hdata,
 971                         u32 start, u8 len, u32 hdr_sum)
 972 {
 973         int i;
 974         /* hdr_sum : header0 + header1 + header2
 975         * start : start address of packet byte1
 976         * len : packet bytes - 1 */
 977         for (i = 0; i < len; ++i)
 978                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 979
 980         return (u8)(0x100 - (hdr_sum & 0xff));
 981 }
 982
 983 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 984                         struct hdmi_infoframe *infoframe)
 985 {
 986         u32 hdr_sum;
 987         u8 chksum;
 988         u32 aspect_ratio;
 989         u32 mod;
 990
 991         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 992         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 993         if (!hdata->has_hdmi_sink) {
 994                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 995                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 996                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 997                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 998                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 999                 return;
1000         }
1001
1002         switch (infoframe->type) {
1003
1004         case HDMI_PACKET_TYPE_AVI:
1005                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1006                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
1007                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
1008                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
1009                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1010                 /* Output format zero hardcoded ,RGB YBCR selection */
1011                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1012                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
1013
1014                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
1015
1016                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
1017                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
1018                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
1019
1020                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1021                                         infoframe->len, hdr_sum);
1022                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1023                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1024                 break;
1025
1026         case HDMI_PACKET_TYPE_AUI:
1027                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1028                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
1029                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
1030                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
1031                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1032                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1033                                         infoframe->len, hdr_sum);
1034                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1035                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1036                 break;
1037
1038         default:
1039                 break;
1040         }
1041 }
1042
1043 static int hdmi_check_timing(void *ctx, void *timing)
1044 {
1045         struct hdmi_context *hdata = ctx;
1046         struct fb_videomode *check_timing = timing;
1047
1048         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1049
1050         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1051                         check_timing->yres, check_timing->refresh,
1052                         check_timing->vmode);
1053
1054         if (hdata->is_v13)
1055                 return hdmi_v13_check_timing(check_timing);
1056         else
1057                 return hdmi_v14_check_timing(check_timing);
1058 }
1059
1060 static void hdmi_set_acr(u32 freq, u8 *acr)
1061 {
1062         u32 n, cts;
1063
1064         switch (freq) {
1065         case 32000:
1066                 n = 4096;
1067                 cts = 27000;
1068                 break;
1069         case 44100:
1070                 n = 6272;
1071                 cts = 30000;
1072                 break;
1073         case 88200:
1074                 n = 12544;
1075                 cts = 30000;
1076                 break;
1077         case 176400:
1078                 n = 25088;
1079                 cts = 30000;
1080                 break;
1081         case 48000:
1082                 n = 6144;
1083                 cts = 27000;
1084                 break;
1085         case 96000:
1086                 n = 12288;
1087                 cts = 27000;
1088                 break;
1089         case 192000:
1090                 n = 24576;
1091                 cts = 27000;
1092                 break;
1093         default:
1094                 n = 0;
1095                 cts = 0;
1096                 break;
1097         }
1098
1099         acr[1] = cts >> 16;
1100         acr[2] = cts >> 8 & 0xff;
1101         acr[3] = cts & 0xff;
1102
1103         acr[4] = n >> 16;
1104         acr[5] = n >> 8 & 0xff;
1105         acr[6] = n & 0xff;
1106 }
1107
1108 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1109 {
1110         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1111         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1112         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1113         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1114         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1115         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1116         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1117         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1118         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1119
1120         if (hdata->is_v13)
1121                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1122         else
1123                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1124 }
1125
1126 static void hdmi_audio_init(struct hdmi_context *hdata)
1127 {
1128         u32 sample_rate, bits_per_sample, frame_size_code;
1129         u32 data_num, bit_ch, sample_frq;
1130         u32 val;
1131         u8 acr[7];
1132
1133         sample_rate = 44100;
1134         bits_per_sample = 16;
1135         frame_size_code = 0;
1136
1137         switch (bits_per_sample) {
1138         case 20:
1139                 data_num = 2;
1140                 bit_ch  = 1;
1141                 break;
1142         case 24:
1143                 data_num = 3;
1144                 bit_ch  = 1;
1145                 break;
1146         default:
1147                 data_num = 1;
1148                 bit_ch  = 0;
1149                 break;
1150         }
1151
1152         hdmi_set_acr(sample_rate, acr);
1153         hdmi_reg_acr(hdata, acr);
1154
1155         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1156                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1157                                 | HDMI_I2S_MUX_ENABLE);
1158
1159         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1160                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1161
1162         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1163
1164         sample_frq = (sample_rate == 44100) ? 0 :
1165                         (sample_rate == 48000) ? 2 :
1166                         (sample_rate == 32000) ? 3 :
1167                         (sample_rate == 96000) ? 0xa : 0x0;
1168
1169         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1170         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1171
1172         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1173         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1174
1175         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1176         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1177                         | HDMI_I2S_SEL_LRCK(6));
1178         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1179                         | HDMI_I2S_SEL_SDATA2(4));
1180         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1181                         | HDMI_I2S_SEL_SDATA2(2));
1182         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1183
1184         /* I2S_CON_1 & 2 */
1185         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1186                         | HDMI_I2S_L_CH_LOW_POL);
1187         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1188                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1189                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1190                         | HDMI_I2S_BASIC_FORMAT);
1191
1192         /* Configure register related to CUV information */
1193         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1194                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1195                         | HDMI_I2S_COPYRIGHT
1196                         | HDMI_I2S_LINEAR_PCM
1197                         | HDMI_I2S_CONSUMER_FORMAT);
1198         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1199         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1200         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1201                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1202         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1203                         HDMI_I2S_ORG_SMP_FREQ_44_1
1204                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1205                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1206
1207         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1208 }
1209
1210 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1211 {
1212         if (!hdata->has_hdmi_audio)
1213                 return;
1214
1215         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1216         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1217                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1218 }
1219
1220 static void hdmi_conf_reset(struct hdmi_context *hdata)
1221 {
1222         u32 reg;
1223
1224         /* disable hpd handle for drm */
1225         hdata->hpd_handle = false;
1226
1227         if (hdata->is_v13)
1228                 reg = HDMI_V13_CORE_RSTOUT;
1229         else
1230                 reg = HDMI_CORE_RSTOUT;
1231
1232         /* resetting HDMI core */
1233         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1234         mdelay(10);
1235         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1236         mdelay(10);
1237
1238         /* enable hpd handle for drm */
1239         hdata->hpd_handle = true;
1240 }
1241
1242 static void hdmi_conf_init(struct hdmi_context *hdata)
1243 {
1244         struct hdmi_infoframe infoframe;
1245         /* disable hpd handle for drm */
1246         hdata->hpd_handle = false;
1247
1248         /* enable HPD interrupts */
1249         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1250                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1251         mdelay(10);
1252         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1253                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1254
1255         /* choose HDMI mode */
1256         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1257                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1258         /* disable bluescreen */
1259         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1260
1261         if (!hdata->has_hdmi_sink) {
1262                 /* choose DVI mode */
1263                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1264                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1265                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1266                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1267         }
1268
1269         if (hdata->is_v13) {
1270                 /* choose bluescreen (fecal) color */
1271                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1272                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1273                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1274
1275                 /* enable AVI packet every vsync, fixes purple line problem */
1276                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1277                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1278                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1279                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1280
1281                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1282                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1283                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1284         } else {
1285                 /* enable AVI packet every vsync, fixes purple line problem */
1286                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1287
1288                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1289                 infoframe.ver = HDMI_AVI_VERSION;
1290                 infoframe.len = HDMI_AVI_LENGTH;
1291                 hdmi_reg_infoframe(hdata, &infoframe);
1292
1293                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1294                 infoframe.ver = HDMI_AUI_VERSION;
1295                 infoframe.len = HDMI_AUI_LENGTH;
1296                 hdmi_reg_infoframe(hdata, &infoframe);
1297
1298         }
1299
1300         /* enable hpd handle for drm */
1301         hdata->hpd_handle = true;
1302 }
1303
1304 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1305 {
1306         const struct hdmi_v13_preset_conf *conf =
1307                 hdmi_v13_confs[hdata->cur_conf].conf;
1308         const struct hdmi_v13_core_regs *core = &conf->core;
1309         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1310         int tries;
1311
1312         /* setting core registers */
1313         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1314         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1315         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1316         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1317         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1318         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1319         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1320         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1321         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1322         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1323         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1324         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1325         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1326         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1327         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1328         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1329         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1330         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1331         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1332         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1333         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1334         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1335         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1336         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1337         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1338         /* Timing generator registers */
1339         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1340         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1341         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1342         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1343         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1344         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1345         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1346         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1347         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1348         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1349         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1350         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1351         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1352         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1353         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1354         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1355         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1356         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1357         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1358         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1359         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1360         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1361         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1362         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1363         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1364         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1365         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1366         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1367
1368         /* waiting for HDMIPHY's PLL to get to steady state */
1369         for (tries = 100; tries; --tries) {
1370                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1371                 if (val & HDMI_PHY_STATUS_READY)
1372                         break;
1373                 mdelay(1);
1374         }
1375         /* steady state not achieved */
1376         if (tries == 0) {
1377                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1378                 hdmi_regs_dump(hdata, "timing apply");
1379         }
1380
1381         clk_disable(hdata->res.sclk_hdmi);
1382         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1383         clk_enable(hdata->res.sclk_hdmi);
1384
1385         /* enable HDMI and timing generator */
1386         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1387         if (core->int_pro_mode[0])
1388                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1389                                 HDMI_FIELD_EN);
1390         else
1391                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1392 }
1393
1394 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1395 {
1396         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1397         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1398         int tries;
1399
1400         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1401         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1402         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1403         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1404         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1405         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1406         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1407         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1408         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1409         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1410         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1411         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1412         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1413         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1414         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1415         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1416         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1417         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1418         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1419         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1420         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1421         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1422                         core->v_sync_line_bef_2[0]);
1423         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1424                         core->v_sync_line_bef_2[1]);
1425         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1426                         core->v_sync_line_bef_1[0]);
1427         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1428                         core->v_sync_line_bef_1[1]);
1429         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1430                         core->v_sync_line_aft_2[0]);
1431         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1432                         core->v_sync_line_aft_2[1]);
1433         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1434                         core->v_sync_line_aft_1[0]);
1435         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1436                         core->v_sync_line_aft_1[1]);
1437         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1438                         core->v_sync_line_aft_pxl_2[0]);
1439         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1440                         core->v_sync_line_aft_pxl_2[1]);
1441         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1442                         core->v_sync_line_aft_pxl_1[0]);
1443         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1444                         core->v_sync_line_aft_pxl_1[1]);
1445         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1446         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1447         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1448         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1449         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1450         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1451         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1452         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1453         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1454                         core->v_sync_line_aft_3[0]);
1455         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1456                         core->v_sync_line_aft_3[1]);
1457         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1458                         core->v_sync_line_aft_4[0]);
1459         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1460                         core->v_sync_line_aft_4[1]);
1461         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1462                         core->v_sync_line_aft_5[0]);
1463         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1464                         core->v_sync_line_aft_5[1]);
1465         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1466                         core->v_sync_line_aft_6[0]);
1467         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1468                         core->v_sync_line_aft_6[1]);
1469         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1470                         core->v_sync_line_aft_pxl_3[0]);
1471         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1472                         core->v_sync_line_aft_pxl_3[1]);
1473         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1474                         core->v_sync_line_aft_pxl_4[0]);
1475         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1476                         core->v_sync_line_aft_pxl_4[1]);
1477         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1478                         core->v_sync_line_aft_pxl_5[0]);
1479         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1480                         core->v_sync_line_aft_pxl_5[1]);
1481         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1482                         core->v_sync_line_aft_pxl_6[0]);
1483         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1484                         core->v_sync_line_aft_pxl_6[1]);
1485         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1486         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1487         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1488         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1489         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1490         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1491         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1492         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1493         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1494         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1495         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1496         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1497
1498         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1499         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1500         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1501         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1502         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1503         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1504         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1505         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1506         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1507         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1508         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1509         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1510         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1511         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1512         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1513         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1514         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1515         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1516         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1517         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1518         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1519         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1520         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1521         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1522         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1523         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1524         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1525         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1526         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1527         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1528         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1529         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1530         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1531
1532         /* waiting for HDMIPHY's PLL to get to steady state */
1533         for (tries = 100; tries; --tries) {
1534                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1535                 if (val & HDMI_PHY_STATUS_READY)
1536                         break;
1537                 mdelay(1);
1538         }
1539         /* steady state not achieved */
1540         if (tries == 0) {
1541                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1542                 hdmi_regs_dump(hdata, "timing apply");
1543         }
1544
1545         clk_disable(hdata->res.sclk_hdmi);
1546         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1547         clk_enable(hdata->res.sclk_hdmi);
1548
1549         /* enable HDMI and timing generator */
1550         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1551         if (core->int_pro_mode[0])
1552                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1553                                 HDMI_FIELD_EN);
1554         else
1555                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1556 }
1557
1558 static void hdmi_timing_apply(struct hdmi_context *hdata)
1559 {
1560         if (hdata->is_v13)
1561                 hdmi_v13_timing_apply(hdata);
1562         else
1563                 hdmi_v14_timing_apply(hdata);
1564 }
1565
1566 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1567 {
1568         u8 buffer[2];
1569         u32 reg;
1570
1571         clk_disable(hdata->res.sclk_hdmi);
1572         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1573         clk_enable(hdata->res.sclk_hdmi);
1574
1575         /* operation mode */
1576         buffer[0] = 0x1f;
1577         buffer[1] = 0x00;
1578
1579         if (hdata->hdmiphy_port)
1580                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1581
1582         if (hdata->is_v13)
1583                 reg = HDMI_V13_PHY_RSTOUT;
1584         else
1585                 reg = HDMI_PHY_RSTOUT;
1586
1587         /* reset hdmiphy */
1588         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1589         mdelay(10);
1590         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1591         mdelay(10);
1592 }
1593
1594 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1595 {
1596         const u8 *hdmiphy_data;
1597         u8 buffer[32];
1598         u8 operation[2];
1599         u8 read_buffer[32] = {0, };
1600         int ret;
1601         int i;
1602
1603         if (!hdata->hdmiphy_port) {
1604                 DRM_ERROR("hdmiphy is not attached\n");
1605                 return;
1606         }
1607
1608         /* pixel clock */
1609         if (hdata->is_v13) {
1610                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1611         } else {
1612                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1613                 hdmiphy_data = phy_configs[i].conf;
1614         }
1615
1616         memcpy(buffer, hdmiphy_data, 32);
1617         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1618         if (ret != 32) {
1619                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1620                 return;
1621         }
1622
1623         mdelay(10);
1624
1625         /* operation mode */
1626         operation[0] = 0x1f;
1627         operation[1] = 0x80;
1628
1629         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1630         if (ret != 2) {
1631                 DRM_ERROR("failed to enable hdmiphy\n");
1632                 return;
1633         }
1634
1635         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1636         if (ret < 0) {
1637                 DRM_ERROR("failed to read hdmiphy config\n");
1638                 return;
1639         }
1640
1641         for (i = 0; i < ret; i++)
1642                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1643                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1644 }
1645
1646 static void hdmi_conf_apply(struct hdmi_context *hdata)
1647 {
1648         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1649
1650         hdmiphy_conf_reset(hdata);
1651         hdmiphy_conf_apply(hdata);
1652
1653         hdmi_conf_reset(hdata);
1654         hdmi_conf_init(hdata);
1655         if (!hdata->is_soc_exynos5)
1656                 hdmi_audio_init(hdata);
1657
1658         /* setting core registers */
1659         hdmi_timing_apply(hdata);
1660         if (!hdata->is_soc_exynos5)
1661                 hdmi_audio_control(hdata, true);
1662
1663         hdmi_regs_dump(hdata, "start");
1664 }
1665
1666 static void hdmi_mode_copy(struct drm_display_mode *dst,
1667         struct drm_display_mode *src)
1668 {
1669         struct drm_mode_object base;
1670
1671         /* following information should be preserved,
1672          * required for releasing the drm_display_mode node,
1673          * duplicated to recieve adjustment info. */
1674
1675         base.id = dst->base.id;
1676         base.type = dst->base.type;
1677
1678         memcpy(dst, src, sizeof(struct drm_display_mode));
1679
1680         dst->base.id = base.id;
1681         dst->base.type = base.type;
1682 }
1683
1684 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1685                                 struct drm_display_mode *mode,
1686                                 struct drm_display_mode *adjusted_mode)
1687 {
1688         struct drm_display_mode *m;
1689         struct hdmi_context *hdata = ctx;
1690         int index;
1691
1692         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1693
1694         drm_mode_set_crtcinfo(adjusted_mode, 0);
1695
1696         if (hdata->is_v13)
1697                 index = hdmi_v13_conf_index(adjusted_mode);
1698         else
1699                 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1700
1701         /* just return if user desired mode exists. */
1702         if (index >= 0)
1703                 return;
1704
1705         /*
1706          * otherwise, find the most suitable mode among modes and change it
1707          * to adjusted_mode.
1708          */
1709         list_for_each_entry(m, &connector->modes, head) {
1710                 if (hdata->is_v13)
1711                         index = hdmi_v13_conf_index(m);
1712                 else
1713                         index = find_hdmiphy_conf(m->clock * 1000);
1714
1715                 if (index >= 0) {
1716                         DRM_INFO("desired mode doesn't exist so\n");
1717                         DRM_INFO("use the most suitable mode among modes.\n");
1718                         hdmi_mode_copy(adjusted_mode, m);
1719                         break;
1720                 }
1721         }
1722 }
1723
1724 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1725 {
1726         int i;
1727         BUG_ON(num_bytes > 4);
1728         for (i = 0; i < num_bytes; i++)
1729                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1730 }
1731
1732 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1733                         struct drm_display_mode *m)
1734 {
1735         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1736         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1737
1738         hdata->mode_conf.vic = drm_match_cea_mode(m);
1739
1740         hdata->mode_conf.pixel_clock = m->clock * 1000;
1741         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1742         hdmi_set_reg(core->v_line, 2, m->vtotal);
1743         hdmi_set_reg(core->h_line, 2, m->htotal);
1744         hdmi_set_reg(core->hsync_pol, 1,
1745                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1746         hdmi_set_reg(core->vsync_pol, 1,
1747                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1748         hdmi_set_reg(core->int_pro_mode, 1,
1749                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1750
1751         /*
1752          * Quirk requirement for exynos 5 HDMI IP design,
1753          * 2 pixels less than the actual calculation for hsync_start
1754          * and end.
1755          */
1756
1757         /* Following values & calculations differ for different type of modes */
1758         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1759                 /* Interlaced Mode */
1760                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1761                         (m->vsync_end - m->vdisplay) / 2);
1762                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1763                         (m->vsync_start - m->vdisplay) / 2);
1764                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1765                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1766                 hdmi_set_reg(core->v_blank_f0, 2,
1767                         (m->vtotal + ((m->vsync_end - m->vsync_start) * 4) + 5) / 2);
1768                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1769                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1770                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1771                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1772                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1773                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1774                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1775                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1776                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1777                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1778                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1779                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1780         } else {
1781                 /* Progressive Mode */
1782                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1783                         m->vsync_end - m->vdisplay);
1784                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1785                         m->vsync_start - m->vdisplay);
1786                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1787                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1788                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1789                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1790                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1791                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1792                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1793                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1794                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1795                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1796                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1797                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1798                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1799         }
1800
1801         /* Following values & calculations are same irrespective of mode type */
1802         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1803         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1804         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1805         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1806         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1807         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1808         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1809         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1810         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1811         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1812         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1813         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1814         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1815         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1816         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1817         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1818         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1819         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1820         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1821         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1822
1823         /* Timing generator registers */
1824         hdmi_set_reg(tg->cmd, 1, 0x0);
1825         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1826         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1827         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1828         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1829         hdmi_set_reg(tg->vsync, 2, 0x1);
1830         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1831         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1832         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1833         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1834         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1835         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1836         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1837
1838         if (hdata->is_soc_exynos5) {
1839                 /* Workaround 4 implementation for 1440x900 resolution support */
1840                 if (m->hdisplay == 1440 && m->vdisplay == 900 && m->clock == 106500) {
1841                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0xe0);
1842                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0xe0);
1843                 }
1844
1845                 /* Workaround 3 implementation for 800x600 resolution support */
1846                 if (m->hdisplay == 800 && m->vdisplay == 600 && m->clock == 40000) {
1847                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0x20);
1848                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0x20);
1849                 }
1850         }
1851 }
1852
1853 static void hdmi_mode_set(void *ctx, void *mode)
1854 {
1855         struct hdmi_context *hdata = ctx;
1856
1857         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1858
1859         if (hdata->is_v13)
1860                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1861         else
1862                 hdmi_v14_mode_set(hdata, mode);
1863 }
1864
1865 static void hdmi_commit(void *ctx)
1866 {
1867         struct hdmi_context *hdata = ctx;
1868
1869         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1870         if (!hdata->is_hdmi_powered_on)
1871                 return;
1872
1873         hdmi_conf_apply(hdata);
1874         hdata->enabled = true;
1875 }
1876
1877 static void hdmi_apply(void *ctx)
1878 {
1879         hdmi_commit(ctx);
1880 }
1881
1882 static int hdmi_power_on(void *ctx, int mode)
1883 {
1884         struct hdmi_context *hdata = ctx;
1885
1886         switch (mode) {
1887         case DRM_MODE_DPMS_ON:
1888                 if (!hdata->is_hdmi_powered_on) {
1889                         pm_runtime_get_sync(hdata->dev);
1890                         hdmi_commit(ctx);
1891                 }
1892                 break;
1893         case DRM_MODE_DPMS_STANDBY:
1894                 break;
1895         case DRM_MODE_DPMS_SUSPEND:
1896                 break;
1897         case DRM_MODE_DPMS_OFF:
1898                 if (hdata->is_hdmi_powered_on)
1899                         pm_runtime_put_sync(hdata->dev);
1900                 break;
1901         default:
1902                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1903                 break;
1904         }
1905
1906         return 0;
1907 }
1908
1909 static int hdmi_subdrv_probe(void *ctx, struct drm_device *drm_dev)
1910 {
1911         struct hdmi_context *hdata = ctx;
1912
1913         hdata->drm_dev = drm_dev;
1914
1915         return 0;
1916 }
1917
1918 static struct exynos_panel_ops hdmi_ops = {
1919         /* display */
1920         .subdrv_probe   = hdmi_subdrv_probe,
1921         .is_connected   = hdmi_is_connected,
1922         .get_edid       = hdmi_get_edid,
1923         .check_timing   = hdmi_check_timing,
1924         .power          = hdmi_power_on,
1925
1926         /* manager */
1927         .mode_fixup     = hdmi_mode_fixup,
1928         .mode_set       = hdmi_mode_set,
1929         .commit         = hdmi_commit,
1930         .apply          = hdmi_apply,
1931 };
1932
1933 /*
1934  * Handle hotplug events outside the interrupt handler proper.
1935  */
1936 static void hdmi_hotplug_func(struct work_struct *work)
1937 {
1938         struct hdmi_context *hdata =
1939                 container_of(work, struct hdmi_context, hotplug_work);
1940
1941         drm_helper_hpd_irq_event(hdata->drm_dev);
1942 }
1943
1944 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
1945 {
1946         struct hdmi_context *hdata = arg;
1947         u32 intc_flag;
1948         if (hdata->is_hdmi_powered_on) {
1949                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
1950                 /* clearing flags for HPD plug/unplug */
1951                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
1952                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
1953                                 hdata->hpd_handle);
1954                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
1955                                 HDMI_INTC_FLAG_HPD_UNPLUG);
1956                 }
1957                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
1958                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
1959                                 hdata->hpd_handle);
1960                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
1961                                 HDMI_INTC_FLAG_HPD_PLUG);
1962                 }
1963         }
1964
1965         if (hdata->drm_dev && hdata->hpd_handle)
1966                 queue_work(hdata->wq, &hdata->hotplug_work);
1967
1968         return IRQ_HANDLED;
1969 }
1970
1971 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
1972 {
1973         struct device *dev = hdata->dev;
1974         struct hdmi_resources *res = &hdata->res;
1975 #ifndef CONFIG_ARCH_EXYNOS5
1976         static char *supply[] = {
1977                 "hdmi-en",
1978                 "vdd",
1979                 "vdd_osc",
1980                 "vdd_pll",
1981         };
1982         int i, ret;
1983 #endif
1984
1985         DRM_DEBUG_KMS("HDMI resource init\n");
1986
1987         memset(res, 0, sizeof *res);
1988
1989         /* get clocks, power */
1990         res->hdmi = clk_get(dev, "hdmi");
1991         if (IS_ERR_OR_NULL(res->hdmi)) {
1992                 DRM_ERROR("failed to get clock 'hdmi'\n");
1993                 goto fail;
1994         }
1995         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
1996         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
1997                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1998                 goto fail;
1999         }
2000         res->sclk_pixel = clk_get(dev, "sclk_pixel");
2001         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
2002                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2003                 goto fail;
2004         }
2005         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
2006         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
2007                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2008                 goto fail;
2009         }
2010         res->hdmiphy = clk_get(dev, "hdmiphy");
2011         if (IS_ERR_OR_NULL(res->hdmiphy)) {
2012                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2013                 goto fail;
2014         }
2015
2016         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2017
2018 #ifndef CONFIG_ARCH_EXYNOS5
2019         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2020                 sizeof res->regul_bulk[0], GFP_KERNEL);
2021         if (!res->regul_bulk) {
2022                 DRM_ERROR("failed to get memory for regulators\n");
2023                 goto fail;
2024         }
2025         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2026                 res->regul_bulk[i].supply = supply[i];
2027                 res->regul_bulk[i].consumer = NULL;
2028         }
2029         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2030         if (ret) {
2031                 DRM_ERROR("failed to get regulators\n");
2032                 goto fail;
2033         }
2034         res->regul_count = ARRAY_SIZE(supply);
2035 #endif
2036         /* TODO:
2037          * These clocks also should be added in
2038          * runtime resume and runtime suspend
2039          */
2040         clk_enable(res->hdmi);
2041         clk_enable(res->sclk_hdmi);
2042
2043         return 0;
2044 fail:
2045         DRM_ERROR("HDMI resource init - failed\n");
2046         return -ENODEV;
2047 }
2048
2049 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2050 {
2051         struct hdmi_resources *res = &hdata->res;
2052
2053         regulator_bulk_free(res->regul_count, res->regul_bulk);
2054         /* kfree is NULL-safe */
2055         kfree(res->regul_bulk);
2056         if (!IS_ERR_OR_NULL(res->hdmiphy))
2057                 clk_put(res->hdmiphy);
2058         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
2059                 clk_put(res->sclk_hdmiphy);
2060         if (!IS_ERR_OR_NULL(res->sclk_pixel))
2061                 clk_put(res->sclk_pixel);
2062         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
2063                 clk_put(res->sclk_hdmi);
2064         if (!IS_ERR_OR_NULL(res->hdmi))
2065                 clk_put(res->hdmi);
2066         memset(res, 0, sizeof *res);
2067
2068         return 0;
2069 }
2070
2071 static int hdmiphy_update_bits(struct i2c_client *client, u8 *reg_cache,
2072                                u8 reg, u8 mask, u8 val)
2073 {
2074         int ret;
2075         u8 buffer[2];
2076
2077         buffer[0] = reg;
2078         buffer[1] = (reg_cache[reg] & ~mask) | (val & mask);
2079         reg_cache[reg] = buffer[1];
2080
2081         ret = i2c_master_send(client, buffer, 2);
2082         if (ret != 2)
2083                 return -EIO;
2084
2085         return 0;
2086 }
2087
2088 static int hdmiphy_s_power(struct i2c_client *client, bool on)
2089 {
2090         u8 reg_cache[32] = { 0 };
2091         u8 buffer[2];
2092         int ret;
2093
2094         DRM_DEBUG_KMS("%s: hdmiphy is %s\n", __func__, on ? "on" : "off");
2095
2096         /* Cache all 32 registers to make the code below faster */
2097         buffer[0] = 0x0;
2098         ret = i2c_master_send(client, buffer, 1);
2099         if (ret != 1) {
2100                 ret = -EIO;
2101                 goto exit;
2102         }
2103         ret = i2c_master_recv(client, reg_cache, 32);
2104         if (ret != 32) {
2105                 ret = -EIO;
2106                 goto exit;
2107         }
2108
2109         /* Go to/from configuration from/to operation mode */
2110         ret = hdmiphy_update_bits(client, reg_cache, 0x1f, 0xff,
2111                                   on ? 0x80 : 0x00);
2112         if (ret)
2113                 goto exit;
2114
2115         /*
2116          * Turn off undocumented "oscpad" if !on; it turns on again in
2117          * hdmiphy_conf_apply()
2118          */
2119         if (!on)
2120                 ret = hdmiphy_update_bits(client, reg_cache, 0x0b, 0xc0, 0x00);
2121                 if (ret)
2122                         goto exit;
2123
2124         /* Disable powerdown if on; enable if !on */
2125         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x80,
2126                                   on ? 0 : ~0);
2127         if (ret)
2128                 goto exit;
2129         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x77,
2130                                   on ? 0 : ~0);
2131         if (ret)
2132                 goto exit;
2133
2134         /*
2135          * Turn off bit 3 of reg 4 if !on; it turns on again in
2136          * hdmiphy_conf_apply().  It's unclear what this bit does.
2137          */
2138         if (!on)
2139                 ret = hdmiphy_update_bits(client, reg_cache, 0x04, BIT(3), 0);
2140                 if (ret)
2141                         goto exit;
2142
2143 exit:
2144         /* Don't expect any errors so just do a single warn */
2145         WARN_ON(ret);
2146
2147         return ret;
2148 }
2149
2150 static void hdmi_resource_poweron(struct hdmi_context *hdata)
2151 {
2152         struct hdmi_resources *res = &hdata->res;
2153
2154         hdata->is_hdmi_powered_on = true;
2155         hdmi_cfg_hpd(hdata, false);
2156
2157         /* irq change by TV power status */
2158         if (hdata->curr_irq == hdata->internal_irq)
2159                 return;
2160
2161         disable_irq(hdata->curr_irq);
2162
2163         hdata->curr_irq = hdata->internal_irq;
2164
2165         enable_irq(hdata->curr_irq);
2166
2167         /* turn HDMI power on */
2168         regulator_bulk_enable(res->regul_count, res->regul_bulk);
2169
2170         /* power-on hdmi clocks */
2171         clk_enable(res->hdmiphy);
2172
2173         hdmiphy_s_power(hdata->hdmiphy_port, 1);
2174         hdmiphy_conf_reset(hdata);
2175         hdmi_conf_reset(hdata);
2176         hdmi_conf_init(hdata);
2177         if (!hdata->is_soc_exynos5)
2178                 hdmi_audio_init(hdata);
2179 }
2180
2181 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
2182 {
2183         struct hdmi_resources *res = &hdata->res;
2184
2185         hdmi_cfg_hpd(hdata, true);
2186
2187         if (hdata->curr_irq == hdata->external_irq)
2188                 return;
2189
2190         disable_irq(hdata->curr_irq);
2191         hdata->curr_irq = hdata->external_irq;
2192
2193         enable_irq(hdata->curr_irq);
2194         hdata->is_hdmi_powered_on = false;
2195
2196         hdmiphy_s_power(hdata->hdmiphy_port, 0);
2197         hdmiphy_conf_reset(hdata);
2198
2199         /* power-off hdmi clocks */
2200         clk_disable(res->hdmiphy);
2201
2202         /* turn HDMI power off */
2203         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2204 }
2205
2206 #ifdef CONFIG_PM_SLEEP
2207 static int hdmi_suspend(struct device *dev)
2208 {
2209         struct hdmi_context *hdata = get_hdmi_context(dev);
2210
2211         DRM_DEBUG_KMS("[hdmi] sleep suspend - start\n");
2212         if (pm_runtime_suspended(dev)) {
2213                 DRM_DEBUG_KMS("[hdmi] sleep suspend - already suspended\n");
2214                 return 0;
2215         }
2216
2217         hdmi_resource_poweroff(hdata);
2218         DRM_DEBUG_KMS("[hdmi] sleep suspend - end\n");
2219
2220         return 0;
2221 }
2222 static int hdmi_resume(struct device *dev)
2223 {
2224         struct hdmi_context *hdata = get_hdmi_context(dev);
2225
2226         DRM_DEBUG_KMS("[hdmi] sleep resume - start\n");
2227
2228         if (!pm_runtime_suspended(dev)) {
2229                 hdmi_resource_poweron(hdata);
2230                 hdmi_commit(hdata);
2231                 DRM_DEBUG_KMS("[hdmi] sleep resuming\n");
2232         }
2233         DRM_DEBUG_KMS("[hdmi] sleep resume - end\n");
2234         return 0;
2235 }
2236 #endif
2237 #ifdef CONFIG_PM_RUNTIME
2238 static int hdmi_runtime_suspend(struct device *dev)
2239 {
2240         struct hdmi_context *hdata = get_hdmi_context(dev);
2241
2242         DRM_DEBUG_KMS("[hdmi] runtime suspend - start\n");
2243         hdmi_resource_poweroff(hdata);
2244         DRM_DEBUG_KMS("[hdmi] runtime suspend - end\n");
2245
2246         return 0;
2247 }
2248
2249 static int hdmi_runtime_resume(struct device *dev)
2250 {
2251         struct hdmi_context *hdata = get_hdmi_context(dev);
2252
2253         DRM_DEBUG_KMS("[hdmi] runtime resume - start\n");
2254
2255         hdmi_resource_poweron(hdata);
2256
2257         DRM_DEBUG_KMS("[hdmi] runtime resume - end\n");
2258         return 0;
2259 }
2260 #endif
2261 static const struct dev_pm_ops hdmi_pm_ops = {
2262         SET_SYSTEM_SLEEP_PM_OPS(hdmi_suspend, hdmi_resume)
2263         SET_RUNTIME_PM_OPS(hdmi_runtime_suspend, hdmi_runtime_resume, NULL)
2264 };
2265
2266 static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
2267
2268 void hdmi_attach_ddc_client(struct i2c_client *ddc)
2269 {
2270         if (ddc)
2271                 hdmi_ddc = ddc;
2272 }
2273
2274 void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
2275 {
2276         if (hdmiphy)
2277                 hdmi_hdmiphy = hdmiphy;
2278 }
2279
2280 struct platform_device *hdmi_audio_device;
2281
2282 int hdmi_register_audio_device(struct platform_device *pdev)
2283 {
2284         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2285         struct platform_device *audio_dev;
2286         int ret;
2287
2288         audio_dev = platform_device_alloc("exynos-hdmi-audio", -1);
2289         if (!audio_dev) {
2290                 DRM_ERROR("hdmi audio device allocation failed.\n");
2291                 ret = -ENOMEM;
2292                 goto err;
2293         }
2294
2295         ret = platform_device_add_resources(audio_dev, pdev->resource,
2296                         pdev->num_resources);
2297         if (ret) {
2298                 ret = -ENOMEM;
2299                 goto err_device;
2300         }
2301
2302         audio_dev->dev.of_node = of_get_next_child(pdev->dev.of_node, NULL);
2303         audio_dev->dev.platform_data = (void *)hdata->hpd_gpio;
2304
2305         ret = platform_device_add(audio_dev);
2306         if (ret) {
2307                 DRM_ERROR("hdmi audio device add failed.\n");
2308                 goto err_device;
2309         }
2310
2311         hdmi_audio_device = audio_dev;
2312         return 0;
2313
2314 err_device:
2315         platform_device_put(audio_dev);
2316
2317 err:
2318         return ret;
2319 }
2320
2321 void hdmi_unregister_audio_device(void)
2322 {
2323         platform_device_unregister(hdmi_audio_device);
2324 }
2325
2326 static int __devinit hdmi_probe(struct platform_device *pdev)
2327 {
2328         struct device *dev = &pdev->dev;
2329         struct hdmi_context *hdata;
2330         struct exynos_drm_hdmi_pdata *pdata;
2331         struct resource *res;
2332         int ret;
2333         enum of_gpio_flags flags;
2334
2335         DRM_DEBUG_KMS("[%d]\n", __LINE__);
2336
2337         pdata = pdev->dev.platform_data;
2338         if (!pdata) {
2339                 DRM_ERROR("no platform data specified\n");
2340                 return -EINVAL;
2341         }
2342
2343         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2344         if (!hdata) {
2345                 DRM_ERROR("out of memory\n");
2346                 return -ENOMEM;
2347         }
2348
2349         platform_set_drvdata(pdev, hdata);
2350
2351         hdata->is_v13 = pdata->is_v13;
2352         hdata->default_win = pdata->default_win;
2353         hdata->default_timing = &pdata->timing;
2354         hdata->default_bpp = pdata->bpp;
2355         hdata->dev = dev;
2356         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2357                 "samsung,exynos5-hdmi");
2358
2359         ret = hdmi_resources_init(hdata);
2360         if (ret) {
2361                 ret = -EINVAL;
2362                 goto err_data;
2363         }
2364
2365         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2366         if (!res) {
2367                 DRM_ERROR("failed to find registers\n");
2368                 ret = -ENOENT;
2369                 goto err_resource;
2370         }
2371
2372         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2373                                            dev_name(dev));
2374         if (!hdata->regs_res) {
2375                 DRM_ERROR("failed to claim register region\n");
2376                 ret = -ENOENT;
2377                 goto err_resource;
2378         }
2379
2380         hdata->regs = ioremap(res->start, resource_size(res));
2381         if (!hdata->regs) {
2382                 DRM_ERROR("failed to map registers\n");
2383                 ret = -ENXIO;
2384                 goto err_req_region;
2385         }
2386
2387         /* DDC i2c driver */
2388         if (i2c_add_driver(&ddc_driver)) {
2389                 DRM_ERROR("failed to register ddc i2c driver\n");
2390                 ret = -ENOENT;
2391                 goto err_iomap;
2392         }
2393
2394         hdata->ddc_port = hdmi_ddc;
2395
2396         /* hdmiphy i2c driver */
2397         if (i2c_add_driver(&hdmiphy_driver)) {
2398                 DRM_ERROR("failed to register hdmiphy i2c driver\n");
2399                 ret = -ENOENT;
2400                 goto err_ddc;
2401         }
2402
2403         hdata->hdmiphy_port = hdmi_hdmiphy;
2404
2405         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2406         if (res == NULL) {
2407                 DRM_ERROR("get interrupt resource failed.\n");
2408                 ret = -ENXIO;
2409                 goto err_hdmiphy;
2410         }
2411
2412         hdata->internal_irq = res->start;
2413
2414         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2415                                 "hpd-gpio", 0, &flags);
2416
2417         if (!gpio_is_valid(hdata->hpd_gpio)) {
2418                 DRM_ERROR("failed to get hpd gpio.");
2419                 ret = -EINVAL;
2420                 goto err_hdmiphy;
2421         }
2422
2423         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2424
2425         /* create workqueue and hotplug work */
2426         hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2427                         WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2428         if (hdata->wq == NULL) {
2429                 DRM_ERROR("Failed to create workqueue.\n");
2430                 ret = -ENOMEM;
2431                 goto err_hdmiphy;
2432         }
2433         INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2434
2435         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2436                         IRQF_SHARED, "int_hdmi", hdata);
2437         if (ret) {
2438                 DRM_ERROR("request int interrupt failed.\n");
2439                 goto err_workqueue;
2440         }
2441         disable_irq(hdata->internal_irq);
2442
2443         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2444                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2445                 hdata);
2446         if (ret) {
2447                 DRM_ERROR("request ext interrupt failed.\n");
2448                 goto err_int_irq;
2449         }
2450         disable_irq(hdata->external_irq);
2451
2452         if (of_device_is_compatible(dev->of_node,
2453                 "samsung,exynos5-hdmi")) {
2454                 ret = hdmi_register_audio_device(pdev);
2455                 if (ret) {
2456                         DRM_ERROR("hdmi-audio device registering failed.\n");
2457                         goto err_ext_irq;
2458                 }
2459         }
2460
2461         hdmi_resource_poweron(hdata);
2462         pm_runtime_enable(dev);
2463
2464         if (!hdmi_is_connected(hdata)) {
2465                 hdmi_resource_poweroff(hdata);
2466                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2467         } else {
2468                 pm_runtime_get_sync(dev);
2469         }
2470
2471         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_MIXER, &hdmi_ops,
2472                         hdata);
2473
2474         return 0;
2475
2476 err_ext_irq:
2477         free_irq(hdata->external_irq, hdata);
2478 err_int_irq:
2479         free_irq(hdata->internal_irq, hdata);
2480  err_workqueue:
2481         destroy_workqueue(hdata->wq);
2482 err_hdmiphy:
2483         i2c_del_driver(&hdmiphy_driver);
2484 err_ddc:
2485         i2c_del_driver(&ddc_driver);
2486 err_iomap:
2487         iounmap(hdata->regs);
2488 err_req_region:
2489         release_mem_region(hdata->regs_res->start,
2490                         resource_size(hdata->regs_res));
2491 err_resource:
2492         hdmi_resources_cleanup(hdata);
2493 err_data:
2494         kfree(hdata);
2495         return ret;
2496 }
2497
2498 static int __devexit hdmi_remove(struct platform_device *pdev)
2499 {
2500         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2501         struct hdmi_resources *res = &hdata->res;
2502
2503         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2504
2505         hdmi_resource_poweroff(hdata);
2506
2507         hdmi_unregister_audio_device();
2508
2509         disable_irq(hdata->curr_irq);
2510         free_irq(hdata->internal_irq, hdata);
2511         free_irq(hdata->external_irq, hdata);
2512
2513         cancel_work_sync(&hdata->hotplug_work);
2514         destroy_workqueue(hdata->wq);
2515
2516         clk_disable(res->hdmi);
2517         clk_disable(res->sclk_hdmi);
2518         hdmi_resources_cleanup(hdata);
2519
2520         iounmap(hdata->regs);
2521
2522         release_mem_region(hdata->regs_res->start,
2523                         resource_size(hdata->regs_res));
2524
2525         /* hdmiphy i2c driver */
2526         i2c_del_driver(&hdmiphy_driver);
2527         /* DDC i2c driver */
2528         i2c_del_driver(&ddc_driver);
2529
2530         kfree(hdata);
2531
2532         return 0;
2533 }
2534
2535 struct platform_driver hdmi_driver = {
2536         .probe          = hdmi_probe,
2537         .remove         = __devexit_p(hdmi_remove),
2538         .driver         = {
2539 #ifdef CONFIG_ARCH_EXYNOS5
2540                 .name   = "exynos5-hdmi",
2541 #else
2542                 .name   = "exynos4-hdmi",
2543 #endif
2544                 .owner  = THIS_MODULE,
2545                 .pm = &hdmi_pm_ops,
2546         },
2547 };