drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_crtc_helper.h>
  20
  21 #include "regs-hdmi.h"
  22
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/wait.h>
  26 #include <linux/i2c.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/io.h>
  35 #include <linux/of.h>
  36 #include <linux/of_address.h>
  37 #include <linux/of_gpio.h>
  38 #include <linux/hdmi.h>
  39 #include <linux/component.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/regmap.h>
  42
  43 #include <drm/exynos_drm.h>
  44
  45 #include "exynos_drm_drv.h"
  46 #include "exynos_drm_crtc.h"
  47 #include "exynos_mixer.h"
  48
  49 #include <linux/gpio.h>
  50 #include <media/s5p_hdmi.h>
  51
  52 #define get_hdmi_display(dev)   platform_get_drvdata(to_platform_device(dev))
  53 #define ctx_from_connector(c)   container_of(c, struct hdmi_context, connector)
  54
  55 #define HOTPLUG_DEBOUNCE_MS             1100
  56
  57 /* AVI header and aspect ratio */
  58 #define HDMI_AVI_VERSION                0x02
  59 #define HDMI_AVI_LENGTH         0x0D
  60
  61 /* AUI header info */
  62 #define HDMI_AUI_VERSION        0x01
  63 #define HDMI_AUI_LENGTH 0x0A
  64 #define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
  65 #define AVI_4_3_CENTER_RATIO    0x9
  66 #define AVI_16_9_CENTER_RATIO   0xa
  67
  68 enum hdmi_type {
  69         HDMI_TYPE13,
  70         HDMI_TYPE14,
  71 };
  72
  73 struct hdmi_driver_data {
  74         unsigned int type;
  75         const struct hdmiphy_config *phy_confs;
  76         unsigned int phy_conf_count;
  77         unsigned int is_apb_phy:1;
  78 };
  79
  80 struct hdmi_resources {
  81         struct clk                      *hdmi;
  82         struct clk                      *sclk_hdmi;
  83         struct clk                      *sclk_pixel;
  84         struct clk                      *sclk_hdmiphy;
  85         struct clk                      *mout_hdmi;
  86         struct regulator_bulk_data      *regul_bulk;
  87         struct regulator                *reg_hdmi_en;
  88         int                             regul_count;
  89 };
  90
  91 struct hdmi_tg_regs {
  92         u8 cmd[1];
  93         u8 h_fsz[2];
  94         u8 hact_st[2];
  95         u8 hact_sz[2];
  96         u8 v_fsz[2];
  97         u8 vsync[2];
  98         u8 vsync2[2];
  99         u8 vact_st[2];
 100         u8 vact_sz[2];
 101         u8 field_chg[2];
 102         u8 vact_st2[2];
 103         u8 vact_st3[2];
 104         u8 vact_st4[2];
 105         u8 vsync_top_hdmi[2];
 106         u8 vsync_bot_hdmi[2];
 107         u8 field_top_hdmi[2];
 108         u8 field_bot_hdmi[2];
 109         u8 tg_3d[1];
 110 };
 111
 112 struct hdmi_v13_core_regs {
 113         u8 h_blank[2];
 114         u8 v_blank[3];
 115         u8 h_v_line[3];
 116         u8 vsync_pol[1];
 117         u8 int_pro_mode[1];
 118         u8 v_blank_f[3];
 119         u8 h_sync_gen[3];
 120         u8 v_sync_gen1[3];
 121         u8 v_sync_gen2[3];
 122         u8 v_sync_gen3[3];
 123 };
 124
 125 struct hdmi_v14_core_regs {
 126         u8 h_blank[2];
 127         u8 v2_blank[2];
 128         u8 v1_blank[2];
 129         u8 v_line[2];
 130         u8 h_line[2];
 131         u8 hsync_pol[1];
 132         u8 vsync_pol[1];
 133         u8 int_pro_mode[1];
 134         u8 v_blank_f0[2];
 135         u8 v_blank_f1[2];
 136         u8 h_sync_start[2];
 137         u8 h_sync_end[2];
 138         u8 v_sync_line_bef_2[2];
 139         u8 v_sync_line_bef_1[2];
 140         u8 v_sync_line_aft_2[2];
 141         u8 v_sync_line_aft_1[2];
 142         u8 v_sync_line_aft_pxl_2[2];
 143         u8 v_sync_line_aft_pxl_1[2];
 144         u8 v_blank_f2[2]; /* for 3D mode */
 145         u8 v_blank_f3[2]; /* for 3D mode */
 146         u8 v_blank_f4[2]; /* for 3D mode */
 147         u8 v_blank_f5[2]; /* for 3D mode */
 148         u8 v_sync_line_aft_3[2];
 149         u8 v_sync_line_aft_4[2];
 150         u8 v_sync_line_aft_5[2];
 151         u8 v_sync_line_aft_6[2];
 152         u8 v_sync_line_aft_pxl_3[2];
 153         u8 v_sync_line_aft_pxl_4[2];
 154         u8 v_sync_line_aft_pxl_5[2];
 155         u8 v_sync_line_aft_pxl_6[2];
 156         u8 vact_space_1[2];
 157         u8 vact_space_2[2];
 158         u8 vact_space_3[2];
 159         u8 vact_space_4[2];
 160         u8 vact_space_5[2];
 161         u8 vact_space_6[2];
 162 };
 163
 164 struct hdmi_v13_conf {
 165         struct hdmi_v13_core_regs core;
 166         struct hdmi_tg_regs tg;
 167 };
 168
 169 struct hdmi_v14_conf {
 170         struct hdmi_v14_core_regs core;
 171         struct hdmi_tg_regs tg;
 172 };
 173
 174 struct hdmi_conf_regs {
 175         int pixel_clock;
 176         int cea_video_id;
 177         enum hdmi_picture_aspect aspect_ratio;
 178         union {
 179                 struct hdmi_v13_conf v13_conf;
 180                 struct hdmi_v14_conf v14_conf;
 181         } conf;
 182 };
 183
 184 struct hdmi_context {
 185         struct device                   *dev;
 186         struct drm_device               *drm_dev;
 187         struct drm_connector            connector;
 188         struct drm_encoder              *encoder;
 189         bool                            hpd;
 190         bool                            powered;
 191         bool                            dvi_mode;
 192         struct mutex                    hdmi_mutex;
 193
 194         void __iomem                    *regs;
 195         int                             irq;
 196         struct delayed_work             hotplug_work;
 197
 198         struct i2c_adapter              *ddc_adpt;
 199         struct i2c_client               *hdmiphy_port;
 200
 201         /* current hdmiphy conf regs */
 202         struct drm_display_mode         current_mode;
 203         struct hdmi_conf_regs           mode_conf;
 204
 205         struct hdmi_resources           res;
 206
 207         int                             hpd_gpio;
 208         void __iomem                    *regs_hdmiphy;
 209         const struct hdmiphy_config             *phy_confs;
 210         unsigned int                    phy_conf_count;
 211
 212         struct regmap                   *pmureg;
 213         enum hdmi_type                  type;
 214 };
 215
 216 struct hdmiphy_config {
 217         int pixel_clock;
 218         u8 conf[32];
 219 };
 220
 221 /* list of phy config settings */
 222 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
 223         {
 224                 .pixel_clock = 27000000,
 225                 .conf = {
 226                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 227                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 228                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 229                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 230                 },
 231         },
 232         {
 233                 .pixel_clock = 27027000,
 234                 .conf = {
 235                         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 236                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 237                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 238                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 239                 },
 240         },
 241         {
 242                 .pixel_clock = 74176000,
 243                 .conf = {
 244                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 245                         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 246                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 247                         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 248                 },
 249         },
 250         {
 251                 .pixel_clock = 74250000,
 252                 .conf = {
 253                         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 254                         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 255                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 256                         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 257                 },
 258         },
 259         {
 260                 .pixel_clock = 148500000,
 261                 .conf = {
 262                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 263                         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 264                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 265                         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 266                 },
 267         },
 268 };
 269
 270 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
 271         {
 272                 .pixel_clock = 25200000,
 273                 .conf = {
 274                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 275                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 276                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 277                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 278                 },
 279         },
 280         {
 281                 .pixel_clock = 27000000,
 282                 .conf = {
 283                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 284                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 285                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 286                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 287                 },
 288         },
 289         {
 290                 .pixel_clock = 27027000,
 291                 .conf = {
 292                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 293                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 294                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 295                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 296                 },
 297         },
 298         {
 299                 .pixel_clock = 36000000,
 300                 .conf = {
 301                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 302                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 303                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 304                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 305                 },
 306         },
 307         {
 308                 .pixel_clock = 40000000,
 309                 .conf = {
 310                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 311                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 312                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 313                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 314                 },
 315         },
 316         {
 317                 .pixel_clock = 65000000,
 318                 .conf = {
 319                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 320                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 321                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 322                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 323                 },
 324         },
 325         {
 326                 .pixel_clock = 71000000,
 327                 .conf = {
 328                         0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
 329                         0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 330                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 331                         0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 332                 },
 333         },
 334         {
 335                 .pixel_clock = 73250000,
 336                 .conf = {
 337                         0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
 338                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 339                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 340                         0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 341                 },
 342         },
 343         {
 344                 .pixel_clock = 74176000,
 345                 .conf = {
 346                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 347                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 348                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 349                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 350                 },
 351         },
 352         {
 353                 .pixel_clock = 74250000,
 354                 .conf = {
 355                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 356                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 357                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 358                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 359                 },
 360         },
 361         {
 362                 .pixel_clock = 83500000,
 363                 .conf = {
 364                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 365                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 366                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 367                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 368                 },
 369         },
 370         {
 371                 .pixel_clock = 106500000,
 372                 .conf = {
 373                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 374                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 375                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 376                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 377                 },
 378         },
 379         {
 380                 .pixel_clock = 108000000,
 381                 .conf = {
 382                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 383                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 384                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 385                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 386                 },
 387         },
 388         {
 389                 .pixel_clock = 115500000,
 390                 .conf = {
 391                         0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
 392                         0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 393                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 394                         0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 395                 },
 396         },
 397         {
 398                 .pixel_clock = 119000000,
 399                 .conf = {
 400                         0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
 401                         0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 402                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 403                         0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 404                 },
 405         },
 406         {
 407                 .pixel_clock = 146250000,
 408                 .conf = {
 409                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 410                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 411                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 412                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 413                 },
 414         },
 415         {
 416                 .pixel_clock = 148500000,
 417                 .conf = {
 418                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 419                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 420                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 421                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 422                 },
 423         },
 424 };
 425
 426 static const struct hdmiphy_config hdmiphy_5420_configs[] = {
 427         {
 428                 .pixel_clock = 25200000,
 429                 .conf = {
 430                         0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
 431                         0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 432                         0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
 433                         0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 434                 },
 435         },
 436         {
 437                 .pixel_clock = 27000000,
 438                 .conf = {
 439                         0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
 440                         0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 441                         0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 442                         0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 443                 },
 444         },
 445         {
 446                 .pixel_clock = 27027000,
 447                 .conf = {
 448                         0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
 449                         0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 450                         0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 451                         0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 452                 },
 453         },
 454         {
 455                 .pixel_clock = 36000000,
 456                 .conf = {
 457                         0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
 458                         0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 459                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 460                         0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 461                 },
 462         },
 463         {
 464                 .pixel_clock = 40000000,
 465                 .conf = {
 466                         0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
 467                         0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 468                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 469                         0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 470                 },
 471         },
 472         {
 473                 .pixel_clock = 65000000,
 474                 .conf = {
 475                         0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
 476                         0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 477                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 478                         0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 479                 },
 480         },
 481         {
 482                 .pixel_clock = 71000000,
 483                 .conf = {
 484                         0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
 485                         0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 486                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 487                         0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 488                 },
 489         },
 490         {
 491                 .pixel_clock = 73250000,
 492                 .conf = {
 493                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
 494                         0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 495                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 496                         0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 497                 },
 498         },
 499         {
 500                 .pixel_clock = 74176000,
 501                 .conf = {
 502                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
 503                         0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 504                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 505                         0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 506                 },
 507         },
 508         {
 509                 .pixel_clock = 74250000,
 510                 .conf = {
 511                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
 512                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 513                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 514                         0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 515                 },
 516         },
 517         {
 518                 .pixel_clock = 83500000,
 519                 .conf = {
 520                         0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
 521                         0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 522                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 523                         0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 524                 },
 525         },
 526         {
 527                 .pixel_clock = 88750000,
 528                 .conf = {
 529                         0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
 530                         0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 531                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 532                         0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 533                 },
 534         },
 535         {
 536                 .pixel_clock = 106500000,
 537                 .conf = {
 538                         0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
 539                         0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 540                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 541                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 542                 },
 543         },
 544         {
 545                 .pixel_clock = 108000000,
 546                 .conf = {
 547                         0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
 548                         0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 549                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 550                         0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 551                 },
 552         },
 553         {
 554                 .pixel_clock = 115500000,
 555                 .conf = {
 556                         0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
 557                         0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 558                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 559                         0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 560                 },
 561         },
 562         {
 563                 .pixel_clock = 146250000,
 564                 .conf = {
 565                         0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
 566                         0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 567                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 568                         0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 569                 },
 570         },
 571         {
 572                 .pixel_clock = 148500000,
 573                 .conf = {
 574                         0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
 575                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 576                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 577                         0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
 578                 },
 579         },
 580 };
 581
 582 static struct hdmi_driver_data exynos5420_hdmi_driver_data = {
 583         .type           = HDMI_TYPE14,
 584         .phy_confs      = hdmiphy_5420_configs,
 585         .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs),
 586         .is_apb_phy     = 1,
 587 };
 588
 589 static struct hdmi_driver_data exynos4212_hdmi_driver_data = {
 590         .type           = HDMI_TYPE14,
 591         .phy_confs      = hdmiphy_v14_configs,
 592         .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs),
 593         .is_apb_phy     = 0,
 594 };
 595
 596 static struct hdmi_driver_data exynos4210_hdmi_driver_data = {
 597         .type           = HDMI_TYPE13,
 598         .phy_confs      = hdmiphy_v13_configs,
 599         .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
 600         .is_apb_phy     = 0,
 601 };
 602
 603 static struct hdmi_driver_data exynos5_hdmi_driver_data = {
 604         .type           = HDMI_TYPE14,
 605         .phy_confs      = hdmiphy_v13_configs,
 606         .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs),
 607         .is_apb_phy     = 0,
 608 };
 609
 610 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 611 {
 612         return readl(hdata->regs + reg_id);
 613 }
 614
 615 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 616                                  u32 reg_id, u8 value)
 617 {
 618         writeb(value, hdata->regs + reg_id);
 619 }
 620
 621 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 622                                  u32 reg_id, u32 value, u32 mask)
 623 {
 624         u32 old = readl(hdata->regs + reg_id);
 625         value = (value & mask) | (old & ~mask);
 626         writel(value, hdata->regs + reg_id);
 627 }
 628
 629 static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
 630                         u32 reg_offset, u8 value)
 631 {
 632         if (hdata->hdmiphy_port) {
 633                 u8 buffer[2];
 634                 int ret;
 635
 636                 buffer[0] = reg_offset;
 637                 buffer[1] = value;
 638
 639                 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
 640                 if (ret == 2)
 641                         return 0;
 642                 return ret;
 643         } else {
 644                 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
 645                 return 0;
 646         }
 647 }
 648
 649 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
 650                         u32 reg_offset, const u8 *buf, u32 len)
 651 {
 652         if ((reg_offset + len) > 32)
 653                 return -EINVAL;
 654
 655         if (hdata->hdmiphy_port) {
 656                 int ret;
 657
 658                 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
 659                 if (ret == len)
 660                         return 0;
 661                 return ret;
 662         } else {
 663                 int i;
 664                 for (i = 0; i < len; i++)
 665                         writeb(buf[i], hdata->regs_hdmiphy +
 666                                 ((reg_offset + i)<<2));
 667                 return 0;
 668         }
 669 }
 670
 671 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 672 {
 673 #define DUMPREG(reg_id) \
 674         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 675         readl(hdata->regs + reg_id))
 676         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 677         DUMPREG(HDMI_INTC_FLAG);
 678         DUMPREG(HDMI_INTC_CON);
 679         DUMPREG(HDMI_HPD_STATUS);
 680         DUMPREG(HDMI_V13_PHY_RSTOUT);
 681         DUMPREG(HDMI_V13_PHY_VPLL);
 682         DUMPREG(HDMI_V13_PHY_CMU);
 683         DUMPREG(HDMI_V13_CORE_RSTOUT);
 684
 685         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 686         DUMPREG(HDMI_CON_0);
 687         DUMPREG(HDMI_CON_1);
 688         DUMPREG(HDMI_CON_2);
 689         DUMPREG(HDMI_SYS_STATUS);
 690         DUMPREG(HDMI_V13_PHY_STATUS);
 691         DUMPREG(HDMI_STATUS_EN);
 692         DUMPREG(HDMI_HPD);
 693         DUMPREG(HDMI_MODE_SEL);
 694         DUMPREG(HDMI_V13_HPD_GEN);
 695         DUMPREG(HDMI_V13_DC_CONTROL);
 696         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 697
 698         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 699         DUMPREG(HDMI_H_BLANK_0);
 700         DUMPREG(HDMI_H_BLANK_1);
 701         DUMPREG(HDMI_V13_V_BLANK_0);
 702         DUMPREG(HDMI_V13_V_BLANK_1);
 703         DUMPREG(HDMI_V13_V_BLANK_2);
 704         DUMPREG(HDMI_V13_H_V_LINE_0);
 705         DUMPREG(HDMI_V13_H_V_LINE_1);
 706         DUMPREG(HDMI_V13_H_V_LINE_2);
 707         DUMPREG(HDMI_VSYNC_POL);
 708         DUMPREG(HDMI_INT_PRO_MODE);
 709         DUMPREG(HDMI_V13_V_BLANK_F_0);
 710         DUMPREG(HDMI_V13_V_BLANK_F_1);
 711         DUMPREG(HDMI_V13_V_BLANK_F_2);
 712         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 713         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 714         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 715         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 716         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 717         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 718         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 719         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 720         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 721         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 722         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 723         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 724
 725         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 726         DUMPREG(HDMI_TG_CMD);
 727         DUMPREG(HDMI_TG_H_FSZ_L);
 728         DUMPREG(HDMI_TG_H_FSZ_H);
 729         DUMPREG(HDMI_TG_HACT_ST_L);
 730         DUMPREG(HDMI_TG_HACT_ST_H);
 731         DUMPREG(HDMI_TG_HACT_SZ_L);
 732         DUMPREG(HDMI_TG_HACT_SZ_H);
 733         DUMPREG(HDMI_TG_V_FSZ_L);
 734         DUMPREG(HDMI_TG_V_FSZ_H);
 735         DUMPREG(HDMI_TG_VSYNC_L);
 736         DUMPREG(HDMI_TG_VSYNC_H);
 737         DUMPREG(HDMI_TG_VSYNC2_L);
 738         DUMPREG(HDMI_TG_VSYNC2_H);
 739         DUMPREG(HDMI_TG_VACT_ST_L);
 740         DUMPREG(HDMI_TG_VACT_ST_H);
 741         DUMPREG(HDMI_TG_VACT_SZ_L);
 742         DUMPREG(HDMI_TG_VACT_SZ_H);
 743         DUMPREG(HDMI_TG_FIELD_CHG_L);
 744         DUMPREG(HDMI_TG_FIELD_CHG_H);
 745         DUMPREG(HDMI_TG_VACT_ST2_L);
 746         DUMPREG(HDMI_TG_VACT_ST2_H);
 747         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 748         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 749         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 750         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 751         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 752         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 753         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 754         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 755 #undef DUMPREG
 756 }
 757
 758 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 759 {
 760         int i;
 761
 762 #define DUMPREG(reg_id) \
 763         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 764         readl(hdata->regs + reg_id))
 765
 766         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 767         DUMPREG(HDMI_INTC_CON);
 768         DUMPREG(HDMI_INTC_FLAG);
 769         DUMPREG(HDMI_HPD_STATUS);
 770         DUMPREG(HDMI_INTC_CON_1);
 771         DUMPREG(HDMI_INTC_FLAG_1);
 772         DUMPREG(HDMI_PHY_STATUS_0);
 773         DUMPREG(HDMI_PHY_STATUS_PLL);
 774         DUMPREG(HDMI_PHY_CON_0);
 775         DUMPREG(HDMI_PHY_RSTOUT);
 776         DUMPREG(HDMI_PHY_VPLL);
 777         DUMPREG(HDMI_PHY_CMU);
 778         DUMPREG(HDMI_CORE_RSTOUT);
 779
 780         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 781         DUMPREG(HDMI_CON_0);
 782         DUMPREG(HDMI_CON_1);
 783         DUMPREG(HDMI_CON_2);
 784         DUMPREG(HDMI_SYS_STATUS);
 785         DUMPREG(HDMI_PHY_STATUS_0);
 786         DUMPREG(HDMI_STATUS_EN);
 787         DUMPREG(HDMI_HPD);
 788         DUMPREG(HDMI_MODE_SEL);
 789         DUMPREG(HDMI_ENC_EN);
 790         DUMPREG(HDMI_DC_CONTROL);
 791         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 792
 793         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 794         DUMPREG(HDMI_H_BLANK_0);
 795         DUMPREG(HDMI_H_BLANK_1);
 796         DUMPREG(HDMI_V2_BLANK_0);
 797         DUMPREG(HDMI_V2_BLANK_1);
 798         DUMPREG(HDMI_V1_BLANK_0);
 799         DUMPREG(HDMI_V1_BLANK_1);
 800         DUMPREG(HDMI_V_LINE_0);
 801         DUMPREG(HDMI_V_LINE_1);
 802         DUMPREG(HDMI_H_LINE_0);
 803         DUMPREG(HDMI_H_LINE_1);
 804         DUMPREG(HDMI_HSYNC_POL);
 805
 806         DUMPREG(HDMI_VSYNC_POL);
 807         DUMPREG(HDMI_INT_PRO_MODE);
 808         DUMPREG(HDMI_V_BLANK_F0_0);
 809         DUMPREG(HDMI_V_BLANK_F0_1);
 810         DUMPREG(HDMI_V_BLANK_F1_0);
 811         DUMPREG(HDMI_V_BLANK_F1_1);
 812
 813         DUMPREG(HDMI_H_SYNC_START_0);
 814         DUMPREG(HDMI_H_SYNC_START_1);
 815         DUMPREG(HDMI_H_SYNC_END_0);
 816         DUMPREG(HDMI_H_SYNC_END_1);
 817
 818         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 819         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 820         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 821         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 822
 823         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 824         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 825         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 826         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 827
 828         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 829         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 830         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 831         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 832
 833         DUMPREG(HDMI_V_BLANK_F2_0);
 834         DUMPREG(HDMI_V_BLANK_F2_1);
 835         DUMPREG(HDMI_V_BLANK_F3_0);
 836         DUMPREG(HDMI_V_BLANK_F3_1);
 837         DUMPREG(HDMI_V_BLANK_F4_0);
 838         DUMPREG(HDMI_V_BLANK_F4_1);
 839         DUMPREG(HDMI_V_BLANK_F5_0);
 840         DUMPREG(HDMI_V_BLANK_F5_1);
 841
 842         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 843         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 844         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 845         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 846         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 847         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 848         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 849         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 850
 851         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 852         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 853         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 854         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 855         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 856         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 857         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 858         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 859
 860         DUMPREG(HDMI_VACT_SPACE_1_0);
 861         DUMPREG(HDMI_VACT_SPACE_1_1);
 862         DUMPREG(HDMI_VACT_SPACE_2_0);
 863         DUMPREG(HDMI_VACT_SPACE_2_1);
 864         DUMPREG(HDMI_VACT_SPACE_3_0);
 865         DUMPREG(HDMI_VACT_SPACE_3_1);
 866         DUMPREG(HDMI_VACT_SPACE_4_0);
 867         DUMPREG(HDMI_VACT_SPACE_4_1);
 868         DUMPREG(HDMI_VACT_SPACE_5_0);
 869         DUMPREG(HDMI_VACT_SPACE_5_1);
 870         DUMPREG(HDMI_VACT_SPACE_6_0);
 871         DUMPREG(HDMI_VACT_SPACE_6_1);
 872
 873         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 874         DUMPREG(HDMI_TG_CMD);
 875         DUMPREG(HDMI_TG_H_FSZ_L);
 876         DUMPREG(HDMI_TG_H_FSZ_H);
 877         DUMPREG(HDMI_TG_HACT_ST_L);
 878         DUMPREG(HDMI_TG_HACT_ST_H);
 879         DUMPREG(HDMI_TG_HACT_SZ_L);
 880         DUMPREG(HDMI_TG_HACT_SZ_H);
 881         DUMPREG(HDMI_TG_V_FSZ_L);
 882         DUMPREG(HDMI_TG_V_FSZ_H);
 883         DUMPREG(HDMI_TG_VSYNC_L);
 884         DUMPREG(HDMI_TG_VSYNC_H);
 885         DUMPREG(HDMI_TG_VSYNC2_L);
 886         DUMPREG(HDMI_TG_VSYNC2_H);
 887         DUMPREG(HDMI_TG_VACT_ST_L);
 888         DUMPREG(HDMI_TG_VACT_ST_H);
 889         DUMPREG(HDMI_TG_VACT_SZ_L);
 890         DUMPREG(HDMI_TG_VACT_SZ_H);
 891         DUMPREG(HDMI_TG_FIELD_CHG_L);
 892         DUMPREG(HDMI_TG_FIELD_CHG_H);
 893         DUMPREG(HDMI_TG_VACT_ST2_L);
 894         DUMPREG(HDMI_TG_VACT_ST2_H);
 895         DUMPREG(HDMI_TG_VACT_ST3_L);
 896         DUMPREG(HDMI_TG_VACT_ST3_H);
 897         DUMPREG(HDMI_TG_VACT_ST4_L);
 898         DUMPREG(HDMI_TG_VACT_ST4_H);
 899         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 900         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 901         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 902         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 903         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 904         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 905         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 906         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 907         DUMPREG(HDMI_TG_3D);
 908
 909         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 910         DUMPREG(HDMI_AVI_CON);
 911         DUMPREG(HDMI_AVI_HEADER0);
 912         DUMPREG(HDMI_AVI_HEADER1);
 913         DUMPREG(HDMI_AVI_HEADER2);
 914         DUMPREG(HDMI_AVI_CHECK_SUM);
 915         DUMPREG(HDMI_VSI_CON);
 916         DUMPREG(HDMI_VSI_HEADER0);
 917         DUMPREG(HDMI_VSI_HEADER1);
 918         DUMPREG(HDMI_VSI_HEADER2);
 919         for (i = 0; i < 7; ++i)
 920                 DUMPREG(HDMI_VSI_DATA(i));
 921
 922 #undef DUMPREG
 923 }
 924
 925 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 926 {
 927         if (hdata->type == HDMI_TYPE13)
 928                 hdmi_v13_regs_dump(hdata, prefix);
 929         else
 930                 hdmi_v14_regs_dump(hdata, prefix);
 931 }
 932
 933 static u8 hdmi_chksum(struct hdmi_context *hdata,
 934                         u32 start, u8 len, u32 hdr_sum)
 935 {
 936         int i;
 937
 938         /* hdr_sum : header0 + header1 + header2
 939         * start : start address of packet byte1
 940         * len : packet bytes - 1 */
 941         for (i = 0; i < len; ++i)
 942                 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
 943
 944         /* return 2's complement of 8 bit hdr_sum */
 945         return (u8)(~(hdr_sum & 0xff) + 1);
 946 }
 947
 948 static void hdmi_reg_infoframe(struct hdmi_context *hdata,
 949                         union hdmi_infoframe *infoframe)
 950 {
 951         u32 hdr_sum;
 952         u8 chksum;
 953         u32 mod;
 954         u32 vic;
 955
 956         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 957         if (hdata->dvi_mode) {
 958                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 959                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 960                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 961                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 962                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 963                 return;
 964         }
 965
 966         switch (infoframe->any.type) {
 967         case HDMI_INFOFRAME_TYPE_AVI:
 968                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
 969                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
 970                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
 971                                 infoframe->any.version);
 972                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
 973                 hdr_sum = infoframe->any.type + infoframe->any.version +
 974                           infoframe->any.length;
 975
 976                 /* Output format zero hardcoded ,RGB YBCR selection */
 977                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
 978                         AVI_ACTIVE_FORMAT_VALID |
 979                         AVI_UNDERSCANNED_DISPLAY_VALID);
 980
 981                 /*
 982                  * Set the aspect ratio as per the mode, mentioned in
 983                  * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
 984                  */
 985                 switch (hdata->mode_conf.aspect_ratio) {
 986                 case HDMI_PICTURE_ASPECT_4_3:
 987                         hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
 988                                         hdata->mode_conf.aspect_ratio |
 989                                         AVI_4_3_CENTER_RATIO);
 990                         break;
 991                 case HDMI_PICTURE_ASPECT_16_9:
 992                         hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
 993                                         hdata->mode_conf.aspect_ratio |
 994                                         AVI_16_9_CENTER_RATIO);
 995                         break;
 996                 case HDMI_PICTURE_ASPECT_NONE:
 997                 default:
 998                         hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
 999                                         hdata->mode_conf.aspect_ratio |
1000                                         AVI_SAME_AS_PIC_ASPECT_RATIO);
1001                         break;
1002                 }
1003
1004                 vic = hdata->mode_conf.cea_video_id;
1005                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
1006
1007                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1008                                         infoframe->any.length, hdr_sum);
1009                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1010                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1011                 break;
1012         case HDMI_INFOFRAME_TYPE_AUDIO:
1013                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1014                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
1015                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
1016                                 infoframe->any.version);
1017                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
1018                 hdr_sum = infoframe->any.type + infoframe->any.version +
1019                           infoframe->any.length;
1020                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1021                                         infoframe->any.length, hdr_sum);
1022                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1023                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1024                 break;
1025         default:
1026                 break;
1027         }
1028 }
1029
1030 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
1031                                 bool force)
1032 {
1033         struct hdmi_context *hdata = ctx_from_connector(connector);
1034
1035         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1036
1037         return hdata->hpd ? connector_status_connected :
1038                         connector_status_disconnected;
1039 }
1040
1041 static void hdmi_connector_destroy(struct drm_connector *connector)
1042 {
1043         drm_connector_unregister(connector);
1044         drm_connector_cleanup(connector);
1045 }
1046
1047 static struct drm_connector_funcs hdmi_connector_funcs = {
1048         .dpms = drm_helper_connector_dpms,
1049         .fill_modes = drm_helper_probe_single_connector_modes,
1050         .detect = hdmi_detect,
1051         .destroy = hdmi_connector_destroy,
1052 };
1053
1054 static int hdmi_get_modes(struct drm_connector *connector)
1055 {
1056         struct hdmi_context *hdata = ctx_from_connector(connector);
1057         struct edid *edid;
1058
1059         if (!hdata->ddc_adpt)
1060                 return -ENODEV;
1061
1062         edid = drm_get_edid(connector, hdata->ddc_adpt);
1063         if (!edid)
1064                 return -ENODEV;
1065
1066         hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
1067         DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
1068                 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
1069                 edid->width_cm, edid->height_cm);
1070
1071         drm_mode_connector_update_edid_property(connector, edid);
1072
1073         return drm_add_edid_modes(connector, edid);
1074 }
1075
1076 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
1077 {
1078         int i;
1079
1080         for (i = 0; i < hdata->phy_conf_count; i++)
1081                 if (hdata->phy_confs[i].pixel_clock == pixel_clock)
1082                         return i;
1083
1084         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1085         return -EINVAL;
1086 }
1087
1088 static int hdmi_mode_valid(struct drm_connector *connector,
1089                         struct drm_display_mode *mode)
1090 {
1091         struct hdmi_context *hdata = ctx_from_connector(connector);
1092         int ret;
1093
1094         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1095                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1096                 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
1097                 false, mode->clock * 1000);
1098
1099         ret = mixer_check_mode(mode);
1100         if (ret)
1101                 return MODE_BAD;
1102
1103         ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
1104         if (ret < 0)
1105                 return MODE_BAD;
1106
1107         return MODE_OK;
1108 }
1109
1110 static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
1111 {
1112         struct hdmi_context *hdata = ctx_from_connector(connector);
1113
1114         return hdata->encoder;
1115 }
1116
1117 static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
1118         .get_modes = hdmi_get_modes,
1119         .mode_valid = hdmi_mode_valid,
1120         .best_encoder = hdmi_best_encoder,
1121 };
1122
1123 static int hdmi_create_connector(struct exynos_drm_display *display,
1124                         struct drm_encoder *encoder)
1125 {
1126         struct hdmi_context *hdata = display->ctx;
1127         struct drm_connector *connector = &hdata->connector;
1128         int ret;
1129
1130         hdata->encoder = encoder;
1131         connector->interlace_allowed = true;
1132         connector->polled = DRM_CONNECTOR_POLL_HPD;
1133
1134         ret = drm_connector_init(hdata->drm_dev, connector,
1135                         &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1136         if (ret) {
1137                 DRM_ERROR("Failed to initialize connector with drm\n");
1138                 return ret;
1139         }
1140
1141         drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
1142         drm_connector_register(connector);
1143         drm_mode_connector_attach_encoder(connector, encoder);
1144
1145         return 0;
1146 }
1147
1148 static void hdmi_mode_fixup(struct exynos_drm_display *display,
1149                                 struct drm_connector *connector,
1150                                 const struct drm_display_mode *mode,
1151                                 struct drm_display_mode *adjusted_mode)
1152 {
1153         struct drm_display_mode *m;
1154         int mode_ok;
1155
1156         DRM_DEBUG_KMS("%s\n", __FILE__);
1157
1158         drm_mode_set_crtcinfo(adjusted_mode, 0);
1159
1160         mode_ok = hdmi_mode_valid(connector, adjusted_mode);
1161
1162         /* just return if user desired mode exists. */
1163         if (mode_ok == MODE_OK)
1164                 return;
1165
1166         /*
1167          * otherwise, find the most suitable mode among modes and change it
1168          * to adjusted_mode.
1169          */
1170         list_for_each_entry(m, &connector->modes, head) {
1171                 mode_ok = hdmi_mode_valid(connector, m);
1172
1173                 if (mode_ok == MODE_OK) {
1174                         DRM_INFO("desired mode doesn't exist so\n");
1175                         DRM_INFO("use the most suitable mode among modes.\n");
1176
1177                         DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1178                                 m->hdisplay, m->vdisplay, m->vrefresh);
1179
1180                         drm_mode_copy(adjusted_mode, m);
1181                         break;
1182                 }
1183         }
1184 }
1185
1186 static void hdmi_set_acr(u32 freq, u8 *acr)
1187 {
1188         u32 n, cts;
1189
1190         switch (freq) {
1191         case 32000:
1192                 n = 4096;
1193                 cts = 27000;
1194                 break;
1195         case 44100:
1196                 n = 6272;
1197                 cts = 30000;
1198                 break;
1199         case 88200:
1200                 n = 12544;
1201                 cts = 30000;
1202                 break;
1203         case 176400:
1204                 n = 25088;
1205                 cts = 30000;
1206                 break;
1207         case 48000:
1208                 n = 6144;
1209                 cts = 27000;
1210                 break;
1211         case 96000:
1212                 n = 12288;
1213                 cts = 27000;
1214                 break;
1215         case 192000:
1216                 n = 24576;
1217                 cts = 27000;
1218                 break;
1219         default:
1220                 n = 0;
1221                 cts = 0;
1222                 break;
1223         }
1224
1225         acr[1] = cts >> 16;
1226         acr[2] = cts >> 8 & 0xff;
1227         acr[3] = cts & 0xff;
1228
1229         acr[4] = n >> 16;
1230         acr[5] = n >> 8 & 0xff;
1231         acr[6] = n & 0xff;
1232 }
1233
1234 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1235 {
1236         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1237         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1238         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1239         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1240         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1241         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1242         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1243         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1244         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1245
1246         if (hdata->type == HDMI_TYPE13)
1247                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1248         else
1249                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1250 }
1251
1252 static void hdmi_audio_init(struct hdmi_context *hdata)
1253 {
1254         u32 sample_rate, bits_per_sample;
1255         u32 data_num, bit_ch, sample_frq;
1256         u32 val;
1257         u8 acr[7];
1258
1259         sample_rate = 44100;
1260         bits_per_sample = 16;
1261
1262         switch (bits_per_sample) {
1263         case 20:
1264                 data_num = 2;
1265                 bit_ch  = 1;
1266                 break;
1267         case 24:
1268                 data_num = 3;
1269                 bit_ch  = 1;
1270                 break;
1271         default:
1272                 data_num = 1;
1273                 bit_ch  = 0;
1274                 break;
1275         }
1276
1277         hdmi_set_acr(sample_rate, acr);
1278         hdmi_reg_acr(hdata, acr);
1279
1280         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1281                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1282                                 | HDMI_I2S_MUX_ENABLE);
1283
1284         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1285                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1286
1287         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1288
1289         sample_frq = (sample_rate == 44100) ? 0 :
1290                         (sample_rate == 48000) ? 2 :
1291                         (sample_rate == 32000) ? 3 :
1292                         (sample_rate == 96000) ? 0xa : 0x0;
1293
1294         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1295         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1296
1297         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1298         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1299
1300         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1301         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1302                         | HDMI_I2S_SEL_LRCK(6));
1303         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1304                         | HDMI_I2S_SEL_SDATA2(4));
1305         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1306                         | HDMI_I2S_SEL_SDATA2(2));
1307         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1308
1309         /* I2S_CON_1 & 2 */
1310         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1311                         | HDMI_I2S_L_CH_LOW_POL);
1312         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1313                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1314                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1315                         | HDMI_I2S_BASIC_FORMAT);
1316
1317         /* Configure register related to CUV information */
1318         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1319                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1320                         | HDMI_I2S_COPYRIGHT
1321                         | HDMI_I2S_LINEAR_PCM
1322                         | HDMI_I2S_CONSUMER_FORMAT);
1323         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1324         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1325         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1326                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1327         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1328                         HDMI_I2S_ORG_SMP_FREQ_44_1
1329                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1330                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1331
1332         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1333 }
1334
1335 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1336 {
1337         if (hdata->dvi_mode)
1338                 return;
1339
1340         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1341         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1342                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1343 }
1344
1345 static void hdmi_start(struct hdmi_context *hdata, bool start)
1346 {
1347         u32 val = start ? HDMI_TG_EN : 0;
1348
1349         if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1350                 val |= HDMI_FIELD_EN;
1351
1352         hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1353         hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1354 }
1355
1356 static void hdmi_conf_init(struct hdmi_context *hdata)
1357 {
1358         union hdmi_infoframe infoframe;
1359
1360         /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1361         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1362                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1363
1364         /* choose HDMI mode */
1365         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1366                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1367         /* Apply Video preable and Guard band in HDMI mode only */
1368         hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
1369         /* disable bluescreen */
1370         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1371
1372         if (hdata->dvi_mode) {
1373                 /* choose DVI mode */
1374                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1375                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1376                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1377                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1378         }
1379
1380         if (hdata->type == HDMI_TYPE13) {
1381                 /* choose bluescreen (fecal) color */
1382                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1383                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1384                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1385
1386                 /* enable AVI packet every vsync, fixes purple line problem */
1387                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1388                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1389                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1390                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1391
1392                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1393                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1394                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1395         } else {
1396                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1397                 infoframe.any.version = HDMI_AVI_VERSION;
1398                 infoframe.any.length = HDMI_AVI_LENGTH;
1399                 hdmi_reg_infoframe(hdata, &infoframe);
1400
1401                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1402                 infoframe.any.version = HDMI_AUI_VERSION;
1403                 infoframe.any.length = HDMI_AUI_LENGTH;
1404                 hdmi_reg_infoframe(hdata, &infoframe);
1405
1406                 /* enable AVI packet every vsync, fixes purple line problem */
1407                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1408         }
1409 }
1410
1411 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1412 {
1413         const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1414         const struct hdmi_v13_core_regs *core =
1415                 &hdata->mode_conf.conf.v13_conf.core;
1416         int tries;
1417
1418         /* setting core registers */
1419         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1420         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1421         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1422         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1423         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1424         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1425         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1426         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1427         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1428         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1429         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1430         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1431         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1432         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1433         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1434         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1435         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1436         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1437         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1438         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1439         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1440         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1441         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1442         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1443         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1444         /* Timing generator registers */
1445         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1446         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1447         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1448         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1449         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1450         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1451         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1452         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1453         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1454         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1455         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1456         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1457         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1458         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1459         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1460         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1461         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1462         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1463         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1464         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1465         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1466         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1467         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1468         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1469         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1470         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1471         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1472         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1473
1474         /* waiting for HDMIPHY's PLL to get to steady state */
1475         for (tries = 100; tries; --tries) {
1476                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1477                 if (val & HDMI_PHY_STATUS_READY)
1478                         break;
1479                 usleep_range(1000, 2000);
1480         }
1481         /* steady state not achieved */
1482         if (tries == 0) {
1483                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1484                 hdmi_regs_dump(hdata, "timing apply");
1485         }
1486
1487         clk_disable_unprepare(hdata->res.sclk_hdmi);
1488         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1489         clk_prepare_enable(hdata->res.sclk_hdmi);
1490
1491         /* enable HDMI and timing generator */
1492         hdmi_start(hdata, true);
1493 }
1494
1495 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1496 {
1497         const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1498         const struct hdmi_v14_core_regs *core =
1499                 &hdata->mode_conf.conf.v14_conf.core;
1500         int tries;
1501
1502         /* setting core registers */
1503         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1504         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1505         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1506         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1507         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1508         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1509         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1510         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1511         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1512         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1513         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1514         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1515         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1516         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1517         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1518         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1519         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1520         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1521         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1522         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1523         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1524         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1525                         core->v_sync_line_bef_2[0]);
1526         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1527                         core->v_sync_line_bef_2[1]);
1528         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1529                         core->v_sync_line_bef_1[0]);
1530         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1531                         core->v_sync_line_bef_1[1]);
1532         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1533                         core->v_sync_line_aft_2[0]);
1534         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1535                         core->v_sync_line_aft_2[1]);
1536         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1537                         core->v_sync_line_aft_1[0]);
1538         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1539                         core->v_sync_line_aft_1[1]);
1540         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1541                         core->v_sync_line_aft_pxl_2[0]);
1542         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1543                         core->v_sync_line_aft_pxl_2[1]);
1544         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1545                         core->v_sync_line_aft_pxl_1[0]);
1546         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1547                         core->v_sync_line_aft_pxl_1[1]);
1548         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1549         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1550         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1551         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1552         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1553         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1554         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1555         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1556         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1557                         core->v_sync_line_aft_3[0]);
1558         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1559                         core->v_sync_line_aft_3[1]);
1560         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1561                         core->v_sync_line_aft_4[0]);
1562         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1563                         core->v_sync_line_aft_4[1]);
1564         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1565                         core->v_sync_line_aft_5[0]);
1566         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1567                         core->v_sync_line_aft_5[1]);
1568         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1569                         core->v_sync_line_aft_6[0]);
1570         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1571                         core->v_sync_line_aft_6[1]);
1572         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1573                         core->v_sync_line_aft_pxl_3[0]);
1574         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1575                         core->v_sync_line_aft_pxl_3[1]);
1576         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1577                         core->v_sync_line_aft_pxl_4[0]);
1578         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1579                         core->v_sync_line_aft_pxl_4[1]);
1580         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1581                         core->v_sync_line_aft_pxl_5[0]);
1582         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1583                         core->v_sync_line_aft_pxl_5[1]);
1584         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1585                         core->v_sync_line_aft_pxl_6[0]);
1586         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1587                         core->v_sync_line_aft_pxl_6[1]);
1588         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1589         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1590         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1591         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1592         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1593         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1594         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1595         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1596         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1597         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1598         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1599         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1600
1601         /* Timing generator registers */
1602         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1603         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1604         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1605         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1606         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1607         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1608         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1609         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1610         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1611         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1612         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1613         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1614         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1615         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1616         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1617         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1618         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1619         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1620         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1621         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1622         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1623         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1624         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1625         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1626         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1627         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1628         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1629         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1630         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1631         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1632         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1633         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1634         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1635
1636         /* waiting for HDMIPHY's PLL to get to steady state */
1637         for (tries = 100; tries; --tries) {
1638                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1639                 if (val & HDMI_PHY_STATUS_READY)
1640                         break;
1641                 usleep_range(1000, 2000);
1642         }
1643         /* steady state not achieved */
1644         if (tries == 0) {
1645                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1646                 hdmi_regs_dump(hdata, "timing apply");
1647         }
1648
1649         clk_disable_unprepare(hdata->res.sclk_hdmi);
1650         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1651         clk_prepare_enable(hdata->res.sclk_hdmi);
1652
1653         /* enable HDMI and timing generator */
1654         hdmi_start(hdata, true);
1655 }
1656
1657 static void hdmi_mode_apply(struct hdmi_context *hdata)
1658 {
1659         if (hdata->type == HDMI_TYPE13)
1660                 hdmi_v13_mode_apply(hdata);
1661         else
1662                 hdmi_v14_mode_apply(hdata);
1663 }
1664
1665 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1666 {
1667         u8 buffer[2];
1668         u32 reg;
1669
1670         clk_disable_unprepare(hdata->res.sclk_hdmi);
1671         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
1672         clk_prepare_enable(hdata->res.sclk_hdmi);
1673
1674         /* operation mode */
1675         buffer[0] = 0x1f;
1676         buffer[1] = 0x00;
1677
1678         if (hdata->hdmiphy_port)
1679                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1680
1681         if (hdata->type == HDMI_TYPE13)
1682                 reg = HDMI_V13_PHY_RSTOUT;
1683         else
1684                 reg = HDMI_PHY_RSTOUT;
1685
1686         /* reset hdmiphy */
1687         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1688         usleep_range(10000, 12000);
1689         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1690         usleep_range(10000, 12000);
1691 }
1692
1693 static void hdmiphy_poweron(struct hdmi_context *hdata)
1694 {
1695         if (hdata->type != HDMI_TYPE14)
1696                 return;
1697
1698         DRM_DEBUG_KMS("\n");
1699
1700         /* For PHY Mode Setting */
1701         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1702                                 HDMI_PHY_ENABLE_MODE_SET);
1703         /* Phy Power On */
1704         hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1705                                 HDMI_PHY_POWER_ON);
1706         /* For PHY Mode Setting */
1707         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1708                                 HDMI_PHY_DISABLE_MODE_SET);
1709         /* PHY SW Reset */
1710         hdmiphy_conf_reset(hdata);
1711 }
1712
1713 static void hdmiphy_poweroff(struct hdmi_context *hdata)
1714 {
1715         if (hdata->type != HDMI_TYPE14)
1716                 return;
1717
1718         DRM_DEBUG_KMS("\n");
1719
1720         /* PHY SW Reset */
1721         hdmiphy_conf_reset(hdata);
1722         /* For PHY Mode Setting */
1723         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1724                                 HDMI_PHY_ENABLE_MODE_SET);
1725
1726         /* PHY Power Off */
1727         hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
1728                                 HDMI_PHY_POWER_OFF);
1729
1730         /* For PHY Mode Setting */
1731         hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1732                                 HDMI_PHY_DISABLE_MODE_SET);
1733 }
1734
1735 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1736 {
1737         int ret;
1738         int i;
1739
1740         /* pixel clock */
1741         i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1742         if (i < 0) {
1743                 DRM_ERROR("failed to find hdmiphy conf\n");
1744                 return;
1745         }
1746
1747         ret = hdmiphy_reg_write_buf(hdata, 0, hdata->phy_confs[i].conf, 32);
1748         if (ret) {
1749                 DRM_ERROR("failed to configure hdmiphy\n");
1750                 return;
1751         }
1752
1753         usleep_range(10000, 12000);
1754
1755         ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
1756                                 HDMI_PHY_DISABLE_MODE_SET);
1757         if (ret) {
1758                 DRM_ERROR("failed to enable hdmiphy\n");
1759                 return;
1760         }
1761
1762 }
1763
1764 static void hdmi_conf_apply(struct hdmi_context *hdata)
1765 {
1766         hdmiphy_conf_reset(hdata);
1767         hdmiphy_conf_apply(hdata);
1768
1769         mutex_lock(&hdata->hdmi_mutex);
1770         hdmi_start(hdata, false);
1771         hdmi_conf_init(hdata);
1772         mutex_unlock(&hdata->hdmi_mutex);
1773
1774         hdmi_audio_init(hdata);
1775
1776         /* setting core registers */
1777         hdmi_mode_apply(hdata);
1778         hdmi_audio_control(hdata, true);
1779
1780         hdmi_regs_dump(hdata, "start");
1781 }
1782
1783 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1784 {
1785         int i;
1786         BUG_ON(num_bytes > 4);
1787         for (i = 0; i < num_bytes; i++)
1788                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1789 }
1790
1791 static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1792                         struct drm_display_mode *m)
1793 {
1794         struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1795         struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1796         unsigned int val;
1797
1798         hdata->mode_conf.cea_video_id =
1799                 drm_match_cea_mode((struct drm_display_mode *)m);
1800         hdata->mode_conf.pixel_clock = m->clock * 1000;
1801         hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1802
1803         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1804         hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1805
1806         val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1807         hdmi_set_reg(core->vsync_pol, 1, val);
1808
1809         val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1810         hdmi_set_reg(core->int_pro_mode, 1, val);
1811
1812         val = (m->hsync_start - m->hdisplay - 2);
1813         val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1814         val |= ((m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0)<<20;
1815         hdmi_set_reg(core->h_sync_gen, 3, val);
1816
1817         /*
1818          * Quirk requirement for exynos HDMI IP design,
1819          * 2 pixels less than the actual calculation for hsync_start
1820          * and end.
1821          */
1822
1823         /* Following values & calculations differ for different type of modes */
1824         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1825                 /* Interlaced Mode */
1826                 val = ((m->vsync_end - m->vdisplay) / 2);
1827                 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1828                 hdmi_set_reg(core->v_sync_gen1, 3, val);
1829
1830                 val = m->vtotal / 2;
1831                 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1832                 hdmi_set_reg(core->v_blank, 3, val);
1833
1834                 val = (m->vtotal +
1835                         ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1836                 val |= m->vtotal << 11;
1837                 hdmi_set_reg(core->v_blank_f, 3, val);
1838
1839                 val = ((m->vtotal / 2) + 7);
1840                 val |= ((m->vtotal / 2) + 2) << 12;
1841                 hdmi_set_reg(core->v_sync_gen2, 3, val);
1842
1843                 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1844                 val |= ((m->htotal / 2) +
1845                         (m->hsync_start - m->hdisplay)) << 12;
1846                 hdmi_set_reg(core->v_sync_gen3, 3, val);
1847
1848                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1849                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1850
1851                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1852         } else {
1853                 /* Progressive Mode */
1854
1855                 val = m->vtotal;
1856                 val |= (m->vtotal - m->vdisplay) << 11;
1857                 hdmi_set_reg(core->v_blank, 3, val);
1858
1859                 hdmi_set_reg(core->v_blank_f, 3, 0);
1860
1861                 val = (m->vsync_end - m->vdisplay);
1862                 val |= ((m->vsync_start - m->vdisplay) << 12);
1863                 hdmi_set_reg(core->v_sync_gen1, 3, val);
1864
1865                 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value  */
1866                 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value  */
1867                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1868                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1869                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1870         }
1871
1872         /* Timing generator registers */
1873         hdmi_set_reg(tg->cmd, 1, 0x0);
1874         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1875         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1876         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1877         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1878         hdmi_set_reg(tg->vsync, 2, 0x1);
1879         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1880         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1881         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1882         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1883         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1884         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1885         hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1886 }
1887
1888 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1889                         struct drm_display_mode *m)
1890 {
1891         struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1892         struct hdmi_v14_core_regs *core =
1893                 &hdata->mode_conf.conf.v14_conf.core;
1894
1895         hdata->mode_conf.cea_video_id =
1896                 drm_match_cea_mode((struct drm_display_mode *)m);
1897         hdata->mode_conf.pixel_clock = m->clock * 1000;
1898         hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1899
1900         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1901         hdmi_set_reg(core->v_line, 2, m->vtotal);
1902         hdmi_set_reg(core->h_line, 2, m->htotal);
1903         hdmi_set_reg(core->hsync_pol, 1,
1904                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1905         hdmi_set_reg(core->vsync_pol, 1,
1906                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1907         hdmi_set_reg(core->int_pro_mode, 1,
1908                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1909
1910         /*
1911          * Quirk requirement for exynos 5 HDMI IP design,
1912          * 2 pixels less than the actual calculation for hsync_start
1913          * and end.
1914          */
1915
1916         /* Following values & calculations differ for different type of modes */
1917         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1918                 /* Interlaced Mode */
1919                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1920                         (m->vsync_end - m->vdisplay) / 2);
1921                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1922                         (m->vsync_start - m->vdisplay) / 2);
1923                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1924                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1925                 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
1926                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1927                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1928                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1929                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1930                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1931                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1932                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1933                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1934                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1935                 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1936                 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1937                 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1938                 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
1939                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1940                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1941         } else {
1942                 /* Progressive Mode */
1943                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1944                         m->vsync_end - m->vdisplay);
1945                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1946                         m->vsync_start - m->vdisplay);
1947                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1948                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1949                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1950                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1951                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1952                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1953                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1954                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1955                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1956                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1957                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1958                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1959                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1960                 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1961                 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1962                 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1963         }
1964
1965         /* Following values & calculations are same irrespective of mode type */
1966         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1967         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1968         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1969         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1970         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1971         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1972         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1973         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1974         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1975         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1976         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1977         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1978         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1979         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1980         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1981         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1982         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1983         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1984         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1985         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1986
1987         /* Timing generator registers */
1988         hdmi_set_reg(tg->cmd, 1, 0x0);
1989         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1990         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1991         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1992         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1993         hdmi_set_reg(tg->vsync, 2, 0x1);
1994         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1995         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1996         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1997         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1998 }
1999
2000 static void hdmi_mode_set(struct exynos_drm_display *display,
2001                         struct drm_display_mode *mode)
2002 {
2003         struct hdmi_context *hdata = display->ctx;
2004         struct drm_display_mode *m = mode;
2005
2006         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
2007                 m->hdisplay, m->vdisplay,
2008                 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
2009                 "INTERLACED" : "PROGERESSIVE");
2010
2011         /* preserve mode information for later use. */
2012         drm_mode_copy(&hdata->current_mode, mode);
2013
2014         if (hdata->type == HDMI_TYPE13)
2015                 hdmi_v13_mode_set(hdata, mode);
2016         else
2017                 hdmi_v14_mode_set(hdata, mode);
2018 }
2019
2020 static void hdmi_commit(struct exynos_drm_display *display)
2021 {
2022         struct hdmi_context *hdata = display->ctx;
2023
2024         mutex_lock(&hdata->hdmi_mutex);
2025         if (!hdata->powered) {
2026                 mutex_unlock(&hdata->hdmi_mutex);
2027                 return;
2028         }
2029         mutex_unlock(&hdata->hdmi_mutex);
2030
2031         hdmi_conf_apply(hdata);
2032 }
2033
2034 static void hdmi_poweron(struct exynos_drm_display *display)
2035 {
2036         struct hdmi_context *hdata = display->ctx;
2037         struct hdmi_resources *res = &hdata->res;
2038
2039         mutex_lock(&hdata->hdmi_mutex);
2040         if (hdata->powered) {
2041                 mutex_unlock(&hdata->hdmi_mutex);
2042                 return;
2043         }
2044
2045         hdata->powered = true;
2046
2047         mutex_unlock(&hdata->hdmi_mutex);
2048
2049         pm_runtime_get_sync(hdata->dev);
2050
2051         if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
2052                 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
2053
2054         /* set pmu hdmiphy control bit to enable hdmiphy */
2055         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2056                         PMU_HDMI_PHY_ENABLE_BIT, 1);
2057
2058         clk_prepare_enable(res->hdmi);
2059         clk_prepare_enable(res->sclk_hdmi);
2060
2061         hdmiphy_poweron(hdata);
2062         hdmi_commit(display);
2063 }
2064
2065 static void hdmi_poweroff(struct exynos_drm_display *display)
2066 {
2067         struct hdmi_context *hdata = display->ctx;
2068         struct hdmi_resources *res = &hdata->res;
2069
2070         mutex_lock(&hdata->hdmi_mutex);
2071         if (!hdata->powered)
2072                 goto out;
2073         mutex_unlock(&hdata->hdmi_mutex);
2074
2075         /* HDMI System Disable */
2076         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
2077
2078         hdmiphy_poweroff(hdata);
2079
2080         cancel_delayed_work(&hdata->hotplug_work);
2081
2082         clk_disable_unprepare(res->sclk_hdmi);
2083         clk_disable_unprepare(res->hdmi);
2084
2085         /* reset pmu hdmiphy control bit to disable hdmiphy */
2086         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
2087                         PMU_HDMI_PHY_ENABLE_BIT, 0);
2088
2089         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2090
2091         pm_runtime_put_sync(hdata->dev);
2092
2093         mutex_lock(&hdata->hdmi_mutex);
2094         hdata->powered = false;
2095
2096 out:
2097         mutex_unlock(&hdata->hdmi_mutex);
2098 }
2099
2100 static void hdmi_dpms(struct exynos_drm_display *display, int mode)
2101 {
2102         struct hdmi_context *hdata = display->ctx;
2103         struct drm_encoder *encoder = hdata->encoder;
2104         struct drm_crtc *crtc = encoder->crtc;
2105         struct drm_crtc_helper_funcs *funcs = NULL;
2106
2107         DRM_DEBUG_KMS("mode %d\n", mode);
2108
2109         switch (mode) {
2110         case DRM_MODE_DPMS_ON:
2111                 hdmi_poweron(display);
2112                 break;
2113         case DRM_MODE_DPMS_STANDBY:
2114         case DRM_MODE_DPMS_SUSPEND:
2115         case DRM_MODE_DPMS_OFF:
2116                 /*
2117                  * The SFRs of VP and Mixer are updated by Vertical Sync of
2118                  * Timing generator which is a part of HDMI so the sequence
2119                  * to disable TV Subsystem should be as following,
2120                  *      VP -> Mixer -> HDMI
2121                  *
2122                  * Below codes will try to disable Mixer and VP(if used)
2123                  * prior to disabling HDMI.
2124                  */
2125                 if (crtc)
2126                         funcs = crtc->helper_private;
2127                 if (funcs && funcs->dpms)
2128                         (*funcs->dpms)(crtc, mode);
2129
2130                 hdmi_poweroff(display);
2131                 break;
2132         default:
2133                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2134                 break;
2135         }
2136 }
2137
2138 static struct exynos_drm_display_ops hdmi_display_ops = {
2139         .create_connector = hdmi_create_connector,
2140         .mode_fixup     = hdmi_mode_fixup,
2141         .mode_set       = hdmi_mode_set,
2142         .dpms           = hdmi_dpms,
2143         .commit         = hdmi_commit,
2144 };
2145
2146 static struct exynos_drm_display hdmi_display = {
2147         .type = EXYNOS_DISPLAY_TYPE_HDMI,
2148         .ops = &hdmi_display_ops,
2149 };
2150
2151 static void hdmi_hotplug_work_func(struct work_struct *work)
2152 {
2153         struct hdmi_context *hdata;
2154
2155         hdata = container_of(work, struct hdmi_context, hotplug_work.work);
2156
2157         mutex_lock(&hdata->hdmi_mutex);
2158         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2159         mutex_unlock(&hdata->hdmi_mutex);
2160
2161         if (hdata->drm_dev)
2162                 drm_helper_hpd_irq_event(hdata->drm_dev);
2163 }
2164
2165 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
2166 {
2167         struct hdmi_context *hdata = arg;
2168
2169         mod_delayed_work(system_wq, &hdata->hotplug_work,
2170                         msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
2171
2172         return IRQ_HANDLED;
2173 }
2174
2175 static int hdmi_resources_init(struct hdmi_context *hdata)
2176 {
2177         struct device *dev = hdata->dev;
2178         struct hdmi_resources *res = &hdata->res;
2179         static char *supply[] = {
2180                 "vdd",
2181                 "vdd_osc",
2182                 "vdd_pll",
2183         };
2184         int i, ret;
2185
2186         DRM_DEBUG_KMS("HDMI resource init\n");
2187
2188         /* get clocks, power */
2189         res->hdmi = devm_clk_get(dev, "hdmi");
2190         if (IS_ERR(res->hdmi)) {
2191                 DRM_ERROR("failed to get clock 'hdmi'\n");
2192                 ret = PTR_ERR(res->hdmi);
2193                 goto fail;
2194         }
2195         res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
2196         if (IS_ERR(res->sclk_hdmi)) {
2197                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2198                 ret = PTR_ERR(res->sclk_hdmi);
2199                 goto fail;
2200         }
2201         res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
2202         if (IS_ERR(res->sclk_pixel)) {
2203                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2204                 ret = PTR_ERR(res->sclk_pixel);
2205                 goto fail;
2206         }
2207         res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
2208         if (IS_ERR(res->sclk_hdmiphy)) {
2209                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2210                 ret = PTR_ERR(res->sclk_hdmiphy);
2211                 goto fail;
2212         }
2213         res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
2214         if (IS_ERR(res->mout_hdmi)) {
2215                 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
2216                 ret = PTR_ERR(res->mout_hdmi);
2217                 goto fail;
2218         }
2219
2220         clk_set_parent(res->mout_hdmi, res->sclk_pixel);
2221
2222         res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
2223                 sizeof(res->regul_bulk[0]), GFP_KERNEL);
2224         if (!res->regul_bulk) {
2225                 ret = -ENOMEM;
2226                 goto fail;
2227         }
2228         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2229                 res->regul_bulk[i].supply = supply[i];
2230                 res->regul_bulk[i].consumer = NULL;
2231         }
2232         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2233         if (ret) {
2234                 DRM_ERROR("failed to get regulators\n");
2235                 return ret;
2236         }
2237         res->regul_count = ARRAY_SIZE(supply);
2238
2239         res->reg_hdmi_en = devm_regulator_get(dev, "hdmi-en");
2240         if (IS_ERR(res->reg_hdmi_en) && PTR_ERR(res->reg_hdmi_en) != -ENOENT) {
2241                 DRM_ERROR("failed to get hdmi-en regulator\n");
2242                 return PTR_ERR(res->reg_hdmi_en);
2243         }
2244         if (!IS_ERR(res->reg_hdmi_en)) {
2245                 ret = regulator_enable(res->reg_hdmi_en);
2246                 if (ret) {
2247                         DRM_ERROR("failed to enable hdmi-en regulator\n");
2248                         return ret;
2249                 }
2250         } else
2251                 res->reg_hdmi_en = NULL;
2252
2253         return ret;
2254 fail:
2255         DRM_ERROR("HDMI resource init - failed\n");
2256         return ret;
2257 }
2258
2259 static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
2260                                         (struct device *dev)
2261 {
2262         struct device_node *np = dev->of_node;
2263         struct s5p_hdmi_platform_data *pd;
2264         u32 value;
2265
2266         pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
2267         if (!pd)
2268                 goto err_data;
2269
2270         if (!of_find_property(np, "hpd-gpio", &value)) {
2271                 DRM_ERROR("no hpd gpio property found\n");
2272                 goto err_data;
2273         }
2274
2275         pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
2276
2277         return pd;
2278
2279 err_data:
2280         return NULL;
2281 }
2282
2283 static struct of_device_id hdmi_match_types[] = {
2284         {
2285                 .compatible = "samsung,exynos5-hdmi",
2286                 .data = &exynos5_hdmi_driver_data,
2287         }, {
2288                 .compatible = "samsung,exynos4210-hdmi",
2289                 .data = &exynos4210_hdmi_driver_data,
2290         }, {
2291                 .compatible = "samsung,exynos4212-hdmi",
2292                 .data = &exynos4212_hdmi_driver_data,
2293         }, {
2294                 .compatible = "samsung,exynos5420-hdmi",
2295                 .data = &exynos5420_hdmi_driver_data,
2296         }, {
2297                 /* end node */
2298         }
2299 };
2300 MODULE_DEVICE_TABLE (of, hdmi_match_types);
2301
2302 static int hdmi_bind(struct device *dev, struct device *master, void *data)
2303 {
2304         struct drm_device *drm_dev = data;
2305         struct hdmi_context *hdata;
2306
2307         hdata = hdmi_display.ctx;
2308         hdata->drm_dev = drm_dev;
2309
2310         return exynos_drm_create_enc_conn(drm_dev, &hdmi_display);
2311 }
2312
2313 static void hdmi_unbind(struct device *dev, struct device *master, void *data)
2314 {
2315 }
2316
2317 static const struct component_ops hdmi_component_ops = {
2318         .bind   = hdmi_bind,
2319         .unbind = hdmi_unbind,
2320 };
2321
2322 static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev)
2323 {
2324         const char *compatible_str = "samsung,exynos4210-hdmiddc";
2325         struct device_node *np;
2326
2327         np = of_find_compatible_node(NULL, NULL, compatible_str);
2328         if (np)
2329                 return of_get_next_parent(np);
2330
2331         return NULL;
2332 }
2333
2334 static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
2335 {
2336         const char *compatible_str = "samsung,exynos4212-hdmiphy";
2337
2338         return of_find_compatible_node(NULL, NULL, compatible_str);
2339 }
2340
2341 static int hdmi_probe(struct platform_device *pdev)
2342 {
2343         struct device_node *ddc_node, *phy_node;
2344         struct s5p_hdmi_platform_data *pdata;
2345         struct hdmi_driver_data *drv_data;
2346         const struct of_device_id *match;
2347         struct device *dev = &pdev->dev;
2348         struct hdmi_context *hdata;
2349         struct resource *res;
2350         int ret;
2351
2352         ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
2353                                         hdmi_display.type);
2354         if (ret)
2355                 return ret;
2356
2357         if (!dev->of_node) {
2358                 ret = -ENODEV;
2359                 goto err_del_component;
2360         }
2361
2362         pdata = drm_hdmi_dt_parse_pdata(dev);
2363         if (!pdata) {
2364                 ret = -EINVAL;
2365                 goto err_del_component;
2366         }
2367
2368         hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2369         if (!hdata) {
2370                 ret = -ENOMEM;
2371                 goto err_del_component;
2372         }
2373
2374         mutex_init(&hdata->hdmi_mutex);
2375
2376         platform_set_drvdata(pdev, &hdmi_display);
2377
2378         match = of_match_node(hdmi_match_types, dev->of_node);
2379         if (!match) {
2380                 ret = -ENODEV;
2381                 goto err_del_component;
2382         }
2383
2384         drv_data = (struct hdmi_driver_data *)match->data;
2385         hdata->type = drv_data->type;
2386         hdata->phy_confs = drv_data->phy_confs;
2387         hdata->phy_conf_count = drv_data->phy_conf_count;
2388
2389         hdata->hpd_gpio = pdata->hpd_gpio;
2390         hdata->dev = dev;
2391
2392         ret = hdmi_resources_init(hdata);
2393         if (ret) {
2394                 DRM_ERROR("hdmi_resources_init failed\n");
2395                 return ret;
2396         }
2397
2398         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2399         hdata->regs = devm_ioremap_resource(dev, res);
2400         if (IS_ERR(hdata->regs)) {
2401                 ret = PTR_ERR(hdata->regs);
2402                 goto err_del_component;
2403         }
2404
2405         ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
2406         if (ret) {
2407                 DRM_ERROR("failed to request HPD gpio\n");
2408                 goto err_del_component;
2409         }
2410
2411         ddc_node = hdmi_legacy_ddc_dt_binding(dev);
2412         if (ddc_node)
2413                 goto out_get_ddc_adpt;
2414
2415         /* DDC i2c driver */
2416         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2417         if (!ddc_node) {
2418                 DRM_ERROR("Failed to find ddc node in device tree\n");
2419                 ret = -ENODEV;
2420                 goto err_del_component;
2421         }
2422
2423 out_get_ddc_adpt:
2424         hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2425         if (!hdata->ddc_adpt) {
2426                 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
2427                 return -EPROBE_DEFER;
2428         }
2429
2430         phy_node = hdmi_legacy_phy_dt_binding(dev);
2431         if (phy_node)
2432                 goto out_get_phy_port;
2433
2434         /* hdmiphy i2c driver */
2435         phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2436         if (!phy_node) {
2437                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2438                 ret = -ENODEV;
2439                 goto err_ddc;
2440         }
2441
2442 out_get_phy_port:
2443         if (drv_data->is_apb_phy) {
2444                 hdata->regs_hdmiphy = of_iomap(phy_node, 0);
2445                 if (!hdata->regs_hdmiphy) {
2446                         DRM_ERROR("failed to ioremap hdmi phy\n");
2447                         ret = -ENOMEM;
2448                         goto err_ddc;
2449                 }
2450         } else {
2451                 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2452                 if (!hdata->hdmiphy_port) {
2453                         DRM_ERROR("Failed to get hdmi phy i2c client\n");
2454                         ret = -EPROBE_DEFER;
2455                         goto err_ddc;
2456                 }
2457         }
2458
2459         hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2460         if (hdata->irq < 0) {
2461                 DRM_ERROR("failed to get GPIO irq\n");
2462                 ret = hdata->irq;
2463                 goto err_hdmiphy;
2464         }
2465
2466         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2467
2468         INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2469
2470         ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2471                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
2472                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2473                         "hdmi", hdata);
2474         if (ret) {
2475                 DRM_ERROR("failed to register hdmi interrupt\n");
2476                 goto err_hdmiphy;
2477         }
2478
2479         hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2480                         "samsung,syscon-phandle");
2481         if (IS_ERR(hdata->pmureg)) {
2482                 DRM_ERROR("syscon regmap lookup failed.\n");
2483                 ret = -EPROBE_DEFER;
2484                 goto err_hdmiphy;
2485         }
2486
2487         pm_runtime_enable(dev);
2488         hdmi_display.ctx = hdata;
2489
2490         ret = component_add(&pdev->dev, &hdmi_component_ops);
2491         if (ret)
2492                 goto err_disable_pm_runtime;
2493
2494         return ret;
2495
2496 err_disable_pm_runtime:
2497         pm_runtime_disable(dev);
2498
2499 err_hdmiphy:
2500         if (hdata->hdmiphy_port)
2501                 put_device(&hdata->hdmiphy_port->dev);
2502 err_ddc:
2503         put_device(&hdata->ddc_adpt->dev);
2504
2505 err_del_component:
2506         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
2507
2508         return ret;
2509 }
2510
2511 static int hdmi_remove(struct platform_device *pdev)
2512 {
2513         struct hdmi_context *hdata = hdmi_display.ctx;
2514
2515         cancel_delayed_work_sync(&hdata->hotplug_work);
2516
2517         if (hdata->res.reg_hdmi_en)
2518                 regulator_disable(hdata->res.reg_hdmi_en);
2519
2520         if (hdata->hdmiphy_port)
2521                 put_device(&hdata->hdmiphy_port->dev);
2522         put_device(&hdata->ddc_adpt->dev);
2523
2524         pm_runtime_disable(&pdev->dev);
2525         component_del(&pdev->dev, &hdmi_component_ops);
2526
2527         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
2528         return 0;
2529 }
2530
2531 struct platform_driver hdmi_driver = {
2532         .probe          = hdmi_probe,
2533         .remove         = hdmi_remove,
2534         .driver         = {
2535                 .name   = "exynos-hdmi",
2536                 .owner  = THIS_MODULE,
2537                 .of_match_table = hdmi_match_types,
2538         },
2539 };