drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_crtc_helper.h>
  20
  21 #include "regs-hdmi.h"
  22
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/wait.h>
  26 #include <linux/i2c.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/io.h>
  35 #include <linux/of.h>
  36 #include <linux/i2c.h>
  37 #include <linux/of_gpio.h>
  38 #include <linux/hdmi.h>
  39 #include <linux/component.h>
  40
  41 #include <drm/exynos_drm.h>
  42
  43 #include "exynos_drm_drv.h"
  44 #include "exynos_drm_crtc.h"
  45 #include "exynos_mixer.h"
  46
  47 #include <linux/gpio.h>
  48 #include <media/s5p_hdmi.h>
  49
  50 #define get_hdmi_display(dev)   platform_get_drvdata(to_platform_device(dev))
  51 #define ctx_from_connector(c)   container_of(c, struct hdmi_context, connector)
  52
  53 #define HOTPLUG_DEBOUNCE_MS             1100
  54
  55 /* AVI header and aspect ratio */
  56 #define HDMI_AVI_VERSION                0x02
  57 #define HDMI_AVI_LENGTH         0x0D
  58
  59 /* AUI header info */
  60 #define HDMI_AUI_VERSION        0x01
  61 #define HDMI_AUI_LENGTH 0x0A
  62 #define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
  63 #define AVI_4_3_CENTER_RATIO    0x9
  64 #define AVI_16_9_CENTER_RATIO   0xa
  65
  66 enum hdmi_type {
  67         HDMI_TYPE13,
  68         HDMI_TYPE14,
  69 };
  70
  71 struct hdmi_driver_data {
  72         unsigned int type;
  73         unsigned int is_apb_phy:1;
  74 };
  75
  76 struct hdmi_resources {
  77         struct clk                      *hdmi;
  78         struct clk                      *sclk_hdmi;
  79         struct clk                      *sclk_pixel;
  80         struct clk                      *sclk_hdmiphy;
  81         struct clk                      *hdmiphy;
  82         struct clk                      *mout_hdmi;
  83         struct regulator_bulk_data      *regul_bulk;
  84         int                             regul_count;
  85 };
  86
  87 struct hdmi_tg_regs {
  88         u8 cmd[1];
  89         u8 h_fsz[2];
  90         u8 hact_st[2];
  91         u8 hact_sz[2];
  92         u8 v_fsz[2];
  93         u8 vsync[2];
  94         u8 vsync2[2];
  95         u8 vact_st[2];
  96         u8 vact_sz[2];
  97         u8 field_chg[2];
  98         u8 vact_st2[2];
  99         u8 vact_st3[2];
 100         u8 vact_st4[2];
 101         u8 vsync_top_hdmi[2];
 102         u8 vsync_bot_hdmi[2];
 103         u8 field_top_hdmi[2];
 104         u8 field_bot_hdmi[2];
 105         u8 tg_3d[1];
 106 };
 107
 108 struct hdmi_v13_core_regs {
 109         u8 h_blank[2];
 110         u8 v_blank[3];
 111         u8 h_v_line[3];
 112         u8 vsync_pol[1];
 113         u8 int_pro_mode[1];
 114         u8 v_blank_f[3];
 115         u8 h_sync_gen[3];
 116         u8 v_sync_gen1[3];
 117         u8 v_sync_gen2[3];
 118         u8 v_sync_gen3[3];
 119 };
 120
 121 struct hdmi_v14_core_regs {
 122         u8 h_blank[2];
 123         u8 v2_blank[2];
 124         u8 v1_blank[2];
 125         u8 v_line[2];
 126         u8 h_line[2];
 127         u8 hsync_pol[1];
 128         u8 vsync_pol[1];
 129         u8 int_pro_mode[1];
 130         u8 v_blank_f0[2];
 131         u8 v_blank_f1[2];
 132         u8 h_sync_start[2];
 133         u8 h_sync_end[2];
 134         u8 v_sync_line_bef_2[2];
 135         u8 v_sync_line_bef_1[2];
 136         u8 v_sync_line_aft_2[2];
 137         u8 v_sync_line_aft_1[2];
 138         u8 v_sync_line_aft_pxl_2[2];
 139         u8 v_sync_line_aft_pxl_1[2];
 140         u8 v_blank_f2[2]; /* for 3D mode */
 141         u8 v_blank_f3[2]; /* for 3D mode */
 142         u8 v_blank_f4[2]; /* for 3D mode */
 143         u8 v_blank_f5[2]; /* for 3D mode */
 144         u8 v_sync_line_aft_3[2];
 145         u8 v_sync_line_aft_4[2];
 146         u8 v_sync_line_aft_5[2];
 147         u8 v_sync_line_aft_6[2];
 148         u8 v_sync_line_aft_pxl_3[2];
 149         u8 v_sync_line_aft_pxl_4[2];
 150         u8 v_sync_line_aft_pxl_5[2];
 151         u8 v_sync_line_aft_pxl_6[2];
 152         u8 vact_space_1[2];
 153         u8 vact_space_2[2];
 154         u8 vact_space_3[2];
 155         u8 vact_space_4[2];
 156         u8 vact_space_5[2];
 157         u8 vact_space_6[2];
 158 };
 159
 160 struct hdmi_v13_conf {
 161         struct hdmi_v13_core_regs core;
 162         struct hdmi_tg_regs tg;
 163 };
 164
 165 struct hdmi_v14_conf {
 166         struct hdmi_v14_core_regs core;
 167         struct hdmi_tg_regs tg;
 168 };
 169
 170 struct hdmi_conf_regs {
 171         int pixel_clock;
 172         int cea_video_id;
 173         enum hdmi_picture_aspect aspect_ratio;
 174         union {
 175                 struct hdmi_v13_conf v13_conf;
 176                 struct hdmi_v14_conf v14_conf;
 177         } conf;
 178 };
 179
 180 struct hdmi_context {
 181         struct device                   *dev;
 182         struct drm_device               *drm_dev;
 183         struct drm_connector            connector;
 184         struct drm_encoder              *encoder;
 185         bool                            hpd;
 186         bool                            powered;
 187         bool                            dvi_mode;
 188         struct mutex                    hdmi_mutex;
 189
 190         void __iomem                    *regs;
 191         int                             irq;
 192         struct delayed_work             hotplug_work;
 193
 194         struct i2c_adapter              *ddc_adpt;
 195         struct i2c_client               *hdmiphy_port;
 196
 197         /* current hdmiphy conf regs */
 198         struct drm_display_mode         current_mode;
 199         struct hdmi_conf_regs           mode_conf;
 200
 201         struct hdmi_resources           res;
 202
 203         int                             hpd_gpio;
 204
 205         enum hdmi_type                  type;
 206 };
 207
 208 struct hdmiphy_config {
 209         int pixel_clock;
 210         u8 conf[32];
 211 };
 212
 213 static struct hdmi_driver_data exynos4212_hdmi_driver_data = {
 214         .type   = HDMI_TYPE14,
 215 };
 216
 217 static struct hdmi_driver_data exynos5_hdmi_driver_data = {
 218         .type   = HDMI_TYPE14,
 219 };
 220
 221 /* list of phy config settings */
 222 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
 223         {
 224                 .pixel_clock = 27000000,
 225                 .conf = {
 226                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 227                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 228                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 229                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 230                 },
 231         },
 232         {
 233                 .pixel_clock = 27027000,
 234                 .conf = {
 235                         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 236                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 237                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 238                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 239                 },
 240         },
 241         {
 242                 .pixel_clock = 74176000,
 243                 .conf = {
 244                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 245                         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 246                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 247                         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 248                 },
 249         },
 250         {
 251                 .pixel_clock = 74250000,
 252                 .conf = {
 253                         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 254                         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 255                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 256                         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 257                 },
 258         },
 259         {
 260                 .pixel_clock = 148500000,
 261                 .conf = {
 262                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 263                         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 264                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 265                         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 266                 },
 267         },
 268 };
 269
 270 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
 271         {
 272                 .pixel_clock = 25200000,
 273                 .conf = {
 274                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 275                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 276                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 277                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 278                 },
 279         },
 280         {
 281                 .pixel_clock = 27000000,
 282                 .conf = {
 283                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 284                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 285                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 286                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 287                 },
 288         },
 289         {
 290                 .pixel_clock = 27027000,
 291                 .conf = {
 292                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 293                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 294                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 295                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 296                 },
 297         },
 298         {
 299                 .pixel_clock = 36000000,
 300                 .conf = {
 301                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 302                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 303                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 304                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 305                 },
 306         },
 307         {
 308                 .pixel_clock = 40000000,
 309                 .conf = {
 310                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 311                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 312                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 313                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 314                 },
 315         },
 316         {
 317                 .pixel_clock = 65000000,
 318                 .conf = {
 319                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 320                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 321                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 322                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 323                 },
 324         },
 325         {
 326                 .pixel_clock = 71000000,
 327                 .conf = {
 328                         0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
 329                         0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 330                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 331                         0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 332                 },
 333         },
 334         {
 335                 .pixel_clock = 73250000,
 336                 .conf = {
 337                         0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
 338                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 339                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 340                         0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 341                 },
 342         },
 343         {
 344                 .pixel_clock = 74176000,
 345                 .conf = {
 346                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 347                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 348                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 349                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 350                 },
 351         },
 352         {
 353                 .pixel_clock = 74250000,
 354                 .conf = {
 355                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 356                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 357                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 358                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 359                 },
 360         },
 361         {
 362                 .pixel_clock = 83500000,
 363                 .conf = {
 364                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 365                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 366                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 367                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 368                 },
 369         },
 370         {
 371                 .pixel_clock = 106500000,
 372                 .conf = {
 373                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 374                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 375                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 376                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 377                 },
 378         },
 379         {
 380                 .pixel_clock = 108000000,
 381                 .conf = {
 382                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 383                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 384                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 385                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 386                 },
 387         },
 388         {
 389                 .pixel_clock = 115500000,
 390                 .conf = {
 391                         0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
 392                         0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 393                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 394                         0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 395                 },
 396         },
 397         {
 398                 .pixel_clock = 119000000,
 399                 .conf = {
 400                         0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
 401                         0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 402                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 403                         0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 404                 },
 405         },
 406         {
 407                 .pixel_clock = 146250000,
 408                 .conf = {
 409                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 410                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 411                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 412                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 413                 },
 414         },
 415         {
 416                 .pixel_clock = 148500000,
 417                 .conf = {
 418                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 419                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 420                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 421                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 422                 },
 423         },
 424 };
 425
 426 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 427 {
 428         return readl(hdata->regs + reg_id);
 429 }
 430
 431 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 432                                  u32 reg_id, u8 value)
 433 {
 434         writeb(value, hdata->regs + reg_id);
 435 }
 436
 437 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 438                                  u32 reg_id, u32 value, u32 mask)
 439 {
 440         u32 old = readl(hdata->regs + reg_id);
 441         value = (value & mask) | (old & ~mask);
 442         writel(value, hdata->regs + reg_id);
 443 }
 444
 445 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 446 {
 447 #define DUMPREG(reg_id) \
 448         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 449         readl(hdata->regs + reg_id))
 450         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 451         DUMPREG(HDMI_INTC_FLAG);
 452         DUMPREG(HDMI_INTC_CON);
 453         DUMPREG(HDMI_HPD_STATUS);
 454         DUMPREG(HDMI_V13_PHY_RSTOUT);
 455         DUMPREG(HDMI_V13_PHY_VPLL);
 456         DUMPREG(HDMI_V13_PHY_CMU);
 457         DUMPREG(HDMI_V13_CORE_RSTOUT);
 458
 459         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 460         DUMPREG(HDMI_CON_0);
 461         DUMPREG(HDMI_CON_1);
 462         DUMPREG(HDMI_CON_2);
 463         DUMPREG(HDMI_SYS_STATUS);
 464         DUMPREG(HDMI_V13_PHY_STATUS);
 465         DUMPREG(HDMI_STATUS_EN);
 466         DUMPREG(HDMI_HPD);
 467         DUMPREG(HDMI_MODE_SEL);
 468         DUMPREG(HDMI_V13_HPD_GEN);
 469         DUMPREG(HDMI_V13_DC_CONTROL);
 470         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 471
 472         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 473         DUMPREG(HDMI_H_BLANK_0);
 474         DUMPREG(HDMI_H_BLANK_1);
 475         DUMPREG(HDMI_V13_V_BLANK_0);
 476         DUMPREG(HDMI_V13_V_BLANK_1);
 477         DUMPREG(HDMI_V13_V_BLANK_2);
 478         DUMPREG(HDMI_V13_H_V_LINE_0);
 479         DUMPREG(HDMI_V13_H_V_LINE_1);
 480         DUMPREG(HDMI_V13_H_V_LINE_2);
 481         DUMPREG(HDMI_VSYNC_POL);
 482         DUMPREG(HDMI_INT_PRO_MODE);
 483         DUMPREG(HDMI_V13_V_BLANK_F_0);
 484         DUMPREG(HDMI_V13_V_BLANK_F_1);
 485         DUMPREG(HDMI_V13_V_BLANK_F_2);
 486         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 487         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 488         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 489         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 490         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 491         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 492         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 493         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 494         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 495         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 496         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 497         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 498
 499         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 500         DUMPREG(HDMI_TG_CMD);
 501         DUMPREG(HDMI_TG_H_FSZ_L);
 502         DUMPREG(HDMI_TG_H_FSZ_H);
 503         DUMPREG(HDMI_TG_HACT_ST_L);
 504         DUMPREG(HDMI_TG_HACT_ST_H);
 505         DUMPREG(HDMI_TG_HACT_SZ_L);
 506         DUMPREG(HDMI_TG_HACT_SZ_H);
 507         DUMPREG(HDMI_TG_V_FSZ_L);
 508         DUMPREG(HDMI_TG_V_FSZ_H);
 509         DUMPREG(HDMI_TG_VSYNC_L);
 510         DUMPREG(HDMI_TG_VSYNC_H);
 511         DUMPREG(HDMI_TG_VSYNC2_L);
 512         DUMPREG(HDMI_TG_VSYNC2_H);
 513         DUMPREG(HDMI_TG_VACT_ST_L);
 514         DUMPREG(HDMI_TG_VACT_ST_H);
 515         DUMPREG(HDMI_TG_VACT_SZ_L);
 516         DUMPREG(HDMI_TG_VACT_SZ_H);
 517         DUMPREG(HDMI_TG_FIELD_CHG_L);
 518         DUMPREG(HDMI_TG_FIELD_CHG_H);
 519         DUMPREG(HDMI_TG_VACT_ST2_L);
 520         DUMPREG(HDMI_TG_VACT_ST2_H);
 521         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 522         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 523         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 524         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 525         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 526         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 527         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 528         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 529 #undef DUMPREG
 530 }
 531
 532 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 533 {
 534         int i;
 535
 536 #define DUMPREG(reg_id) \
 537         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 538         readl(hdata->regs + reg_id))
 539
 540         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 541         DUMPREG(HDMI_INTC_CON);
 542         DUMPREG(HDMI_INTC_FLAG);
 543         DUMPREG(HDMI_HPD_STATUS);
 544         DUMPREG(HDMI_INTC_CON_1);
 545         DUMPREG(HDMI_INTC_FLAG_1);
 546         DUMPREG(HDMI_PHY_STATUS_0);
 547         DUMPREG(HDMI_PHY_STATUS_PLL);
 548         DUMPREG(HDMI_PHY_CON_0);
 549         DUMPREG(HDMI_PHY_RSTOUT);
 550         DUMPREG(HDMI_PHY_VPLL);
 551         DUMPREG(HDMI_PHY_CMU);
 552         DUMPREG(HDMI_CORE_RSTOUT);
 553
 554         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 555         DUMPREG(HDMI_CON_0);
 556         DUMPREG(HDMI_CON_1);
 557         DUMPREG(HDMI_CON_2);
 558         DUMPREG(HDMI_SYS_STATUS);
 559         DUMPREG(HDMI_PHY_STATUS_0);
 560         DUMPREG(HDMI_STATUS_EN);
 561         DUMPREG(HDMI_HPD);
 562         DUMPREG(HDMI_MODE_SEL);
 563         DUMPREG(HDMI_ENC_EN);
 564         DUMPREG(HDMI_DC_CONTROL);
 565         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 566
 567         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 568         DUMPREG(HDMI_H_BLANK_0);
 569         DUMPREG(HDMI_H_BLANK_1);
 570         DUMPREG(HDMI_V2_BLANK_0);
 571         DUMPREG(HDMI_V2_BLANK_1);
 572         DUMPREG(HDMI_V1_BLANK_0);
 573         DUMPREG(HDMI_V1_BLANK_1);
 574         DUMPREG(HDMI_V_LINE_0);
 575         DUMPREG(HDMI_V_LINE_1);
 576         DUMPREG(HDMI_H_LINE_0);
 577         DUMPREG(HDMI_H_LINE_1);
 578         DUMPREG(HDMI_HSYNC_POL);
 579
 580         DUMPREG(HDMI_VSYNC_POL);
 581         DUMPREG(HDMI_INT_PRO_MODE);
 582         DUMPREG(HDMI_V_BLANK_F0_0);
 583         DUMPREG(HDMI_V_BLANK_F0_1);
 584         DUMPREG(HDMI_V_BLANK_F1_0);
 585         DUMPREG(HDMI_V_BLANK_F1_1);
 586
 587         DUMPREG(HDMI_H_SYNC_START_0);
 588         DUMPREG(HDMI_H_SYNC_START_1);
 589         DUMPREG(HDMI_H_SYNC_END_0);
 590         DUMPREG(HDMI_H_SYNC_END_1);
 591
 592         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 593         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 594         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 595         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 596
 597         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 598         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 599         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 600         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 601
 602         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 603         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 604         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 605         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 606
 607         DUMPREG(HDMI_V_BLANK_F2_0);
 608         DUMPREG(HDMI_V_BLANK_F2_1);
 609         DUMPREG(HDMI_V_BLANK_F3_0);
 610         DUMPREG(HDMI_V_BLANK_F3_1);
 611         DUMPREG(HDMI_V_BLANK_F4_0);
 612         DUMPREG(HDMI_V_BLANK_F4_1);
 613         DUMPREG(HDMI_V_BLANK_F5_0);
 614         DUMPREG(HDMI_V_BLANK_F5_1);
 615
 616         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 617         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 618         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 619         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 620         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 621         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 622         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 623         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 624
 625         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 626         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 627         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 628         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 629         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 630         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 631         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 632         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 633
 634         DUMPREG(HDMI_VACT_SPACE_1_0);
 635         DUMPREG(HDMI_VACT_SPACE_1_1);
 636         DUMPREG(HDMI_VACT_SPACE_2_0);
 637         DUMPREG(HDMI_VACT_SPACE_2_1);
 638         DUMPREG(HDMI_VACT_SPACE_3_0);
 639         DUMPREG(HDMI_VACT_SPACE_3_1);
 640         DUMPREG(HDMI_VACT_SPACE_4_0);
 641         DUMPREG(HDMI_VACT_SPACE_4_1);
 642         DUMPREG(HDMI_VACT_SPACE_5_0);
 643         DUMPREG(HDMI_VACT_SPACE_5_1);
 644         DUMPREG(HDMI_VACT_SPACE_6_0);
 645         DUMPREG(HDMI_VACT_SPACE_6_1);
 646
 647         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 648         DUMPREG(HDMI_TG_CMD);
 649         DUMPREG(HDMI_TG_H_FSZ_L);
 650         DUMPREG(HDMI_TG_H_FSZ_H);
 651         DUMPREG(HDMI_TG_HACT_ST_L);
 652         DUMPREG(HDMI_TG_HACT_ST_H);
 653         DUMPREG(HDMI_TG_HACT_SZ_L);
 654         DUMPREG(HDMI_TG_HACT_SZ_H);
 655         DUMPREG(HDMI_TG_V_FSZ_L);
 656         DUMPREG(HDMI_TG_V_FSZ_H);
 657         DUMPREG(HDMI_TG_VSYNC_L);
 658         DUMPREG(HDMI_TG_VSYNC_H);
 659         DUMPREG(HDMI_TG_VSYNC2_L);
 660         DUMPREG(HDMI_TG_VSYNC2_H);
 661         DUMPREG(HDMI_TG_VACT_ST_L);
 662         DUMPREG(HDMI_TG_VACT_ST_H);
 663         DUMPREG(HDMI_TG_VACT_SZ_L);
 664         DUMPREG(HDMI_TG_VACT_SZ_H);
 665         DUMPREG(HDMI_TG_FIELD_CHG_L);
 666         DUMPREG(HDMI_TG_FIELD_CHG_H);
 667         DUMPREG(HDMI_TG_VACT_ST2_L);
 668         DUMPREG(HDMI_TG_VACT_ST2_H);
 669         DUMPREG(HDMI_TG_VACT_ST3_L);
 670         DUMPREG(HDMI_TG_VACT_ST3_H);
 671         DUMPREG(HDMI_TG_VACT_ST4_L);
 672         DUMPREG(HDMI_TG_VACT_ST4_H);
 673         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 674         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 675         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 676         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 677         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 678         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 679         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 680         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 681         DUMPREG(HDMI_TG_3D);
 682
 683         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 684         DUMPREG(HDMI_AVI_CON);
 685         DUMPREG(HDMI_AVI_HEADER0);
 686         DUMPREG(HDMI_AVI_HEADER1);
 687         DUMPREG(HDMI_AVI_HEADER2);
 688         DUMPREG(HDMI_AVI_CHECK_SUM);
 689         DUMPREG(HDMI_VSI_CON);
 690         DUMPREG(HDMI_VSI_HEADER0);
 691         DUMPREG(HDMI_VSI_HEADER1);
 692         DUMPREG(HDMI_VSI_HEADER2);
 693         for (i = 0; i < 7; ++i)
 694                 DUMPREG(HDMI_VSI_DATA(i));
 695
 696 #undef DUMPREG
 697 }
 698
 699 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 700 {
 701         if (hdata->type == HDMI_TYPE13)
 702                 hdmi_v13_regs_dump(hdata, prefix);
 703         else
 704                 hdmi_v14_regs_dump(hdata, prefix);
 705 }
 706
 707 static u8 hdmi_chksum(struct hdmi_context *hdata,
 708                         u32 start, u8 len, u32 hdr_sum)
 709 {
 710         int i;
 711
 712         /* hdr_sum : header0 + header1 + header2
 713         * start : start address of packet byte1
 714         * len : packet bytes - 1 */
 715         for (i = 0; i < len; ++i)
 716                 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
 717
 718         /* return 2's complement of 8 bit hdr_sum */
 719         return (u8)(~(hdr_sum & 0xff) + 1);
 720 }
 721
 722 static void hdmi_reg_infoframe(struct hdmi_context *hdata,
 723                         union hdmi_infoframe *infoframe)
 724 {
 725         u32 hdr_sum;
 726         u8 chksum;
 727         u32 mod;
 728         u32 vic;
 729
 730         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 731         if (hdata->dvi_mode) {
 732                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 733                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 734                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 735                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 736                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 737                 return;
 738         }
 739
 740         switch (infoframe->any.type) {
 741         case HDMI_INFOFRAME_TYPE_AVI:
 742                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
 743                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
 744                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
 745                                 infoframe->any.version);
 746                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
 747                 hdr_sum = infoframe->any.type + infoframe->any.version +
 748                           infoframe->any.length;
 749
 750                 /* Output format zero hardcoded ,RGB YBCR selection */
 751                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
 752                         AVI_ACTIVE_FORMAT_VALID |
 753                         AVI_UNDERSCANNED_DISPLAY_VALID);
 754
 755                 /*
 756                  * Set the aspect ratio as per the mode, mentioned in
 757                  * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
 758                  */
 759                 switch (hdata->mode_conf.aspect_ratio) {
 760                 case HDMI_PICTURE_ASPECT_4_3:
 761                         hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
 762                                         hdata->mode_conf.aspect_ratio |
 763                                         AVI_4_3_CENTER_RATIO);
 764                         break;
 765                 case HDMI_PICTURE_ASPECT_16_9:
 766                         hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
 767                                         hdata->mode_conf.aspect_ratio |
 768                                         AVI_16_9_CENTER_RATIO);
 769                         break;
 770                 case HDMI_PICTURE_ASPECT_NONE:
 771                 default:
 772                         hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
 773                                         hdata->mode_conf.aspect_ratio |
 774                                         AVI_SAME_AS_PIC_ASPECT_RATIO);
 775                         break;
 776                 }
 777
 778                 vic = hdata->mode_conf.cea_video_id;
 779                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
 780
 781                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
 782                                         infoframe->any.length, hdr_sum);
 783                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
 784                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
 785                 break;
 786         case HDMI_INFOFRAME_TYPE_AUDIO:
 787                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
 788                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
 789                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
 790                                 infoframe->any.version);
 791                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
 792                 hdr_sum = infoframe->any.type + infoframe->any.version +
 793                           infoframe->any.length;
 794                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
 795                                         infoframe->any.length, hdr_sum);
 796                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
 797                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
 798                 break;
 799         default:
 800                 break;
 801         }
 802 }
 803
 804 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
 805                                 bool force)
 806 {
 807         struct hdmi_context *hdata = ctx_from_connector(connector);
 808
 809         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
 810
 811         return hdata->hpd ? connector_status_connected :
 812                         connector_status_disconnected;
 813 }
 814
 815 static void hdmi_connector_destroy(struct drm_connector *connector)
 816 {
 817 }
 818
 819 static struct drm_connector_funcs hdmi_connector_funcs = {
 820         .dpms = drm_helper_connector_dpms,
 821         .fill_modes = drm_helper_probe_single_connector_modes,
 822         .detect = hdmi_detect,
 823         .destroy = hdmi_connector_destroy,
 824 };
 825
 826 static int hdmi_get_modes(struct drm_connector *connector)
 827 {
 828         struct hdmi_context *hdata = ctx_from_connector(connector);
 829         struct edid *edid;
 830
 831         if (!hdata->ddc_adpt)
 832                 return -ENODEV;
 833
 834         edid = drm_get_edid(connector, hdata->ddc_adpt);
 835         if (!edid)
 836                 return -ENODEV;
 837
 838         hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
 839         DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
 840                 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
 841                 edid->width_cm, edid->height_cm);
 842
 843         drm_mode_connector_update_edid_property(connector, edid);
 844
 845         return drm_add_edid_modes(connector, edid);
 846 }
 847
 848 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
 849 {
 850         const struct hdmiphy_config *confs;
 851         int count, i;
 852
 853         if (hdata->type == HDMI_TYPE13) {
 854                 confs = hdmiphy_v13_configs;
 855                 count = ARRAY_SIZE(hdmiphy_v13_configs);
 856         } else if (hdata->type == HDMI_TYPE14) {
 857                 confs = hdmiphy_v14_configs;
 858                 count = ARRAY_SIZE(hdmiphy_v14_configs);
 859         } else
 860                 return -EINVAL;
 861
 862         for (i = 0; i < count; i++)
 863                 if (confs[i].pixel_clock == pixel_clock)
 864                         return i;
 865
 866         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 867         return -EINVAL;
 868 }
 869
 870 static int hdmi_mode_valid(struct drm_connector *connector,
 871                         struct drm_display_mode *mode)
 872 {
 873         struct hdmi_context *hdata = ctx_from_connector(connector);
 874         int ret;
 875
 876         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
 877                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
 878                 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
 879                 false, mode->clock * 1000);
 880
 881         ret = mixer_check_mode(mode);
 882         if (ret)
 883                 return MODE_BAD;
 884
 885         ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
 886         if (ret < 0)
 887                 return MODE_BAD;
 888
 889         return MODE_OK;
 890 }
 891
 892 static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
 893 {
 894         struct hdmi_context *hdata = ctx_from_connector(connector);
 895
 896         return hdata->encoder;
 897 }
 898
 899 static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
 900         .get_modes = hdmi_get_modes,
 901         .mode_valid = hdmi_mode_valid,
 902         .best_encoder = hdmi_best_encoder,
 903 };
 904
 905 static int hdmi_create_connector(struct exynos_drm_display *display,
 906                         struct drm_encoder *encoder)
 907 {
 908         struct hdmi_context *hdata = display->ctx;
 909         struct drm_connector *connector = &hdata->connector;
 910         int ret;
 911
 912         hdata->encoder = encoder;
 913         connector->interlace_allowed = true;
 914         connector->polled = DRM_CONNECTOR_POLL_HPD;
 915
 916         ret = drm_connector_init(hdata->drm_dev, connector,
 917                         &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
 918         if (ret) {
 919                 DRM_ERROR("Failed to initialize connector with drm\n");
 920                 return ret;
 921         }
 922
 923         drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
 924         drm_sysfs_connector_add(connector);
 925         drm_mode_connector_attach_encoder(connector, encoder);
 926
 927         return 0;
 928 }
 929
 930 static void hdmi_mode_fixup(struct exynos_drm_display *display,
 931                                 struct drm_connector *connector,
 932                                 const struct drm_display_mode *mode,
 933                                 struct drm_display_mode *adjusted_mode)
 934 {
 935         struct drm_display_mode *m;
 936         int mode_ok;
 937
 938         DRM_DEBUG_KMS("%s\n", __FILE__);
 939
 940         drm_mode_set_crtcinfo(adjusted_mode, 0);
 941
 942         mode_ok = hdmi_mode_valid(connector, adjusted_mode);
 943
 944         /* just return if user desired mode exists. */
 945         if (mode_ok == MODE_OK)
 946                 return;
 947
 948         /*
 949          * otherwise, find the most suitable mode among modes and change it
 950          * to adjusted_mode.
 951          */
 952         list_for_each_entry(m, &connector->modes, head) {
 953                 mode_ok = hdmi_mode_valid(connector, m);
 954
 955                 if (mode_ok == MODE_OK) {
 956                         DRM_INFO("desired mode doesn't exist so\n");
 957                         DRM_INFO("use the most suitable mode among modes.\n");
 958
 959                         DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
 960                                 m->hdisplay, m->vdisplay, m->vrefresh);
 961
 962                         drm_mode_copy(adjusted_mode, m);
 963                         break;
 964                 }
 965         }
 966 }
 967
 968 static void hdmi_set_acr(u32 freq, u8 *acr)
 969 {
 970         u32 n, cts;
 971
 972         switch (freq) {
 973         case 32000:
 974                 n = 4096;
 975                 cts = 27000;
 976                 break;
 977         case 44100:
 978                 n = 6272;
 979                 cts = 30000;
 980                 break;
 981         case 88200:
 982                 n = 12544;
 983                 cts = 30000;
 984                 break;
 985         case 176400:
 986                 n = 25088;
 987                 cts = 30000;
 988                 break;
 989         case 48000:
 990                 n = 6144;
 991                 cts = 27000;
 992                 break;
 993         case 96000:
 994                 n = 12288;
 995                 cts = 27000;
 996                 break;
 997         case 192000:
 998                 n = 24576;
 999                 cts = 27000;
1000                 break;
1001         default:
1002                 n = 0;
1003                 cts = 0;
1004                 break;
1005         }
1006
1007         acr[1] = cts >> 16;
1008         acr[2] = cts >> 8 & 0xff;
1009         acr[3] = cts & 0xff;
1010
1011         acr[4] = n >> 16;
1012         acr[5] = n >> 8 & 0xff;
1013         acr[6] = n & 0xff;
1014 }
1015
1016 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1017 {
1018         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1019         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1020         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1021         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1022         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1023         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1024         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1025         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1026         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1027
1028         if (hdata->type == HDMI_TYPE13)
1029                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1030         else
1031                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1032 }
1033
1034 static void hdmi_audio_init(struct hdmi_context *hdata)
1035 {
1036         u32 sample_rate, bits_per_sample, frame_size_code;
1037         u32 data_num, bit_ch, sample_frq;
1038         u32 val;
1039         u8 acr[7];
1040
1041         sample_rate = 44100;
1042         bits_per_sample = 16;
1043         frame_size_code = 0;
1044
1045         switch (bits_per_sample) {
1046         case 20:
1047                 data_num = 2;
1048                 bit_ch  = 1;
1049                 break;
1050         case 24:
1051                 data_num = 3;
1052                 bit_ch  = 1;
1053                 break;
1054         default:
1055                 data_num = 1;
1056                 bit_ch  = 0;
1057                 break;
1058         }
1059
1060         hdmi_set_acr(sample_rate, acr);
1061         hdmi_reg_acr(hdata, acr);
1062
1063         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1064                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1065                                 | HDMI_I2S_MUX_ENABLE);
1066
1067         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1068                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1069
1070         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1071
1072         sample_frq = (sample_rate == 44100) ? 0 :
1073                         (sample_rate == 48000) ? 2 :
1074                         (sample_rate == 32000) ? 3 :
1075                         (sample_rate == 96000) ? 0xa : 0x0;
1076
1077         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1078         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1079
1080         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1081         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1082
1083         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1084         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1085                         | HDMI_I2S_SEL_LRCK(6));
1086         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1087                         | HDMI_I2S_SEL_SDATA2(4));
1088         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1089                         | HDMI_I2S_SEL_SDATA2(2));
1090         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1091
1092         /* I2S_CON_1 & 2 */
1093         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1094                         | HDMI_I2S_L_CH_LOW_POL);
1095         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1096                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1097                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1098                         | HDMI_I2S_BASIC_FORMAT);
1099
1100         /* Configure register related to CUV information */
1101         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1102                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1103                         | HDMI_I2S_COPYRIGHT
1104                         | HDMI_I2S_LINEAR_PCM
1105                         | HDMI_I2S_CONSUMER_FORMAT);
1106         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1107         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1108         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1109                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1110         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1111                         HDMI_I2S_ORG_SMP_FREQ_44_1
1112                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1113                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1114
1115         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1116 }
1117
1118 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1119 {
1120         if (hdata->dvi_mode)
1121                 return;
1122
1123         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1124         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1125                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1126 }
1127
1128 static void hdmi_start(struct hdmi_context *hdata, bool start)
1129 {
1130         u32 val = start ? HDMI_TG_EN : 0;
1131
1132         if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1133                 val |= HDMI_FIELD_EN;
1134
1135         hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1136         hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1137 }
1138
1139 static void hdmi_conf_init(struct hdmi_context *hdata)
1140 {
1141         union hdmi_infoframe infoframe;
1142
1143         /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1144         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1145                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1146
1147         /* choose HDMI mode */
1148         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1149                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1150         /* disable bluescreen */
1151         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1152
1153         if (hdata->dvi_mode) {
1154                 /* choose DVI mode */
1155                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1156                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1157                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1158                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1159         }
1160
1161         if (hdata->type == HDMI_TYPE13) {
1162                 /* choose bluescreen (fecal) color */
1163                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1164                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1165                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1166
1167                 /* enable AVI packet every vsync, fixes purple line problem */
1168                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1169                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1170                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1171                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1172
1173                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1174                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1175                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1176         } else {
1177                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1178                 infoframe.any.version = HDMI_AVI_VERSION;
1179                 infoframe.any.length = HDMI_AVI_LENGTH;
1180                 hdmi_reg_infoframe(hdata, &infoframe);
1181
1182                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1183                 infoframe.any.version = HDMI_AUI_VERSION;
1184                 infoframe.any.length = HDMI_AUI_LENGTH;
1185                 hdmi_reg_infoframe(hdata, &infoframe);
1186
1187                 /* enable AVI packet every vsync, fixes purple line problem */
1188                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1189         }
1190 }
1191
1192 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1193 {
1194         const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1195         const struct hdmi_v13_core_regs *core =
1196                 &hdata->mode_conf.conf.v13_conf.core;
1197         int tries;
1198
1199         /* setting core registers */
1200         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1201         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1202         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1203         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1204         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1205         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1206         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1207         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1208         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1209         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1210         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1211         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1212         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1213         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1214         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1215         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1216         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1217         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1218         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1219         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1220         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1221         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1222         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1223         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1224         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1225         /* Timing generator registers */
1226         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1227         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1228         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1229         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1230         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1231         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1232         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1233         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1234         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1235         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1236         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1237         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1238         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1239         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1240         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1241         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1242         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1243         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1244         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1245         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1246         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1247         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1248         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1249         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1250         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1251         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1252         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1253         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1254
1255         /* waiting for HDMIPHY's PLL to get to steady state */
1256         for (tries = 100; tries; --tries) {
1257                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1258                 if (val & HDMI_PHY_STATUS_READY)
1259                         break;
1260                 usleep_range(1000, 2000);
1261         }
1262         /* steady state not achieved */
1263         if (tries == 0) {
1264                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1265                 hdmi_regs_dump(hdata, "timing apply");
1266         }
1267
1268         clk_disable_unprepare(hdata->res.sclk_hdmi);
1269         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1270         clk_prepare_enable(hdata->res.sclk_hdmi);
1271
1272         /* enable HDMI and timing generator */
1273         hdmi_start(hdata, true);
1274 }
1275
1276 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1277 {
1278         const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1279         const struct hdmi_v14_core_regs *core =
1280                 &hdata->mode_conf.conf.v14_conf.core;
1281         int tries;
1282
1283         /* setting core registers */
1284         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1285         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1286         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1287         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1288         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1289         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1290         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1291         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1292         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1293         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1294         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1295         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1296         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1297         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1298         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1299         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1300         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1301         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1302         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1303         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1304         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1305         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1306                         core->v_sync_line_bef_2[0]);
1307         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1308                         core->v_sync_line_bef_2[1]);
1309         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1310                         core->v_sync_line_bef_1[0]);
1311         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1312                         core->v_sync_line_bef_1[1]);
1313         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1314                         core->v_sync_line_aft_2[0]);
1315         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1316                         core->v_sync_line_aft_2[1]);
1317         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1318                         core->v_sync_line_aft_1[0]);
1319         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1320                         core->v_sync_line_aft_1[1]);
1321         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1322                         core->v_sync_line_aft_pxl_2[0]);
1323         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1324                         core->v_sync_line_aft_pxl_2[1]);
1325         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1326                         core->v_sync_line_aft_pxl_1[0]);
1327         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1328                         core->v_sync_line_aft_pxl_1[1]);
1329         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1330         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1331         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1332         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1333         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1334         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1335         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1336         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1337         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1338                         core->v_sync_line_aft_3[0]);
1339         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1340                         core->v_sync_line_aft_3[1]);
1341         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1342                         core->v_sync_line_aft_4[0]);
1343         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1344                         core->v_sync_line_aft_4[1]);
1345         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1346                         core->v_sync_line_aft_5[0]);
1347         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1348                         core->v_sync_line_aft_5[1]);
1349         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1350                         core->v_sync_line_aft_6[0]);
1351         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1352                         core->v_sync_line_aft_6[1]);
1353         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1354                         core->v_sync_line_aft_pxl_3[0]);
1355         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1356                         core->v_sync_line_aft_pxl_3[1]);
1357         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1358                         core->v_sync_line_aft_pxl_4[0]);
1359         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1360                         core->v_sync_line_aft_pxl_4[1]);
1361         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1362                         core->v_sync_line_aft_pxl_5[0]);
1363         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1364                         core->v_sync_line_aft_pxl_5[1]);
1365         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1366                         core->v_sync_line_aft_pxl_6[0]);
1367         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1368                         core->v_sync_line_aft_pxl_6[1]);
1369         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1370         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1371         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1372         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1373         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1374         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1375         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1376         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1377         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1378         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1379         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1380         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1381
1382         /* Timing generator registers */
1383         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1384         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1385         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1386         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1387         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1388         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1389         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1390         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1391         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1392         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1393         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1394         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1395         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1396         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1397         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1398         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1399         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1400         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1401         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1402         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1403         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1404         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1405         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1406         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1407         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1408         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1409         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1410         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1411         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1412         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1413         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1414         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1415         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1416
1417         /* waiting for HDMIPHY's PLL to get to steady state */
1418         for (tries = 100; tries; --tries) {
1419                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1420                 if (val & HDMI_PHY_STATUS_READY)
1421                         break;
1422                 usleep_range(1000, 2000);
1423         }
1424         /* steady state not achieved */
1425         if (tries == 0) {
1426                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1427                 hdmi_regs_dump(hdata, "timing apply");
1428         }
1429
1430         clk_disable_unprepare(hdata->res.sclk_hdmi);
1431         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1432         clk_prepare_enable(hdata->res.sclk_hdmi);
1433
1434         /* enable HDMI and timing generator */
1435         hdmi_start(hdata, true);
1436 }
1437
1438 static void hdmi_mode_apply(struct hdmi_context *hdata)
1439 {
1440         if (hdata->type == HDMI_TYPE13)
1441                 hdmi_v13_mode_apply(hdata);
1442         else
1443                 hdmi_v14_mode_apply(hdata);
1444 }
1445
1446 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1447 {
1448         u8 buffer[2];
1449         u32 reg;
1450
1451         clk_disable_unprepare(hdata->res.sclk_hdmi);
1452         clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
1453         clk_prepare_enable(hdata->res.sclk_hdmi);
1454
1455         /* operation mode */
1456         buffer[0] = 0x1f;
1457         buffer[1] = 0x00;
1458
1459         if (hdata->hdmiphy_port)
1460                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1461
1462         if (hdata->type == HDMI_TYPE13)
1463                 reg = HDMI_V13_PHY_RSTOUT;
1464         else
1465                 reg = HDMI_PHY_RSTOUT;
1466
1467         /* reset hdmiphy */
1468         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1469         usleep_range(10000, 12000);
1470         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1471         usleep_range(10000, 12000);
1472 }
1473
1474 static void hdmiphy_poweron(struct hdmi_context *hdata)
1475 {
1476         if (hdata->type == HDMI_TYPE14)
1477                 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
1478                         HDMI_PHY_POWER_OFF_EN);
1479 }
1480
1481 static void hdmiphy_poweroff(struct hdmi_context *hdata)
1482 {
1483         if (hdata->type == HDMI_TYPE14)
1484                 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
1485                         HDMI_PHY_POWER_OFF_EN);
1486 }
1487
1488 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1489 {
1490         const u8 *hdmiphy_data;
1491         u8 buffer[32];
1492         u8 operation[2];
1493         u8 read_buffer[32] = {0, };
1494         int ret;
1495         int i;
1496
1497         if (!hdata->hdmiphy_port) {
1498                 DRM_ERROR("hdmiphy is not attached\n");
1499                 return;
1500         }
1501
1502         /* pixel clock */
1503         i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1504         if (i < 0) {
1505                 DRM_ERROR("failed to find hdmiphy conf\n");
1506                 return;
1507         }
1508
1509         if (hdata->type == HDMI_TYPE13)
1510                 hdmiphy_data = hdmiphy_v13_configs[i].conf;
1511         else
1512                 hdmiphy_data = hdmiphy_v14_configs[i].conf;
1513
1514         memcpy(buffer, hdmiphy_data, 32);
1515         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1516         if (ret != 32) {
1517                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1518                 return;
1519         }
1520
1521         usleep_range(10000, 12000);
1522
1523         /* operation mode */
1524         operation[0] = 0x1f;
1525         operation[1] = 0x80;
1526
1527         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1528         if (ret != 2) {
1529                 DRM_ERROR("failed to enable hdmiphy\n");
1530                 return;
1531         }
1532
1533         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1534         if (ret < 0) {
1535                 DRM_ERROR("failed to read hdmiphy config\n");
1536                 return;
1537         }
1538
1539         for (i = 0; i < ret; i++)
1540                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1541                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1542 }
1543
1544 static void hdmi_conf_apply(struct hdmi_context *hdata)
1545 {
1546         hdmiphy_conf_reset(hdata);
1547         hdmiphy_conf_apply(hdata);
1548
1549         mutex_lock(&hdata->hdmi_mutex);
1550         hdmi_start(hdata, false);
1551         hdmi_conf_init(hdata);
1552         mutex_unlock(&hdata->hdmi_mutex);
1553
1554         hdmi_audio_init(hdata);
1555
1556         /* setting core registers */
1557         hdmi_mode_apply(hdata);
1558         hdmi_audio_control(hdata, true);
1559
1560         hdmi_regs_dump(hdata, "start");
1561 }
1562
1563 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1564 {
1565         int i;
1566         BUG_ON(num_bytes > 4);
1567         for (i = 0; i < num_bytes; i++)
1568                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1569 }
1570
1571 static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1572                         struct drm_display_mode *m)
1573 {
1574         struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1575         struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1576         unsigned int val;
1577
1578         hdata->mode_conf.cea_video_id =
1579                 drm_match_cea_mode((struct drm_display_mode *)m);
1580         hdata->mode_conf.pixel_clock = m->clock * 1000;
1581         hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1582
1583         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1584         hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1585
1586         val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1587         hdmi_set_reg(core->vsync_pol, 1, val);
1588
1589         val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1590         hdmi_set_reg(core->int_pro_mode, 1, val);
1591
1592         val = (m->hsync_start - m->hdisplay - 2);
1593         val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1594         val |= ((m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0)<<20;
1595         hdmi_set_reg(core->h_sync_gen, 3, val);
1596
1597         /*
1598          * Quirk requirement for exynos HDMI IP design,
1599          * 2 pixels less than the actual calculation for hsync_start
1600          * and end.
1601          */
1602
1603         /* Following values & calculations differ for different type of modes */
1604         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1605                 /* Interlaced Mode */
1606                 val = ((m->vsync_end - m->vdisplay) / 2);
1607                 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1608                 hdmi_set_reg(core->v_sync_gen1, 3, val);
1609
1610                 val = m->vtotal / 2;
1611                 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1612                 hdmi_set_reg(core->v_blank, 3, val);
1613
1614                 val = (m->vtotal +
1615                         ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1616                 val |= m->vtotal << 11;
1617                 hdmi_set_reg(core->v_blank_f, 3, val);
1618
1619                 val = ((m->vtotal / 2) + 7);
1620                 val |= ((m->vtotal / 2) + 2) << 12;
1621                 hdmi_set_reg(core->v_sync_gen2, 3, val);
1622
1623                 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1624                 val |= ((m->htotal / 2) +
1625                         (m->hsync_start - m->hdisplay)) << 12;
1626                 hdmi_set_reg(core->v_sync_gen3, 3, val);
1627
1628                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1629                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1630
1631                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1632         } else {
1633                 /* Progressive Mode */
1634
1635                 val = m->vtotal;
1636                 val |= (m->vtotal - m->vdisplay) << 11;
1637                 hdmi_set_reg(core->v_blank, 3, val);
1638
1639                 hdmi_set_reg(core->v_blank_f, 3, 0);
1640
1641                 val = (m->vsync_end - m->vdisplay);
1642                 val |= ((m->vsync_start - m->vdisplay) << 12);
1643                 hdmi_set_reg(core->v_sync_gen1, 3, val);
1644
1645                 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value  */
1646                 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value  */
1647                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1648                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1649                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1650         }
1651
1652         /* Timing generator registers */
1653         hdmi_set_reg(tg->cmd, 1, 0x0);
1654         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1655         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1656         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1657         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1658         hdmi_set_reg(tg->vsync, 2, 0x1);
1659         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1660         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1661         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1662         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1663         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1664         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1665         hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1666 }
1667
1668 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1669                         struct drm_display_mode *m)
1670 {
1671         struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1672         struct hdmi_v14_core_regs *core =
1673                 &hdata->mode_conf.conf.v14_conf.core;
1674
1675         hdata->mode_conf.cea_video_id =
1676                 drm_match_cea_mode((struct drm_display_mode *)m);
1677         hdata->mode_conf.pixel_clock = m->clock * 1000;
1678         hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1679
1680         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1681         hdmi_set_reg(core->v_line, 2, m->vtotal);
1682         hdmi_set_reg(core->h_line, 2, m->htotal);
1683         hdmi_set_reg(core->hsync_pol, 1,
1684                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1685         hdmi_set_reg(core->vsync_pol, 1,
1686                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1687         hdmi_set_reg(core->int_pro_mode, 1,
1688                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1689
1690         /*
1691          * Quirk requirement for exynos 5 HDMI IP design,
1692          * 2 pixels less than the actual calculation for hsync_start
1693          * and end.
1694          */
1695
1696         /* Following values & calculations differ for different type of modes */
1697         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1698                 /* Interlaced Mode */
1699                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1700                         (m->vsync_end - m->vdisplay) / 2);
1701                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1702                         (m->vsync_start - m->vdisplay) / 2);
1703                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1704                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1705                 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
1706                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1707                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1708                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1709                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1710                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1711                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1712                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1713                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1714                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1715                 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1716                 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1717                 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1718                 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
1719                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1720                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1721         } else {
1722                 /* Progressive Mode */
1723                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1724                         m->vsync_end - m->vdisplay);
1725                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1726                         m->vsync_start - m->vdisplay);
1727                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1728                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1729                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1730                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1731                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1732                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1733                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1734                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1735                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1736                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1737                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1738                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1739                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1740                 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1741                 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1742                 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1743         }
1744
1745         /* Following values & calculations are same irrespective of mode type */
1746         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1747         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1748         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1749         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1750         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1751         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1752         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1753         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1754         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1755         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1756         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1757         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1758         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1759         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1760         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1761         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1762         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1763         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1764         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1765         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1766
1767         /* Timing generator registers */
1768         hdmi_set_reg(tg->cmd, 1, 0x0);
1769         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1770         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1771         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1772         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1773         hdmi_set_reg(tg->vsync, 2, 0x1);
1774         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1775         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1776         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1777         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1778 }
1779
1780 static void hdmi_mode_set(struct exynos_drm_display *display,
1781                         struct drm_display_mode *mode)
1782 {
1783         struct hdmi_context *hdata = display->ctx;
1784         struct drm_display_mode *m = mode;
1785
1786         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1787                 m->hdisplay, m->vdisplay,
1788                 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1789                 "INTERLACED" : "PROGERESSIVE");
1790
1791         /* preserve mode information for later use. */
1792         drm_mode_copy(&hdata->current_mode, mode);
1793
1794         if (hdata->type == HDMI_TYPE13)
1795                 hdmi_v13_mode_set(hdata, mode);
1796         else
1797                 hdmi_v14_mode_set(hdata, mode);
1798 }
1799
1800 static void hdmi_commit(struct exynos_drm_display *display)
1801 {
1802         struct hdmi_context *hdata = display->ctx;
1803
1804         mutex_lock(&hdata->hdmi_mutex);
1805         if (!hdata->powered) {
1806                 mutex_unlock(&hdata->hdmi_mutex);
1807                 return;
1808         }
1809         mutex_unlock(&hdata->hdmi_mutex);
1810
1811         hdmi_conf_apply(hdata);
1812 }
1813
1814 static void hdmi_poweron(struct exynos_drm_display *display)
1815 {
1816         struct hdmi_context *hdata = display->ctx;
1817         struct hdmi_resources *res = &hdata->res;
1818
1819         mutex_lock(&hdata->hdmi_mutex);
1820         if (hdata->powered) {
1821                 mutex_unlock(&hdata->hdmi_mutex);
1822                 return;
1823         }
1824
1825         hdata->powered = true;
1826
1827         mutex_unlock(&hdata->hdmi_mutex);
1828
1829         pm_runtime_get_sync(hdata->dev);
1830
1831         if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
1832                 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1833
1834         clk_prepare_enable(res->hdmiphy);
1835         clk_prepare_enable(res->hdmi);
1836         clk_prepare_enable(res->sclk_hdmi);
1837
1838         hdmiphy_poweron(hdata);
1839         hdmi_commit(display);
1840 }
1841
1842 static void hdmi_poweroff(struct exynos_drm_display *display)
1843 {
1844         struct hdmi_context *hdata = display->ctx;
1845         struct hdmi_resources *res = &hdata->res;
1846
1847         mutex_lock(&hdata->hdmi_mutex);
1848         if (!hdata->powered)
1849                 goto out;
1850         mutex_unlock(&hdata->hdmi_mutex);
1851
1852         /* HDMI System Disable */
1853         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
1854
1855         hdmiphy_poweroff(hdata);
1856
1857         cancel_delayed_work(&hdata->hotplug_work);
1858
1859         clk_disable_unprepare(res->sclk_hdmi);
1860         clk_disable_unprepare(res->hdmi);
1861         clk_disable_unprepare(res->hdmiphy);
1862         regulator_bulk_disable(res->regul_count, res->regul_bulk);
1863
1864         pm_runtime_put_sync(hdata->dev);
1865
1866         mutex_lock(&hdata->hdmi_mutex);
1867         hdata->powered = false;
1868
1869 out:
1870         mutex_unlock(&hdata->hdmi_mutex);
1871 }
1872
1873 static void hdmi_dpms(struct exynos_drm_display *display, int mode)
1874 {
1875         DRM_DEBUG_KMS("mode %d\n", mode);
1876
1877         switch (mode) {
1878         case DRM_MODE_DPMS_ON:
1879                 hdmi_poweron(display);
1880                 break;
1881         case DRM_MODE_DPMS_STANDBY:
1882         case DRM_MODE_DPMS_SUSPEND:
1883         case DRM_MODE_DPMS_OFF:
1884                 hdmi_poweroff(display);
1885                 break;
1886         default:
1887                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1888                 break;
1889         }
1890 }
1891
1892 static struct exynos_drm_display_ops hdmi_display_ops = {
1893         .create_connector = hdmi_create_connector,
1894         .mode_fixup     = hdmi_mode_fixup,
1895         .mode_set       = hdmi_mode_set,
1896         .dpms           = hdmi_dpms,
1897         .commit         = hdmi_commit,
1898 };
1899
1900 static struct exynos_drm_display hdmi_display = {
1901         .type = EXYNOS_DISPLAY_TYPE_HDMI,
1902         .ops = &hdmi_display_ops,
1903 };
1904
1905 static void hdmi_hotplug_work_func(struct work_struct *work)
1906 {
1907         struct hdmi_context *hdata;
1908
1909         hdata = container_of(work, struct hdmi_context, hotplug_work.work);
1910
1911         mutex_lock(&hdata->hdmi_mutex);
1912         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1913         mutex_unlock(&hdata->hdmi_mutex);
1914
1915         if (hdata->drm_dev)
1916                 drm_helper_hpd_irq_event(hdata->drm_dev);
1917 }
1918
1919 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1920 {
1921         struct hdmi_context *hdata = arg;
1922
1923         mod_delayed_work(system_wq, &hdata->hotplug_work,
1924                         msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
1925
1926         return IRQ_HANDLED;
1927 }
1928
1929 static int hdmi_resources_init(struct hdmi_context *hdata)
1930 {
1931         struct device *dev = hdata->dev;
1932         struct hdmi_resources *res = &hdata->res;
1933         static char *supply[] = {
1934                 "hdmi-en",
1935                 "vdd",
1936                 "vdd_osc",
1937                 "vdd_pll",
1938         };
1939         int i, ret;
1940
1941         DRM_DEBUG_KMS("HDMI resource init\n");
1942
1943         /* get clocks, power */
1944         res->hdmi = devm_clk_get(dev, "hdmi");
1945         if (IS_ERR(res->hdmi)) {
1946                 DRM_ERROR("failed to get clock 'hdmi'\n");
1947                 goto fail;
1948         }
1949         res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
1950         if (IS_ERR(res->sclk_hdmi)) {
1951                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1952                 goto fail;
1953         }
1954         res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
1955         if (IS_ERR(res->sclk_pixel)) {
1956                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1957                 goto fail;
1958         }
1959         res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
1960         if (IS_ERR(res->sclk_hdmiphy)) {
1961                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1962                 goto fail;
1963         }
1964         res->hdmiphy = devm_clk_get(dev, "hdmiphy");
1965         if (IS_ERR(res->hdmiphy)) {
1966                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1967                 goto fail;
1968         }
1969         res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
1970         if (IS_ERR(res->mout_hdmi)) {
1971                 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
1972                 goto fail;
1973         }
1974
1975         clk_set_parent(res->mout_hdmi, res->sclk_pixel);
1976
1977         res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
1978                 sizeof(res->regul_bulk[0]), GFP_KERNEL);
1979         if (!res->regul_bulk)
1980                 goto fail;
1981         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1982                 res->regul_bulk[i].supply = supply[i];
1983                 res->regul_bulk[i].consumer = NULL;
1984         }
1985         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
1986         if (ret) {
1987                 DRM_ERROR("failed to get regulators\n");
1988                 goto fail;
1989         }
1990         res->regul_count = ARRAY_SIZE(supply);
1991
1992         return 0;
1993 fail:
1994         DRM_ERROR("HDMI resource init - failed\n");
1995         return -ENODEV;
1996 }
1997
1998 static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
1999                                         (struct device *dev)
2000 {
2001         struct device_node *np = dev->of_node;
2002         struct s5p_hdmi_platform_data *pd;
2003         u32 value;
2004
2005         pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
2006         if (!pd)
2007                 goto err_data;
2008
2009         if (!of_find_property(np, "hpd-gpio", &value)) {
2010                 DRM_ERROR("no hpd gpio property found\n");
2011                 goto err_data;
2012         }
2013
2014         pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
2015
2016         return pd;
2017
2018 err_data:
2019         return NULL;
2020 }
2021
2022 static struct of_device_id hdmi_match_types[] = {
2023         {
2024                 .compatible = "samsung,exynos5-hdmi",
2025                 .data = &exynos5_hdmi_driver_data,
2026         }, {
2027                 .compatible = "samsung,exynos4212-hdmi",
2028                 .data = &exynos4212_hdmi_driver_data,
2029         }, {
2030                 /* end node */
2031         }
2032 };
2033
2034 static int hdmi_bind(struct device *dev, struct device *master, void *data)
2035 {
2036         struct drm_device *drm_dev = data;
2037         struct hdmi_context *hdata;
2038
2039         hdata = hdmi_display.ctx;
2040         hdata->drm_dev = drm_dev;
2041
2042         return exynos_drm_create_enc_conn(drm_dev, &hdmi_display);
2043 }
2044
2045 static void hdmi_unbind(struct device *dev, struct device *master, void *data)
2046 {
2047         struct exynos_drm_display *display = get_hdmi_display(dev);
2048         struct drm_encoder *encoder = display->encoder;
2049         struct hdmi_context *hdata = display->ctx;
2050
2051         encoder->funcs->destroy(encoder);
2052         drm_connector_cleanup(&hdata->connector);
2053 }
2054
2055 static const struct component_ops hdmi_component_ops = {
2056         .bind   = hdmi_bind,
2057         .unbind = hdmi_unbind,
2058 };
2059
2060 static int hdmi_probe(struct platform_device *pdev)
2061 {
2062         struct device_node *ddc_node, *phy_node;
2063         struct s5p_hdmi_platform_data *pdata;
2064         struct hdmi_driver_data *drv_data;
2065         const struct of_device_id *match;
2066         struct device *dev = &pdev->dev;
2067         struct hdmi_context *hdata;
2068         struct resource *res;
2069         int ret;
2070
2071         if (!dev->of_node)
2072                 return -ENODEV;
2073
2074         pdata = drm_hdmi_dt_parse_pdata(dev);
2075         if (!pdata)
2076                 return -EINVAL;
2077
2078         hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2079         if (!hdata)
2080                 return -ENOMEM;
2081
2082         mutex_init(&hdata->hdmi_mutex);
2083
2084         platform_set_drvdata(pdev, &hdmi_display);
2085
2086         match = of_match_node(hdmi_match_types, dev->of_node);
2087         if (!match)
2088                 return -ENODEV;
2089
2090         drv_data = (struct hdmi_driver_data *)match->data;
2091         hdata->type = drv_data->type;
2092
2093         hdata->hpd_gpio = pdata->hpd_gpio;
2094         hdata->dev = dev;
2095
2096         ret = hdmi_resources_init(hdata);
2097         if (ret) {
2098                 DRM_ERROR("hdmi_resources_init failed\n");
2099                 return -EINVAL;
2100         }
2101
2102         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2103         hdata->regs = devm_ioremap_resource(dev, res);
2104         if (IS_ERR(hdata->regs))
2105                 return PTR_ERR(hdata->regs);
2106
2107         ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
2108         if (ret) {
2109                 DRM_ERROR("failed to request HPD gpio\n");
2110                 return ret;
2111         }
2112
2113         /* DDC i2c driver */
2114         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2115         if (!ddc_node) {
2116                 DRM_ERROR("Failed to find ddc node in device tree\n");
2117                 return -ENODEV;
2118         }
2119         hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2120         if (!hdata->ddc_adpt) {
2121                 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
2122                 return -ENODEV;
2123         }
2124
2125         /* Not support APB PHY yet. */
2126         if (drv_data->is_apb_phy)
2127                 return -EPERM;
2128
2129         /* hdmiphy i2c driver */
2130         phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2131         if (!phy_node) {
2132                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2133                 ret = -ENODEV;
2134                 goto err_ddc;
2135         }
2136         hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2137         if (!hdata->hdmiphy_port) {
2138                 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2139                 ret = -ENODEV;
2140                 goto err_ddc;
2141         }
2142
2143         hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2144         if (hdata->irq < 0) {
2145                 DRM_ERROR("failed to get GPIO irq\n");
2146                 ret = hdata->irq;
2147                 goto err_hdmiphy;
2148         }
2149
2150         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2151
2152         INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2153
2154         ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2155                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
2156                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2157                         "hdmi", hdata);
2158         if (ret) {
2159                 DRM_ERROR("failed to register hdmi interrupt\n");
2160                 goto err_hdmiphy;
2161         }
2162
2163         pm_runtime_enable(dev);
2164         hdmi_display.ctx = hdata;
2165
2166         return exynos_drm_component_add(&pdev->dev, &hdmi_component_ops);
2167
2168 err_hdmiphy:
2169         if (hdata->hdmiphy_port)
2170                 put_device(&hdata->hdmiphy_port->dev);
2171 err_ddc:
2172         put_device(&hdata->ddc_adpt->dev);
2173         return ret;
2174 }
2175
2176 static int hdmi_remove(struct platform_device *pdev)
2177 {
2178         struct hdmi_context *hdata = hdmi_display.ctx;
2179
2180         cancel_delayed_work_sync(&hdata->hotplug_work);
2181
2182         put_device(&hdata->hdmiphy_port->dev);
2183         put_device(&hdata->ddc_adpt->dev);
2184
2185         pm_runtime_disable(&pdev->dev);
2186
2187         exynos_drm_component_del(&pdev->dev, &hdmi_component_ops);
2188         return 0;
2189 }
2190
2191 struct platform_driver hdmi_driver = {
2192         .probe          = hdmi_probe,
2193         .remove         = hdmi_remove,
2194         .driver         = {
2195                 .name   = "exynos-hdmi",
2196                 .owner  = THIS_MODULE,
2197                 .of_match_table = hdmi_match_types,
2198         },
2199 };