drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * Freescale DCU drm device driver
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/regmap.h>
  14
  15 #include <drm/drmP.h>
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20
  21 #include "fsl_dcu_drm_crtc.h"
  22 #include "fsl_dcu_drm_drv.h"
  23 #include "fsl_dcu_drm_plane.h"
  24
  25 static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  26                                           struct drm_crtc_state *old_crtc_state)
  27 {
  28         struct drm_pending_vblank_event *event = crtc->state->event;
  29
  30         if (event) {
  31                 crtc->state->event = NULL;
  32
  33                 spin_lock_irq(&crtc->dev->event_lock);
  34                 if (drm_crtc_vblank_get(crtc) == 0)
  35                         drm_crtc_arm_vblank_event(crtc, event);
  36                 else
  37                         drm_crtc_send_vblank_event(crtc, event);
  38                 spin_unlock_irq(&crtc->dev->event_lock);
  39         }
  40 }
  41
  42 static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
  43 {
  44         struct drm_device *dev = crtc->dev;
  45         struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  46
  47         regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  48                            DCU_MODE_DCU_MODE_MASK,
  49                            DCU_MODE_DCU_MODE(DCU_MODE_OFF));
  50         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  51                      DCU_UPDATE_MODE_READREG);
  52 }
  53
  54 static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
  55 {
  56         struct drm_device *dev = crtc->dev;
  57         struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  58
  59         regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  60                            DCU_MODE_DCU_MODE_MASK,
  61                            DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
  62         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  63                      DCU_UPDATE_MODE_READREG);
  64 }
  65
  66 static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
  67 {
  68         struct drm_device *dev = crtc->dev;
  69         struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  70         struct drm_connector *con = &fsl_dev->connector.base;
  71         struct drm_display_mode *mode = &crtc->state->mode;
  72         unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
  73
  74         index = drm_crtc_index(crtc);
  75         clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
  76
  77         /* Configure timings: */
  78         hbp = mode->htotal - mode->hsync_end;
  79         hfp = mode->hsync_start - mode->hdisplay;
  80         hsw = mode->hsync_end - mode->hsync_start;
  81         vbp = mode->vtotal - mode->vsync_end;
  82         vfp = mode->vsync_start - mode->vdisplay;
  83         vsw = mode->vsync_end - mode->vsync_start;
  84
  85         /* INV_PXCK as default (most display sample data on rising edge) */
  86         if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE))
  87                 pol |= DCU_SYN_POL_INV_PXCK;
  88
  89         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  90                 pol |= DCU_SYN_POL_INV_HS_LOW;
  91
  92         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  93                 pol |= DCU_SYN_POL_INV_VS_LOW;
  94
  95         regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
  96                      DCU_HSYN_PARA_BP(hbp) |
  97                      DCU_HSYN_PARA_PW(hsw) |
  98                      DCU_HSYN_PARA_FP(hfp));
  99         regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
 100                      DCU_VSYN_PARA_BP(vbp) |
 101                      DCU_VSYN_PARA_PW(vsw) |
 102                      DCU_VSYN_PARA_FP(vfp));
 103         regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
 104                      DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
 105                      DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
 106         regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
 107         regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
 108                      DCU_BGND_G(0) | DCU_BGND_B(0));
 109         regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
 110                      DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
 111         regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
 112                      DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
 113                      DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
 114                      DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
 115         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
 116                      DCU_UPDATE_MODE_READREG);
 117         return;
 118 }
 119
 120 static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
 121         .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
 122         .disable = fsl_dcu_drm_disable_crtc,
 123         .enable = fsl_dcu_drm_crtc_enable,
 124         .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
 125 };
 126
 127 static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
 128         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 129         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 130         .destroy = drm_crtc_cleanup,
 131         .page_flip = drm_atomic_helper_page_flip,
 132         .reset = drm_atomic_helper_crtc_reset,
 133         .set_config = drm_atomic_helper_set_config,
 134 };
 135
 136 int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
 137 {
 138         struct drm_plane *primary;
 139         struct drm_crtc *crtc = &fsl_dev->crtc;
 140         unsigned int i, j, reg_num;
 141         int ret;
 142
 143         primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
 144         if (!primary)
 145                 return -ENOMEM;
 146
 147         ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
 148                                         &fsl_dcu_drm_crtc_funcs, NULL);
 149         if (ret) {
 150                 primary->funcs->destroy(primary);
 151                 return ret;
 152         }
 153
 154         drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
 155
 156         if (!strcmp(fsl_dev->soc->name, "ls1021a"))
 157                 reg_num = LS1021A_LAYER_REG_NUM;
 158         else
 159                 reg_num = VF610_LAYER_REG_NUM;
 160         for (i = 0; i < fsl_dev->soc->total_layer; i++) {
 161                 for (j = 1; j <= reg_num; j++)
 162                         regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
 163         }
 164         regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
 165                            DCU_MODE_DCU_MODE_MASK,
 166                            DCU_MODE_DCU_MODE(DCU_MODE_OFF));
 167         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
 168                      DCU_UPDATE_MODE_READREG);
 169
 170         return 0;
 171 }