drivers/gpu/drm/gma500/oaktrail_crtc.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  */
  17
  18 #include <linux/i2c.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #include <drm/drmP.h>
  22 #include "framebuffer.h"
  23 #include "psb_drv.h"
  24 #include "psb_intel_drv.h"
  25 #include "psb_intel_reg.h"
  26 #include "psb_intel_display.h"
  27 #include "power.h"
  28
  29 struct psb_intel_range_t {
  30         int min, max;
  31 };
  32
  33 struct oaktrail_limit_t {
  34         struct psb_intel_range_t dot, m, p1;
  35 };
  36
  37 struct oaktrail_clock_t {
  38         /* derived values */
  39         int dot;
  40         int m;
  41         int p1;
  42 };
  43
  44 #define MRST_LIMIT_LVDS_100L        0
  45 #define MRST_LIMIT_LVDS_83          1
  46 #define MRST_LIMIT_LVDS_100         2
  47
  48 #define MRST_DOT_MIN              19750
  49 #define MRST_DOT_MAX              120000
  50 #define MRST_M_MIN_100L             20
  51 #define MRST_M_MIN_100              10
  52 #define MRST_M_MIN_83               12
  53 #define MRST_M_MAX_100L             34
  54 #define MRST_M_MAX_100              17
  55 #define MRST_M_MAX_83               20
  56 #define MRST_P1_MIN                 2
  57 #define MRST_P1_MAX_0               7
  58 #define MRST_P1_MAX_1               8
  59
  60 static const struct oaktrail_limit_t oaktrail_limits[] = {
  61         {                       /* MRST_LIMIT_LVDS_100L */
  62          .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  63          .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
  64          .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
  65          },
  66         {                       /* MRST_LIMIT_LVDS_83L */
  67          .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  68          .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
  69          .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
  70          },
  71         {                       /* MRST_LIMIT_LVDS_100 */
  72          .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
  73          .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
  74          .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
  75          },
  76 };
  77
  78 #define MRST_M_MIN          10
  79 static const u32 oaktrail_m_converts[] = {
  80         0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
  81         0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
  82         0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
  83 };
  84
  85 static const struct oaktrail_limit_t *oaktrail_limit(struct drm_crtc *crtc)
  86 {
  87         const struct oaktrail_limit_t *limit = NULL;
  88         struct drm_device *dev = crtc->dev;
  89         struct drm_psb_private *dev_priv = dev->dev_private;
  90
  91         if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
  92             || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
  93                 switch (dev_priv->core_freq) {
  94                 case 100:
  95                         limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L];
  96                         break;
  97                 case 166:
  98                         limit = &oaktrail_limits[MRST_LIMIT_LVDS_83];
  99                         break;
 100                 case 200:
 101                         limit = &oaktrail_limits[MRST_LIMIT_LVDS_100];
 102                         break;
 103                 }
 104         } else {
 105                 limit = NULL;
 106                 dev_err(dev->dev, "oaktrail_limit Wrong display type.\n");
 107         }
 108
 109         return limit;
 110 }
 111
 112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
 113 static void oaktrail_clock(int refclk, struct oaktrail_clock_t *clock)
 114 {
 115         clock->dot = (refclk * clock->m) / (14 * clock->p1);
 116 }
 117
 118 static void mrstPrintPll(char *prefix, struct oaktrail_clock_t *clock)
 119 {
 120         pr_debug("%s: dotclock = %d,  m = %d, p1 = %d.\n",
 121              prefix, clock->dot, clock->m, clock->p1);
 122 }
 123
 124 /**
 125  * Returns a set of divisors for the desired target clock with the given refclk,
 126  * or FALSE.  Divisor values are the actual divisors for
 127  */
 128 static bool
 129 mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
 130                 struct oaktrail_clock_t *best_clock)
 131 {
 132         struct oaktrail_clock_t clock;
 133         const struct oaktrail_limit_t *limit = oaktrail_limit(crtc);
 134         int err = target;
 135
 136         memset(best_clock, 0, sizeof(*best_clock));
 137
 138         for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
 139                 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
 140                      clock.p1++) {
 141                         int this_err;
 142
 143                         oaktrail_clock(refclk, &clock);
 144
 145                         this_err = abs(clock.dot - target);
 146                         if (this_err < err) {
 147                                 *best_clock = clock;
 148                                 err = this_err;
 149                         }
 150                 }
 151         }
 152         dev_dbg(crtc->dev->dev, "mrstFindBestPLL err = %d.\n", err);
 153         return err != target;
 154 }
 155
 156 /**
 157  * Sets the power management mode of the pipe and plane.
 158  *
 159  * This code should probably grow support for turning the cursor off and back
 160  * on appropriately at the same time as we're turning the pipe off/on.
 161  */
 162 static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
 163 {
 164         struct drm_device *dev = crtc->dev;
 165         struct drm_psb_private *dev_priv = dev->dev_private;
 166         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 167         int pipe = psb_intel_crtc->pipe;
 168         const struct psb_offset *map = &dev_priv->regmap[pipe];
 169         u32 temp;
 170
 171         if (!gma_power_begin(dev, true))
 172                 return;
 173
 174         /* XXX: When our outputs are all unaware of DPMS modes other than off
 175          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 176          */
 177         switch (mode) {
 178         case DRM_MODE_DPMS_ON:
 179         case DRM_MODE_DPMS_STANDBY:
 180         case DRM_MODE_DPMS_SUSPEND:
 181                 /* Enable the DPLL */
 182                 temp = REG_READ(map->dpll);
 183                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 184                         REG_WRITE(map->dpll, temp);
 185                         REG_READ(map->dpll);
 186                         /* Wait for the clocks to stabilize. */
 187                         udelay(150);
 188                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 189                         REG_READ(map->dpll);
 190                         /* Wait for the clocks to stabilize. */
 191                         udelay(150);
 192                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 193                         REG_READ(map->dpll);
 194                         /* Wait for the clocks to stabilize. */
 195                         udelay(150);
 196                 }
 197                 /* Enable the pipe */
 198                 temp = REG_READ(map->conf);
 199                 if ((temp & PIPEACONF_ENABLE) == 0)
 200                         REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
 201                 /* Enable the plane */
 202                 temp = REG_READ(map->cntr);
 203                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 204                         REG_WRITE(map->cntr,
 205                                   temp | DISPLAY_PLANE_ENABLE);
 206                         /* Flush the plane changes */
 207                         REG_WRITE(map->base, REG_READ(map->base));
 208                 }
 209
 210                 psb_intel_crtc_load_lut(crtc);
 211
 212                 /* Give the overlay scaler a chance to enable
 213                    if it's on this pipe */
 214                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
 215                 break;
 216         case DRM_MODE_DPMS_OFF:
 217                 /* Give the overlay scaler a chance to disable
 218                  * if it's on this pipe */
 219                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
 220
 221                 /* Disable the VGA plane that we never use */
 222                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 223                 /* Disable display plane */
 224                 temp = REG_READ(map->cntr);
 225                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 226                         REG_WRITE(map->cntr,
 227                                   temp & ~DISPLAY_PLANE_ENABLE);
 228                         /* Flush the plane changes */
 229                         REG_WRITE(map->base, REG_READ(map->base));
 230                         REG_READ(map->base);
 231                 }
 232
 233                 /* Next, disable display pipes */
 234                 temp = REG_READ(map->conf);
 235                 if ((temp & PIPEACONF_ENABLE) != 0) {
 236                         REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
 237                         REG_READ(map->conf);
 238                 }
 239                 /* Wait for for the pipe disable to take effect. */
 240                 psb_intel_wait_for_vblank(dev);
 241
 242                 temp = REG_READ(map->dpll);
 243                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 244                         REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
 245                         REG_READ(map->dpll);
 246                 }
 247
 248                 /* Wait for the clocks to turn off. */
 249                 udelay(150);
 250                 break;
 251         }
 252
 253         /*Set FIFO Watermarks*/
 254         REG_WRITE(DSPARB, 0x3FFF);
 255         REG_WRITE(DSPFW1, 0x3F88080A);
 256         REG_WRITE(DSPFW2, 0x0b060808);
 257         REG_WRITE(DSPFW3, 0x0);
 258         REG_WRITE(DSPFW4, 0x08030404);
 259         REG_WRITE(DSPFW5, 0x04040404);
 260         REG_WRITE(DSPFW6, 0x78);
 261         REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
 262         /* Must write Bit 14 of the Chicken Bit Register */
 263
 264         gma_power_end(dev);
 265 }
 266
 267 /**
 268  * Return the pipe currently connected to the panel fitter,
 269  * or -1 if the panel fitter is not present or not in use
 270  */
 271 static int oaktrail_panel_fitter_pipe(struct drm_device *dev)
 272 {
 273         u32 pfit_control;
 274
 275         pfit_control = REG_READ(PFIT_CONTROL);
 276
 277         /* See if the panel fitter is in use */
 278         if ((pfit_control & PFIT_ENABLE) == 0)
 279                 return -1;
 280         return (pfit_control >> 29) & 3;
 281 }
 282
 283 static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
 284                               struct drm_display_mode *mode,
 285                               struct drm_display_mode *adjusted_mode,
 286                               int x, int y,
 287                               struct drm_framebuffer *old_fb)
 288 {
 289         struct drm_device *dev = crtc->dev;
 290         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 291         struct drm_psb_private *dev_priv = dev->dev_private;
 292         int pipe = psb_intel_crtc->pipe;
 293         const struct psb_offset *map = &dev_priv->regmap[pipe];
 294         int refclk = 0;
 295         struct oaktrail_clock_t clock;
 296         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
 297         bool ok, is_sdvo = false;
 298         bool is_lvds = false;
 299         bool is_mipi = false;
 300         struct drm_mode_config *mode_config = &dev->mode_config;
 301         struct psb_intel_encoder *psb_intel_encoder = NULL;
 302         uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
 303         struct drm_connector *connector;
 304
 305         if (!gma_power_begin(dev, true))
 306                 return 0;
 307
 308         memcpy(&psb_intel_crtc->saved_mode,
 309                 mode,
 310                 sizeof(struct drm_display_mode));
 311         memcpy(&psb_intel_crtc->saved_adjusted_mode,
 312                 adjusted_mode,
 313                 sizeof(struct drm_display_mode));
 314
 315         list_for_each_entry(connector, &mode_config->connector_list, head) {
 316                 if (!connector->encoder || connector->encoder->crtc != crtc)
 317                         continue;
 318
 319                 psb_intel_encoder = psb_intel_attached_encoder(connector);
 320
 321                 switch (psb_intel_encoder->type) {
 322                 case INTEL_OUTPUT_LVDS:
 323                         is_lvds = true;
 324                         break;
 325                 case INTEL_OUTPUT_SDVO:
 326                         is_sdvo = true;
 327                         break;
 328                 case INTEL_OUTPUT_MIPI:
 329                         is_mipi = true;
 330                         break;
 331                 }
 332         }
 333
 334         /* Disable the VGA plane that we never use */
 335         REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 336
 337         /* Disable the panel fitter if it was on our pipe */
 338         if (oaktrail_panel_fitter_pipe(dev) == pipe)
 339                 REG_WRITE(PFIT_CONTROL, 0);
 340
 341         REG_WRITE(map->src,
 342                   ((mode->crtc_hdisplay - 1) << 16) |
 343                   (mode->crtc_vdisplay - 1));
 344
 345         if (psb_intel_encoder)
 346                 drm_connector_property_get_value(connector,
 347                         dev->mode_config.scaling_mode_property, &scalingType);
 348
 349         if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
 350                 /* Moorestown doesn't have register support for centering so
 351                  * we need to mess with the h/vblank and h/vsync start and
 352                  * ends to get centering */
 353                 int offsetX = 0, offsetY = 0;
 354
 355                 offsetX = (adjusted_mode->crtc_hdisplay -
 356                            mode->crtc_hdisplay) / 2;
 357                 offsetY = (adjusted_mode->crtc_vdisplay -
 358                            mode->crtc_vdisplay) / 2;
 359
 360                 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
 361                         ((adjusted_mode->crtc_htotal - 1) << 16));
 362                 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
 363                         ((adjusted_mode->crtc_vtotal - 1) << 16));
 364                 REG_WRITE(map->hblank,
 365                         (adjusted_mode->crtc_hblank_start - offsetX - 1) |
 366                         ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
 367                 REG_WRITE(map->hsync,
 368                         (adjusted_mode->crtc_hsync_start - offsetX - 1) |
 369                         ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
 370                 REG_WRITE(map->vblank,
 371                         (adjusted_mode->crtc_vblank_start - offsetY - 1) |
 372                         ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
 373                 REG_WRITE(map->vsync,
 374                         (adjusted_mode->crtc_vsync_start - offsetY - 1) |
 375                         ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
 376         } else {
 377                 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
 378                         ((adjusted_mode->crtc_htotal - 1) << 16));
 379                 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
 380                         ((adjusted_mode->crtc_vtotal - 1) << 16));
 381                 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
 382                         ((adjusted_mode->crtc_hblank_end - 1) << 16));
 383                 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
 384                         ((adjusted_mode->crtc_hsync_end - 1) << 16));
 385                 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
 386                         ((adjusted_mode->crtc_vblank_end - 1) << 16));
 387                 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
 388                         ((adjusted_mode->crtc_vsync_end - 1) << 16));
 389         }
 390
 391         /* Flush the plane changes */
 392         {
 393                 struct drm_crtc_helper_funcs *crtc_funcs =
 394                     crtc->helper_private;
 395                 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
 396         }
 397
 398         /* setup pipeconf */
 399         pipeconf = REG_READ(map->conf);
 400
 401         /* Set up the display plane register */
 402         dspcntr = REG_READ(map->cntr);
 403         dspcntr |= DISPPLANE_GAMMA_ENABLE;
 404
 405         if (pipe == 0)
 406                 dspcntr |= DISPPLANE_SEL_PIPE_A;
 407         else
 408                 dspcntr |= DISPPLANE_SEL_PIPE_B;
 409
 410         if (is_mipi)
 411                 goto oaktrail_crtc_mode_set_exit;
 412
 413         refclk = dev_priv->core_freq * 1000;
 414
 415         dpll = 0;               /*BIT16 = 0 for 100MHz reference */
 416
 417         ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock);
 418
 419         if (!ok) {
 420                 dev_dbg(dev->dev, "mrstFindBestPLL fail in oaktrail_crtc_mode_set.\n");
 421         } else {
 422                 dev_dbg(dev->dev, "oaktrail_crtc_mode_set pixel clock = %d,"
 423                          "m = %x, p1 = %x.\n", clock.dot, clock.m,
 424                          clock.p1);
 425         }
 426
 427         fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
 428
 429         dpll |= DPLL_VGA_MODE_DIS;
 430
 431
 432         dpll |= DPLL_VCO_ENABLE;
 433
 434         if (is_lvds)
 435                 dpll |= DPLLA_MODE_LVDS;
 436         else
 437                 dpll |= DPLLB_MODE_DAC_SERIAL;
 438
 439         if (is_sdvo) {
 440                 int sdvo_pixel_multiply =
 441                     adjusted_mode->clock / mode->clock;
 442
 443                 dpll |= DPLL_DVO_HIGH_SPEED;
 444                 dpll |=
 445                     (sdvo_pixel_multiply -
 446                      1) << SDVO_MULTIPLIER_SHIFT_HIRES;
 447         }
 448
 449
 450         /* compute bitmask from p1 value */
 451         dpll |= (1 << (clock.p1 - 2)) << 17;
 452
 453         dpll |= DPLL_VCO_ENABLE;
 454
 455         mrstPrintPll("chosen", &clock);
 456
 457         if (dpll & DPLL_VCO_ENABLE) {
 458                 REG_WRITE(map->fp0, fp);
 459                 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
 460                 REG_READ(map->dpll);
 461                 /* Check the DPLLA lock bit PIPEACONF[29] */
 462                 udelay(150);
 463         }
 464
 465         REG_WRITE(map->fp0, fp);
 466         REG_WRITE(map->dpll, dpll);
 467         REG_READ(map->dpll);
 468         /* Wait for the clocks to stabilize. */
 469         udelay(150);
 470
 471         /* write it again -- the BIOS does, after all */
 472         REG_WRITE(map->dpll, dpll);
 473         REG_READ(map->dpll);
 474         /* Wait for the clocks to stabilize. */
 475         udelay(150);
 476
 477         REG_WRITE(map->conf, pipeconf);
 478         REG_READ(map->conf);
 479         psb_intel_wait_for_vblank(dev);
 480
 481         REG_WRITE(map->cntr, dspcntr);
 482         psb_intel_wait_for_vblank(dev);
 483
 484 oaktrail_crtc_mode_set_exit:
 485         gma_power_end(dev);
 486         return 0;
 487 }
 488
 489 static bool oaktrail_crtc_mode_fixup(struct drm_crtc *crtc,
 490                                   const struct drm_display_mode *mode,
 491                                   struct drm_display_mode *adjusted_mode)
 492 {
 493         return true;
 494 }
 495
 496 static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
 497                             int x, int y, struct drm_framebuffer *old_fb)
 498 {
 499         struct drm_device *dev = crtc->dev;
 500         struct drm_psb_private *dev_priv = dev->dev_private;
 501         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 502         struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
 503         int pipe = psb_intel_crtc->pipe;
 504         const struct psb_offset *map = &dev_priv->regmap[pipe];
 505         unsigned long start, offset;
 506
 507         u32 dspcntr;
 508         int ret = 0;
 509
 510         /* no fb bound */
 511         if (!crtc->fb) {
 512                 dev_dbg(dev->dev, "No FB bound\n");
 513                 return 0;
 514         }
 515
 516         if (!gma_power_begin(dev, true))
 517                 return 0;
 518
 519         start = psbfb->gtt->offset;
 520         offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 521
 522         REG_WRITE(map->stride, crtc->fb->pitches[0]);
 523
 524         dspcntr = REG_READ(map->cntr);
 525         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 526
 527         switch (crtc->fb->bits_per_pixel) {
 528         case 8:
 529                 dspcntr |= DISPPLANE_8BPP;
 530                 break;
 531         case 16:
 532                 if (crtc->fb->depth == 15)
 533                         dspcntr |= DISPPLANE_15_16BPP;
 534                 else
 535                         dspcntr |= DISPPLANE_16BPP;
 536                 break;
 537         case 24:
 538         case 32:
 539                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 540                 break;
 541         default:
 542                 dev_err(dev->dev, "Unknown color depth\n");
 543                 ret = -EINVAL;
 544                 goto pipe_set_base_exit;
 545         }
 546         REG_WRITE(map->cntr, dspcntr);
 547
 548         REG_WRITE(map->base, offset);
 549         REG_READ(map->base);
 550         REG_WRITE(map->surf, start);
 551         REG_READ(map->surf);
 552
 553 pipe_set_base_exit:
 554         gma_power_end(dev);
 555         return ret;
 556 }
 557
 558 static void oaktrail_crtc_prepare(struct drm_crtc *crtc)
 559 {
 560         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 561         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 562 }
 563
 564 static void oaktrail_crtc_commit(struct drm_crtc *crtc)
 565 {
 566         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 567         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 568 }
 569
 570 const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
 571         .dpms = oaktrail_crtc_dpms,
 572         .mode_fixup = oaktrail_crtc_mode_fixup,
 573         .mode_set = oaktrail_crtc_mode_set,
 574         .mode_set_base = oaktrail_pipe_set_base,
 575         .prepare = oaktrail_crtc_prepare,
 576         .commit = oaktrail_crtc_commit,
 577 };
 578