drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc_helper.h"
  34 #include "drm_fb_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include "../../../platform/x86/intel_ips.h"
  40 #include <linux/pci.h>
  41 #include <linux/vgaarb.h>
  42 #include <linux/acpi.h>
  43 #include <linux/pnp.h>
  44 #include <linux/vga_switcheroo.h>
  45 #include <linux/slab.h>
  46 #include <linux/module.h>
  47 #include <acpi/video.h>
  48 #include <asm/pat.h>
  49
  50 static void i915_write_hws_pga(struct drm_device *dev)
  51 {
  52         drm_i915_private_t *dev_priv = dev->dev_private;
  53         u32 addr;
  54
  55         addr = dev_priv->status_page_dmah->busaddr;
  56         if (INTEL_INFO(dev)->gen >= 4)
  57                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  58         I915_WRITE(HWS_PGA, addr);
  59 }
  60
  61 /**
  62  * Sets up the hardware status page for devices that need a physical address
  63  * in the register.
  64  */
  65 static int i915_init_phys_hws(struct drm_device *dev)
  66 {
  67         drm_i915_private_t *dev_priv = dev->dev_private;
  68
  69         /* Program Hardware Status Page */
  70         dev_priv->status_page_dmah =
  71                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  72
  73         if (!dev_priv->status_page_dmah) {
  74                 DRM_ERROR("Can not allocate hardware status page\n");
  75                 return -ENOMEM;
  76         }
  77
  78         memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
  79                   0, PAGE_SIZE);
  80
  81         i915_write_hws_pga(dev);
  82
  83         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  84         return 0;
  85 }
  86
  87 /**
  88  * Frees the hardware status page, whether it's a physical address or a virtual
  89  * address set up by the X Server.
  90  */
  91 static void i915_free_hws(struct drm_device *dev)
  92 {
  93         drm_i915_private_t *dev_priv = dev->dev_private;
  94         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  95
  96         if (dev_priv->status_page_dmah) {
  97                 drm_pci_free(dev, dev_priv->status_page_dmah);
  98                 dev_priv->status_page_dmah = NULL;
  99         }
 100
 101         if (ring->status_page.gfx_addr) {
 102                 ring->status_page.gfx_addr = 0;
 103                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 104         }
 105
 106         /* Need to rewrite hardware status page */
 107         I915_WRITE(HWS_PGA, 0x1ffff000);
 108 }
 109
 110 void i915_kernel_lost_context(struct drm_device * dev)
 111 {
 112         drm_i915_private_t *dev_priv = dev->dev_private;
 113         struct drm_i915_master_private *master_priv;
 114         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 115
 116         /*
 117          * We should never lose context on the ring with modesetting
 118          * as we don't expose it to userspace
 119          */
 120         if (drm_core_check_feature(dev, DRIVER_MODESET))
 121                 return;
 122
 123         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 124         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 125         ring->space = ring->head - (ring->tail + 8);
 126         if (ring->space < 0)
 127                 ring->space += ring->size;
 128
 129         if (!dev->primary->master)
 130                 return;
 131
 132         master_priv = dev->primary->master->driver_priv;
 133         if (ring->head == ring->tail && master_priv->sarea_priv)
 134                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 135 }
 136
 137 static int i915_dma_cleanup(struct drm_device * dev)
 138 {
 139         drm_i915_private_t *dev_priv = dev->dev_private;
 140         int i;
 141
 142         /* Make sure interrupts are disabled here because the uninstall ioctl
 143          * may not have been called from userspace and after dev_private
 144          * is freed, it's too late.
 145          */
 146         if (dev->irq_enabled)
 147                 drm_irq_uninstall(dev);
 148
 149         mutex_lock(&dev->struct_mutex);
 150         for (i = 0; i < I915_NUM_RINGS; i++)
 151                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 152         mutex_unlock(&dev->struct_mutex);
 153
 154         /* Clear the HWS virtual address at teardown */
 155         if (I915_NEED_GFX_HWS(dev))
 156                 i915_free_hws(dev);
 157
 158         return 0;
 159 }
 160
 161 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 162 {
 163         drm_i915_private_t *dev_priv = dev->dev_private;
 164         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 165         int ret;
 166
 167         master_priv->sarea = drm_getsarea(dev);
 168         if (master_priv->sarea) {
 169                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 170                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 171         } else {
 172                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 173         }
 174
 175         if (init->ring_size != 0) {
 176                 if (LP_RING(dev_priv)->obj != NULL) {
 177                         i915_dma_cleanup(dev);
 178                         DRM_ERROR("Client tried to initialize ringbuffer in "
 179                                   "GEM mode\n");
 180                         return -EINVAL;
 181                 }
 182
 183                 ret = intel_render_ring_init_dri(dev,
 184                                                  init->ring_start,
 185                                                  init->ring_size);
 186                 if (ret) {
 187                         i915_dma_cleanup(dev);
 188                         return ret;
 189                 }
 190         }
 191
 192         dev_priv->cpp = init->cpp;
 193         dev_priv->back_offset = init->back_offset;
 194         dev_priv->front_offset = init->front_offset;
 195         dev_priv->current_page = 0;
 196         if (master_priv->sarea_priv)
 197                 master_priv->sarea_priv->pf_current_page = 0;
 198
 199         /* Allow hardware batchbuffers unless told otherwise.
 200          */
 201         dev_priv->allow_batchbuffer = 1;
 202
 203         return 0;
 204 }
 205
 206 static int i915_dma_resume(struct drm_device * dev)
 207 {
 208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 209         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 210
 211         DRM_DEBUG_DRIVER("%s\n", __func__);
 212
 213         if (ring->map.handle == NULL) {
 214                 DRM_ERROR("can not ioremap virtual address for"
 215                           " ring buffer\n");
 216                 return -ENOMEM;
 217         }
 218
 219         /* Program Hardware Status Page */
 220         if (!ring->status_page.page_addr) {
 221                 DRM_ERROR("Can not find hardware status page\n");
 222                 return -EINVAL;
 223         }
 224         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 225                                 ring->status_page.page_addr);
 226         if (ring->status_page.gfx_addr != 0)
 227                 intel_ring_setup_status_page(ring);
 228         else
 229                 i915_write_hws_pga(dev);
 230
 231         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 232
 233         return 0;
 234 }
 235
 236 static int i915_dma_init(struct drm_device *dev, void *data,
 237                          struct drm_file *file_priv)
 238 {
 239         drm_i915_init_t *init = data;
 240         int retcode = 0;
 241
 242         if (drm_core_check_feature(dev, DRIVER_MODESET))
 243                 return -ENODEV;
 244
 245         switch (init->func) {
 246         case I915_INIT_DMA:
 247                 retcode = i915_initialize(dev, init);
 248                 break;
 249         case I915_CLEANUP_DMA:
 250                 retcode = i915_dma_cleanup(dev);
 251                 break;
 252         case I915_RESUME_DMA:
 253                 retcode = i915_dma_resume(dev);
 254                 break;
 255         default:
 256                 retcode = -EINVAL;
 257                 break;
 258         }
 259
 260         return retcode;
 261 }
 262
 263 /* Implement basically the same security restrictions as hardware does
 264  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 265  *
 266  * Most of the calculations below involve calculating the size of a
 267  * particular instruction.  It's important to get the size right as
 268  * that tells us where the next instruction to check is.  Any illegal
 269  * instruction detected will be given a size of zero, which is a
 270  * signal to abort the rest of the buffer.
 271  */
 272 static int validate_cmd(int cmd)
 273 {
 274         switch (((cmd >> 29) & 0x7)) {
 275         case 0x0:
 276                 switch ((cmd >> 23) & 0x3f) {
 277                 case 0x0:
 278                         return 1;       /* MI_NOOP */
 279                 case 0x4:
 280                         return 1;       /* MI_FLUSH */
 281                 default:
 282                         return 0;       /* disallow everything else */
 283                 }
 284                 break;
 285         case 0x1:
 286                 return 0;       /* reserved */
 287         case 0x2:
 288                 return (cmd & 0xff) + 2;        /* 2d commands */
 289         case 0x3:
 290                 if (((cmd >> 24) & 0x1f) <= 0x18)
 291                         return 1;
 292
 293                 switch ((cmd >> 24) & 0x1f) {
 294                 case 0x1c:
 295                         return 1;
 296                 case 0x1d:
 297                         switch ((cmd >> 16) & 0xff) {
 298                         case 0x3:
 299                                 return (cmd & 0x1f) + 2;
 300                         case 0x4:
 301                                 return (cmd & 0xf) + 2;
 302                         default:
 303                                 return (cmd & 0xffff) + 2;
 304                         }
 305                 case 0x1e:
 306                         if (cmd & (1 << 23))
 307                                 return (cmd & 0xffff) + 1;
 308                         else
 309                                 return 1;
 310                 case 0x1f:
 311                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 312                                 return (cmd & 0x1ffff) + 2;
 313                         else if (cmd & (1 << 17))       /* indirect random */
 314                                 if ((cmd & 0xffff) == 0)
 315                                         return 0;       /* unknown length, too hard */
 316                                 else
 317                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 318                         else
 319                                 return 2;       /* indirect sequential */
 320                 default:
 321                         return 0;
 322                 }
 323         default:
 324                 return 0;
 325         }
 326
 327         return 0;
 328 }
 329
 330 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 331 {
 332         drm_i915_private_t *dev_priv = dev->dev_private;
 333         int i, ret;
 334
 335         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 336                 return -EINVAL;
 337
 338         for (i = 0; i < dwords;) {
 339                 int sz = validate_cmd(buffer[i]);
 340                 if (sz == 0 || i + sz > dwords)
 341                         return -EINVAL;
 342                 i += sz;
 343         }
 344
 345         ret = BEGIN_LP_RING((dwords+1)&~1);
 346         if (ret)
 347                 return ret;
 348
 349         for (i = 0; i < dwords; i++)
 350                 OUT_RING(buffer[i]);
 351         if (dwords & 1)
 352                 OUT_RING(0);
 353
 354         ADVANCE_LP_RING();
 355
 356         return 0;
 357 }
 358
 359 int
 360 i915_emit_box(struct drm_device *dev,
 361               struct drm_clip_rect *box,
 362               int DR1, int DR4)
 363 {
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         int ret;
 366
 367         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 368             box->y2 <= 0 || box->x2 <= 0) {
 369                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 370                           box->x1, box->y1, box->x2, box->y2);
 371                 return -EINVAL;
 372         }
 373
 374         if (INTEL_INFO(dev)->gen >= 4) {
 375                 ret = BEGIN_LP_RING(4);
 376                 if (ret)
 377                         return ret;
 378
 379                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 380                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 381                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 382                 OUT_RING(DR4);
 383         } else {
 384                 ret = BEGIN_LP_RING(6);
 385                 if (ret)
 386                         return ret;
 387
 388                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 389                 OUT_RING(DR1);
 390                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 391                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 392                 OUT_RING(DR4);
 393                 OUT_RING(0);
 394         }
 395         ADVANCE_LP_RING();
 396
 397         return 0;
 398 }
 399
 400 /* XXX: Emitting the counter should really be moved to part of the IRQ
 401  * emit. For now, do it in both places:
 402  */
 403
 404 static void i915_emit_breadcrumb(struct drm_device *dev)
 405 {
 406         drm_i915_private_t *dev_priv = dev->dev_private;
 407         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 408
 409         dev_priv->counter++;
 410         if (dev_priv->counter > 0x7FFFFFFFUL)
 411                 dev_priv->counter = 0;
 412         if (master_priv->sarea_priv)
 413                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 414
 415         if (BEGIN_LP_RING(4) == 0) {
 416                 OUT_RING(MI_STORE_DWORD_INDEX);
 417                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 418                 OUT_RING(dev_priv->counter);
 419                 OUT_RING(0);
 420                 ADVANCE_LP_RING();
 421         }
 422 }
 423
 424 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 425                                    drm_i915_cmdbuffer_t *cmd,
 426                                    struct drm_clip_rect *cliprects,
 427                                    void *cmdbuf)
 428 {
 429         int nbox = cmd->num_cliprects;
 430         int i = 0, count, ret;
 431
 432         if (cmd->sz & 0x3) {
 433                 DRM_ERROR("alignment");
 434                 return -EINVAL;
 435         }
 436
 437         i915_kernel_lost_context(dev);
 438
 439         count = nbox ? nbox : 1;
 440
 441         for (i = 0; i < count; i++) {
 442                 if (i < nbox) {
 443                         ret = i915_emit_box(dev, &cliprects[i],
 444                                             cmd->DR1, cmd->DR4);
 445                         if (ret)
 446                                 return ret;
 447                 }
 448
 449                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 450                 if (ret)
 451                         return ret;
 452         }
 453
 454         i915_emit_breadcrumb(dev);
 455         return 0;
 456 }
 457
 458 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 459                                      drm_i915_batchbuffer_t * batch,
 460                                      struct drm_clip_rect *cliprects)
 461 {
 462         struct drm_i915_private *dev_priv = dev->dev_private;
 463         int nbox = batch->num_cliprects;
 464         int i, count, ret;
 465
 466         if ((batch->start | batch->used) & 0x7) {
 467                 DRM_ERROR("alignment");
 468                 return -EINVAL;
 469         }
 470
 471         i915_kernel_lost_context(dev);
 472
 473         count = nbox ? nbox : 1;
 474         for (i = 0; i < count; i++) {
 475                 if (i < nbox) {
 476                         ret = i915_emit_box(dev, &cliprects[i],
 477                                             batch->DR1, batch->DR4);
 478                         if (ret)
 479                                 return ret;
 480                 }
 481
 482                 if (!IS_I830(dev) && !IS_845G(dev)) {
 483                         ret = BEGIN_LP_RING(2);
 484                         if (ret)
 485                                 return ret;
 486
 487                         if (INTEL_INFO(dev)->gen >= 4) {
 488                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 489                                 OUT_RING(batch->start);
 490                         } else {
 491                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 492                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 493                         }
 494                 } else {
 495                         ret = BEGIN_LP_RING(4);
 496                         if (ret)
 497                                 return ret;
 498
 499                         OUT_RING(MI_BATCH_BUFFER);
 500                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 501                         OUT_RING(batch->start + batch->used - 4);
 502                         OUT_RING(0);
 503                 }
 504                 ADVANCE_LP_RING();
 505         }
 506
 507
 508         if (IS_G4X(dev) || IS_GEN5(dev)) {
 509                 if (BEGIN_LP_RING(2) == 0) {
 510                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 511                         OUT_RING(MI_NOOP);
 512                         ADVANCE_LP_RING();
 513                 }
 514         }
 515
 516         i915_emit_breadcrumb(dev);
 517         return 0;
 518 }
 519
 520 static int i915_dispatch_flip(struct drm_device * dev)
 521 {
 522         drm_i915_private_t *dev_priv = dev->dev_private;
 523         struct drm_i915_master_private *master_priv =
 524                 dev->primary->master->driver_priv;
 525         int ret;
 526
 527         if (!master_priv->sarea_priv)
 528                 return -EINVAL;
 529
 530         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 531                           __func__,
 532                          dev_priv->current_page,
 533                          master_priv->sarea_priv->pf_current_page);
 534
 535         i915_kernel_lost_context(dev);
 536
 537         ret = BEGIN_LP_RING(10);
 538         if (ret)
 539                 return ret;
 540
 541         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 542         OUT_RING(0);
 543
 544         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 545         OUT_RING(0);
 546         if (dev_priv->current_page == 0) {
 547                 OUT_RING(dev_priv->back_offset);
 548                 dev_priv->current_page = 1;
 549         } else {
 550                 OUT_RING(dev_priv->front_offset);
 551                 dev_priv->current_page = 0;
 552         }
 553         OUT_RING(0);
 554
 555         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 556         OUT_RING(0);
 557
 558         ADVANCE_LP_RING();
 559
 560         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 561
 562         if (BEGIN_LP_RING(4) == 0) {
 563                 OUT_RING(MI_STORE_DWORD_INDEX);
 564                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 565                 OUT_RING(dev_priv->counter);
 566                 OUT_RING(0);
 567                 ADVANCE_LP_RING();
 568         }
 569
 570         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 571         return 0;
 572 }
 573
 574 static int i915_quiescent(struct drm_device *dev)
 575 {
 576         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 577
 578         i915_kernel_lost_context(dev);
 579         return intel_wait_ring_idle(ring);
 580 }
 581
 582 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 583                             struct drm_file *file_priv)
 584 {
 585         int ret;
 586
 587         if (drm_core_check_feature(dev, DRIVER_MODESET))
 588                 return -ENODEV;
 589
 590         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 591
 592         mutex_lock(&dev->struct_mutex);
 593         ret = i915_quiescent(dev);
 594         mutex_unlock(&dev->struct_mutex);
 595
 596         return ret;
 597 }
 598
 599 static int i915_batchbuffer(struct drm_device *dev, void *data,
 600                             struct drm_file *file_priv)
 601 {
 602         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 603         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 604         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 605             master_priv->sarea_priv;
 606         drm_i915_batchbuffer_t *batch = data;
 607         int ret;
 608         struct drm_clip_rect *cliprects = NULL;
 609
 610         if (drm_core_check_feature(dev, DRIVER_MODESET))
 611                 return -ENODEV;
 612
 613         if (!dev_priv->allow_batchbuffer) {
 614                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 615                 return -EINVAL;
 616         }
 617
 618         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 619                         batch->start, batch->used, batch->num_cliprects);
 620
 621         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 622
 623         if (batch->num_cliprects < 0)
 624                 return -EINVAL;
 625
 626         if (batch->num_cliprects) {
 627                 cliprects = kcalloc(batch->num_cliprects,
 628                                     sizeof(struct drm_clip_rect),
 629                                     GFP_KERNEL);
 630                 if (cliprects == NULL)
 631                         return -ENOMEM;
 632
 633                 ret = copy_from_user(cliprects, batch->cliprects,
 634                                      batch->num_cliprects *
 635                                      sizeof(struct drm_clip_rect));
 636                 if (ret != 0) {
 637                         ret = -EFAULT;
 638                         goto fail_free;
 639                 }
 640         }
 641
 642         mutex_lock(&dev->struct_mutex);
 643         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 644         mutex_unlock(&dev->struct_mutex);
 645
 646         if (sarea_priv)
 647                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 648
 649 fail_free:
 650         kfree(cliprects);
 651
 652         return ret;
 653 }
 654
 655 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 656                           struct drm_file *file_priv)
 657 {
 658         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 659         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 660         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 661             master_priv->sarea_priv;
 662         drm_i915_cmdbuffer_t *cmdbuf = data;
 663         struct drm_clip_rect *cliprects = NULL;
 664         void *batch_data;
 665         int ret;
 666
 667         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 668                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 669
 670         if (drm_core_check_feature(dev, DRIVER_MODESET))
 671                 return -ENODEV;
 672
 673         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 674
 675         if (cmdbuf->num_cliprects < 0)
 676                 return -EINVAL;
 677
 678         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 679         if (batch_data == NULL)
 680                 return -ENOMEM;
 681
 682         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 683         if (ret != 0) {
 684                 ret = -EFAULT;
 685                 goto fail_batch_free;
 686         }
 687
 688         if (cmdbuf->num_cliprects) {
 689                 cliprects = kcalloc(cmdbuf->num_cliprects,
 690                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 691                 if (cliprects == NULL) {
 692                         ret = -ENOMEM;
 693                         goto fail_batch_free;
 694                 }
 695
 696                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 697                                      cmdbuf->num_cliprects *
 698                                      sizeof(struct drm_clip_rect));
 699                 if (ret != 0) {
 700                         ret = -EFAULT;
 701                         goto fail_clip_free;
 702                 }
 703         }
 704
 705         mutex_lock(&dev->struct_mutex);
 706         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 707         mutex_unlock(&dev->struct_mutex);
 708         if (ret) {
 709                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 710                 goto fail_clip_free;
 711         }
 712
 713         if (sarea_priv)
 714                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 715
 716 fail_clip_free:
 717         kfree(cliprects);
 718 fail_batch_free:
 719         kfree(batch_data);
 720
 721         return ret;
 722 }
 723
 724 static int i915_flip_bufs(struct drm_device *dev, void *data,
 725                           struct drm_file *file_priv)
 726 {
 727         int ret;
 728
 729         if (drm_core_check_feature(dev, DRIVER_MODESET))
 730                 return -ENODEV;
 731
 732         DRM_DEBUG_DRIVER("%s\n", __func__);
 733
 734         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 735
 736         mutex_lock(&dev->struct_mutex);
 737         ret = i915_dispatch_flip(dev);
 738         mutex_unlock(&dev->struct_mutex);
 739
 740         return ret;
 741 }
 742
 743 static int i915_getparam(struct drm_device *dev, void *data,
 744                          struct drm_file *file_priv)
 745 {
 746         drm_i915_private_t *dev_priv = dev->dev_private;
 747         drm_i915_getparam_t *param = data;
 748         int value;
 749
 750         if (!dev_priv) {
 751                 DRM_ERROR("called with no initialization\n");
 752                 return -EINVAL;
 753         }
 754
 755         switch (param->param) {
 756         case I915_PARAM_IRQ_ACTIVE:
 757                 value = dev->pdev->irq ? 1 : 0;
 758                 break;
 759         case I915_PARAM_ALLOW_BATCHBUFFER:
 760                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 761                 break;
 762         case I915_PARAM_LAST_DISPATCH:
 763                 value = READ_BREADCRUMB(dev_priv);
 764                 break;
 765         case I915_PARAM_CHIPSET_ID:
 766                 value = dev->pci_device;
 767                 break;
 768         case I915_PARAM_HAS_GEM:
 769                 value = 1;
 770                 break;
 771         case I915_PARAM_NUM_FENCES_AVAIL:
 772                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 773                 break;
 774         case I915_PARAM_HAS_OVERLAY:
 775                 value = dev_priv->overlay ? 1 : 0;
 776                 break;
 777         case I915_PARAM_HAS_PAGEFLIPPING:
 778                 value = 1;
 779                 break;
 780         case I915_PARAM_HAS_EXECBUF2:
 781                 /* depends on GEM */
 782                 value = 1;
 783                 break;
 784         case I915_PARAM_HAS_BSD:
 785                 value = HAS_BSD(dev);
 786                 break;
 787         case I915_PARAM_HAS_BLT:
 788                 value = HAS_BLT(dev);
 789                 break;
 790         case I915_PARAM_HAS_RELAXED_FENCING:
 791                 value = 1;
 792                 break;
 793         case I915_PARAM_HAS_COHERENT_RINGS:
 794                 value = 1;
 795                 break;
 796         case I915_PARAM_HAS_EXEC_CONSTANTS:
 797                 value = INTEL_INFO(dev)->gen >= 4;
 798                 break;
 799         case I915_PARAM_HAS_RELAXED_DELTA:
 800                 value = 1;
 801                 break;
 802         case I915_PARAM_HAS_GEN7_SOL_RESET:
 803                 value = 1;
 804                 break;
 805         case I915_PARAM_HAS_LLC:
 806                 value = HAS_LLC(dev);
 807                 break;
 808         case I915_PARAM_HAS_ALIASING_PPGTT:
 809                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 810                 break;
 811         default:
 812                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 813                                  param->param);
 814                 return -EINVAL;
 815         }
 816
 817         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 818                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 819                 return -EFAULT;
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int i915_setparam(struct drm_device *dev, void *data,
 826                          struct drm_file *file_priv)
 827 {
 828         drm_i915_private_t *dev_priv = dev->dev_private;
 829         drm_i915_setparam_t *param = data;
 830
 831         if (!dev_priv) {
 832                 DRM_ERROR("called with no initialization\n");
 833                 return -EINVAL;
 834         }
 835
 836         switch (param->param) {
 837         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 838                 break;
 839         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 840                 dev_priv->tex_lru_log_granularity = param->value;
 841                 break;
 842         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 843                 dev_priv->allow_batchbuffer = param->value;
 844                 break;
 845         case I915_SETPARAM_NUM_USED_FENCES:
 846                 if (param->value > dev_priv->num_fence_regs ||
 847                     param->value < 0)
 848                         return -EINVAL;
 849                 /* Userspace can use first N regs */
 850                 dev_priv->fence_reg_start = param->value;
 851                 break;
 852         default:
 853                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 854                                         param->param);
 855                 return -EINVAL;
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int i915_set_status_page(struct drm_device *dev, void *data,
 862                                 struct drm_file *file_priv)
 863 {
 864         drm_i915_private_t *dev_priv = dev->dev_private;
 865         drm_i915_hws_addr_t *hws = data;
 866         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 867
 868         if (drm_core_check_feature(dev, DRIVER_MODESET))
 869                 return -ENODEV;
 870
 871         if (!I915_NEED_GFX_HWS(dev))
 872                 return -EINVAL;
 873
 874         if (!dev_priv) {
 875                 DRM_ERROR("called with no initialization\n");
 876                 return -EINVAL;
 877         }
 878
 879         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 880                 WARN(1, "tried to set status page when mode setting active\n");
 881                 return 0;
 882         }
 883
 884         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 885
 886         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 887
 888         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 889         dev_priv->hws_map.size = 4*1024;
 890         dev_priv->hws_map.type = 0;
 891         dev_priv->hws_map.flags = 0;
 892         dev_priv->hws_map.mtrr = 0;
 893
 894         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 895         if (dev_priv->hws_map.handle == NULL) {
 896                 i915_dma_cleanup(dev);
 897                 ring->status_page.gfx_addr = 0;
 898                 DRM_ERROR("can not ioremap virtual address for"
 899                                 " G33 hw status page\n");
 900                 return -ENOMEM;
 901         }
 902         ring->status_page.page_addr =
 903                 (void __force __iomem *)dev_priv->hws_map.handle;
 904         memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
 905         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 906
 907         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 908                          ring->status_page.gfx_addr);
 909         DRM_DEBUG_DRIVER("load hws at %p\n",
 910                          ring->status_page.page_addr);
 911         return 0;
 912 }
 913
 914 static int i915_get_bridge_dev(struct drm_device *dev)
 915 {
 916         struct drm_i915_private *dev_priv = dev->dev_private;
 917
 918         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 919         if (!dev_priv->bridge_dev) {
 920                 DRM_ERROR("bridge device not found\n");
 921                 return -1;
 922         }
 923         return 0;
 924 }
 925
 926 #define MCHBAR_I915 0x44
 927 #define MCHBAR_I965 0x48
 928 #define MCHBAR_SIZE (4*4096)
 929
 930 #define DEVEN_REG 0x54
 931 #define   DEVEN_MCHBAR_EN (1 << 28)
 932
 933 /* Allocate space for the MCH regs if needed, return nonzero on error */
 934 static int
 935 intel_alloc_mchbar_resource(struct drm_device *dev)
 936 {
 937         drm_i915_private_t *dev_priv = dev->dev_private;
 938         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 939         u32 temp_lo, temp_hi = 0;
 940         u64 mchbar_addr;
 941         int ret;
 942
 943         if (INTEL_INFO(dev)->gen >= 4)
 944                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 945         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 946         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 947
 948         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 949 #ifdef CONFIG_PNP
 950         if (mchbar_addr &&
 951             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 952                 return 0;
 953 #endif
 954
 955         /* Get some space for it */
 956         dev_priv->mch_res.name = "i915 MCHBAR";
 957         dev_priv->mch_res.flags = IORESOURCE_MEM;
 958         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 959                                      &dev_priv->mch_res,
 960                                      MCHBAR_SIZE, MCHBAR_SIZE,
 961                                      PCIBIOS_MIN_MEM,
 962                                      0, pcibios_align_resource,
 963                                      dev_priv->bridge_dev);
 964         if (ret) {
 965                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 966                 dev_priv->mch_res.start = 0;
 967                 return ret;
 968         }
 969
 970         if (INTEL_INFO(dev)->gen >= 4)
 971                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 972                                        upper_32_bits(dev_priv->mch_res.start));
 973
 974         pci_write_config_dword(dev_priv->bridge_dev, reg,
 975                                lower_32_bits(dev_priv->mch_res.start));
 976         return 0;
 977 }
 978
 979 /* Setup MCHBAR if possible, return true if we should disable it again */
 980 static void
 981 intel_setup_mchbar(struct drm_device *dev)
 982 {
 983         drm_i915_private_t *dev_priv = dev->dev_private;
 984         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 985         u32 temp;
 986         bool enabled;
 987
 988         dev_priv->mchbar_need_disable = false;
 989
 990         if (IS_I915G(dev) || IS_I915GM(dev)) {
 991                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 992                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 993         } else {
 994                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 995                 enabled = temp & 1;
 996         }
 997
 998         /* If it's already enabled, don't have to do anything */
 999         if (enabled)
1000                 return;
1001
1002         if (intel_alloc_mchbar_resource(dev))
1003                 return;
1004
1005         dev_priv->mchbar_need_disable = true;
1006
1007         /* Space is allocated or reserved, so enable it. */
1008         if (IS_I915G(dev) || IS_I915GM(dev)) {
1009                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1010                                        temp | DEVEN_MCHBAR_EN);
1011         } else {
1012                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1013                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1014         }
1015 }
1016
1017 static void
1018 intel_teardown_mchbar(struct drm_device *dev)
1019 {
1020         drm_i915_private_t *dev_priv = dev->dev_private;
1021         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1022         u32 temp;
1023
1024         if (dev_priv->mchbar_need_disable) {
1025                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1026                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1027                         temp &= ~DEVEN_MCHBAR_EN;
1028                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1029                 } else {
1030                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1031                         temp &= ~1;
1032                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1033                 }
1034         }
1035
1036         if (dev_priv->mch_res.start)
1037                 release_resource(&dev_priv->mch_res);
1038 }
1039
1040 /* true = enable decode, false = disable decoder */
1041 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1042 {
1043         struct drm_device *dev = cookie;
1044
1045         intel_modeset_vga_set_state(dev, state);
1046         if (state)
1047                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1048                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1049         else
1050                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1051 }
1052
1053 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1054 {
1055         struct drm_device *dev = pci_get_drvdata(pdev);
1056         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1057         if (state == VGA_SWITCHEROO_ON) {
1058                 pr_info("switched on\n");
1059                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1060                 /* i915 resume handler doesn't set to D0 */
1061                 pci_set_power_state(dev->pdev, PCI_D0);
1062                 i915_resume(dev);
1063                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1064         } else {
1065                 pr_err("switched off\n");
1066                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1067                 i915_suspend(dev, pmm);
1068                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1069         }
1070 }
1071
1072 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1073 {
1074         struct drm_device *dev = pci_get_drvdata(pdev);
1075         bool can_switch;
1076
1077         spin_lock(&dev->count_lock);
1078         can_switch = (dev->open_count == 0);
1079         spin_unlock(&dev->count_lock);
1080         return can_switch;
1081 }
1082
1083 static int i915_load_modeset_init(struct drm_device *dev)
1084 {
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086         int ret;
1087
1088         ret = intel_parse_bios(dev);
1089         if (ret)
1090                 DRM_INFO("failed to find VBIOS tables\n");
1091
1092         /* If we have > 1 VGA cards, then we need to arbitrate access
1093          * to the common VGA resources.
1094          *
1095          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1096          * then we do not take part in VGA arbitration and the
1097          * vga_client_register() fails with -ENODEV.
1098          */
1099         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1100         if (ret && ret != -ENODEV)
1101                 goto out;
1102
1103         intel_register_dsm_handler();
1104
1105         ret = vga_switcheroo_register_client(dev->pdev,
1106                                              i915_switcheroo_set_state,
1107                                              NULL,
1108                                              i915_switcheroo_can_switch);
1109         if (ret)
1110                 goto cleanup_vga_client;
1111
1112         /* Initialise stolen first so that we may reserve preallocated
1113          * objects for the BIOS to KMS transition.
1114          */
1115         ret = i915_gem_init_stolen(dev);
1116         if (ret)
1117                 goto cleanup_vga_switcheroo;
1118
1119         intel_modeset_init(dev);
1120
1121         ret = i915_gem_init(dev);
1122         if (ret)
1123                 goto cleanup_gem_stolen;
1124
1125         intel_modeset_gem_init(dev);
1126
1127         ret = drm_irq_install(dev);
1128         if (ret)
1129                 goto cleanup_gem;
1130
1131         /* Always safe in the mode setting case. */
1132         /* FIXME: do pre/post-mode set stuff in core KMS code */
1133         dev->vblank_disable_allowed = 1;
1134
1135         ret = intel_fbdev_init(dev);
1136         if (ret)
1137                 goto cleanup_irq;
1138
1139         drm_kms_helper_poll_init(dev);
1140
1141         /* We're off and running w/KMS */
1142         dev_priv->mm.suspended = 0;
1143
1144         return 0;
1145
1146 cleanup_irq:
1147         drm_irq_uninstall(dev);
1148 cleanup_gem:
1149         mutex_lock(&dev->struct_mutex);
1150         i915_gem_cleanup_ringbuffer(dev);
1151         mutex_unlock(&dev->struct_mutex);
1152         i915_gem_cleanup_aliasing_ppgtt(dev);
1153 cleanup_gem_stolen:
1154         i915_gem_cleanup_stolen(dev);
1155 cleanup_vga_switcheroo:
1156         vga_switcheroo_unregister_client(dev->pdev);
1157 cleanup_vga_client:
1158         vga_client_register(dev->pdev, NULL, NULL, NULL);
1159 out:
1160         return ret;
1161 }
1162
1163 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1164 {
1165         struct drm_i915_master_private *master_priv;
1166
1167         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1168         if (!master_priv)
1169                 return -ENOMEM;
1170
1171         master->driver_priv = master_priv;
1172         return 0;
1173 }
1174
1175 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1176 {
1177         struct drm_i915_master_private *master_priv = master->driver_priv;
1178
1179         if (!master_priv)
1180                 return;
1181
1182         kfree(master_priv);
1183
1184         master->driver_priv = NULL;
1185 }
1186
1187 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1188 {
1189         drm_i915_private_t *dev_priv = dev->dev_private;
1190         u32 tmp;
1191
1192         tmp = I915_READ(CLKCFG);
1193
1194         switch (tmp & CLKCFG_FSB_MASK) {
1195         case CLKCFG_FSB_533:
1196                 dev_priv->fsb_freq = 533; /* 133*4 */
1197                 break;
1198         case CLKCFG_FSB_800:
1199                 dev_priv->fsb_freq = 800; /* 200*4 */
1200                 break;
1201         case CLKCFG_FSB_667:
1202                 dev_priv->fsb_freq =  667; /* 167*4 */
1203                 break;
1204         case CLKCFG_FSB_400:
1205                 dev_priv->fsb_freq = 400; /* 100*4 */
1206                 break;
1207         }
1208
1209         switch (tmp & CLKCFG_MEM_MASK) {
1210         case CLKCFG_MEM_533:
1211                 dev_priv->mem_freq = 533;
1212                 break;
1213         case CLKCFG_MEM_667:
1214                 dev_priv->mem_freq = 667;
1215                 break;
1216         case CLKCFG_MEM_800:
1217                 dev_priv->mem_freq = 800;
1218                 break;
1219         }
1220
1221         /* detect pineview DDR3 setting */
1222         tmp = I915_READ(CSHRDDR3CTL);
1223         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1224 }
1225
1226 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1227 {
1228         drm_i915_private_t *dev_priv = dev->dev_private;
1229         u16 ddrpll, csipll;
1230
1231         ddrpll = I915_READ16(DDRMPLL1);
1232         csipll = I915_READ16(CSIPLL0);
1233
1234         switch (ddrpll & 0xff) {
1235         case 0xc:
1236                 dev_priv->mem_freq = 800;
1237                 break;
1238         case 0x10:
1239                 dev_priv->mem_freq = 1066;
1240                 break;
1241         case 0x14:
1242                 dev_priv->mem_freq = 1333;
1243                 break;
1244         case 0x18:
1245                 dev_priv->mem_freq = 1600;
1246                 break;
1247         default:
1248                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1249                                  ddrpll & 0xff);
1250                 dev_priv->mem_freq = 0;
1251                 break;
1252         }
1253
1254         dev_priv->r_t = dev_priv->mem_freq;
1255
1256         switch (csipll & 0x3ff) {
1257         case 0x00c:
1258                 dev_priv->fsb_freq = 3200;
1259                 break;
1260         case 0x00e:
1261                 dev_priv->fsb_freq = 3733;
1262                 break;
1263         case 0x010:
1264                 dev_priv->fsb_freq = 4266;
1265                 break;
1266         case 0x012:
1267                 dev_priv->fsb_freq = 4800;
1268                 break;
1269         case 0x014:
1270                 dev_priv->fsb_freq = 5333;
1271                 break;
1272         case 0x016:
1273                 dev_priv->fsb_freq = 5866;
1274                 break;
1275         case 0x018:
1276                 dev_priv->fsb_freq = 6400;
1277                 break;
1278         default:
1279                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1280                                  csipll & 0x3ff);
1281                 dev_priv->fsb_freq = 0;
1282                 break;
1283         }
1284
1285         if (dev_priv->fsb_freq == 3200) {
1286                 dev_priv->c_m = 0;
1287         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1288                 dev_priv->c_m = 1;
1289         } else {
1290                 dev_priv->c_m = 2;
1291         }
1292 }
1293
1294 static const struct cparams {
1295         u16 i;
1296         u16 t;
1297         u16 m;
1298         u16 c;
1299 } cparams[] = {
1300         { 1, 1333, 301, 28664 },
1301         { 1, 1066, 294, 24460 },
1302         { 1, 800, 294, 25192 },
1303         { 0, 1333, 276, 27605 },
1304         { 0, 1066, 276, 27605 },
1305         { 0, 800, 231, 23784 },
1306 };
1307
1308 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1309 {
1310         u64 total_count, diff, ret;
1311         u32 count1, count2, count3, m = 0, c = 0;
1312         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1313         int i;
1314
1315         diff1 = now - dev_priv->last_time1;
1316
1317         /* Prevent division-by-zero if we are asking too fast.
1318          * Also, we don't get interesting results if we are polling
1319          * faster than once in 10ms, so just return the saved value
1320          * in such cases.
1321          */
1322         if (diff1 <= 10)
1323                 return dev_priv->chipset_power;
1324
1325         count1 = I915_READ(DMIEC);
1326         count2 = I915_READ(DDREC);
1327         count3 = I915_READ(CSIEC);
1328
1329         total_count = count1 + count2 + count3;
1330
1331         /* FIXME: handle per-counter overflow */
1332         if (total_count < dev_priv->last_count1) {
1333                 diff = ~0UL - dev_priv->last_count1;
1334                 diff += total_count;
1335         } else {
1336                 diff = total_count - dev_priv->last_count1;
1337         }
1338
1339         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1340                 if (cparams[i].i == dev_priv->c_m &&
1341                     cparams[i].t == dev_priv->r_t) {
1342                         m = cparams[i].m;
1343                         c = cparams[i].c;
1344                         break;
1345                 }
1346         }
1347
1348         diff = div_u64(diff, diff1);
1349         ret = ((m * diff) + c);
1350         ret = div_u64(ret, 10);
1351
1352         dev_priv->last_count1 = total_count;
1353         dev_priv->last_time1 = now;
1354
1355         dev_priv->chipset_power = ret;
1356
1357         return ret;
1358 }
1359
1360 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1361 {
1362         unsigned long m, x, b;
1363         u32 tsfs;
1364
1365         tsfs = I915_READ(TSFS);
1366
1367         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1368         x = I915_READ8(TR1);
1369
1370         b = tsfs & TSFS_INTR_MASK;
1371
1372         return ((m * x) / 127) - b;
1373 }
1374
1375 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1376 {
1377         static const struct v_table {
1378                 u16 vd; /* in .1 mil */
1379                 u16 vm; /* in .1 mil */
1380         } v_table[] = {
1381                 { 0, 0, },
1382                 { 375, 0, },
1383                 { 500, 0, },
1384                 { 625, 0, },
1385                 { 750, 0, },
1386                 { 875, 0, },
1387                 { 1000, 0, },
1388                 { 1125, 0, },
1389                 { 4125, 3000, },
1390                 { 4125, 3000, },
1391                 { 4125, 3000, },
1392                 { 4125, 3000, },
1393                 { 4125, 3000, },
1394                 { 4125, 3000, },
1395                 { 4125, 3000, },
1396                 { 4125, 3000, },
1397                 { 4125, 3000, },
1398                 { 4125, 3000, },
1399                 { 4125, 3000, },
1400                 { 4125, 3000, },
1401                 { 4125, 3000, },
1402                 { 4125, 3000, },
1403                 { 4125, 3000, },
1404                 { 4125, 3000, },
1405                 { 4125, 3000, },
1406                 { 4125, 3000, },
1407                 { 4125, 3000, },
1408                 { 4125, 3000, },
1409                 { 4125, 3000, },
1410                 { 4125, 3000, },
1411                 { 4125, 3000, },
1412                 { 4125, 3000, },
1413                 { 4250, 3125, },
1414                 { 4375, 3250, },
1415                 { 4500, 3375, },
1416                 { 4625, 3500, },
1417                 { 4750, 3625, },
1418                 { 4875, 3750, },
1419                 { 5000, 3875, },
1420                 { 5125, 4000, },
1421                 { 5250, 4125, },
1422                 { 5375, 4250, },
1423                 { 5500, 4375, },
1424                 { 5625, 4500, },
1425                 { 5750, 4625, },
1426                 { 5875, 4750, },
1427                 { 6000, 4875, },
1428                 { 6125, 5000, },
1429                 { 6250, 5125, },
1430                 { 6375, 5250, },
1431                 { 6500, 5375, },
1432                 { 6625, 5500, },
1433                 { 6750, 5625, },
1434                 { 6875, 5750, },
1435                 { 7000, 5875, },
1436                 { 7125, 6000, },
1437                 { 7250, 6125, },
1438                 { 7375, 6250, },
1439                 { 7500, 6375, },
1440                 { 7625, 6500, },
1441                 { 7750, 6625, },
1442                 { 7875, 6750, },
1443                 { 8000, 6875, },
1444                 { 8125, 7000, },
1445                 { 8250, 7125, },
1446                 { 8375, 7250, },
1447                 { 8500, 7375, },
1448                 { 8625, 7500, },
1449                 { 8750, 7625, },
1450                 { 8875, 7750, },
1451                 { 9000, 7875, },
1452                 { 9125, 8000, },
1453                 { 9250, 8125, },
1454                 { 9375, 8250, },
1455                 { 9500, 8375, },
1456                 { 9625, 8500, },
1457                 { 9750, 8625, },
1458                 { 9875, 8750, },
1459                 { 10000, 8875, },
1460                 { 10125, 9000, },
1461                 { 10250, 9125, },
1462                 { 10375, 9250, },
1463                 { 10500, 9375, },
1464                 { 10625, 9500, },
1465                 { 10750, 9625, },
1466                 { 10875, 9750, },
1467                 { 11000, 9875, },
1468                 { 11125, 10000, },
1469                 { 11250, 10125, },
1470                 { 11375, 10250, },
1471                 { 11500, 10375, },
1472                 { 11625, 10500, },
1473                 { 11750, 10625, },
1474                 { 11875, 10750, },
1475                 { 12000, 10875, },
1476                 { 12125, 11000, },
1477                 { 12250, 11125, },
1478                 { 12375, 11250, },
1479                 { 12500, 11375, },
1480                 { 12625, 11500, },
1481                 { 12750, 11625, },
1482                 { 12875, 11750, },
1483                 { 13000, 11875, },
1484                 { 13125, 12000, },
1485                 { 13250, 12125, },
1486                 { 13375, 12250, },
1487                 { 13500, 12375, },
1488                 { 13625, 12500, },
1489                 { 13750, 12625, },
1490                 { 13875, 12750, },
1491                 { 14000, 12875, },
1492                 { 14125, 13000, },
1493                 { 14250, 13125, },
1494                 { 14375, 13250, },
1495                 { 14500, 13375, },
1496                 { 14625, 13500, },
1497                 { 14750, 13625, },
1498                 { 14875, 13750, },
1499                 { 15000, 13875, },
1500                 { 15125, 14000, },
1501                 { 15250, 14125, },
1502                 { 15375, 14250, },
1503                 { 15500, 14375, },
1504                 { 15625, 14500, },
1505                 { 15750, 14625, },
1506                 { 15875, 14750, },
1507                 { 16000, 14875, },
1508                 { 16125, 15000, },
1509         };
1510         if (dev_priv->info->is_mobile)
1511                 return v_table[pxvid].vm;
1512         else
1513                 return v_table[pxvid].vd;
1514 }
1515
1516 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1517 {
1518         struct timespec now, diff1;
1519         u64 diff;
1520         unsigned long diffms;
1521         u32 count;
1522
1523         if (dev_priv->info->gen != 5)
1524                 return;
1525
1526         getrawmonotonic(&now);
1527         diff1 = timespec_sub(now, dev_priv->last_time2);
1528
1529         /* Don't divide by 0 */
1530         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1531         if (!diffms)
1532                 return;
1533
1534         count = I915_READ(GFXEC);
1535
1536         if (count < dev_priv->last_count2) {
1537                 diff = ~0UL - dev_priv->last_count2;
1538                 diff += count;
1539         } else {
1540                 diff = count - dev_priv->last_count2;
1541         }
1542
1543         dev_priv->last_count2 = count;
1544         dev_priv->last_time2 = now;
1545
1546         /* More magic constants... */
1547         diff = diff * 1181;
1548         diff = div_u64(diff, diffms * 10);
1549         dev_priv->gfx_power = diff;
1550 }
1551
1552 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1553 {
1554         unsigned long t, corr, state1, corr2, state2;
1555         u32 pxvid, ext_v;
1556
1557         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1558         pxvid = (pxvid >> 24) & 0x7f;
1559         ext_v = pvid_to_extvid(dev_priv, pxvid);
1560
1561         state1 = ext_v;
1562
1563         t = i915_mch_val(dev_priv);
1564
1565         /* Revel in the empirically derived constants */
1566
1567         /* Correction factor in 1/100000 units */
1568         if (t > 80)
1569                 corr = ((t * 2349) + 135940);
1570         else if (t >= 50)
1571                 corr = ((t * 964) + 29317);
1572         else /* < 50 */
1573                 corr = ((t * 301) + 1004);
1574
1575         corr = corr * ((150142 * state1) / 10000 - 78642);
1576         corr /= 100000;
1577         corr2 = (corr * dev_priv->corr);
1578
1579         state2 = (corr2 * state1) / 10000;
1580         state2 /= 100; /* convert to mW */
1581
1582         i915_update_gfx_val(dev_priv);
1583
1584         return dev_priv->gfx_power + state2;
1585 }
1586
1587 /* Global for IPS driver to get at the current i915 device */
1588 static struct drm_i915_private *i915_mch_dev;
1589 /*
1590  * Lock protecting IPS related data structures
1591  *   - i915_mch_dev
1592  *   - dev_priv->max_delay
1593  *   - dev_priv->min_delay
1594  *   - dev_priv->fmax
1595  *   - dev_priv->gpu_busy
1596  */
1597 static DEFINE_SPINLOCK(mchdev_lock);
1598
1599 /**
1600  * i915_read_mch_val - return value for IPS use
1601  *
1602  * Calculate and return a value for the IPS driver to use when deciding whether
1603  * we have thermal and power headroom to increase CPU or GPU power budget.
1604  */
1605 unsigned long i915_read_mch_val(void)
1606 {
1607         struct drm_i915_private *dev_priv;
1608         unsigned long chipset_val, graphics_val, ret = 0;
1609
1610         spin_lock(&mchdev_lock);
1611         if (!i915_mch_dev)
1612                 goto out_unlock;
1613         dev_priv = i915_mch_dev;
1614
1615         chipset_val = i915_chipset_val(dev_priv);
1616         graphics_val = i915_gfx_val(dev_priv);
1617
1618         ret = chipset_val + graphics_val;
1619
1620 out_unlock:
1621         spin_unlock(&mchdev_lock);
1622
1623         return ret;
1624 }
1625 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1626
1627 /**
1628  * i915_gpu_raise - raise GPU frequency limit
1629  *
1630  * Raise the limit; IPS indicates we have thermal headroom.
1631  */
1632 bool i915_gpu_raise(void)
1633 {
1634         struct drm_i915_private *dev_priv;
1635         bool ret = true;
1636
1637         spin_lock(&mchdev_lock);
1638         if (!i915_mch_dev) {
1639                 ret = false;
1640                 goto out_unlock;
1641         }
1642         dev_priv = i915_mch_dev;
1643
1644         if (dev_priv->max_delay > dev_priv->fmax)
1645                 dev_priv->max_delay--;
1646
1647 out_unlock:
1648         spin_unlock(&mchdev_lock);
1649
1650         return ret;
1651 }
1652 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1653
1654 /**
1655  * i915_gpu_lower - lower GPU frequency limit
1656  *
1657  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1658  * frequency maximum.
1659  */
1660 bool i915_gpu_lower(void)
1661 {
1662         struct drm_i915_private *dev_priv;
1663         bool ret = true;
1664
1665         spin_lock(&mchdev_lock);
1666         if (!i915_mch_dev) {
1667                 ret = false;
1668                 goto out_unlock;
1669         }
1670         dev_priv = i915_mch_dev;
1671
1672         if (dev_priv->max_delay < dev_priv->min_delay)
1673                 dev_priv->max_delay++;
1674
1675 out_unlock:
1676         spin_unlock(&mchdev_lock);
1677
1678         return ret;
1679 }
1680 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1681
1682 /**
1683  * i915_gpu_busy - indicate GPU business to IPS
1684  *
1685  * Tell the IPS driver whether or not the GPU is busy.
1686  */
1687 bool i915_gpu_busy(void)
1688 {
1689         struct drm_i915_private *dev_priv;
1690         bool ret = false;
1691
1692         spin_lock(&mchdev_lock);
1693         if (!i915_mch_dev)
1694                 goto out_unlock;
1695         dev_priv = i915_mch_dev;
1696
1697         ret = dev_priv->busy;
1698
1699 out_unlock:
1700         spin_unlock(&mchdev_lock);
1701
1702         return ret;
1703 }
1704 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1705
1706 /**
1707  * i915_gpu_turbo_disable - disable graphics turbo
1708  *
1709  * Disable graphics turbo by resetting the max frequency and setting the
1710  * current frequency to the default.
1711  */
1712 bool i915_gpu_turbo_disable(void)
1713 {
1714         struct drm_i915_private *dev_priv;
1715         bool ret = true;
1716
1717         spin_lock(&mchdev_lock);
1718         if (!i915_mch_dev) {
1719                 ret = false;
1720                 goto out_unlock;
1721         }
1722         dev_priv = i915_mch_dev;
1723
1724         dev_priv->max_delay = dev_priv->fstart;
1725
1726         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1727                 ret = false;
1728
1729 out_unlock:
1730         spin_unlock(&mchdev_lock);
1731
1732         return ret;
1733 }
1734 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1735
1736 /**
1737  * Tells the intel_ips driver that the i915 driver is now loaded, if
1738  * IPS got loaded first.
1739  *
1740  * This awkward dance is so that neither module has to depend on the
1741  * other in order for IPS to do the appropriate communication of
1742  * GPU turbo limits to i915.
1743  */
1744 static void
1745 ips_ping_for_i915_load(void)
1746 {
1747         void (*link)(void);
1748
1749         link = symbol_get(ips_link_to_i915_driver);
1750         if (link) {
1751                 link();
1752                 symbol_put(ips_link_to_i915_driver);
1753         }
1754 }
1755
1756 static void
1757 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1758                 unsigned long size)
1759 {
1760         dev_priv->mm.gtt_mtrr = -1;
1761
1762 #if defined(CONFIG_X86_PAT)
1763         if (cpu_has_pat)
1764                 return;
1765 #endif
1766
1767         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1768          * one would think, because the kernel disables PAT on first
1769          * generation Core chips because WC PAT gets overridden by a UC
1770          * MTRR if present.  Even if a UC MTRR isn't present.
1771          */
1772         dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1773         if (dev_priv->mm.gtt_mtrr < 0) {
1774                 DRM_INFO("MTRR allocation failed.  Graphics "
1775                          "performance may suffer.\n");
1776         }
1777 }
1778
1779 /**
1780  * i915_driver_load - setup chip and create an initial config
1781  * @dev: DRM device
1782  * @flags: startup flags
1783  *
1784  * The driver load routine has to do several things:
1785  *   - drive output discovery via intel_modeset_init()
1786  *   - initialize the memory manager
1787  *   - allocate initial config memory
1788  *   - setup the DRM framebuffer with the allocated memory
1789  */
1790 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1791 {
1792         struct drm_i915_private *dev_priv;
1793         struct intel_device_info *info;
1794         int ret = 0, mmio_bar;
1795         uint32_t aperture_size;
1796
1797         info = (struct intel_device_info *) flags;
1798
1799         /* Refuse to load on gen6+ without kms enabled. */
1800         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1801                 return -ENODEV;
1802
1803
1804         /* i915 has 4 more counters */
1805         dev->counters += 4;
1806         dev->types[6] = _DRM_STAT_IRQ;
1807         dev->types[7] = _DRM_STAT_PRIMARY;
1808         dev->types[8] = _DRM_STAT_SECONDARY;
1809         dev->types[9] = _DRM_STAT_DMA;
1810
1811         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1812         if (dev_priv == NULL)
1813                 return -ENOMEM;
1814
1815         dev->dev_private = (void *)dev_priv;
1816         dev_priv->dev = dev;
1817         dev_priv->info = info;
1818
1819         if (i915_get_bridge_dev(dev)) {
1820                 ret = -EIO;
1821                 goto free_priv;
1822         }
1823
1824         pci_set_master(dev->pdev);
1825
1826         /* overlay on gen2 is broken and can't address above 1G */
1827         if (IS_GEN2(dev))
1828                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1829
1830         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1831          * using 32bit addressing, overwriting memory if HWS is located
1832          * above 4GB.
1833          *
1834          * The documentation also mentions an issue with undefined
1835          * behaviour if any general state is accessed within a page above 4GB,
1836          * which also needs to be handled carefully.
1837          */
1838         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1839                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1840
1841         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1842         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1843         if (!dev_priv->regs) {
1844                 DRM_ERROR("failed to map registers\n");
1845                 ret = -EIO;
1846                 goto put_bridge;
1847         }
1848
1849         dev_priv->mm.gtt = intel_gtt_get();
1850         if (!dev_priv->mm.gtt) {
1851                 DRM_ERROR("Failed to initialize GTT\n");
1852                 ret = -ENODEV;
1853                 goto out_rmmap;
1854         }
1855
1856         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1857
1858         dev_priv->mm.gtt_mapping =
1859                 io_mapping_create_wc(dev->agp->base, aperture_size);
1860         if (dev_priv->mm.gtt_mapping == NULL) {
1861                 ret = -EIO;
1862                 goto out_rmmap;
1863         }
1864
1865         i915_mtrr_setup(dev_priv, dev->agp->base, aperture_size);
1866
1867         /* The i915 workqueue is primarily used for batched retirement of
1868          * requests (and thus managing bo) once the task has been completed
1869          * by the GPU. i915_gem_retire_requests() is called directly when we
1870          * need high-priority retirement, such as waiting for an explicit
1871          * bo.
1872          *
1873          * It is also used for periodic low-priority events, such as
1874          * idle-timers and recording error state.
1875          *
1876          * All tasks on the workqueue are expected to acquire the dev mutex
1877          * so there is no point in running more than one instance of the
1878          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1879          */
1880         dev_priv->wq = alloc_workqueue("i915",
1881                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1882                                        1);
1883         if (dev_priv->wq == NULL) {
1884                 DRM_ERROR("Failed to create our workqueue.\n");
1885                 ret = -ENOMEM;
1886                 goto out_mtrrfree;
1887         }
1888
1889         intel_irq_init(dev);
1890
1891         /* Try to make sure MCHBAR is enabled before poking at it */
1892         intel_setup_mchbar(dev);
1893         intel_setup_gmbus(dev);
1894         intel_opregion_setup(dev);
1895
1896         /* Make sure the bios did its job and set up vital registers */
1897         intel_setup_bios(dev);
1898
1899         i915_gem_load(dev);
1900
1901         /* Init HWS */
1902         if (!I915_NEED_GFX_HWS(dev)) {
1903                 ret = i915_init_phys_hws(dev);
1904                 if (ret)
1905                         goto out_gem_unload;
1906         }
1907
1908         if (IS_PINEVIEW(dev))
1909                 i915_pineview_get_mem_freq(dev);
1910         else if (IS_GEN5(dev))
1911                 i915_ironlake_get_mem_freq(dev);
1912
1913         /* On the 945G/GM, the chipset reports the MSI capability on the
1914          * integrated graphics even though the support isn't actually there
1915          * according to the published specs.  It doesn't appear to function
1916          * correctly in testing on 945G.
1917          * This may be a side effect of MSI having been made available for PEG
1918          * and the registers being closely associated.
1919          *
1920          * According to chipset errata, on the 965GM, MSI interrupts may
1921          * be lost or delayed, but we use them anyways to avoid
1922          * stuck interrupts on some machines.
1923          */
1924         if (!IS_I945G(dev) && !IS_I945GM(dev))
1925                 pci_enable_msi(dev->pdev);
1926
1927         spin_lock_init(&dev_priv->gt_lock);
1928         spin_lock_init(&dev_priv->irq_lock);
1929         spin_lock_init(&dev_priv->error_lock);
1930         spin_lock_init(&dev_priv->rps_lock);
1931
1932         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1933                 dev_priv->num_pipe = 3;
1934         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1935                 dev_priv->num_pipe = 2;
1936         else
1937                 dev_priv->num_pipe = 1;
1938
1939         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1940         if (ret)
1941                 goto out_gem_unload;
1942
1943         /* Start out suspended */
1944         dev_priv->mm.suspended = 1;
1945
1946         intel_detect_pch(dev);
1947
1948         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1949                 ret = i915_load_modeset_init(dev);
1950                 if (ret < 0) {
1951                         DRM_ERROR("failed to init modeset\n");
1952                         goto out_gem_unload;
1953                 }
1954         }
1955
1956         i915_setup_sysfs(dev);
1957
1958         /* Must be done after probing outputs */
1959         intel_opregion_init(dev);
1960         acpi_video_register();
1961
1962         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1963                     (unsigned long) dev);
1964
1965         if (IS_GEN5(dev)) {
1966                 spin_lock(&mchdev_lock);
1967                 i915_mch_dev = dev_priv;
1968                 dev_priv->mchdev_lock = &mchdev_lock;
1969                 spin_unlock(&mchdev_lock);
1970
1971                 ips_ping_for_i915_load();
1972         }
1973
1974         return 0;
1975
1976 out_gem_unload:
1977         if (dev_priv->mm.inactive_shrinker.shrink)
1978                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1979
1980         if (dev->pdev->msi_enabled)
1981                 pci_disable_msi(dev->pdev);
1982
1983         intel_teardown_gmbus(dev);
1984         intel_teardown_mchbar(dev);
1985         destroy_workqueue(dev_priv->wq);
1986 out_mtrrfree:
1987         if (dev_priv->mm.gtt_mtrr >= 0) {
1988                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1989                          dev->agp->agp_info.aper_size * 1024 * 1024);
1990                 dev_priv->mm.gtt_mtrr = -1;
1991         }
1992         io_mapping_free(dev_priv->mm.gtt_mapping);
1993 out_rmmap:
1994         pci_iounmap(dev->pdev, dev_priv->regs);
1995 put_bridge:
1996         pci_dev_put(dev_priv->bridge_dev);
1997 free_priv:
1998         kfree(dev_priv);
1999         return ret;
2000 }
2001
2002 int i915_driver_unload(struct drm_device *dev)
2003 {
2004         struct drm_i915_private *dev_priv = dev->dev_private;
2005         int ret;
2006
2007         spin_lock(&mchdev_lock);
2008         i915_mch_dev = NULL;
2009         spin_unlock(&mchdev_lock);
2010
2011         i915_teardown_sysfs(dev);
2012
2013         if (dev_priv->mm.inactive_shrinker.shrink)
2014                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2015
2016         mutex_lock(&dev->struct_mutex);
2017         ret = i915_gpu_idle(dev);
2018         if (ret)
2019                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2020         i915_gem_retire_requests(dev);
2021         mutex_unlock(&dev->struct_mutex);
2022
2023         /* Cancel the retire work handler, which should be idle now. */
2024         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2025
2026         io_mapping_free(dev_priv->mm.gtt_mapping);
2027         if (dev_priv->mm.gtt_mtrr >= 0) {
2028                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2029                          dev->agp->agp_info.aper_size * 1024 * 1024);
2030                 dev_priv->mm.gtt_mtrr = -1;
2031         }
2032
2033         acpi_video_unregister();
2034
2035         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2036                 intel_fbdev_fini(dev);
2037                 intel_modeset_cleanup(dev);
2038
2039                 /*
2040                  * free the memory space allocated for the child device
2041                  * config parsed from VBT
2042                  */
2043                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2044                         kfree(dev_priv->child_dev);
2045                         dev_priv->child_dev = NULL;
2046                         dev_priv->child_dev_num = 0;
2047                 }
2048
2049                 vga_switcheroo_unregister_client(dev->pdev);
2050                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2051         }
2052
2053         /* Free error state after interrupts are fully disabled. */
2054         del_timer_sync(&dev_priv->hangcheck_timer);
2055         cancel_work_sync(&dev_priv->error_work);
2056         i915_destroy_error_state(dev);
2057
2058         if (dev->pdev->msi_enabled)
2059                 pci_disable_msi(dev->pdev);
2060
2061         intel_opregion_fini(dev);
2062
2063         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2064                 /* Flush any outstanding unpin_work. */
2065                 flush_workqueue(dev_priv->wq);
2066
2067                 mutex_lock(&dev->struct_mutex);
2068                 i915_gem_free_all_phys_object(dev);
2069                 i915_gem_cleanup_ringbuffer(dev);
2070                 mutex_unlock(&dev->struct_mutex);
2071                 i915_gem_cleanup_aliasing_ppgtt(dev);
2072                 i915_gem_cleanup_stolen(dev);
2073                 drm_mm_takedown(&dev_priv->mm.stolen);
2074
2075                 intel_cleanup_overlay(dev);
2076
2077                 if (!I915_NEED_GFX_HWS(dev))
2078                         i915_free_hws(dev);
2079         }
2080
2081         if (dev_priv->regs != NULL)
2082                 pci_iounmap(dev->pdev, dev_priv->regs);
2083
2084         intel_teardown_gmbus(dev);
2085         intel_teardown_mchbar(dev);
2086
2087         destroy_workqueue(dev_priv->wq);
2088
2089         pci_dev_put(dev_priv->bridge_dev);
2090         kfree(dev->dev_private);
2091
2092         return 0;
2093 }
2094
2095 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2096 {
2097         struct drm_i915_file_private *file_priv;
2098
2099         DRM_DEBUG_DRIVER("\n");
2100         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2101         if (!file_priv)
2102                 return -ENOMEM;
2103
2104         file->driver_priv = file_priv;
2105
2106         spin_lock_init(&file_priv->mm.lock);
2107         INIT_LIST_HEAD(&file_priv->mm.request_list);
2108
2109         return 0;
2110 }
2111
2112 /**
2113  * i915_driver_lastclose - clean up after all DRM clients have exited
2114  * @dev: DRM device
2115  *
2116  * Take care of cleaning up after all DRM clients have exited.  In the
2117  * mode setting case, we want to restore the kernel's initial mode (just
2118  * in case the last client left us in a bad state).
2119  *
2120  * Additionally, in the non-mode setting case, we'll tear down the GTT
2121  * and DMA structures, since the kernel won't be using them, and clea
2122  * up any GEM state.
2123  */
2124 void i915_driver_lastclose(struct drm_device * dev)
2125 {
2126         drm_i915_private_t *dev_priv = dev->dev_private;
2127
2128         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2129                 intel_fb_restore_mode(dev);
2130                 vga_switcheroo_process_delayed_switch();
2131                 return;
2132         }
2133
2134         i915_gem_lastclose(dev);
2135
2136         i915_dma_cleanup(dev);
2137 }
2138
2139 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2140 {
2141         i915_gem_release(dev, file_priv);
2142 }
2143
2144 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2145 {
2146         struct drm_i915_file_private *file_priv = file->driver_priv;
2147
2148         kfree(file_priv);
2149 }
2150
2151 struct drm_ioctl_desc i915_ioctls[] = {
2152         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2153         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2154         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2155         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2156         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2157         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2158         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2159         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2160         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2161         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2162         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2163         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2164         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2165         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2166         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2167         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2168         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2169         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2170         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2171         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2172         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2173         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2174         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2175         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2176         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2177         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2178         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2179         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2180         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2181         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2182         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2183         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2184         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2185         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2186         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2187         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2188         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2189         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2190         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2191         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2192         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2193         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2194 };
2195
2196 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2197
2198 /*
2199  * This is really ugly: Because old userspace abused the linux agp interface to
2200  * manage the gtt, we need to claim that all intel devices are agp.  For
2201  * otherwise the drm core refuses to initialize the agp support code.
2202  */
2203 int i915_driver_device_is_agp(struct drm_device * dev)
2204 {
2205         return 1;
2206 }