drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .is_preliminary = 1,
 350         .gen = 8, .num_pipes = 3,
 351         .need_gfx_hws = 1, .has_hotplug = 1,
 352         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 353         .is_valleyview = 1,
 354         .display_mmio_offset = VLV_DISPLAY_BASE,
 355         GEN_CHV_PIPEOFFSETS,
 356         CURSOR_OFFSETS,
 357 };
 358
 359 static const struct intel_device_info intel_skylake_info = {
 360         .is_preliminary = 1,
 361         .is_skylake = 1,
 362         .gen = 9, .num_pipes = 3,
 363         .need_gfx_hws = 1, .has_hotplug = 1,
 364         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 365         .has_llc = 1,
 366         .has_ddi = 1,
 367         .has_fbc = 1,
 368         GEN_DEFAULT_PIPEOFFSETS,
 369         IVB_CURSOR_OFFSETS,
 370 };
 371
 372 static const struct intel_device_info intel_skylake_gt3_info = {
 373         .is_preliminary = 1,
 374         .is_skylake = 1,
 375         .gen = 9, .num_pipes = 3,
 376         .need_gfx_hws = 1, .has_hotplug = 1,
 377         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 378         .has_llc = 1,
 379         .has_ddi = 1,
 380         .has_fbc = 1,
 381         GEN_DEFAULT_PIPEOFFSETS,
 382         IVB_CURSOR_OFFSETS,
 383 };
 384
 385 /*
 386  * Make sure any device matches here are from most specific to most
 387  * general.  For example, since the Quanta match is based on the subsystem
 388  * and subvendor IDs, we need it to come before the more general IVB
 389  * PCI ID matches, otherwise we'll use the wrong info struct above.
 390  */
 391 #define INTEL_PCI_IDS \
 392         INTEL_I830_IDS(&intel_i830_info),       \
 393         INTEL_I845G_IDS(&intel_845g_info),      \
 394         INTEL_I85X_IDS(&intel_i85x_info),       \
 395         INTEL_I865G_IDS(&intel_i865g_info),     \
 396         INTEL_I915G_IDS(&intel_i915g_info),     \
 397         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 398         INTEL_I945G_IDS(&intel_i945g_info),     \
 399         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 400         INTEL_I965G_IDS(&intel_i965g_info),     \
 401         INTEL_G33_IDS(&intel_g33_info),         \
 402         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 403         INTEL_GM45_IDS(&intel_gm45_info),       \
 404         INTEL_G45_IDS(&intel_g45_info),         \
 405         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 406         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 407         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 408         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 409         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 410         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 411         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 412         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 413         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 414         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 415         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 416         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 417         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 418         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 419         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 420         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 421         INTEL_CHV_IDS(&intel_cherryview_info),  \
 422         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
 423         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
 424         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info)      \
 425
 426 static const struct pci_device_id pciidlist[] = {               /* aka */
 427         INTEL_PCI_IDS,
 428         {0, 0, 0}
 429 };
 430
 431 #if defined(CONFIG_DRM_I915_KMS)
 432 MODULE_DEVICE_TABLE(pci, pciidlist);
 433 #endif
 434
 435 void intel_detect_pch(struct drm_device *dev)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         struct pci_dev *pch = NULL;
 439
 440         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 441          * (which really amounts to a PCH but no South Display).
 442          */
 443         if (INTEL_INFO(dev)->num_pipes == 0) {
 444                 dev_priv->pch_type = PCH_NOP;
 445                 return;
 446         }
 447
 448         /*
 449          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 450          * make graphics device passthrough work easy for VMM, that only
 451          * need to expose ISA bridge to let driver know the real hardware
 452          * underneath. This is a requirement from virtualization team.
 453          *
 454          * In some virtualized environments (e.g. XEN), there is irrelevant
 455          * ISA bridge in the system. To work reliably, we should scan trhough
 456          * all the ISA bridge devices and check for the first match, instead
 457          * of only checking the first one.
 458          */
 459         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 460                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 461                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 462                         dev_priv->pch_id = id;
 463
 464                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 465                                 dev_priv->pch_type = PCH_IBX;
 466                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 467                                 WARN_ON(!IS_GEN5(dev));
 468                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 469                                 dev_priv->pch_type = PCH_CPT;
 470                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 471                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 472                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 473                                 /* PantherPoint is CPT compatible */
 474                                 dev_priv->pch_type = PCH_CPT;
 475                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 476                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 477                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 478                                 dev_priv->pch_type = PCH_LPT;
 479                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 480                                 WARN_ON(!IS_HASWELL(dev));
 481                                 WARN_ON(IS_HSW_ULT(dev));
 482                         } else if (IS_BROADWELL(dev)) {
 483                                 dev_priv->pch_type = PCH_LPT;
 484                                 dev_priv->pch_id =
 485                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 486                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 487                                               "LynxPoint LP PCH\n");
 488                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 489                                 dev_priv->pch_type = PCH_LPT;
 490                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 491                                 WARN_ON(!IS_HASWELL(dev));
 492                                 WARN_ON(!IS_HSW_ULT(dev));
 493                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 494                                 dev_priv->pch_type = PCH_SPT;
 495                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 496                                 WARN_ON(!IS_SKYLAKE(dev));
 497                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 498                                 dev_priv->pch_type = PCH_SPT;
 499                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 500                                 WARN_ON(!IS_SKYLAKE(dev));
 501                         } else
 502                                 continue;
 503
 504                         break;
 505                 }
 506         }
 507         if (!pch)
 508                 DRM_DEBUG_KMS("No PCH found.\n");
 509
 510         pci_dev_put(pch);
 511 }
 512
 513 bool i915_semaphore_is_enabled(struct drm_device *dev)
 514 {
 515         if (INTEL_INFO(dev)->gen < 6)
 516                 return false;
 517
 518         if (i915.semaphores >= 0)
 519                 return i915.semaphores;
 520
 521         /* TODO: make semaphores and Execlists play nicely together */
 522         if (i915.enable_execlists)
 523                 return false;
 524
 525         /* Until we get further testing... */
 526         if (IS_GEN8(dev))
 527                 return false;
 528
 529 #ifdef CONFIG_INTEL_IOMMU
 530         /* Enable semaphores on SNB when IO remapping is off */
 531         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 532                 return false;
 533 #endif
 534
 535         return true;
 536 }
 537
 538 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 539 {
 540         spin_lock_irq(&dev_priv->irq_lock);
 541
 542         dev_priv->long_hpd_port_mask = 0;
 543         dev_priv->short_hpd_port_mask = 0;
 544         dev_priv->hpd_event_bits = 0;
 545
 546         spin_unlock_irq(&dev_priv->irq_lock);
 547
 548         cancel_work_sync(&dev_priv->dig_port_work);
 549         cancel_work_sync(&dev_priv->hotplug_work);
 550         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 551 }
 552
 553 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 554 {
 555         struct drm_device *dev = dev_priv->dev;
 556         struct drm_encoder *encoder;
 557
 558         drm_modeset_lock_all(dev);
 559         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 560                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 561
 562                 if (intel_encoder->suspend)
 563                         intel_encoder->suspend(intel_encoder);
 564         }
 565         drm_modeset_unlock_all(dev);
 566 }
 567
 568 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 569 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 570                               bool rpm_resume);
 571
 572 static int i915_drm_suspend(struct drm_device *dev)
 573 {
 574         struct drm_i915_private *dev_priv = dev->dev_private;
 575         struct drm_crtc *crtc;
 576         pci_power_t opregion_target_state;
 577
 578         /* ignore lid events during suspend */
 579         mutex_lock(&dev_priv->modeset_restore_lock);
 580         dev_priv->modeset_restore = MODESET_SUSPENDED;
 581         mutex_unlock(&dev_priv->modeset_restore_lock);
 582
 583         /* We do a lot of poking in a lot of registers, make sure they work
 584          * properly. */
 585         intel_display_set_init_power(dev_priv, true);
 586
 587         drm_kms_helper_poll_disable(dev);
 588
 589         pci_save_state(dev->pdev);
 590
 591         /* If KMS is active, we do the leavevt stuff here */
 592         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 593                 int error;
 594
 595                 error = i915_gem_suspend(dev);
 596                 if (error) {
 597                         dev_err(&dev->pdev->dev,
 598                                 "GEM idle failed, resume might fail\n");
 599                         return error;
 600                 }
 601
 602                 intel_suspend_gt_powersave(dev);
 603
 604                 /*
 605                  * Disable CRTCs directly since we want to preserve sw state
 606                  * for _thaw. Also, power gate the CRTC power wells.
 607                  */
 608                 drm_modeset_lock_all(dev);
 609                 for_each_crtc(dev, crtc)
 610                         intel_crtc_control(crtc, false);
 611                 drm_modeset_unlock_all(dev);
 612
 613                 intel_dp_mst_suspend(dev);
 614
 615                 intel_runtime_pm_disable_interrupts(dev_priv);
 616                 intel_hpd_cancel_work(dev_priv);
 617
 618                 intel_suspend_encoders(dev_priv);
 619
 620                 intel_suspend_hw(dev);
 621         }
 622
 623         i915_gem_suspend_gtt_mappings(dev);
 624
 625         i915_save_state(dev);
 626
 627         opregion_target_state = PCI_D3cold;
 628 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 629         if (acpi_target_system_state() < ACPI_STATE_S3)
 630                 opregion_target_state = PCI_D1;
 631 #endif
 632         intel_opregion_notify_adapter(dev, opregion_target_state);
 633
 634         intel_uncore_forcewake_reset(dev, false);
 635         intel_opregion_fini(dev);
 636
 637         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 638
 639         dev_priv->suspend_count++;
 640
 641         intel_display_set_init_power(dev_priv, false);
 642
 643         return 0;
 644 }
 645
 646 static int i915_drm_suspend_late(struct drm_device *drm_dev)
 647 {
 648         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 649         int ret;
 650
 651         ret = intel_suspend_complete(dev_priv);
 652
 653         if (ret) {
 654                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 655
 656                 return ret;
 657         }
 658
 659         pci_disable_device(drm_dev->pdev);
 660         pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 661
 662         return 0;
 663 }
 664
 665 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
 666 {
 667         int error;
 668
 669         if (!dev || !dev->dev_private) {
 670                 DRM_ERROR("dev: %p\n", dev);
 671                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 672                 return -ENODEV;
 673         }
 674
 675         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 676                          state.event != PM_EVENT_FREEZE))
 677                 return -EINVAL;
 678
 679         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 680                 return 0;
 681
 682         error = i915_drm_suspend(dev);
 683         if (error)
 684                 return error;
 685
 686         return i915_drm_suspend_late(dev);
 687 }
 688
 689 static int i915_drm_resume(struct drm_device *dev)
 690 {
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692
 693         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 694                 mutex_lock(&dev->struct_mutex);
 695                 i915_gem_restore_gtt_mappings(dev);
 696                 mutex_unlock(&dev->struct_mutex);
 697         }
 698
 699         i915_restore_state(dev);
 700         intel_opregion_setup(dev);
 701
 702         /* KMS EnterVT equivalent */
 703         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 704                 intel_init_pch_refclk(dev);
 705                 drm_mode_config_reset(dev);
 706
 707                 mutex_lock(&dev->struct_mutex);
 708                 if (i915_gem_init_hw(dev)) {
 709                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 710                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 711                 }
 712                 mutex_unlock(&dev->struct_mutex);
 713
 714                 /* We need working interrupts for modeset enabling ... */
 715                 intel_runtime_pm_enable_interrupts(dev_priv);
 716
 717                 intel_modeset_init_hw(dev);
 718
 719                 spin_lock_irq(&dev_priv->irq_lock);
 720                 if (dev_priv->display.hpd_irq_setup)
 721                         dev_priv->display.hpd_irq_setup(dev);
 722                 spin_unlock_irq(&dev_priv->irq_lock);
 723
 724                 drm_modeset_lock_all(dev);
 725                 intel_modeset_setup_hw_state(dev, true);
 726                 drm_modeset_unlock_all(dev);
 727
 728                 intel_dp_mst_resume(dev);
 729
 730                 /*
 731                  * ... but also need to make sure that hotplug processing
 732                  * doesn't cause havoc. Like in the driver load code we don't
 733                  * bother with the tiny race here where we might loose hotplug
 734                  * notifications.
 735                  * */
 736                 intel_hpd_init(dev_priv);
 737                 /* Config may have changed between suspend and resume */
 738                 drm_helper_hpd_irq_event(dev);
 739         }
 740
 741         intel_opregion_init(dev);
 742
 743         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 744
 745         mutex_lock(&dev_priv->modeset_restore_lock);
 746         dev_priv->modeset_restore = MODESET_DONE;
 747         mutex_unlock(&dev_priv->modeset_restore_lock);
 748
 749         intel_opregion_notify_adapter(dev, PCI_D0);
 750
 751         drm_kms_helper_poll_enable(dev);
 752
 753         return 0;
 754 }
 755
 756 static int i915_drm_resume_early(struct drm_device *dev)
 757 {
 758         struct drm_i915_private *dev_priv = dev->dev_private;
 759         int ret = 0;
 760
 761         /*
 762          * We have a resume ordering issue with the snd-hda driver also
 763          * requiring our device to be power up. Due to the lack of a
 764          * parent/child relationship we currently solve this with an early
 765          * resume hook.
 766          *
 767          * FIXME: This should be solved with a special hdmi sink device or
 768          * similar so that power domains can be employed.
 769          */
 770         if (pci_enable_device(dev->pdev))
 771                 return -EIO;
 772
 773         pci_set_master(dev->pdev);
 774
 775         if (IS_VALLEYVIEW(dev_priv))
 776                 ret = vlv_resume_prepare(dev_priv, false);
 777         if (ret)
 778                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 779
 780         intel_uncore_early_sanitize(dev, true);
 781
 782         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 783                 hsw_disable_pc8(dev_priv);
 784
 785         intel_uncore_sanitize(dev);
 786         intel_power_domains_init_hw(dev_priv);
 787
 788         return ret;
 789 }
 790
 791 int i915_resume_legacy(struct drm_device *dev)
 792 {
 793         int ret;
 794
 795         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 796                 return 0;
 797
 798         ret = i915_drm_resume_early(dev);
 799         if (ret)
 800                 return ret;
 801
 802         return i915_drm_resume(dev);
 803 }
 804
 805 /**
 806  * i915_reset - reset chip after a hang
 807  * @dev: drm device to reset
 808  *
 809  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 810  * reset or otherwise an error code.
 811  *
 812  * Procedure is fairly simple:
 813  *   - reset the chip using the reset reg
 814  *   - re-init context state
 815  *   - re-init hardware status page
 816  *   - re-init ring buffer
 817  *   - re-init interrupt state
 818  *   - re-init display
 819  */
 820 int i915_reset(struct drm_device *dev)
 821 {
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         bool simulated;
 824         int ret;
 825
 826         if (!i915.reset)
 827                 return 0;
 828
 829         intel_reset_gt_powersave(dev);
 830
 831         mutex_lock(&dev->struct_mutex);
 832
 833         i915_gem_reset(dev);
 834
 835         simulated = dev_priv->gpu_error.stop_rings != 0;
 836
 837         ret = intel_gpu_reset(dev);
 838
 839         /* Also reset the gpu hangman. */
 840         if (simulated) {
 841                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 842                 dev_priv->gpu_error.stop_rings = 0;
 843                 if (ret == -ENODEV) {
 844                         DRM_INFO("Reset not implemented, but ignoring "
 845                                  "error for simulated gpu hangs\n");
 846                         ret = 0;
 847                 }
 848         }
 849
 850         if (i915_stop_ring_allow_warn(dev_priv))
 851                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 852
 853         if (ret) {
 854                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 855                 mutex_unlock(&dev->struct_mutex);
 856                 return ret;
 857         }
 858
 859         intel_overlay_reset(dev_priv);
 860
 861         /* Ok, now get things going again... */
 862
 863         /*
 864          * Everything depends on having the GTT running, so we need to start
 865          * there.  Fortunately we don't need to do this unless we reset the
 866          * chip at a PCI level.
 867          *
 868          * Next we need to restore the context, but we don't use those
 869          * yet either...
 870          *
 871          * Ring buffer needs to be re-initialized in the KMS case, or if X
 872          * was running at the time of the reset (i.e. we weren't VT
 873          * switched away).
 874          */
 875         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 876                 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 877                 dev_priv->gpu_error.reload_in_reset = true;
 878
 879                 ret = i915_gem_init_hw(dev);
 880
 881                 dev_priv->gpu_error.reload_in_reset = false;
 882
 883                 mutex_unlock(&dev->struct_mutex);
 884                 if (ret) {
 885                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 886                         return ret;
 887                 }
 888
 889                 /*
 890                  * FIXME: This races pretty badly against concurrent holders of
 891                  * ring interrupts. This is possible since we've started to drop
 892                  * dev->struct_mutex in select places when waiting for the gpu.
 893                  */
 894
 895                 /*
 896                  * rps/rc6 re-init is necessary to restore state lost after the
 897                  * reset and the re-install of gt irqs. Skip for ironlake per
 898                  * previous concerns that it doesn't respond well to some forms
 899                  * of re-init after reset.
 900                  */
 901                 if (INTEL_INFO(dev)->gen > 5)
 902                         intel_enable_gt_powersave(dev);
 903         } else {
 904                 mutex_unlock(&dev->struct_mutex);
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 911 {
 912         struct intel_device_info *intel_info =
 913                 (struct intel_device_info *) ent->driver_data;
 914
 915         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 916                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 917                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 918                 return -ENODEV;
 919         }
 920
 921         /* Only bind to function 0 of the device. Early generations
 922          * used function 1 as a placeholder for multi-head. This causes
 923          * us confusion instead, especially on the systems where both
 924          * functions have the same PCI-ID!
 925          */
 926         if (PCI_FUNC(pdev->devfn))
 927                 return -ENODEV;
 928
 929         driver.driver_features &= ~(DRIVER_USE_AGP);
 930
 931         return drm_get_pci_dev(pdev, ent, &driver);
 932 }
 933
 934 static void
 935 i915_pci_remove(struct pci_dev *pdev)
 936 {
 937         struct drm_device *dev = pci_get_drvdata(pdev);
 938
 939         drm_put_dev(dev);
 940 }
 941
 942 static int i915_pm_suspend(struct device *dev)
 943 {
 944         struct pci_dev *pdev = to_pci_dev(dev);
 945         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 946
 947         if (!drm_dev || !drm_dev->dev_private) {
 948                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 949                 return -ENODEV;
 950         }
 951
 952         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 953                 return 0;
 954
 955         return i915_drm_suspend(drm_dev);
 956 }
 957
 958 static int i915_pm_suspend_late(struct device *dev)
 959 {
 960         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 961
 962         /*
 963          * We have a suspedn ordering issue with the snd-hda driver also
 964          * requiring our device to be power up. Due to the lack of a
 965          * parent/child relationship we currently solve this with an late
 966          * suspend hook.
 967          *
 968          * FIXME: This should be solved with a special hdmi sink device or
 969          * similar so that power domains can be employed.
 970          */
 971         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 972                 return 0;
 973
 974         return i915_drm_suspend_late(drm_dev);
 975 }
 976
 977 static int i915_pm_resume_early(struct device *dev)
 978 {
 979         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 980
 981         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 982                 return 0;
 983
 984         return i915_drm_resume_early(drm_dev);
 985 }
 986
 987 static int i915_pm_resume(struct device *dev)
 988 {
 989         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 990
 991         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 992                 return 0;
 993
 994         return i915_drm_resume(drm_dev);
 995 }
 996
 997 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
 998 {
 999         hsw_enable_pc8(dev_priv);
1000
1001         return 0;
1002 }
1003
1004 /*
1005  * Save all Gunit registers that may be lost after a D3 and a subsequent
1006  * S0i[R123] transition. The list of registers needing a save/restore is
1007  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1008  * registers in the following way:
1009  * - Driver: saved/restored by the driver
1010  * - Punit : saved/restored by the Punit firmware
1011  * - No, w/o marking: no need to save/restore, since the register is R/O or
1012  *                    used internally by the HW in a way that doesn't depend
1013  *                    keeping the content across a suspend/resume.
1014  * - Debug : used for debugging
1015  *
1016  * We save/restore all registers marked with 'Driver', with the following
1017  * exceptions:
1018  * - Registers out of use, including also registers marked with 'Debug'.
1019  *   These have no effect on the driver's operation, so we don't save/restore
1020  *   them to reduce the overhead.
1021  * - Registers that are fully setup by an initialization function called from
1022  *   the resume path. For example many clock gating and RPS/RC6 registers.
1023  * - Registers that provide the right functionality with their reset defaults.
1024  *
1025  * TODO: Except for registers that based on the above 3 criteria can be safely
1026  * ignored, we save/restore all others, practically treating the HW context as
1027  * a black-box for the driver. Further investigation is needed to reduce the
1028  * saved/restored registers even further, by following the same 3 criteria.
1029  */
1030 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1031 {
1032         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1033         int i;
1034
1035         /* GAM 0x4000-0x4770 */
1036         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1037         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1038         s->arb_mode             = I915_READ(ARB_MODE);
1039         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1040         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1041
1042         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1043                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1044
1045         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1046         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1047
1048         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1049         s->ecochk               = I915_READ(GAM_ECOCHK);
1050         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1051         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1052
1053         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1054
1055         /* MBC 0x9024-0x91D0, 0x8500 */
1056         s->g3dctl               = I915_READ(VLV_G3DCTL);
1057         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1058         s->mbctl                = I915_READ(GEN6_MBCTL);
1059
1060         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1061         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1062         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1063         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1064         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1065         s->rstctl               = I915_READ(GEN6_RSTCTL);
1066         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1067
1068         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1069         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1070         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1071         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1072         s->ecobus               = I915_READ(ECOBUS);
1073         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1074         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1075         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1076         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1077         s->rcedata              = I915_READ(VLV_RCEDATA);
1078         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1079
1080         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1081         s->gt_imr               = I915_READ(GTIMR);
1082         s->gt_ier               = I915_READ(GTIER);
1083         s->pm_imr               = I915_READ(GEN6_PMIMR);
1084         s->pm_ier               = I915_READ(GEN6_PMIER);
1085
1086         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1087                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1088
1089         /* GT SA CZ domain, 0x100000-0x138124 */
1090         s->tilectl              = I915_READ(TILECTL);
1091         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1092         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1093         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1094         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1095
1096         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1097         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1098         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1099         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1100
1101         /*
1102          * Not saving any of:
1103          * DFT,         0x9800-0x9EC0
1104          * SARB,        0xB000-0xB1FC
1105          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1106          * PCI CFG
1107          */
1108 }
1109
1110 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1111 {
1112         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1113         u32 val;
1114         int i;
1115
1116         /* GAM 0x4000-0x4770 */
1117         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1118         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1119         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1120         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1121         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1122
1123         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1124                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1125
1126         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1127         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1128
1129         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1130         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1131         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1132         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1133
1134         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1135
1136         /* MBC 0x9024-0x91D0, 0x8500 */
1137         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1138         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1139         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1140
1141         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1142         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1143         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1144         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1145         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1146         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1147         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1148
1149         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1150         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1151         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1152         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1153         I915_WRITE(ECOBUS,              s->ecobus);
1154         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1155         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1156         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1157         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1158         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1159         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1160
1161         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1162         I915_WRITE(GTIMR,               s->gt_imr);
1163         I915_WRITE(GTIER,               s->gt_ier);
1164         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1165         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1166
1167         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1168                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1169
1170         /* GT SA CZ domain, 0x100000-0x138124 */
1171         I915_WRITE(TILECTL,                     s->tilectl);
1172         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1173         /*
1174          * Preserve the GT allow wake and GFX force clock bit, they are not
1175          * be restored, as they are used to control the s0ix suspend/resume
1176          * sequence by the caller.
1177          */
1178         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1179         val &= VLV_GTLC_ALLOWWAKEREQ;
1180         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1181         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1182
1183         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1184         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1185         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1186         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1187
1188         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1189
1190         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1191         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1192         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1193         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1194 }
1195
1196 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1197 {
1198         u32 val;
1199         int err;
1200
1201         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1202         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1203
1204 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1205         /* Wait for a previous force-off to settle */
1206         if (force_on) {
1207                 err = wait_for(!COND, 20);
1208                 if (err) {
1209                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1210                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1211                         return err;
1212                 }
1213         }
1214
1215         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1216         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1217         if (force_on)
1218                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1219         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1220
1221         if (!force_on)
1222                 return 0;
1223
1224         err = wait_for(COND, 20);
1225         if (err)
1226                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1227                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1228
1229         return err;
1230 #undef COND
1231 }
1232
1233 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1234 {
1235         u32 val;
1236         int err = 0;
1237
1238         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1239         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1240         if (allow)
1241                 val |= VLV_GTLC_ALLOWWAKEREQ;
1242         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1243         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1244
1245 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1246               allow)
1247         err = wait_for(COND, 1);
1248         if (err)
1249                 DRM_ERROR("timeout disabling GT waking\n");
1250         return err;
1251 #undef COND
1252 }
1253
1254 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1255                                  bool wait_for_on)
1256 {
1257         u32 mask;
1258         u32 val;
1259         int err;
1260
1261         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1262         val = wait_for_on ? mask : 0;
1263 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1264         if (COND)
1265                 return 0;
1266
1267         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1268                         wait_for_on ? "on" : "off",
1269                         I915_READ(VLV_GTLC_PW_STATUS));
1270
1271         /*
1272          * RC6 transitioning can be delayed up to 2 msec (see
1273          * valleyview_enable_rps), use 3 msec for safety.
1274          */
1275         err = wait_for(COND, 3);
1276         if (err)
1277                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1278                           wait_for_on ? "on" : "off");
1279
1280         return err;
1281 #undef COND
1282 }
1283
1284 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1285 {
1286         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1287                 return;
1288
1289         DRM_ERROR("GT register access while GT waking disabled\n");
1290         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1291 }
1292
1293 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1294 {
1295         u32 mask;
1296         int err;
1297
1298         /*
1299          * Bspec defines the following GT well on flags as debug only, so
1300          * don't treat them as hard failures.
1301          */
1302         (void)vlv_wait_for_gt_wells(dev_priv, false);
1303
1304         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1305         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1306
1307         vlv_check_no_gt_access(dev_priv);
1308
1309         err = vlv_force_gfx_clock(dev_priv, true);
1310         if (err)
1311                 goto err1;
1312
1313         err = vlv_allow_gt_wake(dev_priv, false);
1314         if (err)
1315                 goto err2;
1316
1317         if (!IS_CHERRYVIEW(dev_priv->dev))
1318                 vlv_save_gunit_s0ix_state(dev_priv);
1319
1320         err = vlv_force_gfx_clock(dev_priv, false);
1321         if (err)
1322                 goto err2;
1323
1324         return 0;
1325
1326 err2:
1327         /* For safety always re-enable waking and disable gfx clock forcing */
1328         vlv_allow_gt_wake(dev_priv, true);
1329 err1:
1330         vlv_force_gfx_clock(dev_priv, false);
1331
1332         return err;
1333 }
1334
1335 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1336                                 bool rpm_resume)
1337 {
1338         struct drm_device *dev = dev_priv->dev;
1339         int err;
1340         int ret;
1341
1342         /*
1343          * If any of the steps fail just try to continue, that's the best we
1344          * can do at this point. Return the first error code (which will also
1345          * leave RPM permanently disabled).
1346          */
1347         ret = vlv_force_gfx_clock(dev_priv, true);
1348
1349         if (!IS_CHERRYVIEW(dev_priv->dev))
1350                 vlv_restore_gunit_s0ix_state(dev_priv);
1351
1352         err = vlv_allow_gt_wake(dev_priv, true);
1353         if (!ret)
1354                 ret = err;
1355
1356         err = vlv_force_gfx_clock(dev_priv, false);
1357         if (!ret)
1358                 ret = err;
1359
1360         vlv_check_no_gt_access(dev_priv);
1361
1362         if (rpm_resume) {
1363                 intel_init_clock_gating(dev);
1364                 i915_gem_restore_fences(dev);
1365         }
1366
1367         return ret;
1368 }
1369
1370 static int intel_runtime_suspend(struct device *device)
1371 {
1372         struct pci_dev *pdev = to_pci_dev(device);
1373         struct drm_device *dev = pci_get_drvdata(pdev);
1374         struct drm_i915_private *dev_priv = dev->dev_private;
1375         int ret;
1376
1377         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1378                 return -ENODEV;
1379
1380         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1381                 return -ENODEV;
1382
1383         DRM_DEBUG_KMS("Suspending device\n");
1384
1385         /*
1386          * We could deadlock here in case another thread holding struct_mutex
1387          * calls RPM suspend concurrently, since the RPM suspend will wait
1388          * first for this RPM suspend to finish. In this case the concurrent
1389          * RPM resume will be followed by its RPM suspend counterpart. Still
1390          * for consistency return -EAGAIN, which will reschedule this suspend.
1391          */
1392         if (!mutex_trylock(&dev->struct_mutex)) {
1393                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1394                 /*
1395                  * Bump the expiration timestamp, otherwise the suspend won't
1396                  * be rescheduled.
1397                  */
1398                 pm_runtime_mark_last_busy(device);
1399
1400                 return -EAGAIN;
1401         }
1402         /*
1403          * We are safe here against re-faults, since the fault handler takes
1404          * an RPM reference.
1405          */
1406         i915_gem_release_all_mmaps(dev_priv);
1407         mutex_unlock(&dev->struct_mutex);
1408
1409         intel_suspend_gt_powersave(dev);
1410         intel_runtime_pm_disable_interrupts(dev_priv);
1411
1412         ret = intel_suspend_complete(dev_priv);
1413         if (ret) {
1414                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1415                 intel_runtime_pm_enable_interrupts(dev_priv);
1416
1417                 return ret;
1418         }
1419
1420         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1421         intel_uncore_forcewake_reset(dev, false);
1422         dev_priv->pm.suspended = true;
1423
1424         /*
1425          * FIXME: We really should find a document that references the arguments
1426          * used below!
1427          */
1428         if (IS_HASWELL(dev)) {
1429                 /*
1430                  * current versions of firmware which depend on this opregion
1431                  * notification have repurposed the D1 definition to mean
1432                  * "runtime suspended" vs. what you would normally expect (D3)
1433                  * to distinguish it from notifications that might be sent via
1434                  * the suspend path.
1435                  */
1436                 intel_opregion_notify_adapter(dev, PCI_D1);
1437         } else {
1438                 /*
1439                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1440                  * being detected, and the call we do at intel_runtime_resume()
1441                  * won't be able to restore them. Since PCI_D3hot matches the
1442                  * actual specification and appears to be working, use it. Let's
1443                  * assume the other non-Haswell platforms will stay the same as
1444                  * Broadwell.
1445                  */
1446                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1447         }
1448
1449         assert_forcewakes_inactive(dev_priv);
1450
1451         DRM_DEBUG_KMS("Device suspended\n");
1452         return 0;
1453 }
1454
1455 static int intel_runtime_resume(struct device *device)
1456 {
1457         struct pci_dev *pdev = to_pci_dev(device);
1458         struct drm_device *dev = pci_get_drvdata(pdev);
1459         struct drm_i915_private *dev_priv = dev->dev_private;
1460         int ret = 0;
1461
1462         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1463                 return -ENODEV;
1464
1465         DRM_DEBUG_KMS("Resuming device\n");
1466
1467         intel_opregion_notify_adapter(dev, PCI_D0);
1468         dev_priv->pm.suspended = false;
1469
1470         if (IS_GEN6(dev_priv))
1471                 intel_init_pch_refclk(dev);
1472         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1473                 hsw_disable_pc8(dev_priv);
1474         else if (IS_VALLEYVIEW(dev_priv))
1475                 ret = vlv_resume_prepare(dev_priv, true);
1476
1477         /*
1478          * No point of rolling back things in case of an error, as the best
1479          * we can do is to hope that things will still work (and disable RPM).
1480          */
1481         i915_gem_init_swizzling(dev);
1482         gen6_update_ring_freq(dev);
1483
1484         intel_runtime_pm_enable_interrupts(dev_priv);
1485         intel_enable_gt_powersave(dev);
1486
1487         if (ret)
1488                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1489         else
1490                 DRM_DEBUG_KMS("Device resumed\n");
1491
1492         return ret;
1493 }
1494
1495 /*
1496  * This function implements common functionality of runtime and system
1497  * suspend sequence.
1498  */
1499 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1500 {
1501         struct drm_device *dev = dev_priv->dev;
1502         int ret;
1503
1504         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1505                 ret = hsw_suspend_complete(dev_priv);
1506         else if (IS_VALLEYVIEW(dev))
1507                 ret = vlv_suspend_complete(dev_priv);
1508         else
1509                 ret = 0;
1510
1511         return ret;
1512 }
1513
1514 static const struct dev_pm_ops i915_pm_ops = {
1515         /*
1516          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1517          * PMSG_RESUME]
1518          */
1519         .suspend = i915_pm_suspend,
1520         .suspend_late = i915_pm_suspend_late,
1521         .resume_early = i915_pm_resume_early,
1522         .resume = i915_pm_resume,
1523
1524         /*
1525          * S4 event handlers
1526          * @freeze, @freeze_late    : called (1) before creating the
1527          *                            hibernation image [PMSG_FREEZE] and
1528          *                            (2) after rebooting, before restoring
1529          *                            the image [PMSG_QUIESCE]
1530          * @thaw, @thaw_early       : called (1) after creating the hibernation
1531          *                            image, before writing it [PMSG_THAW]
1532          *                            and (2) after failing to create or
1533          *                            restore the image [PMSG_RECOVER]
1534          * @poweroff, @poweroff_late: called after writing the hibernation
1535          *                            image, before rebooting [PMSG_HIBERNATE]
1536          * @restore, @restore_early : called after rebooting and restoring the
1537          *                            hibernation image [PMSG_RESTORE]
1538          */
1539         .freeze = i915_pm_suspend,
1540         .freeze_late = i915_pm_suspend_late,
1541         .thaw_early = i915_pm_resume_early,
1542         .thaw = i915_pm_resume,
1543         .poweroff = i915_pm_suspend,
1544         .poweroff_late = i915_pm_suspend_late,
1545         .restore_early = i915_pm_resume_early,
1546         .restore = i915_pm_resume,
1547
1548         /* S0ix (via runtime suspend) event handlers */
1549         .runtime_suspend = intel_runtime_suspend,
1550         .runtime_resume = intel_runtime_resume,
1551 };
1552
1553 static const struct vm_operations_struct i915_gem_vm_ops = {
1554         .fault = i915_gem_fault,
1555         .open = drm_gem_vm_open,
1556         .close = drm_gem_vm_close,
1557 };
1558
1559 static const struct file_operations i915_driver_fops = {
1560         .owner = THIS_MODULE,
1561         .open = drm_open,
1562         .release = drm_release,
1563         .unlocked_ioctl = drm_ioctl,
1564         .mmap = drm_gem_mmap,
1565         .poll = drm_poll,
1566         .read = drm_read,
1567 #ifdef CONFIG_COMPAT
1568         .compat_ioctl = i915_compat_ioctl,
1569 #endif
1570         .llseek = noop_llseek,
1571 };
1572
1573 static struct drm_driver driver = {
1574         /* Don't use MTRRs here; the Xserver or userspace app should
1575          * deal with them for Intel hardware.
1576          */
1577         .driver_features =
1578             DRIVER_USE_AGP |
1579             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1580             DRIVER_RENDER,
1581         .load = i915_driver_load,
1582         .unload = i915_driver_unload,
1583         .open = i915_driver_open,
1584         .lastclose = i915_driver_lastclose,
1585         .preclose = i915_driver_preclose,
1586         .postclose = i915_driver_postclose,
1587         .set_busid = drm_pci_set_busid,
1588
1589         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1590         .suspend = i915_suspend_legacy,
1591         .resume = i915_resume_legacy,
1592
1593         .device_is_agp = i915_driver_device_is_agp,
1594 #if defined(CONFIG_DEBUG_FS)
1595         .debugfs_init = i915_debugfs_init,
1596         .debugfs_cleanup = i915_debugfs_cleanup,
1597 #endif
1598         .gem_free_object = i915_gem_free_object,
1599         .gem_vm_ops = &i915_gem_vm_ops,
1600
1601         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1602         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1603         .gem_prime_export = i915_gem_prime_export,
1604         .gem_prime_import = i915_gem_prime_import,
1605
1606         .dumb_create = i915_gem_dumb_create,
1607         .dumb_map_offset = i915_gem_mmap_gtt,
1608         .dumb_destroy = drm_gem_dumb_destroy,
1609         .ioctls = i915_ioctls,
1610         .fops = &i915_driver_fops,
1611         .name = DRIVER_NAME,
1612         .desc = DRIVER_DESC,
1613         .date = DRIVER_DATE,
1614         .major = DRIVER_MAJOR,
1615         .minor = DRIVER_MINOR,
1616         .patchlevel = DRIVER_PATCHLEVEL,
1617 };
1618
1619 static struct pci_driver i915_pci_driver = {
1620         .name = DRIVER_NAME,
1621         .id_table = pciidlist,
1622         .probe = i915_pci_probe,
1623         .remove = i915_pci_remove,
1624         .driver.pm = &i915_pm_ops,
1625 };
1626
1627 static int __init i915_init(void)
1628 {
1629         driver.num_ioctls = i915_max_ioctl;
1630
1631         /*
1632          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1633          * explicitly disabled with the module pararmeter.
1634          *
1635          * Otherwise, just follow the parameter (defaulting to off).
1636          *
1637          * Allow optional vga_text_mode_force boot option to override
1638          * the default behavior.
1639          */
1640 #if defined(CONFIG_DRM_I915_KMS)
1641         if (i915.modeset != 0)
1642                 driver.driver_features |= DRIVER_MODESET;
1643 #endif
1644         if (i915.modeset == 1)
1645                 driver.driver_features |= DRIVER_MODESET;
1646
1647 #ifdef CONFIG_VGA_CONSOLE
1648         if (vgacon_text_force() && i915.modeset == -1)
1649                 driver.driver_features &= ~DRIVER_MODESET;
1650 #endif
1651
1652         if (!(driver.driver_features & DRIVER_MODESET)) {
1653                 driver.get_vblank_timestamp = NULL;
1654 #ifndef CONFIG_DRM_I915_UMS
1655                 /* Silently fail loading to not upset userspace. */
1656                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1657                 return 0;
1658 #endif
1659         }
1660
1661         /*
1662          * FIXME: Note that we're lying to the DRM core here so that we can get access
1663          * to the atomic ioctl and the atomic properties.  Only plane operations on
1664          * a single CRTC will actually work.
1665          */
1666         if (i915.nuclear_pageflip)
1667                 driver.driver_features |= DRIVER_ATOMIC;
1668
1669         return drm_pci_init(&driver, &i915_pci_driver);
1670 }
1671
1672 static void __exit i915_exit(void)
1673 {
1674 #ifndef CONFIG_DRM_I915_UMS
1675         if (!(driver.driver_features & DRIVER_MODESET))
1676                 return; /* Never loaded a driver. */
1677 #endif
1678
1679         drm_pci_exit(&driver, &i915_pci_driver);
1680 }
1681
1682 module_init(i915_init);
1683 module_exit(i915_exit);
1684
1685 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1686 MODULE_AUTHOR("Intel Corporation");
1687
1688 MODULE_DESCRIPTION(DRIVER_DESC);
1689 MODULE_LICENSE("GPL and additional rights");