drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fbc = 1,
 307         GEN_DEFAULT_PIPEOFFSETS,
 308         IVB_CURSOR_OFFSETS,
 309 };
 310
 311 static const struct intel_device_info intel_broadwell_m_info = {
 312         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 313         .need_gfx_hws = 1, .has_hotplug = 1,
 314         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 315         .has_llc = 1,
 316         .has_ddi = 1,
 317         .has_fbc = 1,
 318         GEN_DEFAULT_PIPEOFFSETS,
 319         IVB_CURSOR_OFFSETS,
 320 };
 321
 322 static const struct intel_device_info intel_broadwell_gt3d_info = {
 323         .gen = 8, .num_pipes = 3,
 324         .need_gfx_hws = 1, .has_hotplug = 1,
 325         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 326         .has_llc = 1,
 327         .has_ddi = 1,
 328         .has_fbc = 1,
 329         GEN_DEFAULT_PIPEOFFSETS,
 330         IVB_CURSOR_OFFSETS,
 331 };
 332
 333 static const struct intel_device_info intel_broadwell_gt3m_info = {
 334         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 335         .need_gfx_hws = 1, .has_hotplug = 1,
 336         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 337         .has_llc = 1,
 338         .has_ddi = 1,
 339         .has_fbc = 1,
 340         GEN_DEFAULT_PIPEOFFSETS,
 341         IVB_CURSOR_OFFSETS,
 342 };
 343
 344 static const struct intel_device_info intel_cherryview_info = {
 345         .is_preliminary = 1,
 346         .gen = 8, .num_pipes = 3,
 347         .need_gfx_hws = 1, .has_hotplug = 1,
 348         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 349         .is_valleyview = 1,
 350         .display_mmio_offset = VLV_DISPLAY_BASE,
 351         GEN_CHV_PIPEOFFSETS,
 352         CURSOR_OFFSETS,
 353 };
 354
 355 /*
 356  * Make sure any device matches here are from most specific to most
 357  * general.  For example, since the Quanta match is based on the subsystem
 358  * and subvendor IDs, we need it to come before the more general IVB
 359  * PCI ID matches, otherwise we'll use the wrong info struct above.
 360  */
 361 #define INTEL_PCI_IDS \
 362         INTEL_I830_IDS(&intel_i830_info),       \
 363         INTEL_I845G_IDS(&intel_845g_info),      \
 364         INTEL_I85X_IDS(&intel_i85x_info),       \
 365         INTEL_I865G_IDS(&intel_i865g_info),     \
 366         INTEL_I915G_IDS(&intel_i915g_info),     \
 367         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 368         INTEL_I945G_IDS(&intel_i945g_info),     \
 369         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 370         INTEL_I965G_IDS(&intel_i965g_info),     \
 371         INTEL_G33_IDS(&intel_g33_info),         \
 372         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 373         INTEL_GM45_IDS(&intel_gm45_info),       \
 374         INTEL_G45_IDS(&intel_g45_info),         \
 375         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 376         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 377         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 378         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 379         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 380         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 381         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 382         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 383         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 384         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 385         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 386         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 387         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 388         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 389         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 390         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 391         INTEL_CHV_IDS(&intel_cherryview_info)
 392
 393 static const struct pci_device_id pciidlist[] = {               /* aka */
 394         INTEL_PCI_IDS,
 395         {0, 0, 0}
 396 };
 397
 398 #if defined(CONFIG_DRM_I915_KMS)
 399 MODULE_DEVICE_TABLE(pci, pciidlist);
 400 #endif
 401
 402 void intel_detect_pch(struct drm_device *dev)
 403 {
 404         struct drm_i915_private *dev_priv = dev->dev_private;
 405         struct pci_dev *pch = NULL;
 406
 407         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 408          * (which really amounts to a PCH but no South Display).
 409          */
 410         if (INTEL_INFO(dev)->num_pipes == 0) {
 411                 dev_priv->pch_type = PCH_NOP;
 412                 return;
 413         }
 414
 415         /*
 416          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 417          * make graphics device passthrough work easy for VMM, that only
 418          * need to expose ISA bridge to let driver know the real hardware
 419          * underneath. This is a requirement from virtualization team.
 420          *
 421          * In some virtualized environments (e.g. XEN), there is irrelevant
 422          * ISA bridge in the system. To work reliably, we should scan trhough
 423          * all the ISA bridge devices and check for the first match, instead
 424          * of only checking the first one.
 425          */
 426         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 427                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 428                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 429                         dev_priv->pch_id = id;
 430
 431                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 432                                 dev_priv->pch_type = PCH_IBX;
 433                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 434                                 WARN_ON(!IS_GEN5(dev));
 435                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_CPT;
 437                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 438                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 439                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 440                                 /* PantherPoint is CPT compatible */
 441                                 dev_priv->pch_type = PCH_CPT;
 442                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 443                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 444                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 445                                 dev_priv->pch_type = PCH_LPT;
 446                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 447                                 WARN_ON(!IS_HASWELL(dev));
 448                                 WARN_ON(IS_ULT(dev));
 449                         } else if (IS_BROADWELL(dev)) {
 450                                 dev_priv->pch_type = PCH_LPT;
 451                                 dev_priv->pch_id =
 452                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 453                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 454                                               "LynxPoint LP PCH\n");
 455                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 456                                 dev_priv->pch_type = PCH_LPT;
 457                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 458                                 WARN_ON(!IS_HASWELL(dev));
 459                                 WARN_ON(!IS_ULT(dev));
 460                         } else
 461                                 continue;
 462
 463                         break;
 464                 }
 465         }
 466         if (!pch)
 467                 DRM_DEBUG_KMS("No PCH found.\n");
 468
 469         pci_dev_put(pch);
 470 }
 471
 472 bool i915_semaphore_is_enabled(struct drm_device *dev)
 473 {
 474         if (INTEL_INFO(dev)->gen < 6)
 475                 return false;
 476
 477         if (i915.semaphores >= 0)
 478                 return i915.semaphores;
 479
 480 #ifdef CONFIG_INTEL_IOMMU
 481         /* Enable semaphores on SNB when IO remapping is off */
 482         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 483                 return false;
 484 #endif
 485
 486         return true;
 487 }
 488
 489 static int i915_drm_freeze(struct drm_device *dev)
 490 {
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         struct drm_crtc *crtc;
 493         pci_power_t opregion_target_state;
 494
 495         /* ignore lid events during suspend */
 496         mutex_lock(&dev_priv->modeset_restore_lock);
 497         dev_priv->modeset_restore = MODESET_SUSPENDED;
 498         mutex_unlock(&dev_priv->modeset_restore_lock);
 499
 500         /* We do a lot of poking in a lot of registers, make sure they work
 501          * properly. */
 502         intel_display_set_init_power(dev_priv, true);
 503
 504         drm_kms_helper_poll_disable(dev);
 505
 506         pci_save_state(dev->pdev);
 507
 508         /* If KMS is active, we do the leavevt stuff here */
 509         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 510                 int error;
 511
 512                 error = i915_gem_suspend(dev);
 513                 if (error) {
 514                         dev_err(&dev->pdev->dev,
 515                                 "GEM idle failed, resume might fail\n");
 516                         return error;
 517                 }
 518
 519                 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 520
 521
 522                 intel_suspend_gt_powersave(dev);
 523
 524                 /*
 525                  * Disable CRTCs directly since we want to preserve sw state
 526                  * for _thaw.
 527                  */
 528                 drm_modeset_lock_all(dev);
 529                 for_each_crtc(dev, crtc) {
 530                         dev_priv->display.crtc_disable(crtc);
 531                 }
 532                 drm_modeset_unlock_all(dev);
 533
 534                 intel_dp_mst_suspend(dev);
 535                 intel_runtime_pm_disable_interrupts(dev);
 536
 537                 intel_modeset_suspend_hw(dev);
 538         }
 539
 540         i915_gem_suspend_gtt_mappings(dev);
 541
 542         i915_save_state(dev);
 543
 544         opregion_target_state = PCI_D3cold;
 545 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 546         if (acpi_target_system_state() < ACPI_STATE_S3)
 547                 opregion_target_state = PCI_D1;
 548 #endif
 549         intel_opregion_notify_adapter(dev, opregion_target_state);
 550
 551         intel_uncore_forcewake_reset(dev, false);
 552         intel_opregion_fini(dev);
 553
 554         console_lock();
 555         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 556         console_unlock();
 557
 558         dev_priv->suspend_count++;
 559
 560         intel_display_set_init_power(dev_priv, false);
 561
 562         return 0;
 563 }
 564
 565 int i915_suspend(struct drm_device *dev, pm_message_t state)
 566 {
 567         int error;
 568
 569         if (!dev || !dev->dev_private) {
 570                 DRM_ERROR("dev: %p\n", dev);
 571                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 572                 return -ENODEV;
 573         }
 574
 575         if (state.event == PM_EVENT_PRETHAW)
 576                 return 0;
 577
 578
 579         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 580                 return 0;
 581
 582         error = i915_drm_freeze(dev);
 583         if (error)
 584                 return error;
 585
 586         if (state.event == PM_EVENT_SUSPEND) {
 587                 /* Shut down the device */
 588                 pci_disable_device(dev->pdev);
 589                 pci_set_power_state(dev->pdev, PCI_D3hot);
 590         }
 591
 592         return 0;
 593 }
 594
 595 void intel_console_resume(struct work_struct *work)
 596 {
 597         struct drm_i915_private *dev_priv =
 598                 container_of(work, struct drm_i915_private,
 599                              console_resume_work);
 600         struct drm_device *dev = dev_priv->dev;
 601
 602         console_lock();
 603         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 604         console_unlock();
 605 }
 606
 607 static int i915_drm_thaw_early(struct drm_device *dev)
 608 {
 609         struct drm_i915_private *dev_priv = dev->dev_private;
 610
 611         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 612                 hsw_disable_pc8(dev_priv);
 613
 614         intel_uncore_early_sanitize(dev, true);
 615         intel_uncore_sanitize(dev);
 616         intel_power_domains_init_hw(dev_priv);
 617
 618         return 0;
 619 }
 620
 621 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 622 {
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624
 625         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 626             restore_gtt_mappings) {
 627                 mutex_lock(&dev->struct_mutex);
 628                 i915_gem_restore_gtt_mappings(dev);
 629                 mutex_unlock(&dev->struct_mutex);
 630         }
 631
 632         i915_restore_state(dev);
 633         intel_opregion_setup(dev);
 634
 635         /* KMS EnterVT equivalent */
 636         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 637                 intel_init_pch_refclk(dev);
 638                 drm_mode_config_reset(dev);
 639
 640                 mutex_lock(&dev->struct_mutex);
 641                 if (i915_gem_init_hw(dev)) {
 642                         DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 643                         atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 644                 }
 645                 mutex_unlock(&dev->struct_mutex);
 646
 647                 intel_runtime_pm_restore_interrupts(dev);
 648
 649                 intel_modeset_init_hw(dev);
 650
 651                 {
 652                         unsigned long irqflags;
 653                         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 654                         if (dev_priv->display.hpd_irq_setup)
 655                                 dev_priv->display.hpd_irq_setup(dev);
 656                         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 657                 }
 658
 659                 intel_dp_mst_resume(dev);
 660                 drm_modeset_lock_all(dev);
 661                 intel_modeset_setup_hw_state(dev, true);
 662                 drm_modeset_unlock_all(dev);
 663
 664                 /*
 665                  * ... but also need to make sure that hotplug processing
 666                  * doesn't cause havoc. Like in the driver load code we don't
 667                  * bother with the tiny race here where we might loose hotplug
 668                  * notifications.
 669                  * */
 670                 intel_hpd_init(dev);
 671                 /* Config may have changed between suspend and resume */
 672                 drm_helper_hpd_irq_event(dev);
 673         }
 674
 675         intel_opregion_init(dev);
 676
 677         /*
 678          * The console lock can be pretty contented on resume due
 679          * to all the printk activity.  Try to keep it out of the hot
 680          * path of resume if possible.
 681          */
 682         if (console_trylock()) {
 683                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 684                 console_unlock();
 685         } else {
 686                 schedule_work(&dev_priv->console_resume_work);
 687         }
 688
 689         mutex_lock(&dev_priv->modeset_restore_lock);
 690         dev_priv->modeset_restore = MODESET_DONE;
 691         mutex_unlock(&dev_priv->modeset_restore_lock);
 692
 693         intel_opregion_notify_adapter(dev, PCI_D0);
 694
 695         return 0;
 696 }
 697
 698 static int i915_drm_thaw(struct drm_device *dev)
 699 {
 700         if (drm_core_check_feature(dev, DRIVER_MODESET))
 701                 i915_check_and_clear_faults(dev);
 702
 703         return __i915_drm_thaw(dev, true);
 704 }
 705
 706 static int i915_resume_early(struct drm_device *dev)
 707 {
 708         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 709                 return 0;
 710
 711         /*
 712          * We have a resume ordering issue with the snd-hda driver also
 713          * requiring our device to be power up. Due to the lack of a
 714          * parent/child relationship we currently solve this with an early
 715          * resume hook.
 716          *
 717          * FIXME: This should be solved with a special hdmi sink device or
 718          * similar so that power domains can be employed.
 719          */
 720         if (pci_enable_device(dev->pdev))
 721                 return -EIO;
 722
 723         pci_set_master(dev->pdev);
 724
 725         return i915_drm_thaw_early(dev);
 726 }
 727
 728 int i915_resume(struct drm_device *dev)
 729 {
 730         struct drm_i915_private *dev_priv = dev->dev_private;
 731         int ret;
 732
 733         /*
 734          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 735          * earlier) need to restore the GTT mappings since the BIOS might clear
 736          * all our scratch PTEs.
 737          */
 738         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 739         if (ret)
 740                 return ret;
 741
 742         drm_kms_helper_poll_enable(dev);
 743         return 0;
 744 }
 745
 746 static int i915_resume_legacy(struct drm_device *dev)
 747 {
 748         i915_resume_early(dev);
 749         i915_resume(dev);
 750
 751         return 0;
 752 }
 753
 754 /**
 755  * i915_reset - reset chip after a hang
 756  * @dev: drm device to reset
 757  *
 758  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 759  * reset or otherwise an error code.
 760  *
 761  * Procedure is fairly simple:
 762  *   - reset the chip using the reset reg
 763  *   - re-init context state
 764  *   - re-init hardware status page
 765  *   - re-init ring buffer
 766  *   - re-init interrupt state
 767  *   - re-init display
 768  */
 769 int i915_reset(struct drm_device *dev)
 770 {
 771         struct drm_i915_private *dev_priv = dev->dev_private;
 772         bool simulated;
 773         int ret;
 774
 775         if (!i915.reset)
 776                 return 0;
 777
 778         mutex_lock(&dev->struct_mutex);
 779
 780         i915_gem_reset(dev);
 781
 782         simulated = dev_priv->gpu_error.stop_rings != 0;
 783
 784         ret = intel_gpu_reset(dev);
 785
 786         /* Also reset the gpu hangman. */
 787         if (simulated) {
 788                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 789                 dev_priv->gpu_error.stop_rings = 0;
 790                 if (ret == -ENODEV) {
 791                         DRM_INFO("Reset not implemented, but ignoring "
 792                                  "error for simulated gpu hangs\n");
 793                         ret = 0;
 794                 }
 795         }
 796
 797         if (ret) {
 798                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 799                 mutex_unlock(&dev->struct_mutex);
 800                 return ret;
 801         }
 802
 803         /* Ok, now get things going again... */
 804
 805         /*
 806          * Everything depends on having the GTT running, so we need to start
 807          * there.  Fortunately we don't need to do this unless we reset the
 808          * chip at a PCI level.
 809          *
 810          * Next we need to restore the context, but we don't use those
 811          * yet either...
 812          *
 813          * Ring buffer needs to be re-initialized in the KMS case, or if X
 814          * was running at the time of the reset (i.e. we weren't VT
 815          * switched away).
 816          */
 817         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 818                         !dev_priv->ums.mm_suspended) {
 819                 dev_priv->ums.mm_suspended = 0;
 820
 821                 ret = i915_gem_init_hw(dev);
 822                 mutex_unlock(&dev->struct_mutex);
 823                 if (ret) {
 824                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 825                         return ret;
 826                 }
 827
 828                 /*
 829                  * FIXME: This races pretty badly against concurrent holders of
 830                  * ring interrupts. This is possible since we've started to drop
 831                  * dev->struct_mutex in select places when waiting for the gpu.
 832                  */
 833
 834                 /*
 835                  * rps/rc6 re-init is necessary to restore state lost after the
 836                  * reset and the re-install of gt irqs. Skip for ironlake per
 837                  * previous concerns that it doesn't respond well to some forms
 838                  * of re-init after reset.
 839                  */
 840                 if (INTEL_INFO(dev)->gen > 5)
 841                         intel_reset_gt_powersave(dev);
 842
 843                 intel_hpd_init(dev);
 844         } else {
 845                 mutex_unlock(&dev->struct_mutex);
 846         }
 847
 848         return 0;
 849 }
 850
 851 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 852 {
 853         struct intel_device_info *intel_info =
 854                 (struct intel_device_info *) ent->driver_data;
 855
 856         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 857                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 858                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 859                 return -ENODEV;
 860         }
 861
 862         /* Only bind to function 0 of the device. Early generations
 863          * used function 1 as a placeholder for multi-head. This causes
 864          * us confusion instead, especially on the systems where both
 865          * functions have the same PCI-ID!
 866          */
 867         if (PCI_FUNC(pdev->devfn))
 868                 return -ENODEV;
 869
 870         driver.driver_features &= ~(DRIVER_USE_AGP);
 871
 872         return drm_get_pci_dev(pdev, ent, &driver);
 873 }
 874
 875 static void
 876 i915_pci_remove(struct pci_dev *pdev)
 877 {
 878         struct drm_device *dev = pci_get_drvdata(pdev);
 879
 880         drm_put_dev(dev);
 881 }
 882
 883 static int i915_pm_suspend(struct device *dev)
 884 {
 885         struct pci_dev *pdev = to_pci_dev(dev);
 886         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 887
 888         if (!drm_dev || !drm_dev->dev_private) {
 889                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 890                 return -ENODEV;
 891         }
 892
 893         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 894                 return 0;
 895
 896         return i915_drm_freeze(drm_dev);
 897 }
 898
 899 static int i915_pm_suspend_late(struct device *dev)
 900 {
 901         struct pci_dev *pdev = to_pci_dev(dev);
 902         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 903         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 904
 905         /*
 906          * We have a suspedn ordering issue with the snd-hda driver also
 907          * requiring our device to be power up. Due to the lack of a
 908          * parent/child relationship we currently solve this with an late
 909          * suspend hook.
 910          *
 911          * FIXME: This should be solved with a special hdmi sink device or
 912          * similar so that power domains can be employed.
 913          */
 914         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 915                 return 0;
 916
 917         if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev))
 918                 hsw_enable_pc8(dev_priv);
 919
 920         pci_disable_device(pdev);
 921         pci_set_power_state(pdev, PCI_D3hot);
 922
 923         return 0;
 924 }
 925
 926 static int i915_pm_resume_early(struct device *dev)
 927 {
 928         struct pci_dev *pdev = to_pci_dev(dev);
 929         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 930
 931         return i915_resume_early(drm_dev);
 932 }
 933
 934 static int i915_pm_resume(struct device *dev)
 935 {
 936         struct pci_dev *pdev = to_pci_dev(dev);
 937         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 938
 939         return i915_resume(drm_dev);
 940 }
 941
 942 static int i915_pm_freeze(struct device *dev)
 943 {
 944         struct pci_dev *pdev = to_pci_dev(dev);
 945         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 946
 947         if (!drm_dev || !drm_dev->dev_private) {
 948                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 949                 return -ENODEV;
 950         }
 951
 952         return i915_drm_freeze(drm_dev);
 953 }
 954
 955 static int i915_pm_thaw_early(struct device *dev)
 956 {
 957         struct pci_dev *pdev = to_pci_dev(dev);
 958         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 959
 960         return i915_drm_thaw_early(drm_dev);
 961 }
 962
 963 static int i915_pm_thaw(struct device *dev)
 964 {
 965         struct pci_dev *pdev = to_pci_dev(dev);
 966         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 967
 968         return i915_drm_thaw(drm_dev);
 969 }
 970
 971 static int i915_pm_poweroff(struct device *dev)
 972 {
 973         struct pci_dev *pdev = to_pci_dev(dev);
 974         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 975
 976         return i915_drm_freeze(drm_dev);
 977 }
 978
 979 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 980 {
 981         hsw_enable_pc8(dev_priv);
 982
 983         return 0;
 984 }
 985
 986 static int snb_runtime_resume(struct drm_i915_private *dev_priv)
 987 {
 988         struct drm_device *dev = dev_priv->dev;
 989
 990         intel_init_pch_refclk(dev);
 991
 992         return 0;
 993 }
 994
 995 static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
 996 {
 997         hsw_disable_pc8(dev_priv);
 998
 999         return 0;
1000 }
1001
1002 /*
1003  * Save all Gunit registers that may be lost after a D3 and a subsequent
1004  * S0i[R123] transition. The list of registers needing a save/restore is
1005  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1006  * registers in the following way:
1007  * - Driver: saved/restored by the driver
1008  * - Punit : saved/restored by the Punit firmware
1009  * - No, w/o marking: no need to save/restore, since the register is R/O or
1010  *                    used internally by the HW in a way that doesn't depend
1011  *                    keeping the content across a suspend/resume.
1012  * - Debug : used for debugging
1013  *
1014  * We save/restore all registers marked with 'Driver', with the following
1015  * exceptions:
1016  * - Registers out of use, including also registers marked with 'Debug'.
1017  *   These have no effect on the driver's operation, so we don't save/restore
1018  *   them to reduce the overhead.
1019  * - Registers that are fully setup by an initialization function called from
1020  *   the resume path. For example many clock gating and RPS/RC6 registers.
1021  * - Registers that provide the right functionality with their reset defaults.
1022  *
1023  * TODO: Except for registers that based on the above 3 criteria can be safely
1024  * ignored, we save/restore all others, practically treating the HW context as
1025  * a black-box for the driver. Further investigation is needed to reduce the
1026  * saved/restored registers even further, by following the same 3 criteria.
1027  */
1028 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1029 {
1030         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1031         int i;
1032
1033         /* GAM 0x4000-0x4770 */
1034         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1035         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1036         s->arb_mode             = I915_READ(ARB_MODE);
1037         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1038         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1039
1040         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1041                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1042
1043         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1044         s->gfx_max_req_count    = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1045
1046         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1047         s->ecochk               = I915_READ(GAM_ECOCHK);
1048         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1049         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1050
1051         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1052
1053         /* MBC 0x9024-0x91D0, 0x8500 */
1054         s->g3dctl               = I915_READ(VLV_G3DCTL);
1055         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1056         s->mbctl                = I915_READ(GEN6_MBCTL);
1057
1058         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1059         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1060         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1061         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1062         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1063         s->rstctl               = I915_READ(GEN6_RSTCTL);
1064         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1065
1066         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1067         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1068         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1069         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1070         s->ecobus               = I915_READ(ECOBUS);
1071         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1072         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1073         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1074         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1075         s->rcedata              = I915_READ(VLV_RCEDATA);
1076         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1077
1078         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1079         s->gt_imr               = I915_READ(GTIMR);
1080         s->gt_ier               = I915_READ(GTIER);
1081         s->pm_imr               = I915_READ(GEN6_PMIMR);
1082         s->pm_ier               = I915_READ(GEN6_PMIER);
1083
1084         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1085                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1086
1087         /* GT SA CZ domain, 0x100000-0x138124 */
1088         s->tilectl              = I915_READ(TILECTL);
1089         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1090         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1091         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1092         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1093
1094         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1095         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1096         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1097         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1098
1099         /*
1100          * Not saving any of:
1101          * DFT,         0x9800-0x9EC0
1102          * SARB,        0xB000-0xB1FC
1103          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1104          * PCI CFG
1105          */
1106 }
1107
1108 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1109 {
1110         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1111         u32 val;
1112         int i;
1113
1114         /* GAM 0x4000-0x4770 */
1115         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1116         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1117         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1118         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1119         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1120
1121         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1122                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1123
1124         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1125         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1126
1127         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1128         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1129         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1130         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1131
1132         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1133
1134         /* MBC 0x9024-0x91D0, 0x8500 */
1135         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1136         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1137         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1138
1139         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1140         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1141         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1142         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1143         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1144         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1145         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1146
1147         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1148         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1149         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1150         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1151         I915_WRITE(ECOBUS,              s->ecobus);
1152         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1153         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1154         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1155         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1156         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1157         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1158
1159         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1160         I915_WRITE(GTIMR,               s->gt_imr);
1161         I915_WRITE(GTIER,               s->gt_ier);
1162         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1163         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1164
1165         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1166                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1167
1168         /* GT SA CZ domain, 0x100000-0x138124 */
1169         I915_WRITE(TILECTL,                     s->tilectl);
1170         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1171         /*
1172          * Preserve the GT allow wake and GFX force clock bit, they are not
1173          * be restored, as they are used to control the s0ix suspend/resume
1174          * sequence by the caller.
1175          */
1176         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1177         val &= VLV_GTLC_ALLOWWAKEREQ;
1178         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1179         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1180
1181         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1182         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1183         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1184         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1185
1186         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1187
1188         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1189         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1190         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1191         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1192 }
1193
1194 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1195 {
1196         u32 val;
1197         int err;
1198
1199         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1200         WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1201
1202 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1203         /* Wait for a previous force-off to settle */
1204         if (force_on) {
1205                 err = wait_for(!COND, 20);
1206                 if (err) {
1207                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1208                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1209                         return err;
1210                 }
1211         }
1212
1213         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1214         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1215         if (force_on)
1216                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1217         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1218
1219         if (!force_on)
1220                 return 0;
1221
1222         err = wait_for(COND, 20);
1223         if (err)
1224                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1225                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1226
1227         return err;
1228 #undef COND
1229 }
1230
1231 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1232 {
1233         u32 val;
1234         int err = 0;
1235
1236         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1237         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1238         if (allow)
1239                 val |= VLV_GTLC_ALLOWWAKEREQ;
1240         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1241         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1242
1243 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1244               allow)
1245         err = wait_for(COND, 1);
1246         if (err)
1247                 DRM_ERROR("timeout disabling GT waking\n");
1248         return err;
1249 #undef COND
1250 }
1251
1252 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1253                                  bool wait_for_on)
1254 {
1255         u32 mask;
1256         u32 val;
1257         int err;
1258
1259         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1260         val = wait_for_on ? mask : 0;
1261 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1262         if (COND)
1263                 return 0;
1264
1265         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1266                         wait_for_on ? "on" : "off",
1267                         I915_READ(VLV_GTLC_PW_STATUS));
1268
1269         /*
1270          * RC6 transitioning can be delayed up to 2 msec (see
1271          * valleyview_enable_rps), use 3 msec for safety.
1272          */
1273         err = wait_for(COND, 3);
1274         if (err)
1275                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1276                           wait_for_on ? "on" : "off");
1277
1278         return err;
1279 #undef COND
1280 }
1281
1282 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1283 {
1284         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1285                 return;
1286
1287         DRM_ERROR("GT register access while GT waking disabled\n");
1288         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1289 }
1290
1291 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1292 {
1293         u32 mask;
1294         int err;
1295
1296         /*
1297          * Bspec defines the following GT well on flags as debug only, so
1298          * don't treat them as hard failures.
1299          */
1300         (void)vlv_wait_for_gt_wells(dev_priv, false);
1301
1302         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1303         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1304
1305         vlv_check_no_gt_access(dev_priv);
1306
1307         err = vlv_force_gfx_clock(dev_priv, true);
1308         if (err)
1309                 goto err1;
1310
1311         err = vlv_allow_gt_wake(dev_priv, false);
1312         if (err)
1313                 goto err2;
1314         vlv_save_gunit_s0ix_state(dev_priv);
1315
1316         err = vlv_force_gfx_clock(dev_priv, false);
1317         if (err)
1318                 goto err2;
1319
1320         return 0;
1321
1322 err2:
1323         /* For safety always re-enable waking and disable gfx clock forcing */
1324         vlv_allow_gt_wake(dev_priv, true);
1325 err1:
1326         vlv_force_gfx_clock(dev_priv, false);
1327
1328         return err;
1329 }
1330
1331 static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1332 {
1333         struct drm_device *dev = dev_priv->dev;
1334         int err;
1335         int ret;
1336
1337         /*
1338          * If any of the steps fail just try to continue, that's the best we
1339          * can do at this point. Return the first error code (which will also
1340          * leave RPM permanently disabled).
1341          */
1342         ret = vlv_force_gfx_clock(dev_priv, true);
1343
1344         vlv_restore_gunit_s0ix_state(dev_priv);
1345
1346         err = vlv_allow_gt_wake(dev_priv, true);
1347         if (!ret)
1348                 ret = err;
1349
1350         err = vlv_force_gfx_clock(dev_priv, false);
1351         if (!ret)
1352                 ret = err;
1353
1354         vlv_check_no_gt_access(dev_priv);
1355
1356         intel_init_clock_gating(dev);
1357         i915_gem_restore_fences(dev);
1358
1359         return ret;
1360 }
1361
1362 static int intel_runtime_suspend(struct device *device)
1363 {
1364         struct pci_dev *pdev = to_pci_dev(device);
1365         struct drm_device *dev = pci_get_drvdata(pdev);
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         int ret;
1368
1369         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1370                 return -ENODEV;
1371
1372         WARN_ON(!HAS_RUNTIME_PM(dev));
1373         assert_force_wake_inactive(dev_priv);
1374
1375         DRM_DEBUG_KMS("Suspending device\n");
1376
1377         /*
1378          * We could deadlock here in case another thread holding struct_mutex
1379          * calls RPM suspend concurrently, since the RPM suspend will wait
1380          * first for this RPM suspend to finish. In this case the concurrent
1381          * RPM resume will be followed by its RPM suspend counterpart. Still
1382          * for consistency return -EAGAIN, which will reschedule this suspend.
1383          */
1384         if (!mutex_trylock(&dev->struct_mutex)) {
1385                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1386                 /*
1387                  * Bump the expiration timestamp, otherwise the suspend won't
1388                  * be rescheduled.
1389                  */
1390                 pm_runtime_mark_last_busy(device);
1391
1392                 return -EAGAIN;
1393         }
1394         /*
1395          * We are safe here against re-faults, since the fault handler takes
1396          * an RPM reference.
1397          */
1398         i915_gem_release_all_mmaps(dev_priv);
1399         mutex_unlock(&dev->struct_mutex);
1400
1401         /*
1402          * rps.work can't be rearmed here, since we get here only after making
1403          * sure the GPU is idle and the RPS freq is set to the minimum. See
1404          * intel_mark_idle().
1405          */
1406         cancel_work_sync(&dev_priv->rps.work);
1407         intel_runtime_pm_disable_interrupts(dev);
1408
1409         if (IS_GEN6(dev)) {
1410                 ret = 0;
1411         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1412                 ret = hsw_runtime_suspend(dev_priv);
1413         } else if (IS_VALLEYVIEW(dev)) {
1414                 ret = vlv_runtime_suspend(dev_priv);
1415         } else {
1416                 ret = -ENODEV;
1417                 WARN_ON(1);
1418         }
1419
1420         if (ret) {
1421                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1422                 intel_runtime_pm_restore_interrupts(dev);
1423
1424                 return ret;
1425         }
1426
1427         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1428         dev_priv->pm.suspended = true;
1429
1430         /*
1431          * current versions of firmware which depend on this opregion
1432          * notification have repurposed the D1 definition to mean
1433          * "runtime suspended" vs. what you would normally expect (D3)
1434          * to distinguish it from notifications that might be sent
1435          * via the suspend path.
1436          */
1437         intel_opregion_notify_adapter(dev, PCI_D1);
1438
1439         DRM_DEBUG_KMS("Device suspended\n");
1440         return 0;
1441 }
1442
1443 static int intel_runtime_resume(struct device *device)
1444 {
1445         struct pci_dev *pdev = to_pci_dev(device);
1446         struct drm_device *dev = pci_get_drvdata(pdev);
1447         struct drm_i915_private *dev_priv = dev->dev_private;
1448         int ret;
1449
1450         WARN_ON(!HAS_RUNTIME_PM(dev));
1451
1452         DRM_DEBUG_KMS("Resuming device\n");
1453
1454         intel_opregion_notify_adapter(dev, PCI_D0);
1455         dev_priv->pm.suspended = false;
1456
1457         if (IS_GEN6(dev)) {
1458                 ret = snb_runtime_resume(dev_priv);
1459         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1460                 ret = hsw_runtime_resume(dev_priv);
1461         } else if (IS_VALLEYVIEW(dev)) {
1462                 ret = vlv_runtime_resume(dev_priv);
1463         } else {
1464                 WARN_ON(1);
1465                 ret = -ENODEV;
1466         }
1467
1468         /*
1469          * No point of rolling back things in case of an error, as the best
1470          * we can do is to hope that things will still work (and disable RPM).
1471          */
1472         i915_gem_init_swizzling(dev);
1473         gen6_update_ring_freq(dev);
1474
1475         intel_runtime_pm_restore_interrupts(dev);
1476         intel_reset_gt_powersave(dev);
1477
1478         if (ret)
1479                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1480         else
1481                 DRM_DEBUG_KMS("Device resumed\n");
1482
1483         return ret;
1484 }
1485
1486 static const struct dev_pm_ops i915_pm_ops = {
1487         .suspend = i915_pm_suspend,
1488         .suspend_late = i915_pm_suspend_late,
1489         .resume_early = i915_pm_resume_early,
1490         .resume = i915_pm_resume,
1491         .freeze = i915_pm_freeze,
1492         .thaw_early = i915_pm_thaw_early,
1493         .thaw = i915_pm_thaw,
1494         .poweroff = i915_pm_poweroff,
1495         .restore_early = i915_pm_resume_early,
1496         .restore = i915_pm_resume,
1497         .runtime_suspend = intel_runtime_suspend,
1498         .runtime_resume = intel_runtime_resume,
1499 };
1500
1501 static const struct vm_operations_struct i915_gem_vm_ops = {
1502         .fault = i915_gem_fault,
1503         .open = drm_gem_vm_open,
1504         .close = drm_gem_vm_close,
1505 };
1506
1507 static const struct file_operations i915_driver_fops = {
1508         .owner = THIS_MODULE,
1509         .open = drm_open,
1510         .release = drm_release,
1511         .unlocked_ioctl = drm_ioctl,
1512         .mmap = drm_gem_mmap,
1513         .poll = drm_poll,
1514         .read = drm_read,
1515 #ifdef CONFIG_COMPAT
1516         .compat_ioctl = i915_compat_ioctl,
1517 #endif
1518         .llseek = noop_llseek,
1519 };
1520
1521 static struct drm_driver driver = {
1522         /* Don't use MTRRs here; the Xserver or userspace app should
1523          * deal with them for Intel hardware.
1524          */
1525         .driver_features =
1526             DRIVER_USE_AGP |
1527             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1528             DRIVER_RENDER,
1529         .load = i915_driver_load,
1530         .unload = i915_driver_unload,
1531         .open = i915_driver_open,
1532         .lastclose = i915_driver_lastclose,
1533         .preclose = i915_driver_preclose,
1534         .postclose = i915_driver_postclose,
1535
1536         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1537         .suspend = i915_suspend,
1538         .resume = i915_resume_legacy,
1539
1540         .device_is_agp = i915_driver_device_is_agp,
1541         .master_create = i915_master_create,
1542         .master_destroy = i915_master_destroy,
1543 #if defined(CONFIG_DEBUG_FS)
1544         .debugfs_init = i915_debugfs_init,
1545         .debugfs_cleanup = i915_debugfs_cleanup,
1546 #endif
1547         .gem_free_object = i915_gem_free_object,
1548         .gem_vm_ops = &i915_gem_vm_ops,
1549
1550         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1551         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1552         .gem_prime_export = i915_gem_prime_export,
1553         .gem_prime_import = i915_gem_prime_import,
1554
1555         .dumb_create = i915_gem_dumb_create,
1556         .dumb_map_offset = i915_gem_mmap_gtt,
1557         .dumb_destroy = drm_gem_dumb_destroy,
1558         .ioctls = i915_ioctls,
1559         .fops = &i915_driver_fops,
1560         .name = DRIVER_NAME,
1561         .desc = DRIVER_DESC,
1562         .date = DRIVER_DATE,
1563         .major = DRIVER_MAJOR,
1564         .minor = DRIVER_MINOR,
1565         .patchlevel = DRIVER_PATCHLEVEL,
1566 };
1567
1568 static struct pci_driver i915_pci_driver = {
1569         .name = DRIVER_NAME,
1570         .id_table = pciidlist,
1571         .probe = i915_pci_probe,
1572         .remove = i915_pci_remove,
1573         .driver.pm = &i915_pm_ops,
1574 };
1575
1576 static int __init i915_init(void)
1577 {
1578         driver.num_ioctls = i915_max_ioctl;
1579
1580         /*
1581          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1582          * explicitly disabled with the module pararmeter.
1583          *
1584          * Otherwise, just follow the parameter (defaulting to off).
1585          *
1586          * Allow optional vga_text_mode_force boot option to override
1587          * the default behavior.
1588          */
1589 #if defined(CONFIG_DRM_I915_KMS)
1590         if (i915.modeset != 0)
1591                 driver.driver_features |= DRIVER_MODESET;
1592 #endif
1593         if (i915.modeset == 1)
1594                 driver.driver_features |= DRIVER_MODESET;
1595
1596 #ifdef CONFIG_VGA_CONSOLE
1597         if (vgacon_text_force() && i915.modeset == -1)
1598                 driver.driver_features &= ~DRIVER_MODESET;
1599 #endif
1600
1601         if (!(driver.driver_features & DRIVER_MODESET)) {
1602                 driver.get_vblank_timestamp = NULL;
1603 #ifndef CONFIG_DRM_I915_UMS
1604                 /* Silently fail loading to not upset userspace. */
1605                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1606                 return 0;
1607 #endif
1608         }
1609
1610         return drm_pci_init(&driver, &i915_pci_driver);
1611 }
1612
1613 static void __exit i915_exit(void)
1614 {
1615 #ifndef CONFIG_DRM_I915_UMS
1616         if (!(driver.driver_features & DRIVER_MODESET))
1617                 return; /* Never loaded a driver. */
1618 #endif
1619
1620         drm_pci_exit(&driver, &i915_pci_driver);
1621 }
1622
1623 module_init(i915_init);
1624 module_exit(i915_exit);
1625
1626 MODULE_AUTHOR(DRIVER_AUTHOR);
1627 MODULE_DESCRIPTION(DRIVER_DESC);
1628 MODULE_LICENSE("GPL and additional rights");