drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. (default: false)");
 125
 126 int i915_disable_power_well __read_mostly = 0;
 127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 128 MODULE_PARM_DESC(disable_power_well,
 129                  "Disable the power well when possible (default: false)");
 130
 131 static struct drm_driver driver;
 132 extern int intel_agp_enabled;
 133
 134 #define INTEL_VGA_DEVICE(id, info) {            \
 135         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 136         .class_mask = 0xff0000,                 \
 137         .vendor = 0x8086,                       \
 138         .device = id,                           \
 139         .subvendor = PCI_ANY_ID,                \
 140         .subdevice = PCI_ANY_ID,                \
 141         .driver_data = (unsigned long) info }
 142
 143 #define INTEL_QUANTA_VGA_DEVICE(info) {         \
 144         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 145         .class_mask = 0xff0000,                 \
 146         .vendor = 0x8086,                       \
 147         .device = 0x16a,                        \
 148         .subvendor = 0x152d,                    \
 149         .subdevice = 0x8990,                    \
 150         .driver_data = (unsigned long) info }
 151
 152
 153 static const struct intel_device_info intel_i830_info = {
 154         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 155         .has_overlay = 1, .overlay_needs_physical = 1,
 156 };
 157
 158 static const struct intel_device_info intel_845g_info = {
 159         .gen = 2, .num_pipes = 1,
 160         .has_overlay = 1, .overlay_needs_physical = 1,
 161 };
 162
 163 static const struct intel_device_info intel_i85x_info = {
 164         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 165         .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168
 169 static const struct intel_device_info intel_i865g_info = {
 170         .gen = 2, .num_pipes = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172 };
 173
 174 static const struct intel_device_info intel_i915g_info = {
 175         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 176         .has_overlay = 1, .overlay_needs_physical = 1,
 177 };
 178 static const struct intel_device_info intel_i915gm_info = {
 179         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 180         .cursor_needs_physical = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .supports_tv = 1,
 183 };
 184 static const struct intel_device_info intel_i945g_info = {
 185         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 186         .has_overlay = 1, .overlay_needs_physical = 1,
 187 };
 188 static const struct intel_device_info intel_i945gm_info = {
 189         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 190         .has_hotplug = 1, .cursor_needs_physical = 1,
 191         .has_overlay = 1, .overlay_needs_physical = 1,
 192         .supports_tv = 1,
 193 };
 194
 195 static const struct intel_device_info intel_i965g_info = {
 196         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 197         .has_hotplug = 1,
 198         .has_overlay = 1,
 199 };
 200
 201 static const struct intel_device_info intel_i965gm_info = {
 202         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 203         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 204         .has_overlay = 1,
 205         .supports_tv = 1,
 206 };
 207
 208 static const struct intel_device_info intel_g33_info = {
 209         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_g45_info = {
 215         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 216         .has_pipe_cxsr = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218 };
 219
 220 static const struct intel_device_info intel_gm45_info = {
 221         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 222         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 223         .has_pipe_cxsr = 1, .has_hotplug = 1,
 224         .supports_tv = 1,
 225         .has_bsd_ring = 1,
 226 };
 227
 228 static const struct intel_device_info intel_pineview_info = {
 229         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 230         .need_gfx_hws = 1, .has_hotplug = 1,
 231         .has_overlay = 1,
 232 };
 233
 234 static const struct intel_device_info intel_ironlake_d_info = {
 235         .gen = 5, .num_pipes = 2,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238 };
 239
 240 static const struct intel_device_info intel_ironlake_m_info = {
 241         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 242         .need_gfx_hws = 1, .has_hotplug = 1,
 243         .has_fbc = 1,
 244         .has_bsd_ring = 1,
 245 };
 246
 247 static const struct intel_device_info intel_sandybridge_d_info = {
 248         .gen = 6, .num_pipes = 2,
 249         .need_gfx_hws = 1, .has_hotplug = 1,
 250         .has_bsd_ring = 1,
 251         .has_blt_ring = 1,
 252         .has_llc = 1,
 253         .has_force_wake = 1,
 254 };
 255
 256 static const struct intel_device_info intel_sandybridge_m_info = {
 257         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 258         .need_gfx_hws = 1, .has_hotplug = 1,
 259         .has_fbc = 1,
 260         .has_bsd_ring = 1,
 261         .has_blt_ring = 1,
 262         .has_llc = 1,
 263         .has_force_wake = 1,
 264 };
 265
 266 #define GEN7_FEATURES  \
 267         .gen = 7, .num_pipes = 3, \
 268         .need_gfx_hws = 1, .has_hotplug = 1, \
 269         .has_bsd_ring = 1, \
 270         .has_blt_ring = 1, \
 271         .has_llc = 1, \
 272         .has_force_wake = 1
 273
 274 static const struct intel_device_info intel_ivybridge_d_info = {
 275         GEN7_FEATURES,
 276         .is_ivybridge = 1,
 277 };
 278
 279 static const struct intel_device_info intel_ivybridge_m_info = {
 280         GEN7_FEATURES,
 281         .is_ivybridge = 1,
 282         .is_mobile = 1,
 283 };
 284
 285 static const struct intel_device_info intel_ivybridge_q_info = {
 286         GEN7_FEATURES,
 287         .is_ivybridge = 1,
 288         .num_pipes = 0, /* legal, last one wins */
 289 };
 290
 291 static const struct intel_device_info intel_valleyview_m_info = {
 292         GEN7_FEATURES,
 293         .is_mobile = 1,
 294         .num_pipes = 2,
 295         .is_valleyview = 1,
 296         .display_mmio_offset = VLV_DISPLAY_BASE,
 297 };
 298
 299 static const struct intel_device_info intel_valleyview_d_info = {
 300         GEN7_FEATURES,
 301         .num_pipes = 2,
 302         .is_valleyview = 1,
 303         .display_mmio_offset = VLV_DISPLAY_BASE,
 304 };
 305
 306 static const struct intel_device_info intel_haswell_d_info = {
 307         GEN7_FEATURES,
 308         .is_haswell = 1,
 309 };
 310
 311 static const struct intel_device_info intel_haswell_m_info = {
 312         GEN7_FEATURES,
 313         .is_haswell = 1,
 314         .is_mobile = 1,
 315 };
 316
 317 static const struct pci_device_id pciidlist[] = {               /* aka */
 318         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 319         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 320         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 321         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 322         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 323         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 324         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 325         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 326         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 327         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 328         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 329         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 330         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 331         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 332         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 333         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 334         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 335         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 336         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 337         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 338         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 339         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 340         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 341         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 342         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 343         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 344         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 345         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 346         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 347         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 348         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 349         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 350         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 351         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 352         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 353         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 354         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 355         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 356         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 357         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 358         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 359         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 360         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 361         INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
 362         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 363         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 364         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 365         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 366         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 367         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 368         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 369         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 370         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 371         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 372         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 373         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 374         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 375         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 376         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 377         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 378         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 379         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 380         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 381         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 382         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 383         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 384         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 385         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 386         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 387         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 388         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 389         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 390         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 391         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 392         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 393         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 394         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 395         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 396         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 397         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 398         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 399         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 400         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
 401         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
 402         INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 403         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 404         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 405         {0, 0, 0}
 406 };
 407
 408 #if defined(CONFIG_DRM_I915_KMS)
 409 MODULE_DEVICE_TABLE(pci, pciidlist);
 410 #endif
 411
 412 void intel_detect_pch(struct drm_device *dev)
 413 {
 414         struct drm_i915_private *dev_priv = dev->dev_private;
 415         struct pci_dev *pch;
 416
 417         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 418          * (which really amounts to a PCH but no South Display).
 419          */
 420         if (INTEL_INFO(dev)->num_pipes == 0) {
 421                 dev_priv->pch_type = PCH_NOP;
 422                 dev_priv->num_pch_pll = 0;
 423                 return;
 424         }
 425
 426         /*
 427          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 428          * make graphics device passthrough work easy for VMM, that only
 429          * need to expose ISA bridge to let driver know the real hardware
 430          * underneath. This is a requirement from virtualization team.
 431          */
 432         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 433         if (pch) {
 434                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 435                         unsigned short id;
 436                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 437                         dev_priv->pch_id = id;
 438
 439                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 440                                 dev_priv->pch_type = PCH_IBX;
 441                                 dev_priv->num_pch_pll = 2;
 442                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 443                                 WARN_ON(!IS_GEN5(dev));
 444                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 445                                 dev_priv->pch_type = PCH_CPT;
 446                                 dev_priv->num_pch_pll = 2;
 447                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 448                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 449                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 450                                 /* PantherPoint is CPT compatible */
 451                                 dev_priv->pch_type = PCH_CPT;
 452                                 dev_priv->num_pch_pll = 2;
 453                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 454                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 455                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 456                                 dev_priv->pch_type = PCH_LPT;
 457                                 dev_priv->num_pch_pll = 0;
 458                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 459                                 WARN_ON(!IS_HASWELL(dev));
 460                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 461                                 dev_priv->pch_type = PCH_LPT;
 462                                 dev_priv->num_pch_pll = 0;
 463                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 464                                 WARN_ON(!IS_HASWELL(dev));
 465                         }
 466                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 467                 }
 468                 pci_dev_put(pch);
 469         }
 470 }
 471
 472 bool i915_semaphore_is_enabled(struct drm_device *dev)
 473 {
 474         if (INTEL_INFO(dev)->gen < 6)
 475                 return 0;
 476
 477         if (i915_semaphores >= 0)
 478                 return i915_semaphores;
 479
 480 #ifdef CONFIG_INTEL_IOMMU
 481         /* Enable semaphores on SNB when IO remapping is off */
 482         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 483                 return false;
 484 #endif
 485
 486         return 1;
 487 }
 488
 489 static int i915_drm_freeze(struct drm_device *dev)
 490 {
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         struct drm_crtc *crtc;
 493
 494         /* ignore lid events during suspend */
 495         mutex_lock(&dev_priv->modeset_restore_lock);
 496         dev_priv->modeset_restore = MODESET_SUSPENDED;
 497         mutex_unlock(&dev_priv->modeset_restore_lock);
 498
 499         intel_set_power_well(dev, true);
 500
 501         drm_kms_helper_poll_disable(dev);
 502
 503         pci_save_state(dev->pdev);
 504
 505         /* If KMS is active, we do the leavevt stuff here */
 506         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 507                 int error = i915_gem_idle(dev);
 508                 if (error) {
 509                         dev_err(&dev->pdev->dev,
 510                                 "GEM idle failed, resume might fail\n");
 511                         return error;
 512                 }
 513
 514                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 515
 516                 drm_irq_uninstall(dev);
 517                 dev_priv->enable_hotplug_processing = false;
 518                 /*
 519                  * Disable CRTCs directly since we want to preserve sw state
 520                  * for _thaw.
 521                  */
 522                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 523                         dev_priv->display.crtc_disable(crtc);
 524         }
 525
 526         i915_save_state(dev);
 527
 528         intel_opregion_fini(dev);
 529
 530         console_lock();
 531         intel_fbdev_set_suspend(dev, 1);
 532         console_unlock();
 533
 534         return 0;
 535 }
 536
 537 int i915_suspend(struct drm_device *dev, pm_message_t state)
 538 {
 539         int error;
 540
 541         if (!dev || !dev->dev_private) {
 542                 DRM_ERROR("dev: %p\n", dev);
 543                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 544                 return -ENODEV;
 545         }
 546
 547         if (state.event == PM_EVENT_PRETHAW)
 548                 return 0;
 549
 550
 551         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 552                 return 0;
 553
 554         error = i915_drm_freeze(dev);
 555         if (error)
 556                 return error;
 557
 558         if (state.event == PM_EVENT_SUSPEND) {
 559                 /* Shut down the device */
 560                 pci_disable_device(dev->pdev);
 561                 pci_set_power_state(dev->pdev, PCI_D3hot);
 562         }
 563
 564         return 0;
 565 }
 566
 567 void intel_console_resume(struct work_struct *work)
 568 {
 569         struct drm_i915_private *dev_priv =
 570                 container_of(work, struct drm_i915_private,
 571                              console_resume_work);
 572         struct drm_device *dev = dev_priv->dev;
 573
 574         console_lock();
 575         intel_fbdev_set_suspend(dev, 0);
 576         console_unlock();
 577 }
 578
 579 static void intel_resume_hotplug(struct drm_device *dev)
 580 {
 581         struct drm_mode_config *mode_config = &dev->mode_config;
 582         struct intel_encoder *encoder;
 583
 584         mutex_lock(&mode_config->mutex);
 585         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 586
 587         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 588                 if (encoder->hot_plug)
 589                         encoder->hot_plug(encoder);
 590
 591         mutex_unlock(&mode_config->mutex);
 592
 593         /* Just fire off a uevent and let userspace tell us what to do */
 594         drm_helper_hpd_irq_event(dev);
 595 }
 596
 597 static int __i915_drm_thaw(struct drm_device *dev)
 598 {
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         int error = 0;
 601
 602         i915_restore_state(dev);
 603         intel_opregion_setup(dev);
 604
 605         /* KMS EnterVT equivalent */
 606         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 607                 intel_init_pch_refclk(dev);
 608
 609                 mutex_lock(&dev->struct_mutex);
 610                 dev_priv->mm.suspended = 0;
 611
 612                 error = i915_gem_init_hw(dev);
 613                 mutex_unlock(&dev->struct_mutex);
 614
 615                 /* We need working interrupts for modeset enabling ... */
 616                 drm_irq_install(dev);
 617
 618                 intel_modeset_init_hw(dev);
 619
 620                 drm_modeset_lock_all(dev);
 621                 intel_modeset_setup_hw_state(dev, true);
 622                 drm_modeset_unlock_all(dev);
 623
 624                 /*
 625                  * ... but also need to make sure that hotplug processing
 626                  * doesn't cause havoc. Like in the driver load code we don't
 627                  * bother with the tiny race here where we might loose hotplug
 628                  * notifications.
 629                  * */
 630                 intel_hpd_init(dev);
 631                 dev_priv->enable_hotplug_processing = true;
 632                 /* Config may have changed between suspend and resume */
 633                 intel_resume_hotplug(dev);
 634         }
 635
 636         intel_opregion_init(dev);
 637
 638         /*
 639          * The console lock can be pretty contented on resume due
 640          * to all the printk activity.  Try to keep it out of the hot
 641          * path of resume if possible.
 642          */
 643         if (console_trylock()) {
 644                 intel_fbdev_set_suspend(dev, 0);
 645                 console_unlock();
 646         } else {
 647                 schedule_work(&dev_priv->console_resume_work);
 648         }
 649
 650         mutex_lock(&dev_priv->modeset_restore_lock);
 651         dev_priv->modeset_restore = MODESET_DONE;
 652         mutex_unlock(&dev_priv->modeset_restore_lock);
 653         return error;
 654 }
 655
 656 static int i915_drm_thaw(struct drm_device *dev)
 657 {
 658         int error = 0;
 659
 660         intel_gt_reset(dev);
 661
 662         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 663                 mutex_lock(&dev->struct_mutex);
 664                 i915_gem_restore_gtt_mappings(dev);
 665                 mutex_unlock(&dev->struct_mutex);
 666         }
 667
 668         __i915_drm_thaw(dev);
 669
 670         return error;
 671 }
 672
 673 int i915_resume(struct drm_device *dev)
 674 {
 675         struct drm_i915_private *dev_priv = dev->dev_private;
 676         int ret;
 677
 678         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 679                 return 0;
 680
 681         if (pci_enable_device(dev->pdev))
 682                 return -EIO;
 683
 684         pci_set_master(dev->pdev);
 685
 686         intel_gt_reset(dev);
 687
 688         /*
 689          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 690          * earlier) need this since the BIOS might clear all our scratch PTEs.
 691          */
 692         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 693             !dev_priv->opregion.header) {
 694                 mutex_lock(&dev->struct_mutex);
 695                 i915_gem_restore_gtt_mappings(dev);
 696                 mutex_unlock(&dev->struct_mutex);
 697         }
 698
 699         ret = __i915_drm_thaw(dev);
 700         if (ret)
 701                 return ret;
 702
 703         drm_kms_helper_poll_enable(dev);
 704         return 0;
 705 }
 706
 707 static int i8xx_do_reset(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710
 711         if (IS_I85X(dev))
 712                 return -ENODEV;
 713
 714         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 715         POSTING_READ(D_STATE);
 716
 717         if (IS_I830(dev) || IS_845G(dev)) {
 718                 I915_WRITE(DEBUG_RESET_I830,
 719                            DEBUG_RESET_DISPLAY |
 720                            DEBUG_RESET_RENDER |
 721                            DEBUG_RESET_FULL);
 722                 POSTING_READ(DEBUG_RESET_I830);
 723                 msleep(1);
 724
 725                 I915_WRITE(DEBUG_RESET_I830, 0);
 726                 POSTING_READ(DEBUG_RESET_I830);
 727         }
 728
 729         msleep(1);
 730
 731         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 732         POSTING_READ(D_STATE);
 733
 734         return 0;
 735 }
 736
 737 static int i965_reset_complete(struct drm_device *dev)
 738 {
 739         u8 gdrst;
 740         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 741         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 742 }
 743
 744 static int i965_do_reset(struct drm_device *dev)
 745 {
 746         int ret;
 747         u8 gdrst;
 748
 749         /*
 750          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 751          * well as the reset bit (GR/bit 0).  Setting the GR bit
 752          * triggers the reset; when done, the hardware will clear it.
 753          */
 754         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 755         pci_write_config_byte(dev->pdev, I965_GDRST,
 756                               gdrst | GRDOM_RENDER |
 757                               GRDOM_RESET_ENABLE);
 758         ret =  wait_for(i965_reset_complete(dev), 500);
 759         if (ret)
 760                 return ret;
 761
 762         /* We can't reset render&media without also resetting display ... */
 763         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 764         pci_write_config_byte(dev->pdev, I965_GDRST,
 765                               gdrst | GRDOM_MEDIA |
 766                               GRDOM_RESET_ENABLE);
 767
 768         return wait_for(i965_reset_complete(dev), 500);
 769 }
 770
 771 static int ironlake_do_reset(struct drm_device *dev)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         u32 gdrst;
 775         int ret;
 776
 777         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 778         gdrst &= ~GRDOM_MASK;
 779         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 780                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 781         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 782         if (ret)
 783                 return ret;
 784
 785         /* We can't reset render&media without also resetting display ... */
 786         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 787         gdrst &= ~GRDOM_MASK;
 788         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 789                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 790         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 791 }
 792
 793 static int gen6_do_reset(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         int     ret;
 797         unsigned long irqflags;
 798
 799         /* Hold gt_lock across reset to prevent any register access
 800          * with forcewake not set correctly
 801          */
 802         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 803
 804         /* Reset the chip */
 805
 806         /* GEN6_GDRST is not in the gt power well, no need to check
 807          * for fifo space for the write or forcewake the chip for
 808          * the read
 809          */
 810         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 811
 812         /* Spin waiting for the device to ack the reset request */
 813         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 814
 815         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 816         if (dev_priv->forcewake_count)
 817                 dev_priv->gt.force_wake_get(dev_priv);
 818         else
 819                 dev_priv->gt.force_wake_put(dev_priv);
 820
 821         /* Restore fifo count */
 822         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 823
 824         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 825         return ret;
 826 }
 827
 828 int intel_gpu_reset(struct drm_device *dev)
 829 {
 830         struct drm_i915_private *dev_priv = dev->dev_private;
 831         int ret = -ENODEV;
 832
 833         switch (INTEL_INFO(dev)->gen) {
 834         case 7:
 835         case 6:
 836                 ret = gen6_do_reset(dev);
 837                 break;
 838         case 5:
 839                 ret = ironlake_do_reset(dev);
 840                 break;
 841         case 4:
 842                 ret = i965_do_reset(dev);
 843                 break;
 844         case 2:
 845                 ret = i8xx_do_reset(dev);
 846                 break;
 847         }
 848
 849         /* Also reset the gpu hangman. */
 850         if (dev_priv->gpu_error.stop_rings) {
 851                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 852                 dev_priv->gpu_error.stop_rings = 0;
 853                 if (ret == -ENODEV) {
 854                         DRM_ERROR("Reset not implemented, but ignoring "
 855                                   "error for simulated gpu hangs\n");
 856                         ret = 0;
 857                 }
 858         }
 859
 860         return ret;
 861 }
 862
 863 /**
 864  * i915_reset - reset chip after a hang
 865  * @dev: drm device to reset
 866  *
 867  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 868  * reset or otherwise an error code.
 869  *
 870  * Procedure is fairly simple:
 871  *   - reset the chip using the reset reg
 872  *   - re-init context state
 873  *   - re-init hardware status page
 874  *   - re-init ring buffer
 875  *   - re-init interrupt state
 876  *   - re-init display
 877  */
 878 int i915_reset(struct drm_device *dev)
 879 {
 880         drm_i915_private_t *dev_priv = dev->dev_private;
 881         int ret;
 882
 883         if (!i915_try_reset)
 884                 return 0;
 885
 886         mutex_lock(&dev->struct_mutex);
 887
 888         i915_gem_reset(dev);
 889
 890         ret = -ENODEV;
 891         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 892                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 893         else
 894                 ret = intel_gpu_reset(dev);
 895
 896         dev_priv->gpu_error.last_reset = get_seconds();
 897         if (ret) {
 898                 DRM_ERROR("Failed to reset chip.\n");
 899                 mutex_unlock(&dev->struct_mutex);
 900                 return ret;
 901         }
 902
 903         /* Ok, now get things going again... */
 904
 905         /*
 906          * Everything depends on having the GTT running, so we need to start
 907          * there.  Fortunately we don't need to do this unless we reset the
 908          * chip at a PCI level.
 909          *
 910          * Next we need to restore the context, but we don't use those
 911          * yet either...
 912          *
 913          * Ring buffer needs to be re-initialized in the KMS case, or if X
 914          * was running at the time of the reset (i.e. we weren't VT
 915          * switched away).
 916          */
 917         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 918                         !dev_priv->mm.suspended) {
 919                 struct intel_ring_buffer *ring;
 920                 int i;
 921
 922                 dev_priv->mm.suspended = 0;
 923
 924                 i915_gem_init_swizzling(dev);
 925
 926                 for_each_ring(ring, dev_priv, i)
 927                         ring->init(ring);
 928
 929                 i915_gem_context_init(dev);
 930                 i915_gem_init_ppgtt(dev);
 931
 932                 /*
 933                  * It would make sense to re-init all the other hw state, at
 934                  * least the rps/rc6/emon init done within modeset_init_hw. For
 935                  * some unknown reason, this blows up my ilk, so don't.
 936                  */
 937
 938                 mutex_unlock(&dev->struct_mutex);
 939
 940                 drm_irq_uninstall(dev);
 941                 drm_irq_install(dev);
 942                 intel_hpd_init(dev);
 943         } else {
 944                 mutex_unlock(&dev->struct_mutex);
 945         }
 946
 947         return 0;
 948 }
 949
 950 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 951 {
 952         struct intel_device_info *intel_info =
 953                 (struct intel_device_info *) ent->driver_data;
 954
 955         if (intel_info->is_valleyview)
 956                 if(!i915_preliminary_hw_support) {
 957                         DRM_ERROR("Preliminary hardware support disabled\n");
 958                         return -ENODEV;
 959                 }
 960
 961         /* Only bind to function 0 of the device. Early generations
 962          * used function 1 as a placeholder for multi-head. This causes
 963          * us confusion instead, especially on the systems where both
 964          * functions have the same PCI-ID!
 965          */
 966         if (PCI_FUNC(pdev->devfn))
 967                 return -ENODEV;
 968
 969         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 970          * implementation for gen3 (and only gen3) that used legacy drm maps
 971          * (gasp!) to share buffers between X and the client. Hence we need to
 972          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 973         if (intel_info->gen != 3) {
 974                 driver.driver_features &=
 975                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 976         } else if (!intel_agp_enabled) {
 977                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 978                 return -ENODEV;
 979         }
 980
 981         return drm_get_pci_dev(pdev, ent, &driver);
 982 }
 983
 984 static void
 985 i915_pci_remove(struct pci_dev *pdev)
 986 {
 987         struct drm_device *dev = pci_get_drvdata(pdev);
 988
 989         drm_put_dev(dev);
 990 }
 991
 992 static int i915_pm_suspend(struct device *dev)
 993 {
 994         struct pci_dev *pdev = to_pci_dev(dev);
 995         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 996         int error;
 997
 998         if (!drm_dev || !drm_dev->dev_private) {
 999                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1000                 return -ENODEV;
1001         }
1002
1003         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1004                 return 0;
1005
1006         error = i915_drm_freeze(drm_dev);
1007         if (error)
1008                 return error;
1009
1010         pci_disable_device(pdev);
1011         pci_set_power_state(pdev, PCI_D3hot);
1012
1013         return 0;
1014 }
1015
1016 static int i915_pm_resume(struct device *dev)
1017 {
1018         struct pci_dev *pdev = to_pci_dev(dev);
1019         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1020
1021         return i915_resume(drm_dev);
1022 }
1023
1024 static int i915_pm_freeze(struct device *dev)
1025 {
1026         struct pci_dev *pdev = to_pci_dev(dev);
1027         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1028
1029         if (!drm_dev || !drm_dev->dev_private) {
1030                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1031                 return -ENODEV;
1032         }
1033
1034         return i915_drm_freeze(drm_dev);
1035 }
1036
1037 static int i915_pm_thaw(struct device *dev)
1038 {
1039         struct pci_dev *pdev = to_pci_dev(dev);
1040         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1041
1042         return i915_drm_thaw(drm_dev);
1043 }
1044
1045 static int i915_pm_poweroff(struct device *dev)
1046 {
1047         struct pci_dev *pdev = to_pci_dev(dev);
1048         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1049
1050         return i915_drm_freeze(drm_dev);
1051 }
1052
1053 static const struct dev_pm_ops i915_pm_ops = {
1054         .suspend = i915_pm_suspend,
1055         .resume = i915_pm_resume,
1056         .freeze = i915_pm_freeze,
1057         .thaw = i915_pm_thaw,
1058         .poweroff = i915_pm_poweroff,
1059         .restore = i915_pm_resume,
1060 };
1061
1062 static const struct vm_operations_struct i915_gem_vm_ops = {
1063         .fault = i915_gem_fault,
1064         .open = drm_gem_vm_open,
1065         .close = drm_gem_vm_close,
1066 };
1067
1068 static const struct file_operations i915_driver_fops = {
1069         .owner = THIS_MODULE,
1070         .open = drm_open,
1071         .release = drm_release,
1072         .unlocked_ioctl = drm_ioctl,
1073         .mmap = drm_gem_mmap,
1074         .poll = drm_poll,
1075         .fasync = drm_fasync,
1076         .read = drm_read,
1077 #ifdef CONFIG_COMPAT
1078         .compat_ioctl = i915_compat_ioctl,
1079 #endif
1080         .llseek = noop_llseek,
1081 };
1082
1083 static struct drm_driver driver = {
1084         /* Don't use MTRRs here; the Xserver or userspace app should
1085          * deal with them for Intel hardware.
1086          */
1087         .driver_features =
1088             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1089             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1090         .load = i915_driver_load,
1091         .unload = i915_driver_unload,
1092         .open = i915_driver_open,
1093         .lastclose = i915_driver_lastclose,
1094         .preclose = i915_driver_preclose,
1095         .postclose = i915_driver_postclose,
1096
1097         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1098         .suspend = i915_suspend,
1099         .resume = i915_resume,
1100
1101         .device_is_agp = i915_driver_device_is_agp,
1102         .master_create = i915_master_create,
1103         .master_destroy = i915_master_destroy,
1104 #if defined(CONFIG_DEBUG_FS)
1105         .debugfs_init = i915_debugfs_init,
1106         .debugfs_cleanup = i915_debugfs_cleanup,
1107 #endif
1108         .gem_init_object = i915_gem_init_object,
1109         .gem_free_object = i915_gem_free_object,
1110         .gem_vm_ops = &i915_gem_vm_ops,
1111
1112         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1113         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1114         .gem_prime_export = i915_gem_prime_export,
1115         .gem_prime_import = i915_gem_prime_import,
1116
1117         .dumb_create = i915_gem_dumb_create,
1118         .dumb_map_offset = i915_gem_mmap_gtt,
1119         .dumb_destroy = i915_gem_dumb_destroy,
1120         .ioctls = i915_ioctls,
1121         .fops = &i915_driver_fops,
1122         .name = DRIVER_NAME,
1123         .desc = DRIVER_DESC,
1124         .date = DRIVER_DATE,
1125         .major = DRIVER_MAJOR,
1126         .minor = DRIVER_MINOR,
1127         .patchlevel = DRIVER_PATCHLEVEL,
1128 };
1129
1130 static struct pci_driver i915_pci_driver = {
1131         .name = DRIVER_NAME,
1132         .id_table = pciidlist,
1133         .probe = i915_pci_probe,
1134         .remove = i915_pci_remove,
1135         .driver.pm = &i915_pm_ops,
1136 };
1137
1138 static int __init i915_init(void)
1139 {
1140         driver.num_ioctls = i915_max_ioctl;
1141
1142         /*
1143          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1144          * explicitly disabled with the module pararmeter.
1145          *
1146          * Otherwise, just follow the parameter (defaulting to off).
1147          *
1148          * Allow optional vga_text_mode_force boot option to override
1149          * the default behavior.
1150          */
1151 #if defined(CONFIG_DRM_I915_KMS)
1152         if (i915_modeset != 0)
1153                 driver.driver_features |= DRIVER_MODESET;
1154 #endif
1155         if (i915_modeset == 1)
1156                 driver.driver_features |= DRIVER_MODESET;
1157
1158 #ifdef CONFIG_VGA_CONSOLE
1159         if (vgacon_text_force() && i915_modeset == -1)
1160                 driver.driver_features &= ~DRIVER_MODESET;
1161 #endif
1162
1163         if (!(driver.driver_features & DRIVER_MODESET))
1164                 driver.get_vblank_timestamp = NULL;
1165
1166         return drm_pci_init(&driver, &i915_pci_driver);
1167 }
1168
1169 static void __exit i915_exit(void)
1170 {
1171         drm_pci_exit(&driver, &i915_pci_driver);
1172 }
1173
1174 module_init(i915_init);
1175 module_exit(i915_exit);
1176
1177 MODULE_AUTHOR(DRIVER_AUTHOR);
1178 MODULE_DESCRIPTION(DRIVER_DESC);
1179 MODULE_LICENSE("GPL and additional rights");
1180
1181 /* We give fast paths for the really cool registers */
1182 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1183         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1184          ((reg) < 0x40000) &&            \
1185          ((reg) != FORCEWAKE))
1186 static void
1187 ilk_dummy_write(struct drm_i915_private *dev_priv)
1188 {
1189         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1190          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1191          * harmless to write 0 into. */
1192         I915_WRITE_NOTRACE(MI_MODE, 0);
1193 }
1194
1195 static void
1196 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1197 {
1198         if (IS_HASWELL(dev_priv->dev) &&
1199             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1200                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1201                           reg);
1202                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1203         }
1204 }
1205
1206 static void
1207 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1208 {
1209         if (IS_HASWELL(dev_priv->dev) &&
1210             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1211                 DRM_ERROR("Unclaimed write to %x\n", reg);
1212                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1213         }
1214 }
1215
1216 #define __i915_read(x, y) \
1217 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1218         u##x val = 0; \
1219         if (IS_GEN5(dev_priv->dev)) \
1220                 ilk_dummy_write(dev_priv); \
1221         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1222                 unsigned long irqflags; \
1223                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1224                 if (dev_priv->forcewake_count == 0) \
1225                         dev_priv->gt.force_wake_get(dev_priv); \
1226                 val = read##y(dev_priv->regs + reg); \
1227                 if (dev_priv->forcewake_count == 0) \
1228                         dev_priv->gt.force_wake_put(dev_priv); \
1229                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1230         } else { \
1231                 val = read##y(dev_priv->regs + reg); \
1232         } \
1233         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1234         return val; \
1235 }
1236
1237 __i915_read(8, b)
1238 __i915_read(16, w)
1239 __i915_read(32, l)
1240 __i915_read(64, q)
1241 #undef __i915_read
1242
1243 #define __i915_write(x, y) \
1244 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1245         u32 __fifo_ret = 0; \
1246         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1247         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1248                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1249         } \
1250         if (IS_GEN5(dev_priv->dev)) \
1251                 ilk_dummy_write(dev_priv); \
1252         hsw_unclaimed_reg_clear(dev_priv, reg); \
1253         write##y(val, dev_priv->regs + reg); \
1254         if (unlikely(__fifo_ret)) { \
1255                 gen6_gt_check_fifodbg(dev_priv); \
1256         } \
1257         hsw_unclaimed_reg_check(dev_priv, reg); \
1258 }
1259 __i915_write(8, b)
1260 __i915_write(16, w)
1261 __i915_write(32, l)
1262 __i915_write(64, q)
1263 #undef __i915_write
1264
1265 static const struct register_whitelist {
1266         uint64_t offset;
1267         uint32_t size;
1268         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1269 } whitelist[] = {
1270         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1271 };
1272
1273 int i915_reg_read_ioctl(struct drm_device *dev,
1274                         void *data, struct drm_file *file)
1275 {
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         struct drm_i915_reg_read *reg = data;
1278         struct register_whitelist const *entry = whitelist;
1279         int i;
1280
1281         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1282                 if (entry->offset == reg->offset &&
1283                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1284                         break;
1285         }
1286
1287         if (i == ARRAY_SIZE(whitelist))
1288                 return -EINVAL;
1289
1290         switch (entry->size) {
1291         case 8:
1292                 reg->val = I915_READ64(reg->offset);
1293                 break;
1294         case 4:
1295                 reg->val = I915_READ(reg->offset);
1296                 break;
1297         case 2:
1298                 reg->val = I915_READ16(reg->offset);
1299                 break;
1300         case 1:
1301                 reg->val = I915_READ8(reg->offset);
1302                 break;
1303         default:
1304                 WARN_ON(1);
1305                 return -EINVAL;
1306         }
1307
1308         return 0;
1309 }