drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  65
  66 static bool cpu_cache_is_coherent(struct drm_device *dev,
  67                                   enum i915_cache_level level)
  68 {
  69         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  70 }
  71
  72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  73 {
  74         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  75                 return true;
  76
  77         return obj->pin_display;
  78 }
  79
  80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  81 {
  82         if (obj->tiling_mode)
  83                 i915_gem_release_mmap(obj);
  84
  85         /* As we do not have an associated fence register, we will force
  86          * a tiling change if we ever need to acquire one.
  87          */
  88         obj->fence_dirty = false;
  89         obj->fence_reg = I915_FENCE_REG_NONE;
  90 }
  91
  92 /* some bookkeeping */
  93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  94                                   size_t size)
  95 {
  96         spin_lock(&dev_priv->mm.object_stat_lock);
  97         dev_priv->mm.object_count++;
  98         dev_priv->mm.object_memory += size;
  99         spin_unlock(&dev_priv->mm.object_stat_lock);
 100 }
 101
 102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 103                                      size_t size)
 104 {
 105         spin_lock(&dev_priv->mm.object_stat_lock);
 106         dev_priv->mm.object_count--;
 107         dev_priv->mm.object_memory -= size;
 108         spin_unlock(&dev_priv->mm.object_stat_lock);
 109 }
 110
 111 static int
 112 i915_gem_wait_for_error(struct i915_gpu_error *error)
 113 {
 114         int ret;
 115
 116 #define EXIT_COND (!i915_reset_in_progress(error) || \
 117                    i915_terminally_wedged(error))
 118         if (EXIT_COND)
 119                 return 0;
 120
 121         /*
 122          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 123          * userspace. If it takes that long something really bad is going on and
 124          * we should simply try to bail out and fail as gracefully as possible.
 125          */
 126         ret = wait_event_interruptible_timeout(error->reset_queue,
 127                                                EXIT_COND,
 128                                                10*HZ);
 129         if (ret == 0) {
 130                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 131                 return -EIO;
 132         } else if (ret < 0) {
 133                 return ret;
 134         }
 135 #undef EXIT_COND
 136
 137         return 0;
 138 }
 139
 140 int i915_mutex_lock_interruptible(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         int ret;
 144
 145         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 146         if (ret)
 147                 return ret;
 148
 149         ret = mutex_lock_interruptible(&dev->struct_mutex);
 150         if (ret)
 151                 return ret;
 152
 153         WARN_ON(i915_verify_lists(dev));
 154         return 0;
 155 }
 156
 157 static inline bool
 158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 159 {
 160         return i915_gem_obj_bound_any(obj) && !obj->active;
 161 }
 162
 163 int
 164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 165                     struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_init *args = data;
 169
 170         if (drm_core_check_feature(dev, DRIVER_MODESET))
 171                 return -ENODEV;
 172
 173         if (args->gtt_start >= args->gtt_end ||
 174             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 175                 return -EINVAL;
 176
 177         /* GEM with user mode setting was never supported on ilk and later. */
 178         if (INTEL_INFO(dev)->gen >= 5)
 179                 return -ENODEV;
 180
 181         mutex_lock(&dev->struct_mutex);
 182         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 183                                   args->gtt_end);
 184         dev_priv->gtt.mappable_end = args->gtt_end;
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         return 0;
 188 }
 189
 190 int
 191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *file)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         struct drm_i915_gem_get_aperture *args = data;
 196         struct drm_i915_gem_object *obj;
 197         size_t pinned;
 198
 199         pinned = 0;
 200         mutex_lock(&dev->struct_mutex);
 201         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 202                 if (i915_gem_obj_is_pinned(obj))
 203                         pinned += i915_gem_obj_ggtt_size(obj);
 204         mutex_unlock(&dev->struct_mutex);
 205
 206         args->aper_size = dev_priv->gtt.base.total;
 207         args->aper_available_size = args->aper_size - pinned;
 208
 209         return 0;
 210 }
 211
 212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
 213 {
 214         drm_dma_handle_t *phys = obj->phys_handle;
 215
 216         if (!phys)
 217                 return;
 218
 219         if (obj->madv == I915_MADV_WILLNEED) {
 220                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 221                 char *vaddr = phys->vaddr;
 222                 int i;
 223
 224                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 225                         struct page *page = shmem_read_mapping_page(mapping, i);
 226                         if (!IS_ERR(page)) {
 227                                 char *dst = kmap_atomic(page);
 228                                 memcpy(dst, vaddr, PAGE_SIZE);
 229                                 drm_clflush_virt_range(dst, PAGE_SIZE);
 230                                 kunmap_atomic(dst);
 231
 232                                 set_page_dirty(page);
 233                                 mark_page_accessed(page);
 234                                 page_cache_release(page);
 235                         }
 236                         vaddr += PAGE_SIZE;
 237                 }
 238                 i915_gem_chipset_flush(obj->base.dev);
 239         }
 240
 241 #ifdef CONFIG_X86
 242         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 243 #endif
 244         drm_pci_free(obj->base.dev, phys);
 245         obj->phys_handle = NULL;
 246 }
 247
 248 int
 249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 250                             int align)
 251 {
 252         drm_dma_handle_t *phys;
 253         struct address_space *mapping;
 254         char *vaddr;
 255         int i;
 256
 257         if (obj->phys_handle) {
 258                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 259                         return -EBUSY;
 260
 261                 return 0;
 262         }
 263
 264         if (obj->madv != I915_MADV_WILLNEED)
 265                 return -EFAULT;
 266
 267         if (obj->base.filp == NULL)
 268                 return -EINVAL;
 269
 270         /* create a new object */
 271         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 272         if (!phys)
 273                 return -ENOMEM;
 274
 275         vaddr = phys->vaddr;
 276 #ifdef CONFIG_X86
 277         set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
 278 #endif
 279         mapping = file_inode(obj->base.filp)->i_mapping;
 280         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 281                 struct page *page;
 282                 char *src;
 283
 284                 page = shmem_read_mapping_page(mapping, i);
 285                 if (IS_ERR(page)) {
 286 #ifdef CONFIG_X86
 287                         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 288 #endif
 289                         drm_pci_free(obj->base.dev, phys);
 290                         return PTR_ERR(page);
 291                 }
 292
 293                 src = kmap_atomic(page);
 294                 memcpy(vaddr, src, PAGE_SIZE);
 295                 kunmap_atomic(src);
 296
 297                 mark_page_accessed(page);
 298                 page_cache_release(page);
 299
 300                 vaddr += PAGE_SIZE;
 301         }
 302
 303         obj->phys_handle = phys;
 304         return 0;
 305 }
 306
 307 static int
 308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 309                      struct drm_i915_gem_pwrite *args,
 310                      struct drm_file *file_priv)
 311 {
 312         struct drm_device *dev = obj->base.dev;
 313         void *vaddr = obj->phys_handle->vaddr + args->offset;
 314         char __user *user_data = to_user_ptr(args->data_ptr);
 315
 316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 317                 unsigned long unwritten;
 318
 319                 /* The physical object once assigned is fixed for the lifetime
 320                  * of the obj, so we can safely drop the lock and continue
 321                  * to access vaddr.
 322                  */
 323                 mutex_unlock(&dev->struct_mutex);
 324                 unwritten = copy_from_user(vaddr, user_data, args->size);
 325                 mutex_lock(&dev->struct_mutex);
 326                 if (unwritten)
 327                         return -EFAULT;
 328         }
 329
 330         i915_gem_chipset_flush(dev);
 331         return 0;
 332 }
 333
 334 void *i915_gem_object_alloc(struct drm_device *dev)
 335 {
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 338 }
 339
 340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 341 {
 342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 343         kmem_cache_free(dev_priv->slab, obj);
 344 }
 345
 346 static int
 347 i915_gem_create(struct drm_file *file,
 348                 struct drm_device *dev,
 349                 uint64_t size,
 350                 uint32_t *handle_p)
 351 {
 352         struct drm_i915_gem_object *obj;
 353         int ret;
 354         u32 handle;
 355
 356         size = roundup(size, PAGE_SIZE);
 357         if (size == 0)
 358                 return -EINVAL;
 359
 360         /* Allocate the new object */
 361         obj = i915_gem_alloc_object(dev, size);
 362         if (obj == NULL)
 363                 return -ENOMEM;
 364
 365         ret = drm_gem_handle_create(file, &obj->base, &handle);
 366         /* drop reference from allocate - handle holds it now */
 367         drm_gem_object_unreference_unlocked(&obj->base);
 368         if (ret)
 369                 return ret;
 370
 371         *handle_p = handle;
 372         return 0;
 373 }
 374
 375 int
 376 i915_gem_dumb_create(struct drm_file *file,
 377                      struct drm_device *dev,
 378                      struct drm_mode_create_dumb *args)
 379 {
 380         /* have to work out size/pitch and return them */
 381         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 382         args->size = args->pitch * args->height;
 383         return i915_gem_create(file, dev,
 384                                args->size, &args->handle);
 385 }
 386
 387 /**
 388  * Creates a new mm object and returns a handle to it.
 389  */
 390 int
 391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 392                       struct drm_file *file)
 393 {
 394         struct drm_i915_gem_create *args = data;
 395
 396         return i915_gem_create(file, dev,
 397                                args->size, &args->handle);
 398 }
 399
 400 static inline int
 401 __copy_to_user_swizzled(char __user *cpu_vaddr,
 402                         const char *gpu_vaddr, int gpu_offset,
 403                         int length)
 404 {
 405         int ret, cpu_offset = 0;
 406
 407         while (length > 0) {
 408                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 409                 int this_length = min(cacheline_end - gpu_offset, length);
 410                 int swizzled_gpu_offset = gpu_offset ^ 64;
 411
 412                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 413                                      gpu_vaddr + swizzled_gpu_offset,
 414                                      this_length);
 415                 if (ret)
 416                         return ret + length;
 417
 418                 cpu_offset += this_length;
 419                 gpu_offset += this_length;
 420                 length -= this_length;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static inline int
 427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 428                           const char __user *cpu_vaddr,
 429                           int length)
 430 {
 431         int ret, cpu_offset = 0;
 432
 433         while (length > 0) {
 434                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 435                 int this_length = min(cacheline_end - gpu_offset, length);
 436                 int swizzled_gpu_offset = gpu_offset ^ 64;
 437
 438                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 439                                        cpu_vaddr + cpu_offset,
 440                                        this_length);
 441                 if (ret)
 442                         return ret + length;
 443
 444                 cpu_offset += this_length;
 445                 gpu_offset += this_length;
 446                 length -= this_length;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * Pins the specified object's pages and synchronizes the object with
 454  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 455  * flush the object from the CPU cache.
 456  */
 457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 458                                     int *needs_clflush)
 459 {
 460         int ret;
 461
 462         *needs_clflush = 0;
 463
 464         if (!obj->base.filp)
 465                 return -EINVAL;
 466
 467         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 468                 /* If we're not in the cpu read domain, set ourself into the gtt
 469                  * read domain and manually flush cachelines (if required). This
 470                  * optimizes for the case when the gpu will dirty the data
 471                  * anyway again before the next pread happens. */
 472                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 473                                                         obj->cache_level);
 474                 ret = i915_gem_object_wait_rendering(obj, true);
 475                 if (ret)
 476                         return ret;
 477
 478                 i915_gem_object_retire(obj);
 479         }
 480
 481         ret = i915_gem_object_get_pages(obj);
 482         if (ret)
 483                 return ret;
 484
 485         i915_gem_object_pin_pages(obj);
 486
 487         return ret;
 488 }
 489
 490 /* Per-page copy function for the shmem pread fastpath.
 491  * Flushes invalid cachelines before reading the target if
 492  * needs_clflush is set. */
 493 static int
 494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 495                  char __user *user_data,
 496                  bool page_do_bit17_swizzling, bool needs_clflush)
 497 {
 498         char *vaddr;
 499         int ret;
 500
 501         if (unlikely(page_do_bit17_swizzling))
 502                 return -EINVAL;
 503
 504         vaddr = kmap_atomic(page);
 505         if (needs_clflush)
 506                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 507                                        page_length);
 508         ret = __copy_to_user_inatomic(user_data,
 509                                       vaddr + shmem_page_offset,
 510                                       page_length);
 511         kunmap_atomic(vaddr);
 512
 513         return ret ? -EFAULT : 0;
 514 }
 515
 516 static void
 517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 518                              bool swizzled)
 519 {
 520         if (unlikely(swizzled)) {
 521                 unsigned long start = (unsigned long) addr;
 522                 unsigned long end = (unsigned long) addr + length;
 523
 524                 /* For swizzling simply ensure that we always flush both
 525                  * channels. Lame, but simple and it works. Swizzled
 526                  * pwrite/pread is far from a hotpath - current userspace
 527                  * doesn't use it at all. */
 528                 start = round_down(start, 128);
 529                 end = round_up(end, 128);
 530
 531                 drm_clflush_virt_range((void *)start, end - start);
 532         } else {
 533                 drm_clflush_virt_range(addr, length);
 534         }
 535
 536 }
 537
 538 /* Only difference to the fast-path function is that this can handle bit17
 539  * and uses non-atomic copy and kmap functions. */
 540 static int
 541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         vaddr = kmap(page);
 549         if (needs_clflush)
 550                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 551                                              page_length,
 552                                              page_do_bit17_swizzling);
 553
 554         if (page_do_bit17_swizzling)
 555                 ret = __copy_to_user_swizzled(user_data,
 556                                               vaddr, shmem_page_offset,
 557                                               page_length);
 558         else
 559                 ret = __copy_to_user(user_data,
 560                                      vaddr + shmem_page_offset,
 561                                      page_length);
 562         kunmap(page);
 563
 564         return ret ? - EFAULT : 0;
 565 }
 566
 567 static int
 568 i915_gem_shmem_pread(struct drm_device *dev,
 569                      struct drm_i915_gem_object *obj,
 570                      struct drm_i915_gem_pread *args,
 571                      struct drm_file *file)
 572 {
 573         char __user *user_data;
 574         ssize_t remain;
 575         loff_t offset;
 576         int shmem_page_offset, page_length, ret = 0;
 577         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 578         int prefaulted = 0;
 579         int needs_clflush = 0;
 580         struct sg_page_iter sg_iter;
 581
 582         user_data = to_user_ptr(args->data_ptr);
 583         remain = args->size;
 584
 585         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 586
 587         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 588         if (ret)
 589                 return ret;
 590
 591         offset = args->offset;
 592
 593         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 594                          offset >> PAGE_SHIFT) {
 595                 struct page *page = sg_page_iter_page(&sg_iter);
 596
 597                 if (remain <= 0)
 598                         break;
 599
 600                 /* Operation in this page
 601                  *
 602                  * shmem_page_offset = offset within page in shmem file
 603                  * page_length = bytes to copy for this page
 604                  */
 605                 shmem_page_offset = offset_in_page(offset);
 606                 page_length = remain;
 607                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 608                         page_length = PAGE_SIZE - shmem_page_offset;
 609
 610                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 611                         (page_to_phys(page) & (1 << 17)) != 0;
 612
 613                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 614                                        user_data, page_do_bit17_swizzling,
 615                                        needs_clflush);
 616                 if (ret == 0)
 617                         goto next_page;
 618
 619                 mutex_unlock(&dev->struct_mutex);
 620
 621                 if (likely(!i915.prefault_disable) && !prefaulted) {
 622                         ret = fault_in_multipages_writeable(user_data, remain);
 623                         /* Userspace is tricking us, but we've already clobbered
 624                          * its pages with the prefault and promised to write the
 625                          * data up to the first fault. Hence ignore any errors
 626                          * and just continue. */
 627                         (void)ret;
 628                         prefaulted = 1;
 629                 }
 630
 631                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 632                                        user_data, page_do_bit17_swizzling,
 633                                        needs_clflush);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636
 637                 if (ret)
 638                         goto out;
 639
 640 next_page:
 641                 remain -= page_length;
 642                 user_data += page_length;
 643                 offset += page_length;
 644         }
 645
 646 out:
 647         i915_gem_object_unpin_pages(obj);
 648
 649         return ret;
 650 }
 651
 652 /**
 653  * Reads data from the object referenced by handle.
 654  *
 655  * On error, the contents of *data are undefined.
 656  */
 657 int
 658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 659                      struct drm_file *file)
 660 {
 661         struct drm_i915_gem_pread *args = data;
 662         struct drm_i915_gem_object *obj;
 663         int ret = 0;
 664
 665         if (args->size == 0)
 666                 return 0;
 667
 668         if (!access_ok(VERIFY_WRITE,
 669                        to_user_ptr(args->data_ptr),
 670                        args->size))
 671                 return -EFAULT;
 672
 673         ret = i915_mutex_lock_interruptible(dev);
 674         if (ret)
 675                 return ret;
 676
 677         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 678         if (&obj->base == NULL) {
 679                 ret = -ENOENT;
 680                 goto unlock;
 681         }
 682
 683         /* Bounds check source.  */
 684         if (args->offset > obj->base.size ||
 685             args->size > obj->base.size - args->offset) {
 686                 ret = -EINVAL;
 687                 goto out;
 688         }
 689
 690         /* prime objects have no backing filp to GEM pread/pwrite
 691          * pages from.
 692          */
 693         if (!obj->base.filp) {
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         trace_i915_gem_object_pread(obj, args->offset, args->size);
 699
 700         ret = i915_gem_shmem_pread(dev, obj, args, file);
 701
 702 out:
 703         drm_gem_object_unreference(&obj->base);
 704 unlock:
 705         mutex_unlock(&dev->struct_mutex);
 706         return ret;
 707 }
 708
 709 /* This is the fast write path which cannot handle
 710  * page faults in the source data
 711  */
 712
 713 static inline int
 714 fast_user_write(struct io_mapping *mapping,
 715                 loff_t page_base, int page_offset,
 716                 char __user *user_data,
 717                 int length)
 718 {
 719         void __iomem *vaddr_atomic;
 720         void *vaddr;
 721         unsigned long unwritten;
 722
 723         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 724         /* We can use the cpu mem copy function because this is X86. */
 725         vaddr = (void __force*)vaddr_atomic + page_offset;
 726         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 727                                                       user_data, length);
 728         io_mapping_unmap_atomic(vaddr_atomic);
 729         return unwritten;
 730 }
 731
 732 /**
 733  * This is the fast pwrite path, where we copy the data directly from the
 734  * user into the GTT, uncached.
 735  */
 736 static int
 737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 738                          struct drm_i915_gem_object *obj,
 739                          struct drm_i915_gem_pwrite *args,
 740                          struct drm_file *file)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         ssize_t remain;
 744         loff_t offset, page_base;
 745         char __user *user_data;
 746         int page_offset, page_length, ret;
 747
 748         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 749         if (ret)
 750                 goto out;
 751
 752         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 753         if (ret)
 754                 goto out_unpin;
 755
 756         ret = i915_gem_object_put_fence(obj);
 757         if (ret)
 758                 goto out_unpin;
 759
 760         user_data = to_user_ptr(args->data_ptr);
 761         remain = args->size;
 762
 763         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 764
 765         while (remain > 0) {
 766                 /* Operation in this page
 767                  *
 768                  * page_base = page offset within aperture
 769                  * page_offset = offset within page
 770                  * page_length = bytes to copy for this page
 771                  */
 772                 page_base = offset & PAGE_MASK;
 773                 page_offset = offset_in_page(offset);
 774                 page_length = remain;
 775                 if ((page_offset + remain) > PAGE_SIZE)
 776                         page_length = PAGE_SIZE - page_offset;
 777
 778                 /* If we get a fault while copying data, then (presumably) our
 779                  * source page isn't available.  Return the error and we'll
 780                  * retry in the slow path.
 781                  */
 782                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 783                                     page_offset, user_data, page_length)) {
 784                         ret = -EFAULT;
 785                         goto out_unpin;
 786                 }
 787
 788                 remain -= page_length;
 789                 user_data += page_length;
 790                 offset += page_length;
 791         }
 792
 793 out_unpin:
 794         i915_gem_object_ggtt_unpin(obj);
 795 out:
 796         return ret;
 797 }
 798
 799 /* Per-page copy function for the shmem pwrite fastpath.
 800  * Flushes invalid cachelines before writing to the target if
 801  * needs_clflush_before is set and flushes out any written cachelines after
 802  * writing if needs_clflush is set. */
 803 static int
 804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 805                   char __user *user_data,
 806                   bool page_do_bit17_swizzling,
 807                   bool needs_clflush_before,
 808                   bool needs_clflush_after)
 809 {
 810         char *vaddr;
 811         int ret;
 812
 813         if (unlikely(page_do_bit17_swizzling))
 814                 return -EINVAL;
 815
 816         vaddr = kmap_atomic(page);
 817         if (needs_clflush_before)
 818                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 819                                        page_length);
 820         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 821                                         user_data, page_length);
 822         if (needs_clflush_after)
 823                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 824                                        page_length);
 825         kunmap_atomic(vaddr);
 826
 827         return ret ? -EFAULT : 0;
 828 }
 829
 830 /* Only difference to the fast-path function is that this can handle bit17
 831  * and uses non-atomic copy and kmap functions. */
 832 static int
 833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 834                   char __user *user_data,
 835                   bool page_do_bit17_swizzling,
 836                   bool needs_clflush_before,
 837                   bool needs_clflush_after)
 838 {
 839         char *vaddr;
 840         int ret;
 841
 842         vaddr = kmap(page);
 843         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 844                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 845                                              page_length,
 846                                              page_do_bit17_swizzling);
 847         if (page_do_bit17_swizzling)
 848                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 849                                                 user_data,
 850                                                 page_length);
 851         else
 852                 ret = __copy_from_user(vaddr + shmem_page_offset,
 853                                        user_data,
 854                                        page_length);
 855         if (needs_clflush_after)
 856                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 857                                              page_length,
 858                                              page_do_bit17_swizzling);
 859         kunmap(page);
 860
 861         return ret ? -EFAULT : 0;
 862 }
 863
 864 static int
 865 i915_gem_shmem_pwrite(struct drm_device *dev,
 866                       struct drm_i915_gem_object *obj,
 867                       struct drm_i915_gem_pwrite *args,
 868                       struct drm_file *file)
 869 {
 870         ssize_t remain;
 871         loff_t offset;
 872         char __user *user_data;
 873         int shmem_page_offset, page_length, ret = 0;
 874         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 875         int hit_slowpath = 0;
 876         int needs_clflush_after = 0;
 877         int needs_clflush_before = 0;
 878         struct sg_page_iter sg_iter;
 879
 880         user_data = to_user_ptr(args->data_ptr);
 881         remain = args->size;
 882
 883         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 886                 /* If we're not in the cpu write domain, set ourself into the gtt
 887                  * write domain and manually flush cachelines (if required). This
 888                  * optimizes for the case when the gpu will use the data
 889                  * right away and we therefore have to clflush anyway. */
 890                 needs_clflush_after = cpu_write_needs_clflush(obj);
 891                 ret = i915_gem_object_wait_rendering(obj, false);
 892                 if (ret)
 893                         return ret;
 894
 895                 i915_gem_object_retire(obj);
 896         }
 897         /* Same trick applies to invalidate partially written cachelines read
 898          * before writing. */
 899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 900                 needs_clflush_before =
 901                         !cpu_cache_is_coherent(dev, obj->cache_level);
 902
 903         ret = i915_gem_object_get_pages(obj);
 904         if (ret)
 905                 return ret;
 906
 907         i915_gem_object_pin_pages(obj);
 908
 909         offset = args->offset;
 910         obj->dirty = 1;
 911
 912         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 913                          offset >> PAGE_SHIFT) {
 914                 struct page *page = sg_page_iter_page(&sg_iter);
 915                 int partial_cacheline_write;
 916
 917                 if (remain <= 0)
 918                         break;
 919
 920                 /* Operation in this page
 921                  *
 922                  * shmem_page_offset = offset within page in shmem file
 923                  * page_length = bytes to copy for this page
 924                  */
 925                 shmem_page_offset = offset_in_page(offset);
 926
 927                 page_length = remain;
 928                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 929                         page_length = PAGE_SIZE - shmem_page_offset;
 930
 931                 /* If we don't overwrite a cacheline completely we need to be
 932                  * careful to have up-to-date data by first clflushing. Don't
 933                  * overcomplicate things and flush the entire patch. */
 934                 partial_cacheline_write = needs_clflush_before &&
 935                         ((shmem_page_offset | page_length)
 936                                 & (boot_cpu_data.x86_clflush_size - 1));
 937
 938                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 939                         (page_to_phys(page) & (1 << 17)) != 0;
 940
 941                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 942                                         user_data, page_do_bit17_swizzling,
 943                                         partial_cacheline_write,
 944                                         needs_clflush_after);
 945                 if (ret == 0)
 946                         goto next_page;
 947
 948                 hit_slowpath = 1;
 949                 mutex_unlock(&dev->struct_mutex);
 950                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 951                                         user_data, page_do_bit17_swizzling,
 952                                         partial_cacheline_write,
 953                                         needs_clflush_after);
 954
 955                 mutex_lock(&dev->struct_mutex);
 956
 957                 if (ret)
 958                         goto out;
 959
 960 next_page:
 961                 remain -= page_length;
 962                 user_data += page_length;
 963                 offset += page_length;
 964         }
 965
 966 out:
 967         i915_gem_object_unpin_pages(obj);
 968
 969         if (hit_slowpath) {
 970                 /*
 971                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 972                  * cachelines in-line while writing and the object moved
 973                  * out of the cpu write domain while we've dropped the lock.
 974                  */
 975                 if (!needs_clflush_after &&
 976                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 977                         if (i915_gem_clflush_object(obj, obj->pin_display))
 978                                 i915_gem_chipset_flush(dev);
 979                 }
 980         }
 981
 982         if (needs_clflush_after)
 983                 i915_gem_chipset_flush(dev);
 984
 985         return ret;
 986 }
 987
 988 /**
 989  * Writes data to the object referenced by handle.
 990  *
 991  * On error, the contents of the buffer that were to be modified are undefined.
 992  */
 993 int
 994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 995                       struct drm_file *file)
 996 {
 997         struct drm_i915_gem_pwrite *args = data;
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         if (args->size == 0)
1002                 return 0;
1003
1004         if (!access_ok(VERIFY_READ,
1005                        to_user_ptr(args->data_ptr),
1006                        args->size))
1007                 return -EFAULT;
1008
1009         if (likely(!i915.prefault_disable)) {
1010                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1011                                                    args->size);
1012                 if (ret)
1013                         return -EFAULT;
1014         }
1015
1016         ret = i915_mutex_lock_interruptible(dev);
1017         if (ret)
1018                 return ret;
1019
1020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021         if (&obj->base == NULL) {
1022                 ret = -ENOENT;
1023                 goto unlock;
1024         }
1025
1026         /* Bounds check destination. */
1027         if (args->offset > obj->base.size ||
1028             args->size > obj->base.size - args->offset) {
1029                 ret = -EINVAL;
1030                 goto out;
1031         }
1032
1033         /* prime objects have no backing filp to GEM pread/pwrite
1034          * pages from.
1035          */
1036         if (!obj->base.filp) {
1037                 ret = -EINVAL;
1038                 goto out;
1039         }
1040
1041         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1042
1043         ret = -EFAULT;
1044         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045          * it would end up going through the fenced access, and we'll get
1046          * different detiling behavior between reading and writing.
1047          * pread/pwrite currently are reading and writing from the CPU
1048          * perspective, requiring manual detiling by the client.
1049          */
1050         if (obj->phys_handle) {
1051                 ret = i915_gem_phys_pwrite(obj, args, file);
1052                 goto out;
1053         }
1054
1055         if (obj->tiling_mode == I915_TILING_NONE &&
1056             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057             cpu_write_needs_clflush(obj)) {
1058                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059                 /* Note that the gtt paths might fail with non-page-backed user
1060                  * pointers (e.g. gtt mappings when moving data between
1061                  * textures). Fallback to the shmem path in that case. */
1062         }
1063
1064         if (ret == -EFAULT || ret == -ENOSPC)
1065                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1066
1067 out:
1068         drm_gem_object_unreference(&obj->base);
1069 unlock:
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 int
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1076                      bool interruptible)
1077 {
1078         if (i915_reset_in_progress(error)) {
1079                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080                  * -EIO unconditionally for these. */
1081                 if (!interruptible)
1082                         return -EIO;
1083
1084                 /* Recovery complete, but the reset failed ... */
1085                 if (i915_terminally_wedged(error))
1086                         return -EIO;
1087
1088                 return -EAGAIN;
1089         }
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Compare seqno against outstanding lazy request. Emit a request if they are
1096  * equal.
1097  */
1098 int
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 {
1101         int ret;
1102
1103         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1104
1105         ret = 0;
1106         if (seqno == ring->outstanding_lazy_seqno)
1107                 ret = i915_add_request(ring, NULL);
1108
1109         return ret;
1110 }
1111
1112 static void fake_irq(unsigned long data)
1113 {
1114         wake_up_process((struct task_struct *)data);
1115 }
1116
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118                        struct intel_engine_cs *ring)
1119 {
1120         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1121 }
1122
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1124 {
1125         if (file_priv == NULL)
1126                 return true;
1127
1128         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 }
1130
1131 /**
1132  * __wait_seqno - wait until execution of seqno has finished
1133  * @ring: the ring expected to report seqno
1134  * @seqno: duh!
1135  * @reset_counter: reset sequence associated with the given seqno
1136  * @interruptible: do an interruptible wait (normally yes)
1137  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1138  *
1139  * Note: It is of utmost importance that the passed in seqno and reset_counter
1140  * values have been read by the caller in an smp safe manner. Where read-side
1141  * locks are involved, it is sufficient to read the reset_counter before
1142  * unlocking the lock that protects the seqno. For lockless tricks, the
1143  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1144  * inserted.
1145  *
1146  * Returns 0 if the seqno was found within the alloted time. Else returns the
1147  * errno with remaining time filled in timeout argument.
1148  */
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150                         unsigned reset_counter,
1151                         bool interruptible,
1152                         s64 *timeout,
1153                         struct drm_i915_file_private *file_priv)
1154 {
1155         struct drm_device *dev = ring->dev;
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         const bool irq_test_in_progress =
1158                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1159         DEFINE_WAIT(wait);
1160         unsigned long timeout_expire;
1161         s64 before, now;
1162         int ret;
1163
1164         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1165
1166         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1167                 return 0;
1168
1169         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1170
1171         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1172                 gen6_rps_boost(dev_priv);
1173                 if (file_priv)
1174                         mod_delayed_work(dev_priv->wq,
1175                                          &file_priv->mm.idle_work,
1176                                          msecs_to_jiffies(100));
1177         }
1178
1179         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1180                 return -ENODEV;
1181
1182         /* Record current time in case interrupted by signal, or wedged */
1183         trace_i915_gem_request_wait_begin(ring, seqno);
1184         before = ktime_get_raw_ns();
1185         for (;;) {
1186                 struct timer_list timer;
1187
1188                 prepare_to_wait(&ring->irq_queue, &wait,
1189                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1190
1191                 /* We need to check whether any gpu reset happened in between
1192                  * the caller grabbing the seqno and now ... */
1193                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195                          * is truely gone. */
1196                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1197                         if (ret == 0)
1198                                 ret = -EAGAIN;
1199                         break;
1200                 }
1201
1202                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1203                         ret = 0;
1204                         break;
1205                 }
1206
1207                 if (interruptible && signal_pending(current)) {
1208                         ret = -ERESTARTSYS;
1209                         break;
1210                 }
1211
1212                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1213                         ret = -ETIME;
1214                         break;
1215                 }
1216
1217                 timer.function = NULL;
1218                 if (timeout || missed_irq(dev_priv, ring)) {
1219                         unsigned long expire;
1220
1221                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223                         mod_timer(&timer, expire);
1224                 }
1225
1226                 io_schedule();
1227
1228                 if (timer.function) {
1229                         del_singleshot_timer_sync(&timer);
1230                         destroy_timer_on_stack(&timer);
1231                 }
1232         }
1233         now = ktime_get_raw_ns();
1234         trace_i915_gem_request_wait_end(ring, seqno);
1235
1236         if (!irq_test_in_progress)
1237                 ring->irq_put(ring);
1238
1239         finish_wait(&ring->irq_queue, &wait);
1240
1241         if (timeout) {
1242                 s64 tres = *timeout - (now - before);
1243
1244                 *timeout = tres < 0 ? 0 : tres;
1245         }
1246
1247         return ret;
1248 }
1249
1250 /**
1251  * Waits for a sequence number to be signaled, and cleans up the
1252  * request and object lists appropriately for that event.
1253  */
1254 int
1255 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1256 {
1257         struct drm_device *dev = ring->dev;
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         bool interruptible = dev_priv->mm.interruptible;
1260         int ret;
1261
1262         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1263         BUG_ON(seqno == 0);
1264
1265         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1266         if (ret)
1267                 return ret;
1268
1269         ret = i915_gem_check_olr(ring, seqno);
1270         if (ret)
1271                 return ret;
1272
1273         return __wait_seqno(ring, seqno,
1274                             atomic_read(&dev_priv->gpu_error.reset_counter),
1275                             interruptible, NULL, NULL);
1276 }
1277
1278 static int
1279 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1280                                      struct intel_engine_cs *ring)
1281 {
1282         if (!obj->active)
1283                 return 0;
1284
1285         /* Manually manage the write flush as we may have not yet
1286          * retired the buffer.
1287          *
1288          * Note that the last_write_seqno is always the earlier of
1289          * the two (read/write) seqno, so if we haved successfully waited,
1290          * we know we have passed the last write.
1291          */
1292         obj->last_write_seqno = 0;
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * Ensures that all rendering to the object has completed and the object is
1299  * safe to unbind from the GTT or access from the CPU.
1300  */
1301 static __must_check int
1302 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1303                                bool readonly)
1304 {
1305         struct intel_engine_cs *ring = obj->ring;
1306         u32 seqno;
1307         int ret;
1308
1309         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1310         if (seqno == 0)
1311                 return 0;
1312
1313         ret = i915_wait_seqno(ring, seqno);
1314         if (ret)
1315                 return ret;
1316
1317         return i915_gem_object_wait_rendering__tail(obj, ring);
1318 }
1319
1320 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1321  * as the object state may change during this call.
1322  */
1323 static __must_check int
1324 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1325                                             struct drm_i915_file_private *file_priv,
1326                                             bool readonly)
1327 {
1328         struct drm_device *dev = obj->base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         struct intel_engine_cs *ring = obj->ring;
1331         unsigned reset_counter;
1332         u32 seqno;
1333         int ret;
1334
1335         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1336         BUG_ON(!dev_priv->mm.interruptible);
1337
1338         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1339         if (seqno == 0)
1340                 return 0;
1341
1342         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1343         if (ret)
1344                 return ret;
1345
1346         ret = i915_gem_check_olr(ring, seqno);
1347         if (ret)
1348                 return ret;
1349
1350         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1351         mutex_unlock(&dev->struct_mutex);
1352         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1353         mutex_lock(&dev->struct_mutex);
1354         if (ret)
1355                 return ret;
1356
1357         return i915_gem_object_wait_rendering__tail(obj, ring);
1358 }
1359
1360 /**
1361  * Called when user space prepares to use an object with the CPU, either
1362  * through the mmap ioctl's mapping or a GTT mapping.
1363  */
1364 int
1365 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1366                           struct drm_file *file)
1367 {
1368         struct drm_i915_gem_set_domain *args = data;
1369         struct drm_i915_gem_object *obj;
1370         uint32_t read_domains = args->read_domains;
1371         uint32_t write_domain = args->write_domain;
1372         int ret;
1373
1374         /* Only handle setting domains to types used by the CPU. */
1375         if (write_domain & I915_GEM_GPU_DOMAINS)
1376                 return -EINVAL;
1377
1378         if (read_domains & I915_GEM_GPU_DOMAINS)
1379                 return -EINVAL;
1380
1381         /* Having something in the write domain implies it's in the read
1382          * domain, and only that read domain.  Enforce that in the request.
1383          */
1384         if (write_domain != 0 && read_domains != write_domain)
1385                 return -EINVAL;
1386
1387         ret = i915_mutex_lock_interruptible(dev);
1388         if (ret)
1389                 return ret;
1390
1391         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1392         if (&obj->base == NULL) {
1393                 ret = -ENOENT;
1394                 goto unlock;
1395         }
1396
1397         /* Try to flush the object off the GPU without holding the lock.
1398          * We will repeat the flush holding the lock in the normal manner
1399          * to catch cases where we are gazumped.
1400          */
1401         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1402                                                           file->driver_priv,
1403                                                           !write_domain);
1404         if (ret)
1405                 goto unref;
1406
1407         if (read_domains & I915_GEM_DOMAIN_GTT) {
1408                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1409
1410                 /* Silently promote "you're not bound, there was nothing to do"
1411                  * to success, since the client was just asking us to
1412                  * make sure everything was done.
1413                  */
1414                 if (ret == -EINVAL)
1415                         ret = 0;
1416         } else {
1417                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1418         }
1419
1420 unref:
1421         drm_gem_object_unreference(&obj->base);
1422 unlock:
1423         mutex_unlock(&dev->struct_mutex);
1424         return ret;
1425 }
1426
1427 /**
1428  * Called when user space has done writes to this buffer
1429  */
1430 int
1431 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1432                          struct drm_file *file)
1433 {
1434         struct drm_i915_gem_sw_finish *args = data;
1435         struct drm_i915_gem_object *obj;
1436         int ret = 0;
1437
1438         ret = i915_mutex_lock_interruptible(dev);
1439         if (ret)
1440                 return ret;
1441
1442         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1443         if (&obj->base == NULL) {
1444                 ret = -ENOENT;
1445                 goto unlock;
1446         }
1447
1448         /* Pinned buffers may be scanout, so flush the cache */
1449         if (obj->pin_display)
1450                 i915_gem_object_flush_cpu_write_domain(obj, true);
1451
1452         drm_gem_object_unreference(&obj->base);
1453 unlock:
1454         mutex_unlock(&dev->struct_mutex);
1455         return ret;
1456 }
1457
1458 /**
1459  * Maps the contents of an object, returning the address it is mapped
1460  * into.
1461  *
1462  * While the mapping holds a reference on the contents of the object, it doesn't
1463  * imply a ref on the object itself.
1464  */
1465 int
1466 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1467                     struct drm_file *file)
1468 {
1469         struct drm_i915_gem_mmap *args = data;
1470         struct drm_gem_object *obj;
1471         unsigned long addr;
1472
1473         obj = drm_gem_object_lookup(dev, file, args->handle);
1474         if (obj == NULL)
1475                 return -ENOENT;
1476
1477         /* prime objects have no backing filp to GEM mmap
1478          * pages from.
1479          */
1480         if (!obj->filp) {
1481                 drm_gem_object_unreference_unlocked(obj);
1482                 return -EINVAL;
1483         }
1484
1485         addr = vm_mmap(obj->filp, 0, args->size,
1486                        PROT_READ | PROT_WRITE, MAP_SHARED,
1487                        args->offset);
1488         drm_gem_object_unreference_unlocked(obj);
1489         if (IS_ERR((void *)addr))
1490                 return addr;
1491
1492         args->addr_ptr = (uint64_t) addr;
1493
1494         return 0;
1495 }
1496
1497 /**
1498  * i915_gem_fault - fault a page into the GTT
1499  * vma: VMA in question
1500  * vmf: fault info
1501  *
1502  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1503  * from userspace.  The fault handler takes care of binding the object to
1504  * the GTT (if needed), allocating and programming a fence register (again,
1505  * only if needed based on whether the old reg is still valid or the object
1506  * is tiled) and inserting a new PTE into the faulting process.
1507  *
1508  * Note that the faulting process may involve evicting existing objects
1509  * from the GTT and/or fence registers to make room.  So performance may
1510  * suffer if the GTT working set is large or there are few fence registers
1511  * left.
1512  */
1513 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1514 {
1515         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1516         struct drm_device *dev = obj->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         pgoff_t page_offset;
1519         unsigned long pfn;
1520         int ret = 0;
1521         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1522
1523         intel_runtime_pm_get(dev_priv);
1524
1525         /* We don't use vmf->pgoff since that has the fake offset */
1526         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1527                 PAGE_SHIFT;
1528
1529         ret = i915_mutex_lock_interruptible(dev);
1530         if (ret)
1531                 goto out;
1532
1533         trace_i915_gem_object_fault(obj, page_offset, true, write);
1534
1535         /* Try to flush the object off the GPU first without holding the lock.
1536          * Upon reacquiring the lock, we will perform our sanity checks and then
1537          * repeat the flush holding the lock in the normal manner to catch cases
1538          * where we are gazumped.
1539          */
1540         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1541         if (ret)
1542                 goto unlock;
1543
1544         /* Access to snoopable pages through the GTT is incoherent. */
1545         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1546                 ret = -EFAULT;
1547                 goto unlock;
1548         }
1549
1550         /* Now bind it into the GTT if needed */
1551         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1552         if (ret)
1553                 goto unlock;
1554
1555         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1556         if (ret)
1557                 goto unpin;
1558
1559         ret = i915_gem_object_get_fence(obj);
1560         if (ret)
1561                 goto unpin;
1562
1563         /* Finally, remap it using the new GTT offset */
1564         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1565         pfn >>= PAGE_SHIFT;
1566
1567         if (!obj->fault_mappable) {
1568                 unsigned long size = min_t(unsigned long,
1569                                            vma->vm_end - vma->vm_start,
1570                                            obj->base.size);
1571                 int i;
1572
1573                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1574                         ret = vm_insert_pfn(vma,
1575                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1576                                             pfn + i);
1577                         if (ret)
1578                                 break;
1579                 }
1580
1581                 obj->fault_mappable = true;
1582         } else
1583                 ret = vm_insert_pfn(vma,
1584                                     (unsigned long)vmf->virtual_address,
1585                                     pfn + page_offset);
1586 unpin:
1587         i915_gem_object_ggtt_unpin(obj);
1588 unlock:
1589         mutex_unlock(&dev->struct_mutex);
1590 out:
1591         switch (ret) {
1592         case -EIO:
1593                 /*
1594                  * We eat errors when the gpu is terminally wedged to avoid
1595                  * userspace unduly crashing (gl has no provisions for mmaps to
1596                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1597                  * and so needs to be reported.
1598                  */
1599                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1600                         ret = VM_FAULT_SIGBUS;
1601                         break;
1602                 }
1603         case -EAGAIN:
1604                 /*
1605                  * EAGAIN means the gpu is hung and we'll wait for the error
1606                  * handler to reset everything when re-faulting in
1607                  * i915_mutex_lock_interruptible.
1608                  */
1609         case 0:
1610         case -ERESTARTSYS:
1611         case -EINTR:
1612         case -EBUSY:
1613                 /*
1614                  * EBUSY is ok: this just means that another thread
1615                  * already did the job.
1616                  */
1617                 ret = VM_FAULT_NOPAGE;
1618                 break;
1619         case -ENOMEM:
1620                 ret = VM_FAULT_OOM;
1621                 break;
1622         case -ENOSPC:
1623         case -EFAULT:
1624                 ret = VM_FAULT_SIGBUS;
1625                 break;
1626         default:
1627                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1628                 ret = VM_FAULT_SIGBUS;
1629                 break;
1630         }
1631
1632         intel_runtime_pm_put(dev_priv);
1633         return ret;
1634 }
1635
1636 /**
1637  * i915_gem_release_mmap - remove physical page mappings
1638  * @obj: obj in question
1639  *
1640  * Preserve the reservation of the mmapping with the DRM core code, but
1641  * relinquish ownership of the pages back to the system.
1642  *
1643  * It is vital that we remove the page mapping if we have mapped a tiled
1644  * object through the GTT and then lose the fence register due to
1645  * resource pressure. Similarly if the object has been moved out of the
1646  * aperture, than pages mapped into userspace must be revoked. Removing the
1647  * mapping will then trigger a page fault on the next user access, allowing
1648  * fixup by i915_gem_fault().
1649  */
1650 void
1651 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1652 {
1653         if (!obj->fault_mappable)
1654                 return;
1655
1656         drm_vma_node_unmap(&obj->base.vma_node,
1657                            obj->base.dev->anon_inode->i_mapping);
1658         obj->fault_mappable = false;
1659 }
1660
1661 void
1662 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1663 {
1664         struct drm_i915_gem_object *obj;
1665
1666         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1667                 i915_gem_release_mmap(obj);
1668 }
1669
1670 uint32_t
1671 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1672 {
1673         uint32_t gtt_size;
1674
1675         if (INTEL_INFO(dev)->gen >= 4 ||
1676             tiling_mode == I915_TILING_NONE)
1677                 return size;
1678
1679         /* Previous chips need a power-of-two fence region when tiling */
1680         if (INTEL_INFO(dev)->gen == 3)
1681                 gtt_size = 1024*1024;
1682         else
1683                 gtt_size = 512*1024;
1684
1685         while (gtt_size < size)
1686                 gtt_size <<= 1;
1687
1688         return gtt_size;
1689 }
1690
1691 /**
1692  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1693  * @obj: object to check
1694  *
1695  * Return the required GTT alignment for an object, taking into account
1696  * potential fence register mapping.
1697  */
1698 uint32_t
1699 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1700                            int tiling_mode, bool fenced)
1701 {
1702         /*
1703          * Minimum alignment is 4k (GTT page size), but might be greater
1704          * if a fence register is needed for the object.
1705          */
1706         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1707             tiling_mode == I915_TILING_NONE)
1708                 return 4096;
1709
1710         /*
1711          * Previous chips need to be aligned to the size of the smallest
1712          * fence register that can contain the object.
1713          */
1714         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1715 }
1716
1717 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1718 {
1719         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1720         int ret;
1721
1722         if (drm_vma_node_has_offset(&obj->base.vma_node))
1723                 return 0;
1724
1725         dev_priv->mm.shrinker_no_lock_stealing = true;
1726
1727         ret = drm_gem_create_mmap_offset(&obj->base);
1728         if (ret != -ENOSPC)
1729                 goto out;
1730
1731         /* Badly fragmented mmap space? The only way we can recover
1732          * space is by destroying unwanted objects. We can't randomly release
1733          * mmap_offsets as userspace expects them to be persistent for the
1734          * lifetime of the objects. The closest we can is to release the
1735          * offsets on purgeable objects by truncating it and marking it purged,
1736          * which prevents userspace from ever using that object again.
1737          */
1738         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1739         ret = drm_gem_create_mmap_offset(&obj->base);
1740         if (ret != -ENOSPC)
1741                 goto out;
1742
1743         i915_gem_shrink_all(dev_priv);
1744         ret = drm_gem_create_mmap_offset(&obj->base);
1745 out:
1746         dev_priv->mm.shrinker_no_lock_stealing = false;
1747
1748         return ret;
1749 }
1750
1751 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1752 {
1753         drm_gem_free_mmap_offset(&obj->base);
1754 }
1755
1756 int
1757 i915_gem_mmap_gtt(struct drm_file *file,
1758                   struct drm_device *dev,
1759                   uint32_t handle,
1760                   uint64_t *offset)
1761 {
1762         struct drm_i915_private *dev_priv = dev->dev_private;
1763         struct drm_i915_gem_object *obj;
1764         int ret;
1765
1766         ret = i915_mutex_lock_interruptible(dev);
1767         if (ret)
1768                 return ret;
1769
1770         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1771         if (&obj->base == NULL) {
1772                 ret = -ENOENT;
1773                 goto unlock;
1774         }
1775
1776         if (obj->base.size > dev_priv->gtt.mappable_end) {
1777                 ret = -E2BIG;
1778                 goto out;
1779         }
1780
1781         if (obj->madv != I915_MADV_WILLNEED) {
1782                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1783                 ret = -EFAULT;
1784                 goto out;
1785         }
1786
1787         ret = i915_gem_object_create_mmap_offset(obj);
1788         if (ret)
1789                 goto out;
1790
1791         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1792
1793 out:
1794         drm_gem_object_unreference(&obj->base);
1795 unlock:
1796         mutex_unlock(&dev->struct_mutex);
1797         return ret;
1798 }
1799
1800 /**
1801  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1802  * @dev: DRM device
1803  * @data: GTT mapping ioctl data
1804  * @file: GEM object info
1805  *
1806  * Simply returns the fake offset to userspace so it can mmap it.
1807  * The mmap call will end up in drm_gem_mmap(), which will set things
1808  * up so we can get faults in the handler above.
1809  *
1810  * The fault handler will take care of binding the object into the GTT
1811  * (since it may have been evicted to make room for something), allocating
1812  * a fence register, and mapping the appropriate aperture address into
1813  * userspace.
1814  */
1815 int
1816 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1817                         struct drm_file *file)
1818 {
1819         struct drm_i915_gem_mmap_gtt *args = data;
1820
1821         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1822 }
1823
1824 static inline int
1825 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1826 {
1827         return obj->madv == I915_MADV_DONTNEED;
1828 }
1829
1830 /* Immediately discard the backing storage */
1831 static void
1832 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1833 {
1834         i915_gem_object_free_mmap_offset(obj);
1835
1836         if (obj->base.filp == NULL)
1837                 return;
1838
1839         /* Our goal here is to return as much of the memory as
1840          * is possible back to the system as we are called from OOM.
1841          * To do this we must instruct the shmfs to drop all of its
1842          * backing pages, *now*.
1843          */
1844         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1845         obj->madv = __I915_MADV_PURGED;
1846 }
1847
1848 /* Try to discard unwanted pages */
1849 static void
1850 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1851 {
1852         struct address_space *mapping;
1853
1854         switch (obj->madv) {
1855         case I915_MADV_DONTNEED:
1856                 i915_gem_object_truncate(obj);
1857         case __I915_MADV_PURGED:
1858                 return;
1859         }
1860
1861         if (obj->base.filp == NULL)
1862                 return;
1863
1864         mapping = file_inode(obj->base.filp)->i_mapping,
1865         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1866 }
1867
1868 static void
1869 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1870 {
1871         struct sg_page_iter sg_iter;
1872         int ret;
1873
1874         BUG_ON(obj->madv == __I915_MADV_PURGED);
1875
1876         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1877         if (ret) {
1878                 /* In the event of a disaster, abandon all caches and
1879                  * hope for the best.
1880                  */
1881                 WARN_ON(ret != -EIO);
1882                 i915_gem_clflush_object(obj, true);
1883                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1884         }
1885
1886         if (i915_gem_object_needs_bit17_swizzle(obj))
1887                 i915_gem_object_save_bit_17_swizzle(obj);
1888
1889         if (obj->madv == I915_MADV_DONTNEED)
1890                 obj->dirty = 0;
1891
1892         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1893                 struct page *page = sg_page_iter_page(&sg_iter);
1894
1895                 if (obj->dirty)
1896                         set_page_dirty(page);
1897
1898                 if (obj->madv == I915_MADV_WILLNEED)
1899                         mark_page_accessed(page);
1900
1901                 page_cache_release(page);
1902         }
1903         obj->dirty = 0;
1904
1905         sg_free_table(obj->pages);
1906         kfree(obj->pages);
1907 }
1908
1909 int
1910 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1911 {
1912         const struct drm_i915_gem_object_ops *ops = obj->ops;
1913
1914         if (obj->pages == NULL)
1915                 return 0;
1916
1917         if (obj->pages_pin_count)
1918                 return -EBUSY;
1919
1920         BUG_ON(i915_gem_obj_bound_any(obj));
1921
1922         /* ->put_pages might need to allocate memory for the bit17 swizzle
1923          * array, hence protect them from being reaped by removing them from gtt
1924          * lists early. */
1925         list_del(&obj->global_list);
1926
1927         ops->put_pages(obj);
1928         obj->pages = NULL;
1929
1930         i915_gem_object_invalidate(obj);
1931
1932         return 0;
1933 }
1934
1935 static unsigned long
1936 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1937                   bool purgeable_only)
1938 {
1939         struct list_head still_in_list;
1940         struct drm_i915_gem_object *obj;
1941         unsigned long count = 0;
1942
1943         /*
1944          * As we may completely rewrite the (un)bound list whilst unbinding
1945          * (due to retiring requests) we have to strictly process only
1946          * one element of the list at the time, and recheck the list
1947          * on every iteration.
1948          *
1949          * In particular, we must hold a reference whilst removing the
1950          * object as we may end up waiting for and/or retiring the objects.
1951          * This might release the final reference (held by the active list)
1952          * and result in the object being freed from under us. This is
1953          * similar to the precautions the eviction code must take whilst
1954          * removing objects.
1955          *
1956          * Also note that although these lists do not hold a reference to
1957          * the object we can safely grab one here: The final object
1958          * unreferencing and the bound_list are both protected by the
1959          * dev->struct_mutex and so we won't ever be able to observe an
1960          * object on the bound_list with a reference count equals 0.
1961          */
1962         INIT_LIST_HEAD(&still_in_list);
1963         while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1964                 obj = list_first_entry(&dev_priv->mm.unbound_list,
1965                                        typeof(*obj), global_list);
1966                 list_move_tail(&obj->global_list, &still_in_list);
1967
1968                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1969                         continue;
1970
1971                 drm_gem_object_reference(&obj->base);
1972
1973                 if (i915_gem_object_put_pages(obj) == 0)
1974                         count += obj->base.size >> PAGE_SHIFT;
1975
1976                 drm_gem_object_unreference(&obj->base);
1977         }
1978         list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1979
1980         INIT_LIST_HEAD(&still_in_list);
1981         while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1982                 struct i915_vma *vma, *v;
1983
1984                 obj = list_first_entry(&dev_priv->mm.bound_list,
1985                                        typeof(*obj), global_list);
1986                 list_move_tail(&obj->global_list, &still_in_list);
1987
1988                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1989                         continue;
1990
1991                 drm_gem_object_reference(&obj->base);
1992
1993                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1994                         if (i915_vma_unbind(vma))
1995                                 break;
1996
1997                 if (i915_gem_object_put_pages(obj) == 0)
1998                         count += obj->base.size >> PAGE_SHIFT;
1999
2000                 drm_gem_object_unreference(&obj->base);
2001         }
2002         list_splice(&still_in_list, &dev_priv->mm.bound_list);
2003
2004         return count;
2005 }
2006
2007 static unsigned long
2008 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2009 {
2010         return __i915_gem_shrink(dev_priv, target, true);
2011 }
2012
2013 static unsigned long
2014 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2015 {
2016         i915_gem_evict_everything(dev_priv->dev);
2017         return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2018 }
2019
2020 static int
2021 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2022 {
2023         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2024         int page_count, i;
2025         struct address_space *mapping;
2026         struct sg_table *st;
2027         struct scatterlist *sg;
2028         struct sg_page_iter sg_iter;
2029         struct page *page;
2030         unsigned long last_pfn = 0;     /* suppress gcc warning */
2031         gfp_t gfp;
2032
2033         /* Assert that the object is not currently in any GPU domain. As it
2034          * wasn't in the GTT, there shouldn't be any way it could have been in
2035          * a GPU cache
2036          */
2037         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2038         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2039
2040         st = kmalloc(sizeof(*st), GFP_KERNEL);
2041         if (st == NULL)
2042                 return -ENOMEM;
2043
2044         page_count = obj->base.size / PAGE_SIZE;
2045         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2046                 kfree(st);
2047                 return -ENOMEM;
2048         }
2049
2050         /* Get the list of pages out of our struct file.  They'll be pinned
2051          * at this point until we release them.
2052          *
2053          * Fail silently without starting the shrinker
2054          */
2055         mapping = file_inode(obj->base.filp)->i_mapping;
2056         gfp = mapping_gfp_mask(mapping);
2057         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2058         gfp &= ~(__GFP_IO | __GFP_WAIT);
2059         sg = st->sgl;
2060         st->nents = 0;
2061         for (i = 0; i < page_count; i++) {
2062                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2063                 if (IS_ERR(page)) {
2064                         i915_gem_purge(dev_priv, page_count);
2065                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2066                 }
2067                 if (IS_ERR(page)) {
2068                         /* We've tried hard to allocate the memory by reaping
2069                          * our own buffer, now let the real VM do its job and
2070                          * go down in flames if truly OOM.
2071                          */
2072                         i915_gem_shrink_all(dev_priv);
2073                         page = shmem_read_mapping_page(mapping, i);
2074                         if (IS_ERR(page))
2075                                 goto err_pages;
2076                 }
2077 #ifdef CONFIG_SWIOTLB
2078                 if (swiotlb_nr_tbl()) {
2079                         st->nents++;
2080                         sg_set_page(sg, page, PAGE_SIZE, 0);
2081                         sg = sg_next(sg);
2082                         continue;
2083                 }
2084 #endif
2085                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2086                         if (i)
2087                                 sg = sg_next(sg);
2088                         st->nents++;
2089                         sg_set_page(sg, page, PAGE_SIZE, 0);
2090                 } else {
2091                         sg->length += PAGE_SIZE;
2092                 }
2093                 last_pfn = page_to_pfn(page);
2094
2095                 /* Check that the i965g/gm workaround works. */
2096                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2097         }
2098 #ifdef CONFIG_SWIOTLB
2099         if (!swiotlb_nr_tbl())
2100 #endif
2101                 sg_mark_end(sg);
2102         obj->pages = st;
2103
2104         if (i915_gem_object_needs_bit17_swizzle(obj))
2105                 i915_gem_object_do_bit_17_swizzle(obj);
2106
2107         return 0;
2108
2109 err_pages:
2110         sg_mark_end(sg);
2111         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2112                 page_cache_release(sg_page_iter_page(&sg_iter));
2113         sg_free_table(st);
2114         kfree(st);
2115
2116         /* shmemfs first checks if there is enough memory to allocate the page
2117          * and reports ENOSPC should there be insufficient, along with the usual
2118          * ENOMEM for a genuine allocation failure.
2119          *
2120          * We use ENOSPC in our driver to mean that we have run out of aperture
2121          * space and so want to translate the error from shmemfs back to our
2122          * usual understanding of ENOMEM.
2123          */
2124         if (PTR_ERR(page) == -ENOSPC)
2125                 return -ENOMEM;
2126         else
2127                 return PTR_ERR(page);
2128 }
2129
2130 /* Ensure that the associated pages are gathered from the backing storage
2131  * and pinned into our object. i915_gem_object_get_pages() may be called
2132  * multiple times before they are released by a single call to
2133  * i915_gem_object_put_pages() - once the pages are no longer referenced
2134  * either as a result of memory pressure (reaping pages under the shrinker)
2135  * or as the object is itself released.
2136  */
2137 int
2138 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2139 {
2140         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141         const struct drm_i915_gem_object_ops *ops = obj->ops;
2142         int ret;
2143
2144         if (obj->pages)
2145                 return 0;
2146
2147         if (obj->madv != I915_MADV_WILLNEED) {
2148                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2149                 return -EFAULT;
2150         }
2151
2152         BUG_ON(obj->pages_pin_count);
2153
2154         ret = ops->get_pages(obj);
2155         if (ret)
2156                 return ret;
2157
2158         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2159         return 0;
2160 }
2161
2162 static void
2163 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2164                                struct intel_engine_cs *ring)
2165 {
2166         struct drm_device *dev = obj->base.dev;
2167         struct drm_i915_private *dev_priv = dev->dev_private;
2168         u32 seqno = intel_ring_get_seqno(ring);
2169
2170         BUG_ON(ring == NULL);
2171         if (obj->ring != ring && obj->last_write_seqno) {
2172                 /* Keep the seqno relative to the current ring */
2173                 obj->last_write_seqno = seqno;
2174         }
2175         obj->ring = ring;
2176
2177         /* Add a reference if we're newly entering the active list. */
2178         if (!obj->active) {
2179                 drm_gem_object_reference(&obj->base);
2180                 obj->active = 1;
2181         }
2182
2183         list_move_tail(&obj->ring_list, &ring->active_list);
2184
2185         obj->last_read_seqno = seqno;
2186
2187         if (obj->fenced_gpu_access) {
2188                 obj->last_fenced_seqno = seqno;
2189
2190                 /* Bump MRU to take account of the delayed flush */
2191                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2192                         struct drm_i915_fence_reg *reg;
2193
2194                         reg = &dev_priv->fence_regs[obj->fence_reg];
2195                         list_move_tail(&reg->lru_list,
2196                                        &dev_priv->mm.fence_list);
2197                 }
2198         }
2199 }
2200
2201 void i915_vma_move_to_active(struct i915_vma *vma,
2202                              struct intel_engine_cs *ring)
2203 {
2204         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2205         return i915_gem_object_move_to_active(vma->obj, ring);
2206 }
2207
2208 static void
2209 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2210 {
2211         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212         struct i915_address_space *vm;
2213         struct i915_vma *vma;
2214
2215         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2216         BUG_ON(!obj->active);
2217
2218         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2219                 vma = i915_gem_obj_to_vma(obj, vm);
2220                 if (vma && !list_empty(&vma->mm_list))
2221                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2222         }
2223
2224         intel_fb_obj_flush(obj, true);
2225
2226         list_del_init(&obj->ring_list);
2227         obj->ring = NULL;
2228
2229         obj->last_read_seqno = 0;
2230         obj->last_write_seqno = 0;
2231         obj->base.write_domain = 0;
2232
2233         obj->last_fenced_seqno = 0;
2234         obj->fenced_gpu_access = false;
2235
2236         obj->active = 0;
2237         drm_gem_object_unreference(&obj->base);
2238
2239         WARN_ON(i915_verify_lists(dev));
2240 }
2241
2242 static void
2243 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2244 {
2245         struct intel_engine_cs *ring = obj->ring;
2246
2247         if (ring == NULL)
2248                 return;
2249
2250         if (i915_seqno_passed(ring->get_seqno(ring, true),
2251                               obj->last_read_seqno))
2252                 i915_gem_object_move_to_inactive(obj);
2253 }
2254
2255 static int
2256 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2257 {
2258         struct drm_i915_private *dev_priv = dev->dev_private;
2259         struct intel_engine_cs *ring;
2260         int ret, i, j;
2261
2262         /* Carefully retire all requests without writing to the rings */
2263         for_each_ring(ring, dev_priv, i) {
2264                 ret = intel_ring_idle(ring);
2265                 if (ret)
2266                         return ret;
2267         }
2268         i915_gem_retire_requests(dev);
2269
2270         /* Finally reset hw state */
2271         for_each_ring(ring, dev_priv, i) {
2272                 intel_ring_init_seqno(ring, seqno);
2273
2274                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2275                         ring->semaphore.sync_seqno[j] = 0;
2276         }
2277
2278         return 0;
2279 }
2280
2281 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2282 {
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         int ret;
2285
2286         if (seqno == 0)
2287                 return -EINVAL;
2288
2289         /* HWS page needs to be set less than what we
2290          * will inject to ring
2291          */
2292         ret = i915_gem_init_seqno(dev, seqno - 1);
2293         if (ret)
2294                 return ret;
2295
2296         /* Carefully set the last_seqno value so that wrap
2297          * detection still works
2298          */
2299         dev_priv->next_seqno = seqno;
2300         dev_priv->last_seqno = seqno - 1;
2301         if (dev_priv->last_seqno == 0)
2302                 dev_priv->last_seqno--;
2303
2304         return 0;
2305 }
2306
2307 int
2308 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2309 {
2310         struct drm_i915_private *dev_priv = dev->dev_private;
2311
2312         /* reserve 0 for non-seqno */
2313         if (dev_priv->next_seqno == 0) {
2314                 int ret = i915_gem_init_seqno(dev, 0);
2315                 if (ret)
2316                         return ret;
2317
2318                 dev_priv->next_seqno = 1;
2319         }
2320
2321         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2322         return 0;
2323 }
2324
2325 int __i915_add_request(struct intel_engine_cs *ring,
2326                        struct drm_file *file,
2327                        struct drm_i915_gem_object *obj,
2328                        u32 *out_seqno)
2329 {
2330         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2331         struct drm_i915_gem_request *request;
2332         u32 request_ring_position, request_start;
2333         int ret;
2334
2335         request_start = intel_ring_get_tail(ring->buffer);
2336         /*
2337          * Emit any outstanding flushes - execbuf can fail to emit the flush
2338          * after having emitted the batchbuffer command. Hence we need to fix
2339          * things up similar to emitting the lazy request. The difference here
2340          * is that the flush _must_ happen before the next request, no matter
2341          * what.
2342          */
2343         ret = intel_ring_flush_all_caches(ring);
2344         if (ret)
2345                 return ret;
2346
2347         request = ring->preallocated_lazy_request;
2348         if (WARN_ON(request == NULL))
2349                 return -ENOMEM;
2350
2351         /* Record the position of the start of the request so that
2352          * should we detect the updated seqno part-way through the
2353          * GPU processing the request, we never over-estimate the
2354          * position of the head.
2355          */
2356         request_ring_position = intel_ring_get_tail(ring->buffer);
2357
2358         ret = ring->add_request(ring);
2359         if (ret)
2360                 return ret;
2361
2362         request->seqno = intel_ring_get_seqno(ring);
2363         request->ring = ring;
2364         request->head = request_start;
2365         request->tail = request_ring_position;
2366
2367         /* Whilst this request exists, batch_obj will be on the
2368          * active_list, and so will hold the active reference. Only when this
2369          * request is retired will the the batch_obj be moved onto the
2370          * inactive_list and lose its active reference. Hence we do not need
2371          * to explicitly hold another reference here.
2372          */
2373         request->batch_obj = obj;
2374
2375         /* Hold a reference to the current context so that we can inspect
2376          * it later in case a hangcheck error event fires.
2377          */
2378         request->ctx = ring->last_context;
2379         if (request->ctx)
2380                 i915_gem_context_reference(request->ctx);
2381
2382         request->emitted_jiffies = jiffies;
2383         list_add_tail(&request->list, &ring->request_list);
2384         request->file_priv = NULL;
2385
2386         if (file) {
2387                 struct drm_i915_file_private *file_priv = file->driver_priv;
2388
2389                 spin_lock(&file_priv->mm.lock);
2390                 request->file_priv = file_priv;
2391                 list_add_tail(&request->client_list,
2392                               &file_priv->mm.request_list);
2393                 spin_unlock(&file_priv->mm.lock);
2394         }
2395
2396         trace_i915_gem_request_add(ring, request->seqno);
2397         ring->outstanding_lazy_seqno = 0;
2398         ring->preallocated_lazy_request = NULL;
2399
2400         if (!dev_priv->ums.mm_suspended) {
2401                 i915_queue_hangcheck(ring->dev);
2402
2403                 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2404                 queue_delayed_work(dev_priv->wq,
2405                                    &dev_priv->mm.retire_work,
2406                                    round_jiffies_up_relative(HZ));
2407                 intel_mark_busy(dev_priv->dev);
2408         }
2409
2410         if (out_seqno)
2411                 *out_seqno = request->seqno;
2412         return 0;
2413 }
2414
2415 static inline void
2416 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2417 {
2418         struct drm_i915_file_private *file_priv = request->file_priv;
2419
2420         if (!file_priv)
2421                 return;
2422
2423         spin_lock(&file_priv->mm.lock);
2424         list_del(&request->client_list);
2425         request->file_priv = NULL;
2426         spin_unlock(&file_priv->mm.lock);
2427 }
2428
2429 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2430                                    const struct intel_context *ctx)
2431 {
2432         unsigned long elapsed;
2433
2434         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2435
2436         if (ctx->hang_stats.banned)
2437                 return true;
2438
2439         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2440                 if (!i915_gem_context_is_default(ctx)) {
2441                         DRM_DEBUG("context hanging too fast, banning!\n");
2442                         return true;
2443                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2444                         if (i915_stop_ring_allow_warn(dev_priv))
2445                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2446                         return true;
2447                 }
2448         }
2449
2450         return false;
2451 }
2452
2453 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2454                                   struct intel_context *ctx,
2455                                   const bool guilty)
2456 {
2457         struct i915_ctx_hang_stats *hs;
2458
2459         if (WARN_ON(!ctx))
2460                 return;
2461
2462         hs = &ctx->hang_stats;
2463
2464         if (guilty) {
2465                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2466                 hs->batch_active++;
2467                 hs->guilty_ts = get_seconds();
2468         } else {
2469                 hs->batch_pending++;
2470         }
2471 }
2472
2473 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2474 {
2475         list_del(&request->list);
2476         i915_gem_request_remove_from_client(request);
2477
2478         if (request->ctx)
2479                 i915_gem_context_unreference(request->ctx);
2480
2481         kfree(request);
2482 }
2483
2484 struct drm_i915_gem_request *
2485 i915_gem_find_active_request(struct intel_engine_cs *ring)
2486 {
2487         struct drm_i915_gem_request *request;
2488         u32 completed_seqno;
2489
2490         completed_seqno = ring->get_seqno(ring, false);
2491
2492         list_for_each_entry(request, &ring->request_list, list) {
2493                 if (i915_seqno_passed(completed_seqno, request->seqno))
2494                         continue;
2495
2496                 return request;
2497         }
2498
2499         return NULL;
2500 }
2501
2502 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2503                                        struct intel_engine_cs *ring)
2504 {
2505         struct drm_i915_gem_request *request;
2506         bool ring_hung;
2507
2508         request = i915_gem_find_active_request(ring);
2509
2510         if (request == NULL)
2511                 return;
2512
2513         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2514
2515         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2516
2517         list_for_each_entry_continue(request, &ring->request_list, list)
2518                 i915_set_reset_status(dev_priv, request->ctx, false);
2519 }
2520
2521 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2522                                         struct intel_engine_cs *ring)
2523 {
2524         while (!list_empty(&ring->active_list)) {
2525                 struct drm_i915_gem_object *obj;
2526
2527                 obj = list_first_entry(&ring->active_list,
2528                                        struct drm_i915_gem_object,
2529                                        ring_list);
2530
2531                 i915_gem_object_move_to_inactive(obj);
2532         }
2533
2534         /*
2535          * We must free the requests after all the corresponding objects have
2536          * been moved off active lists. Which is the same order as the normal
2537          * retire_requests function does. This is important if object hold
2538          * implicit references on things like e.g. ppgtt address spaces through
2539          * the request.
2540          */
2541         while (!list_empty(&ring->request_list)) {
2542                 struct drm_i915_gem_request *request;
2543
2544                 request = list_first_entry(&ring->request_list,
2545                                            struct drm_i915_gem_request,
2546                                            list);
2547
2548                 i915_gem_free_request(request);
2549         }
2550
2551         /* These may not have been flush before the reset, do so now */
2552         kfree(ring->preallocated_lazy_request);
2553         ring->preallocated_lazy_request = NULL;
2554         ring->outstanding_lazy_seqno = 0;
2555 }
2556
2557 void i915_gem_restore_fences(struct drm_device *dev)
2558 {
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         int i;
2561
2562         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2563                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2564
2565                 /*
2566                  * Commit delayed tiling changes if we have an object still
2567                  * attached to the fence, otherwise just clear the fence.
2568                  */
2569                 if (reg->obj) {
2570                         i915_gem_object_update_fence(reg->obj, reg,
2571                                                      reg->obj->tiling_mode);
2572                 } else {
2573                         i915_gem_write_fence(dev, i, NULL);
2574                 }
2575         }
2576 }
2577
2578 void i915_gem_reset(struct drm_device *dev)
2579 {
2580         struct drm_i915_private *dev_priv = dev->dev_private;
2581         struct intel_engine_cs *ring;
2582         int i;
2583
2584         /*
2585          * Before we free the objects from the requests, we need to inspect
2586          * them for finding the guilty party. As the requests only borrow
2587          * their reference to the objects, the inspection must be done first.
2588          */
2589         for_each_ring(ring, dev_priv, i)
2590                 i915_gem_reset_ring_status(dev_priv, ring);
2591
2592         for_each_ring(ring, dev_priv, i)
2593                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2594
2595         i915_gem_context_reset(dev);
2596
2597         i915_gem_restore_fences(dev);
2598 }
2599
2600 /**
2601  * This function clears the request list as sequence numbers are passed.
2602  */
2603 void
2604 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2605 {
2606         uint32_t seqno;
2607
2608         if (list_empty(&ring->request_list))
2609                 return;
2610
2611         WARN_ON(i915_verify_lists(ring->dev));
2612
2613         seqno = ring->get_seqno(ring, true);
2614
2615         /* Move any buffers on the active list that are no longer referenced
2616          * by the ringbuffer to the flushing/inactive lists as appropriate,
2617          * before we free the context associated with the requests.
2618          */
2619         while (!list_empty(&ring->active_list)) {
2620                 struct drm_i915_gem_object *obj;
2621
2622                 obj = list_first_entry(&ring->active_list,
2623                                       struct drm_i915_gem_object,
2624                                       ring_list);
2625
2626                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2627                         break;
2628
2629                 i915_gem_object_move_to_inactive(obj);
2630         }
2631
2632
2633         while (!list_empty(&ring->request_list)) {
2634                 struct drm_i915_gem_request *request;
2635
2636                 request = list_first_entry(&ring->request_list,
2637                                            struct drm_i915_gem_request,
2638                                            list);
2639
2640                 if (!i915_seqno_passed(seqno, request->seqno))
2641                         break;
2642
2643                 trace_i915_gem_request_retire(ring, request->seqno);
2644                 /* We know the GPU must have read the request to have
2645                  * sent us the seqno + interrupt, so use the position
2646                  * of tail of the request to update the last known position
2647                  * of the GPU head.
2648                  */
2649                 ring->buffer->last_retired_head = request->tail;
2650
2651                 i915_gem_free_request(request);
2652         }
2653
2654         if (unlikely(ring->trace_irq_seqno &&
2655                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2656                 ring->irq_put(ring);
2657                 ring->trace_irq_seqno = 0;
2658         }
2659
2660         WARN_ON(i915_verify_lists(ring->dev));
2661 }
2662
2663 bool
2664 i915_gem_retire_requests(struct drm_device *dev)
2665 {
2666         struct drm_i915_private *dev_priv = dev->dev_private;
2667         struct intel_engine_cs *ring;
2668         bool idle = true;
2669         int i;
2670
2671         for_each_ring(ring, dev_priv, i) {
2672                 i915_gem_retire_requests_ring(ring);
2673                 idle &= list_empty(&ring->request_list);
2674         }
2675
2676         if (idle)
2677                 mod_delayed_work(dev_priv->wq,
2678                                    &dev_priv->mm.idle_work,
2679                                    msecs_to_jiffies(100));
2680
2681         return idle;
2682 }
2683
2684 static void
2685 i915_gem_retire_work_handler(struct work_struct *work)
2686 {
2687         struct drm_i915_private *dev_priv =
2688                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2689         struct drm_device *dev = dev_priv->dev;
2690         bool idle;
2691
2692         /* Come back later if the device is busy... */
2693         idle = false;
2694         if (mutex_trylock(&dev->struct_mutex)) {
2695                 idle = i915_gem_retire_requests(dev);
2696                 mutex_unlock(&dev->struct_mutex);
2697         }
2698         if (!idle)
2699                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2700                                    round_jiffies_up_relative(HZ));
2701 }
2702
2703 static void
2704 i915_gem_idle_work_handler(struct work_struct *work)
2705 {
2706         struct drm_i915_private *dev_priv =
2707                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2708
2709         intel_mark_idle(dev_priv->dev);
2710 }
2711
2712 /**
2713  * Ensures that an object will eventually get non-busy by flushing any required
2714  * write domains, emitting any outstanding lazy request and retiring and
2715  * completed requests.
2716  */
2717 static int
2718 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2719 {
2720         int ret;
2721
2722         if (obj->active) {
2723                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2724                 if (ret)
2725                         return ret;
2726
2727                 i915_gem_retire_requests_ring(obj->ring);
2728         }
2729
2730         return 0;
2731 }
2732
2733 /**
2734  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2735  * @DRM_IOCTL_ARGS: standard ioctl arguments
2736  *
2737  * Returns 0 if successful, else an error is returned with the remaining time in
2738  * the timeout parameter.
2739  *  -ETIME: object is still busy after timeout
2740  *  -ERESTARTSYS: signal interrupted the wait
2741  *  -ENONENT: object doesn't exist
2742  * Also possible, but rare:
2743  *  -EAGAIN: GPU wedged
2744  *  -ENOMEM: damn
2745  *  -ENODEV: Internal IRQ fail
2746  *  -E?: The add request failed
2747  *
2748  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2749  * non-zero timeout parameter the wait ioctl will wait for the given number of
2750  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2751  * without holding struct_mutex the object may become re-busied before this
2752  * function completes. A similar but shorter * race condition exists in the busy
2753  * ioctl
2754  */
2755 int
2756 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2757 {
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759         struct drm_i915_gem_wait *args = data;
2760         struct drm_i915_gem_object *obj;
2761         struct intel_engine_cs *ring = NULL;
2762         unsigned reset_counter;
2763         u32 seqno = 0;
2764         int ret = 0;
2765
2766         ret = i915_mutex_lock_interruptible(dev);
2767         if (ret)
2768                 return ret;
2769
2770         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2771         if (&obj->base == NULL) {
2772                 mutex_unlock(&dev->struct_mutex);
2773                 return -ENOENT;
2774         }
2775
2776         /* Need to make sure the object gets inactive eventually. */
2777         ret = i915_gem_object_flush_active(obj);
2778         if (ret)
2779                 goto out;
2780
2781         if (obj->active) {
2782                 seqno = obj->last_read_seqno;
2783                 ring = obj->ring;
2784         }
2785
2786         if (seqno == 0)
2787                  goto out;
2788
2789         /* Do this after OLR check to make sure we make forward progress polling
2790          * on this IOCTL with a timeout <=0 (like busy ioctl)
2791          */
2792         if (args->timeout_ns <= 0) {
2793                 ret = -ETIME;
2794                 goto out;
2795         }
2796
2797         drm_gem_object_unreference(&obj->base);
2798         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2799         mutex_unlock(&dev->struct_mutex);
2800
2801         return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
2802                             file->driver_priv);
2803
2804 out:
2805         drm_gem_object_unreference(&obj->base);
2806         mutex_unlock(&dev->struct_mutex);
2807         return ret;
2808 }
2809
2810 /**
2811  * i915_gem_object_sync - sync an object to a ring.
2812  *
2813  * @obj: object which may be in use on another ring.
2814  * @to: ring we wish to use the object on. May be NULL.
2815  *
2816  * This code is meant to abstract object synchronization with the GPU.
2817  * Calling with NULL implies synchronizing the object with the CPU
2818  * rather than a particular GPU ring.
2819  *
2820  * Returns 0 if successful, else propagates up the lower layer error.
2821  */
2822 int
2823 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2824                      struct intel_engine_cs *to)
2825 {
2826         struct intel_engine_cs *from = obj->ring;
2827         u32 seqno;
2828         int ret, idx;
2829
2830         if (from == NULL || to == from)
2831                 return 0;
2832
2833         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2834                 return i915_gem_object_wait_rendering(obj, false);
2835
2836         idx = intel_ring_sync_index(from, to);
2837
2838         seqno = obj->last_read_seqno;
2839         /* Optimization: Avoid semaphore sync when we are sure we already
2840          * waited for an object with higher seqno */
2841         if (seqno <= from->semaphore.sync_seqno[idx])
2842                 return 0;
2843
2844         ret = i915_gem_check_olr(obj->ring, seqno);
2845         if (ret)
2846                 return ret;
2847
2848         trace_i915_gem_ring_sync_to(from, to, seqno);
2849         ret = to->semaphore.sync_to(to, from, seqno);
2850         if (!ret)
2851                 /* We use last_read_seqno because sync_to()
2852                  * might have just caused seqno wrap under
2853                  * the radar.
2854                  */
2855                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2856
2857         return ret;
2858 }
2859
2860 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2861 {
2862         u32 old_write_domain, old_read_domains;
2863
2864         /* Force a pagefault for domain tracking on next user access */
2865         i915_gem_release_mmap(obj);
2866
2867         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2868                 return;
2869
2870         /* Wait for any direct GTT access to complete */
2871         mb();
2872
2873         old_read_domains = obj->base.read_domains;
2874         old_write_domain = obj->base.write_domain;
2875
2876         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2877         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2878
2879         trace_i915_gem_object_change_domain(obj,
2880                                             old_read_domains,
2881                                             old_write_domain);
2882 }
2883
2884 int i915_vma_unbind(struct i915_vma *vma)
2885 {
2886         struct drm_i915_gem_object *obj = vma->obj;
2887         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2888         int ret;
2889
2890         if (list_empty(&vma->vma_link))
2891                 return 0;
2892
2893         if (!drm_mm_node_allocated(&vma->node)) {
2894                 i915_gem_vma_destroy(vma);
2895                 return 0;
2896         }
2897
2898         if (vma->pin_count)
2899                 return -EBUSY;
2900
2901         BUG_ON(obj->pages == NULL);
2902
2903         ret = i915_gem_object_finish_gpu(obj);
2904         if (ret)
2905                 return ret;
2906         /* Continue on if we fail due to EIO, the GPU is hung so we
2907          * should be safe and we need to cleanup or else we might
2908          * cause memory corruption through use-after-free.
2909          */
2910
2911         if (i915_is_ggtt(vma->vm)) {
2912                 i915_gem_object_finish_gtt(obj);
2913
2914                 /* release the fence reg _after_ flushing */
2915                 ret = i915_gem_object_put_fence(obj);
2916                 if (ret)
2917                         return ret;
2918         }
2919
2920         trace_i915_vma_unbind(vma);
2921
2922         vma->unbind_vma(vma);
2923
2924         list_del_init(&vma->mm_list);
2925         /* Avoid an unnecessary call to unbind on rebind. */
2926         if (i915_is_ggtt(vma->vm))
2927                 obj->map_and_fenceable = true;
2928
2929         drm_mm_remove_node(&vma->node);
2930         i915_gem_vma_destroy(vma);
2931
2932         /* Since the unbound list is global, only move to that list if
2933          * no more VMAs exist. */
2934         if (list_empty(&obj->vma_list)) {
2935                 i915_gem_gtt_finish_object(obj);
2936                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2937         }
2938
2939         /* And finally now the object is completely decoupled from this vma,
2940          * we can drop its hold on the backing storage and allow it to be
2941          * reaped by the shrinker.
2942          */
2943         i915_gem_object_unpin_pages(obj);
2944
2945         return 0;
2946 }
2947
2948 int i915_gpu_idle(struct drm_device *dev)
2949 {
2950         struct drm_i915_private *dev_priv = dev->dev_private;
2951         struct intel_engine_cs *ring;
2952         int ret, i;
2953
2954         /* Flush everything onto the inactive list. */
2955         for_each_ring(ring, dev_priv, i) {
2956                 ret = i915_switch_context(ring, ring->default_context);
2957                 if (ret)
2958                         return ret;
2959
2960                 ret = intel_ring_idle(ring);
2961                 if (ret)
2962                         return ret;
2963         }
2964
2965         return 0;
2966 }
2967
2968 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2969                                  struct drm_i915_gem_object *obj)
2970 {
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         int fence_reg;
2973         int fence_pitch_shift;
2974
2975         if (INTEL_INFO(dev)->gen >= 6) {
2976                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2977                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2978         } else {
2979                 fence_reg = FENCE_REG_965_0;
2980                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2981         }
2982
2983         fence_reg += reg * 8;
2984
2985         /* To w/a incoherency with non-atomic 64-bit register updates,
2986          * we split the 64-bit update into two 32-bit writes. In order
2987          * for a partial fence not to be evaluated between writes, we
2988          * precede the update with write to turn off the fence register,
2989          * and only enable the fence as the last step.
2990          *
2991          * For extra levels of paranoia, we make sure each step lands
2992          * before applying the next step.
2993          */
2994         I915_WRITE(fence_reg, 0);
2995         POSTING_READ(fence_reg);
2996
2997         if (obj) {
2998                 u32 size = i915_gem_obj_ggtt_size(obj);
2999                 uint64_t val;
3000
3001                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3002                                  0xfffff000) << 32;
3003                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3004                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3005                 if (obj->tiling_mode == I915_TILING_Y)
3006                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3007                 val |= I965_FENCE_REG_VALID;
3008
3009                 I915_WRITE(fence_reg + 4, val >> 32);
3010                 POSTING_READ(fence_reg + 4);
3011
3012                 I915_WRITE(fence_reg + 0, val);
3013                 POSTING_READ(fence_reg);
3014         } else {
3015                 I915_WRITE(fence_reg + 4, 0);
3016                 POSTING_READ(fence_reg + 4);
3017         }
3018 }
3019
3020 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3021                                  struct drm_i915_gem_object *obj)
3022 {
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         u32 val;
3025
3026         if (obj) {
3027                 u32 size = i915_gem_obj_ggtt_size(obj);
3028                 int pitch_val;
3029                 int tile_width;
3030
3031                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3032                      (size & -size) != size ||
3033                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3034                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3035                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3036
3037                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3038                         tile_width = 128;
3039                 else
3040                         tile_width = 512;
3041
3042                 /* Note: pitch better be a power of two tile widths */
3043                 pitch_val = obj->stride / tile_width;
3044                 pitch_val = ffs(pitch_val) - 1;
3045
3046                 val = i915_gem_obj_ggtt_offset(obj);
3047                 if (obj->tiling_mode == I915_TILING_Y)
3048                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3049                 val |= I915_FENCE_SIZE_BITS(size);
3050                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3051                 val |= I830_FENCE_REG_VALID;
3052         } else
3053                 val = 0;
3054
3055         if (reg < 8)
3056                 reg = FENCE_REG_830_0 + reg * 4;
3057         else
3058                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3059
3060         I915_WRITE(reg, val);
3061         POSTING_READ(reg);
3062 }
3063
3064 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3065                                 struct drm_i915_gem_object *obj)
3066 {
3067         struct drm_i915_private *dev_priv = dev->dev_private;
3068         uint32_t val;
3069
3070         if (obj) {
3071                 u32 size = i915_gem_obj_ggtt_size(obj);
3072                 uint32_t pitch_val;
3073
3074                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3075                      (size & -size) != size ||
3076                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3077                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3078                      i915_gem_obj_ggtt_offset(obj), size);
3079
3080                 pitch_val = obj->stride / 128;
3081                 pitch_val = ffs(pitch_val) - 1;
3082
3083                 val = i915_gem_obj_ggtt_offset(obj);
3084                 if (obj->tiling_mode == I915_TILING_Y)
3085                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3086                 val |= I830_FENCE_SIZE_BITS(size);
3087                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3088                 val |= I830_FENCE_REG_VALID;
3089         } else
3090                 val = 0;
3091
3092         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3093         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3094 }
3095
3096 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3097 {
3098         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3099 }
3100
3101 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3102                                  struct drm_i915_gem_object *obj)
3103 {
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105
3106         /* Ensure that all CPU reads are completed before installing a fence
3107          * and all writes before removing the fence.
3108          */
3109         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3110                 mb();
3111
3112         WARN(obj && (!obj->stride || !obj->tiling_mode),
3113              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3114              obj->stride, obj->tiling_mode);
3115
3116         switch (INTEL_INFO(dev)->gen) {
3117         case 8:
3118         case 7:
3119         case 6:
3120         case 5:
3121         case 4: i965_write_fence_reg(dev, reg, obj); break;
3122         case 3: i915_write_fence_reg(dev, reg, obj); break;
3123         case 2: i830_write_fence_reg(dev, reg, obj); break;
3124         default: BUG();
3125         }
3126
3127         /* And similarly be paranoid that no direct access to this region
3128          * is reordered to before the fence is installed.
3129          */
3130         if (i915_gem_object_needs_mb(obj))
3131                 mb();
3132 }
3133
3134 static inline int fence_number(struct drm_i915_private *dev_priv,
3135                                struct drm_i915_fence_reg *fence)
3136 {
3137         return fence - dev_priv->fence_regs;
3138 }
3139
3140 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3141                                          struct drm_i915_fence_reg *fence,
3142                                          bool enable)
3143 {
3144         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3145         int reg = fence_number(dev_priv, fence);
3146
3147         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3148
3149         if (enable) {
3150                 obj->fence_reg = reg;
3151                 fence->obj = obj;
3152                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3153         } else {
3154                 obj->fence_reg = I915_FENCE_REG_NONE;
3155                 fence->obj = NULL;
3156                 list_del_init(&fence->lru_list);
3157         }
3158         obj->fence_dirty = false;
3159 }
3160
3161 static int
3162 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3163 {
3164         if (obj->last_fenced_seqno) {
3165                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3166                 if (ret)
3167                         return ret;
3168
3169                 obj->last_fenced_seqno = 0;
3170         }
3171
3172         obj->fenced_gpu_access = false;
3173         return 0;
3174 }
3175
3176 int
3177 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3178 {
3179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3180         struct drm_i915_fence_reg *fence;
3181         int ret;
3182
3183         ret = i915_gem_object_wait_fence(obj);
3184         if (ret)
3185                 return ret;
3186
3187         if (obj->fence_reg == I915_FENCE_REG_NONE)
3188                 return 0;
3189
3190         fence = &dev_priv->fence_regs[obj->fence_reg];
3191
3192         if (WARN_ON(fence->pin_count))
3193                 return -EBUSY;
3194
3195         i915_gem_object_fence_lost(obj);
3196         i915_gem_object_update_fence(obj, fence, false);
3197
3198         return 0;
3199 }
3200
3201 static struct drm_i915_fence_reg *
3202 i915_find_fence_reg(struct drm_device *dev)
3203 {
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         struct drm_i915_fence_reg *reg, *avail;
3206         int i;
3207
3208         /* First try to find a free reg */
3209         avail = NULL;
3210         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3211                 reg = &dev_priv->fence_regs[i];
3212                 if (!reg->obj)
3213                         return reg;
3214
3215                 if (!reg->pin_count)
3216                         avail = reg;
3217         }
3218
3219         if (avail == NULL)
3220                 goto deadlock;
3221
3222         /* None available, try to steal one or wait for a user to finish */
3223         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3224                 if (reg->pin_count)
3225                         continue;
3226
3227                 return reg;
3228         }
3229
3230 deadlock:
3231         /* Wait for completion of pending flips which consume fences */
3232         if (intel_has_pending_fb_unpin(dev))
3233                 return ERR_PTR(-EAGAIN);
3234
3235         return ERR_PTR(-EDEADLK);
3236 }
3237
3238 /**
3239  * i915_gem_object_get_fence - set up fencing for an object
3240  * @obj: object to map through a fence reg
3241  *
3242  * When mapping objects through the GTT, userspace wants to be able to write
3243  * to them without having to worry about swizzling if the object is tiled.
3244  * This function walks the fence regs looking for a free one for @obj,
3245  * stealing one if it can't find any.
3246  *
3247  * It then sets up the reg based on the object's properties: address, pitch
3248  * and tiling format.
3249  *
3250  * For an untiled surface, this removes any existing fence.
3251  */
3252 int
3253 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3254 {
3255         struct drm_device *dev = obj->base.dev;
3256         struct drm_i915_private *dev_priv = dev->dev_private;
3257         bool enable = obj->tiling_mode != I915_TILING_NONE;
3258         struct drm_i915_fence_reg *reg;
3259         int ret;
3260
3261         /* Have we updated the tiling parameters upon the object and so
3262          * will need to serialise the write to the associated fence register?
3263          */
3264         if (obj->fence_dirty) {
3265                 ret = i915_gem_object_wait_fence(obj);
3266                 if (ret)
3267                         return ret;
3268         }
3269
3270         /* Just update our place in the LRU if our fence is getting reused. */
3271         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3272                 reg = &dev_priv->fence_regs[obj->fence_reg];
3273                 if (!obj->fence_dirty) {
3274                         list_move_tail(&reg->lru_list,
3275                                        &dev_priv->mm.fence_list);
3276                         return 0;
3277                 }
3278         } else if (enable) {
3279                 reg = i915_find_fence_reg(dev);
3280                 if (IS_ERR(reg))
3281                         return PTR_ERR(reg);
3282
3283                 if (reg->obj) {
3284                         struct drm_i915_gem_object *old = reg->obj;
3285
3286                         ret = i915_gem_object_wait_fence(old);
3287                         if (ret)
3288                                 return ret;
3289
3290                         i915_gem_object_fence_lost(old);
3291                 }
3292         } else
3293                 return 0;
3294
3295         i915_gem_object_update_fence(obj, reg, enable);
3296
3297         return 0;
3298 }
3299
3300 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3301                                      struct drm_mm_node *gtt_space,
3302                                      unsigned long cache_level)
3303 {
3304         struct drm_mm_node *other;
3305
3306         /* On non-LLC machines we have to be careful when putting differing
3307          * types of snoopable memory together to avoid the prefetcher
3308          * crossing memory domains and dying.
3309          */
3310         if (HAS_LLC(dev))
3311                 return true;
3312
3313         if (!drm_mm_node_allocated(gtt_space))
3314                 return true;
3315
3316         if (list_empty(&gtt_space->node_list))
3317                 return true;
3318
3319         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3320         if (other->allocated && !other->hole_follows && other->color != cache_level)
3321                 return false;
3322
3323         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3324         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3325                 return false;
3326
3327         return true;
3328 }
3329
3330 static void i915_gem_verify_gtt(struct drm_device *dev)
3331 {
3332 #if WATCH_GTT
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334         struct drm_i915_gem_object *obj;
3335         int err = 0;
3336
3337         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3338                 if (obj->gtt_space == NULL) {
3339                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3340                         err++;
3341                         continue;
3342                 }
3343
3344                 if (obj->cache_level != obj->gtt_space->color) {
3345                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3346                                i915_gem_obj_ggtt_offset(obj),
3347                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3348                                obj->cache_level,
3349                                obj->gtt_space->color);
3350                         err++;
3351                         continue;
3352                 }
3353
3354                 if (!i915_gem_valid_gtt_space(dev,
3355                                               obj->gtt_space,
3356                                               obj->cache_level)) {
3357                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3358                                i915_gem_obj_ggtt_offset(obj),
3359                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3360                                obj->cache_level);
3361                         err++;
3362                         continue;
3363                 }
3364         }
3365
3366         WARN_ON(err);
3367 #endif
3368 }
3369
3370 /**
3371  * Finds free space in the GTT aperture and binds the object there.
3372  */
3373 static struct i915_vma *
3374 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3375                            struct i915_address_space *vm,
3376                            unsigned alignment,
3377                            uint64_t flags)
3378 {
3379         struct drm_device *dev = obj->base.dev;
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381         u32 size, fence_size, fence_alignment, unfenced_alignment;
3382         unsigned long start =
3383                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3384         unsigned long end =
3385                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3386         struct i915_vma *vma;
3387         int ret;
3388
3389         fence_size = i915_gem_get_gtt_size(dev,
3390                                            obj->base.size,
3391                                            obj->tiling_mode);
3392         fence_alignment = i915_gem_get_gtt_alignment(dev,
3393                                                      obj->base.size,
3394                                                      obj->tiling_mode, true);
3395         unfenced_alignment =
3396                 i915_gem_get_gtt_alignment(dev,
3397                                            obj->base.size,
3398                                            obj->tiling_mode, false);
3399
3400         if (alignment == 0)
3401                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3402                                                 unfenced_alignment;
3403         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3404                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3405                 return ERR_PTR(-EINVAL);
3406         }
3407
3408         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3409
3410         /* If the object is bigger than the entire aperture, reject it early
3411          * before evicting everything in a vain attempt to find space.
3412          */
3413         if (obj->base.size > end) {
3414                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3415                           obj->base.size,
3416                           flags & PIN_MAPPABLE ? "mappable" : "total",
3417                           end);
3418                 return ERR_PTR(-E2BIG);
3419         }
3420
3421         ret = i915_gem_object_get_pages(obj);
3422         if (ret)
3423                 return ERR_PTR(ret);
3424
3425         i915_gem_object_pin_pages(obj);
3426
3427         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3428         if (IS_ERR(vma))
3429                 goto err_unpin;
3430
3431 search_free:
3432         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3433                                                   size, alignment,
3434                                                   obj->cache_level,
3435                                                   start, end,
3436                                                   DRM_MM_SEARCH_DEFAULT,
3437                                                   DRM_MM_CREATE_DEFAULT);
3438         if (ret) {
3439                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3440                                                obj->cache_level,
3441                                                start, end,
3442                                                flags);
3443                 if (ret == 0)
3444                         goto search_free;
3445
3446                 goto err_free_vma;
3447         }
3448         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3449                                               obj->cache_level))) {
3450                 ret = -EINVAL;
3451                 goto err_remove_node;
3452         }
3453
3454         ret = i915_gem_gtt_prepare_object(obj);
3455         if (ret)
3456                 goto err_remove_node;
3457
3458         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3459         list_add_tail(&vma->mm_list, &vm->inactive_list);
3460
3461         if (i915_is_ggtt(vm)) {
3462                 bool mappable, fenceable;
3463
3464                 fenceable = (vma->node.size == fence_size &&
3465                              (vma->node.start & (fence_alignment - 1)) == 0);
3466
3467                 mappable = (vma->node.start + obj->base.size <=
3468                             dev_priv->gtt.mappable_end);
3469
3470                 obj->map_and_fenceable = mappable && fenceable;
3471         }
3472
3473         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3474
3475         trace_i915_vma_bind(vma, flags);
3476         vma->bind_vma(vma, obj->cache_level,
3477                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3478
3479         i915_gem_verify_gtt(dev);
3480         return vma;
3481
3482 err_remove_node:
3483         drm_mm_remove_node(&vma->node);
3484 err_free_vma:
3485         i915_gem_vma_destroy(vma);
3486         vma = ERR_PTR(ret);
3487 err_unpin:
3488         i915_gem_object_unpin_pages(obj);
3489         return vma;
3490 }
3491
3492 bool
3493 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3494                         bool force)
3495 {
3496         /* If we don't have a page list set up, then we're not pinned
3497          * to GPU, and we can ignore the cache flush because it'll happen
3498          * again at bind time.
3499          */
3500         if (obj->pages == NULL)
3501                 return false;
3502
3503         /*
3504          * Stolen memory is always coherent with the GPU as it is explicitly
3505          * marked as wc by the system, or the system is cache-coherent.
3506          */
3507         if (obj->stolen)
3508                 return false;
3509
3510         /* If the GPU is snooping the contents of the CPU cache,
3511          * we do not need to manually clear the CPU cache lines.  However,
3512          * the caches are only snooped when the render cache is
3513          * flushed/invalidated.  As we always have to emit invalidations
3514          * and flushes when moving into and out of the RENDER domain, correct
3515          * snooping behaviour occurs naturally as the result of our domain
3516          * tracking.
3517          */
3518         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3519                 return false;
3520
3521         trace_i915_gem_object_clflush(obj);
3522         drm_clflush_sg(obj->pages);
3523
3524         return true;
3525 }
3526
3527 /** Flushes the GTT write domain for the object if it's dirty. */
3528 static void
3529 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3530 {
3531         uint32_t old_write_domain;
3532
3533         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3534                 return;
3535
3536         /* No actual flushing is required for the GTT write domain.  Writes
3537          * to it immediately go to main memory as far as we know, so there's
3538          * no chipset flush.  It also doesn't land in render cache.
3539          *
3540          * However, we do have to enforce the order so that all writes through
3541          * the GTT land before any writes to the device, such as updates to
3542          * the GATT itself.
3543          */
3544         wmb();
3545
3546         old_write_domain = obj->base.write_domain;
3547         obj->base.write_domain = 0;
3548
3549         intel_fb_obj_flush(obj, false);
3550
3551         trace_i915_gem_object_change_domain(obj,
3552                                             obj->base.read_domains,
3553                                             old_write_domain);
3554 }
3555
3556 /** Flushes the CPU write domain for the object if it's dirty. */
3557 static void
3558 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3559                                        bool force)
3560 {
3561         uint32_t old_write_domain;
3562
3563         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3564                 return;
3565
3566         if (i915_gem_clflush_object(obj, force))
3567                 i915_gem_chipset_flush(obj->base.dev);
3568
3569         old_write_domain = obj->base.write_domain;
3570         obj->base.write_domain = 0;
3571
3572         intel_fb_obj_flush(obj, false);
3573
3574         trace_i915_gem_object_change_domain(obj,
3575                                             obj->base.read_domains,
3576                                             old_write_domain);
3577 }
3578
3579 /**
3580  * Moves a single object to the GTT read, and possibly write domain.
3581  *
3582  * This function returns when the move is complete, including waiting on
3583  * flushes to occur.
3584  */
3585 int
3586 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3587 {
3588         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3589         uint32_t old_write_domain, old_read_domains;
3590         int ret;
3591
3592         /* Not valid to be called on unbound objects. */
3593         if (!i915_gem_obj_bound_any(obj))
3594                 return -EINVAL;
3595
3596         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3597                 return 0;
3598
3599         ret = i915_gem_object_wait_rendering(obj, !write);
3600         if (ret)
3601                 return ret;
3602
3603         i915_gem_object_retire(obj);
3604         i915_gem_object_flush_cpu_write_domain(obj, false);
3605
3606         /* Serialise direct access to this object with the barriers for
3607          * coherent writes from the GPU, by effectively invalidating the
3608          * GTT domain upon first access.
3609          */
3610         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3611                 mb();
3612
3613         old_write_domain = obj->base.write_domain;
3614         old_read_domains = obj->base.read_domains;
3615
3616         /* It should now be out of any other write domains, and we can update
3617          * the domain values for our changes.
3618          */
3619         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3620         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3621         if (write) {
3622                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3623                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3624                 obj->dirty = 1;
3625         }
3626
3627         if (write)
3628                 intel_fb_obj_invalidate(obj, NULL);
3629
3630         trace_i915_gem_object_change_domain(obj,
3631                                             old_read_domains,
3632                                             old_write_domain);
3633
3634         /* And bump the LRU for this access */
3635         if (i915_gem_object_is_inactive(obj)) {
3636                 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3637                 if (vma)
3638                         list_move_tail(&vma->mm_list,
3639                                        &dev_priv->gtt.base.inactive_list);
3640
3641         }
3642
3643         return 0;
3644 }
3645
3646 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3647                                     enum i915_cache_level cache_level)
3648 {
3649         struct drm_device *dev = obj->base.dev;
3650         struct i915_vma *vma, *next;
3651         int ret;
3652
3653         if (obj->cache_level == cache_level)
3654                 return 0;
3655
3656         if (i915_gem_obj_is_pinned(obj)) {
3657                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3658                 return -EBUSY;
3659         }
3660
3661         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3662                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3663                         ret = i915_vma_unbind(vma);
3664                         if (ret)
3665                                 return ret;
3666                 }
3667         }
3668
3669         if (i915_gem_obj_bound_any(obj)) {
3670                 ret = i915_gem_object_finish_gpu(obj);
3671                 if (ret)
3672                         return ret;
3673
3674                 i915_gem_object_finish_gtt(obj);
3675
3676                 /* Before SandyBridge, you could not use tiling or fence
3677                  * registers with snooped memory, so relinquish any fences
3678                  * currently pointing to our region in the aperture.
3679                  */
3680                 if (INTEL_INFO(dev)->gen < 6) {
3681                         ret = i915_gem_object_put_fence(obj);
3682                         if (ret)
3683                                 return ret;
3684                 }
3685
3686                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3687                         if (drm_mm_node_allocated(&vma->node))
3688                                 vma->bind_vma(vma, cache_level,
3689                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3690         }
3691
3692         list_for_each_entry(vma, &obj->vma_list, vma_link)
3693                 vma->node.color = cache_level;
3694         obj->cache_level = cache_level;
3695
3696         if (cpu_write_needs_clflush(obj)) {
3697                 u32 old_read_domains, old_write_domain;
3698
3699                 /* If we're coming from LLC cached, then we haven't
3700                  * actually been tracking whether the data is in the
3701                  * CPU cache or not, since we only allow one bit set
3702                  * in obj->write_domain and have been skipping the clflushes.
3703                  * Just set it to the CPU cache for now.
3704                  */
3705                 i915_gem_object_retire(obj);
3706                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3707
3708                 old_read_domains = obj->base.read_domains;
3709                 old_write_domain = obj->base.write_domain;
3710
3711                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3712                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3713
3714                 trace_i915_gem_object_change_domain(obj,
3715                                                     old_read_domains,
3716                                                     old_write_domain);
3717         }
3718
3719         i915_gem_verify_gtt(dev);
3720         return 0;
3721 }
3722
3723 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3724                                struct drm_file *file)
3725 {
3726         struct drm_i915_gem_caching *args = data;
3727         struct drm_i915_gem_object *obj;
3728         int ret;
3729
3730         ret = i915_mutex_lock_interruptible(dev);
3731         if (ret)
3732                 return ret;
3733
3734         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3735         if (&obj->base == NULL) {
3736                 ret = -ENOENT;
3737                 goto unlock;
3738         }
3739
3740         switch (obj->cache_level) {
3741         case I915_CACHE_LLC:
3742         case I915_CACHE_L3_LLC:
3743                 args->caching = I915_CACHING_CACHED;
3744                 break;
3745
3746         case I915_CACHE_WT:
3747                 args->caching = I915_CACHING_DISPLAY;
3748                 break;
3749
3750         default:
3751                 args->caching = I915_CACHING_NONE;
3752                 break;
3753         }
3754
3755         drm_gem_object_unreference(&obj->base);
3756 unlock:
3757         mutex_unlock(&dev->struct_mutex);
3758         return ret;
3759 }
3760
3761 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3762                                struct drm_file *file)
3763 {
3764         struct drm_i915_gem_caching *args = data;
3765         struct drm_i915_gem_object *obj;
3766         enum i915_cache_level level;
3767         int ret;
3768
3769         switch (args->caching) {
3770         case I915_CACHING_NONE:
3771                 level = I915_CACHE_NONE;
3772                 break;
3773         case I915_CACHING_CACHED:
3774                 level = I915_CACHE_LLC;
3775                 break;
3776         case I915_CACHING_DISPLAY:
3777                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3778                 break;
3779         default:
3780                 return -EINVAL;
3781         }
3782
3783         ret = i915_mutex_lock_interruptible(dev);
3784         if (ret)
3785                 return ret;
3786
3787         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3788         if (&obj->base == NULL) {
3789                 ret = -ENOENT;
3790                 goto unlock;
3791         }
3792
3793         ret = i915_gem_object_set_cache_level(obj, level);
3794
3795         drm_gem_object_unreference(&obj->base);
3796 unlock:
3797         mutex_unlock(&dev->struct_mutex);
3798         return ret;
3799 }
3800
3801 static bool is_pin_display(struct drm_i915_gem_object *obj)
3802 {
3803         struct i915_vma *vma;
3804
3805         if (list_empty(&obj->vma_list))
3806                 return false;
3807
3808         vma = i915_gem_obj_to_ggtt(obj);
3809         if (!vma)
3810                 return false;
3811
3812         /* There are 3 sources that pin objects:
3813          *   1. The display engine (scanouts, sprites, cursors);
3814          *   2. Reservations for execbuffer;
3815          *   3. The user.
3816          *
3817          * We can ignore reservations as we hold the struct_mutex and
3818          * are only called outside of the reservation path.  The user
3819          * can only increment pin_count once, and so if after
3820          * subtracting the potential reference by the user, any pin_count
3821          * remains, it must be due to another use by the display engine.
3822          */
3823         return vma->pin_count - !!obj->user_pin_count;
3824 }
3825
3826 /*
3827  * Prepare buffer for display plane (scanout, cursors, etc).
3828  * Can be called from an uninterruptible phase (modesetting) and allows
3829  * any flushes to be pipelined (for pageflips).
3830  */
3831 int
3832 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3833                                      u32 alignment,
3834                                      struct intel_engine_cs *pipelined)
3835 {
3836         u32 old_read_domains, old_write_domain;
3837         bool was_pin_display;
3838         int ret;
3839
3840         if (pipelined != obj->ring) {
3841                 ret = i915_gem_object_sync(obj, pipelined);
3842                 if (ret)
3843                         return ret;
3844         }
3845
3846         /* Mark the pin_display early so that we account for the
3847          * display coherency whilst setting up the cache domains.
3848          */
3849         was_pin_display = obj->pin_display;
3850         obj->pin_display = true;
3851
3852         /* The display engine is not coherent with the LLC cache on gen6.  As
3853          * a result, we make sure that the pinning that is about to occur is
3854          * done with uncached PTEs. This is lowest common denominator for all
3855          * chipsets.
3856          *
3857          * However for gen6+, we could do better by using the GFDT bit instead
3858          * of uncaching, which would allow us to flush all the LLC-cached data
3859          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3860          */
3861         ret = i915_gem_object_set_cache_level(obj,
3862                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3863         if (ret)
3864                 goto err_unpin_display;
3865
3866         /* As the user may map the buffer once pinned in the display plane
3867          * (e.g. libkms for the bootup splash), we have to ensure that we
3868          * always use map_and_fenceable for all scanout buffers.
3869          */
3870         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3871         if (ret)
3872                 goto err_unpin_display;
3873
3874         i915_gem_object_flush_cpu_write_domain(obj, true);
3875
3876         old_write_domain = obj->base.write_domain;
3877         old_read_domains = obj->base.read_domains;
3878
3879         /* It should now be out of any other write domains, and we can update
3880          * the domain values for our changes.
3881          */
3882         obj->base.write_domain = 0;
3883         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3884
3885         trace_i915_gem_object_change_domain(obj,
3886                                             old_read_domains,
3887                                             old_write_domain);
3888
3889         return 0;
3890
3891 err_unpin_display:
3892         WARN_ON(was_pin_display != is_pin_display(obj));
3893         obj->pin_display = was_pin_display;
3894         return ret;
3895 }
3896
3897 void
3898 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3899 {
3900         i915_gem_object_ggtt_unpin(obj);
3901         obj->pin_display = is_pin_display(obj);
3902 }
3903
3904 int
3905 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3906 {
3907         int ret;
3908
3909         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3910                 return 0;
3911
3912         ret = i915_gem_object_wait_rendering(obj, false);
3913         if (ret)
3914                 return ret;
3915
3916         /* Ensure that we invalidate the GPU's caches and TLBs. */
3917         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3918         return 0;
3919 }
3920
3921 /**
3922  * Moves a single object to the CPU read, and possibly write domain.
3923  *
3924  * This function returns when the move is complete, including waiting on
3925  * flushes to occur.
3926  */
3927 int
3928 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3929 {
3930         uint32_t old_write_domain, old_read_domains;
3931         int ret;
3932
3933         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3934                 return 0;
3935
3936         ret = i915_gem_object_wait_rendering(obj, !write);
3937         if (ret)
3938                 return ret;
3939
3940         i915_gem_object_retire(obj);
3941         i915_gem_object_flush_gtt_write_domain(obj);
3942
3943         old_write_domain = obj->base.write_domain;
3944         old_read_domains = obj->base.read_domains;
3945
3946         /* Flush the CPU cache if it's still invalid. */
3947         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3948                 i915_gem_clflush_object(obj, false);
3949
3950                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3951         }
3952
3953         /* It should now be out of any other write domains, and we can update
3954          * the domain values for our changes.
3955          */
3956         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3957
3958         /* If we're writing through the CPU, then the GPU read domains will
3959          * need to be invalidated at next use.
3960          */
3961         if (write) {
3962                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3963                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3964         }
3965
3966         if (write)
3967                 intel_fb_obj_invalidate(obj, NULL);
3968
3969         trace_i915_gem_object_change_domain(obj,
3970                                             old_read_domains,
3971                                             old_write_domain);
3972
3973         return 0;
3974 }
3975
3976 /* Throttle our rendering by waiting until the ring has completed our requests
3977  * emitted over 20 msec ago.
3978  *
3979  * Note that if we were to use the current jiffies each time around the loop,
3980  * we wouldn't escape the function with any frames outstanding if the time to
3981  * render a frame was over 20ms.
3982  *
3983  * This should get us reasonable parallelism between CPU and GPU but also
3984  * relatively low latency when blocking on a particular request to finish.
3985  */
3986 static int
3987 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3988 {
3989         struct drm_i915_private *dev_priv = dev->dev_private;
3990         struct drm_i915_file_private *file_priv = file->driver_priv;
3991         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3992         struct drm_i915_gem_request *request;
3993         struct intel_engine_cs *ring = NULL;
3994         unsigned reset_counter;
3995         u32 seqno = 0;
3996         int ret;
3997
3998         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3999         if (ret)
4000                 return ret;
4001
4002         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4003         if (ret)
4004                 return ret;
4005
4006         spin_lock(&file_priv->mm.lock);
4007         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4008                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4009                         break;
4010
4011                 ring = request->ring;
4012                 seqno = request->seqno;
4013         }
4014         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4015         spin_unlock(&file_priv->mm.lock);
4016
4017         if (seqno == 0)
4018                 return 0;
4019
4020         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4021         if (ret == 0)
4022                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4023
4024         return ret;
4025 }
4026
4027 static bool
4028 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4029 {
4030         struct drm_i915_gem_object *obj = vma->obj;
4031
4032         if (alignment &&
4033             vma->node.start & (alignment - 1))
4034                 return true;
4035
4036         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4037                 return true;
4038
4039         if (flags & PIN_OFFSET_BIAS &&
4040             vma->node.start < (flags & PIN_OFFSET_MASK))
4041                 return true;
4042
4043         return false;
4044 }
4045
4046 int
4047 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4048                     struct i915_address_space *vm,
4049                     uint32_t alignment,
4050                     uint64_t flags)
4051 {
4052         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4053         struct i915_vma *vma;
4054         int ret;
4055
4056         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4057                 return -ENODEV;
4058
4059         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4060                 return -EINVAL;
4061
4062         vma = i915_gem_obj_to_vma(obj, vm);
4063         if (vma) {
4064                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4065                         return -EBUSY;
4066
4067                 if (i915_vma_misplaced(vma, alignment, flags)) {
4068                         WARN(vma->pin_count,
4069                              "bo is already pinned with incorrect alignment:"
4070                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4071                              " obj->map_and_fenceable=%d\n",
4072                              i915_gem_obj_offset(obj, vm), alignment,
4073                              !!(flags & PIN_MAPPABLE),
4074                              obj->map_and_fenceable);
4075                         ret = i915_vma_unbind(vma);
4076                         if (ret)
4077                                 return ret;
4078
4079                         vma = NULL;
4080                 }
4081         }
4082
4083         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4084                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4085                 if (IS_ERR(vma))
4086                         return PTR_ERR(vma);
4087         }
4088
4089         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4090                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4091
4092         vma->pin_count++;
4093         if (flags & PIN_MAPPABLE)
4094                 obj->pin_mappable |= true;
4095
4096         return 0;
4097 }
4098
4099 void
4100 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4101 {
4102         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4103
4104         BUG_ON(!vma);
4105         BUG_ON(vma->pin_count == 0);
4106         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4107
4108         if (--vma->pin_count == 0)
4109                 obj->pin_mappable = false;
4110 }
4111
4112 bool
4113 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4114 {
4115         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4116                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4117                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4118
4119                 WARN_ON(!ggtt_vma ||
4120                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4121                         ggtt_vma->pin_count);
4122                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4123                 return true;
4124         } else
4125                 return false;
4126 }
4127
4128 void
4129 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4130 {
4131         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4132                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4133                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4134                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4135         }
4136 }
4137
4138 int
4139 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4140                    struct drm_file *file)
4141 {
4142         struct drm_i915_gem_pin *args = data;
4143         struct drm_i915_gem_object *obj;
4144         int ret;
4145
4146         if (INTEL_INFO(dev)->gen >= 6)
4147                 return -ENODEV;
4148
4149         ret = i915_mutex_lock_interruptible(dev);
4150         if (ret)
4151                 return ret;
4152
4153         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4154         if (&obj->base == NULL) {
4155                 ret = -ENOENT;
4156                 goto unlock;
4157         }
4158
4159         if (obj->madv != I915_MADV_WILLNEED) {
4160                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4161                 ret = -EFAULT;
4162                 goto out;
4163         }
4164
4165         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4166                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4167                           args->handle);
4168                 ret = -EINVAL;
4169                 goto out;
4170         }
4171
4172         if (obj->user_pin_count == ULONG_MAX) {
4173                 ret = -EBUSY;
4174                 goto out;
4175         }
4176
4177         if (obj->user_pin_count == 0) {
4178                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4179                 if (ret)
4180                         goto out;
4181         }
4182
4183         obj->user_pin_count++;
4184         obj->pin_filp = file;
4185
4186         args->offset = i915_gem_obj_ggtt_offset(obj);
4187 out:
4188         drm_gem_object_unreference(&obj->base);
4189 unlock:
4190         mutex_unlock(&dev->struct_mutex);
4191         return ret;
4192 }
4193
4194 int
4195 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4196                      struct drm_file *file)
4197 {
4198         struct drm_i915_gem_pin *args = data;
4199         struct drm_i915_gem_object *obj;
4200         int ret;
4201
4202         ret = i915_mutex_lock_interruptible(dev);
4203         if (ret)
4204                 return ret;
4205
4206         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4207         if (&obj->base == NULL) {
4208                 ret = -ENOENT;
4209                 goto unlock;
4210         }
4211
4212         if (obj->pin_filp != file) {
4213                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4214                           args->handle);
4215                 ret = -EINVAL;
4216                 goto out;
4217         }
4218         obj->user_pin_count--;
4219         if (obj->user_pin_count == 0) {
4220                 obj->pin_filp = NULL;
4221                 i915_gem_object_ggtt_unpin(obj);
4222         }
4223
4224 out:
4225         drm_gem_object_unreference(&obj->base);
4226 unlock:
4227         mutex_unlock(&dev->struct_mutex);
4228         return ret;
4229 }
4230
4231 int
4232 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4233                     struct drm_file *file)
4234 {
4235         struct drm_i915_gem_busy *args = data;
4236         struct drm_i915_gem_object *obj;
4237         int ret;
4238
4239         ret = i915_mutex_lock_interruptible(dev);
4240         if (ret)
4241                 return ret;
4242
4243         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4244         if (&obj->base == NULL) {
4245                 ret = -ENOENT;
4246                 goto unlock;
4247         }
4248
4249         /* Count all active objects as busy, even if they are currently not used
4250          * by the gpu. Users of this interface expect objects to eventually
4251          * become non-busy without any further actions, therefore emit any
4252          * necessary flushes here.
4253          */
4254         ret = i915_gem_object_flush_active(obj);
4255
4256         args->busy = obj->active;
4257         if (obj->ring) {
4258                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4259                 args->busy |= intel_ring_flag(obj->ring) << 16;
4260         }
4261
4262         drm_gem_object_unreference(&obj->base);
4263 unlock:
4264         mutex_unlock(&dev->struct_mutex);
4265         return ret;
4266 }
4267
4268 int
4269 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4270                         struct drm_file *file_priv)
4271 {
4272         return i915_gem_ring_throttle(dev, file_priv);
4273 }
4274
4275 int
4276 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4277                        struct drm_file *file_priv)
4278 {
4279         struct drm_i915_gem_madvise *args = data;
4280         struct drm_i915_gem_object *obj;
4281         int ret;
4282
4283         switch (args->madv) {
4284         case I915_MADV_DONTNEED:
4285         case I915_MADV_WILLNEED:
4286             break;
4287         default:
4288             return -EINVAL;
4289         }
4290
4291         ret = i915_mutex_lock_interruptible(dev);
4292         if (ret)
4293                 return ret;
4294
4295         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4296         if (&obj->base == NULL) {
4297                 ret = -ENOENT;
4298                 goto unlock;
4299         }
4300
4301         if (i915_gem_obj_is_pinned(obj)) {
4302                 ret = -EINVAL;
4303                 goto out;
4304         }
4305
4306         if (obj->madv != __I915_MADV_PURGED)
4307                 obj->madv = args->madv;
4308
4309         /* if the object is no longer attached, discard its backing storage */
4310         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4311                 i915_gem_object_truncate(obj);
4312
4313         args->retained = obj->madv != __I915_MADV_PURGED;
4314
4315 out:
4316         drm_gem_object_unreference(&obj->base);
4317 unlock:
4318         mutex_unlock(&dev->struct_mutex);
4319         return ret;
4320 }
4321
4322 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4323                           const struct drm_i915_gem_object_ops *ops)
4324 {
4325         INIT_LIST_HEAD(&obj->global_list);
4326         INIT_LIST_HEAD(&obj->ring_list);
4327         INIT_LIST_HEAD(&obj->obj_exec_link);
4328         INIT_LIST_HEAD(&obj->vma_list);
4329
4330         obj->ops = ops;
4331
4332         obj->fence_reg = I915_FENCE_REG_NONE;
4333         obj->madv = I915_MADV_WILLNEED;
4334         /* Avoid an unnecessary call to unbind on the first bind. */
4335         obj->map_and_fenceable = true;
4336
4337         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4338 }
4339
4340 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4341         .get_pages = i915_gem_object_get_pages_gtt,
4342         .put_pages = i915_gem_object_put_pages_gtt,
4343 };
4344
4345 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4346                                                   size_t size)
4347 {
4348         struct drm_i915_gem_object *obj;
4349         struct address_space *mapping;
4350         gfp_t mask;
4351
4352         obj = i915_gem_object_alloc(dev);
4353         if (obj == NULL)
4354                 return NULL;
4355
4356         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4357                 i915_gem_object_free(obj);
4358                 return NULL;
4359         }
4360
4361         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4362         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4363                 /* 965gm cannot relocate objects above 4GiB. */
4364                 mask &= ~__GFP_HIGHMEM;
4365                 mask |= __GFP_DMA32;
4366         }
4367
4368         mapping = file_inode(obj->base.filp)->i_mapping;
4369         mapping_set_gfp_mask(mapping, mask);
4370
4371         i915_gem_object_init(obj, &i915_gem_object_ops);
4372
4373         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4374         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4375
4376         if (HAS_LLC(dev)) {
4377                 /* On some devices, we can have the GPU use the LLC (the CPU
4378                  * cache) for about a 10% performance improvement
4379                  * compared to uncached.  Graphics requests other than
4380                  * display scanout are coherent with the CPU in
4381                  * accessing this cache.  This means in this mode we
4382                  * don't need to clflush on the CPU side, and on the
4383                  * GPU side we only need to flush internal caches to
4384                  * get data visible to the CPU.
4385                  *
4386                  * However, we maintain the display planes as UC, and so
4387                  * need to rebind when first used as such.
4388                  */
4389                 obj->cache_level = I915_CACHE_LLC;
4390         } else
4391                 obj->cache_level = I915_CACHE_NONE;
4392
4393         trace_i915_gem_object_create(obj);
4394
4395         return obj;
4396 }
4397
4398 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4399 {
4400         /* If we are the last user of the backing storage (be it shmemfs
4401          * pages or stolen etc), we know that the pages are going to be
4402          * immediately released. In this case, we can then skip copying
4403          * back the contents from the GPU.
4404          */
4405
4406         if (obj->madv != I915_MADV_WILLNEED)
4407                 return false;
4408
4409         if (obj->base.filp == NULL)
4410                 return true;
4411
4412         /* At first glance, this looks racy, but then again so would be
4413          * userspace racing mmap against close. However, the first external
4414          * reference to the filp can only be obtained through the
4415          * i915_gem_mmap_ioctl() which safeguards us against the user
4416          * acquiring such a reference whilst we are in the middle of
4417          * freeing the object.
4418          */
4419         return atomic_long_read(&obj->base.filp->f_count) == 1;
4420 }
4421
4422 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4423 {
4424         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4425         struct drm_device *dev = obj->base.dev;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         struct i915_vma *vma, *next;
4428
4429         intel_runtime_pm_get(dev_priv);
4430
4431         trace_i915_gem_object_destroy(obj);
4432
4433         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4434                 int ret;
4435
4436                 vma->pin_count = 0;
4437                 ret = i915_vma_unbind(vma);
4438                 if (WARN_ON(ret == -ERESTARTSYS)) {
4439                         bool was_interruptible;
4440
4441                         was_interruptible = dev_priv->mm.interruptible;
4442                         dev_priv->mm.interruptible = false;
4443
4444                         WARN_ON(i915_vma_unbind(vma));
4445
4446                         dev_priv->mm.interruptible = was_interruptible;
4447                 }
4448         }
4449
4450         i915_gem_object_detach_phys(obj);
4451
4452         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4453          * before progressing. */
4454         if (obj->stolen)
4455                 i915_gem_object_unpin_pages(obj);
4456
4457         WARN_ON(obj->frontbuffer_bits);
4458
4459         if (WARN_ON(obj->pages_pin_count))
4460                 obj->pages_pin_count = 0;
4461         if (discard_backing_storage(obj))
4462                 obj->madv = I915_MADV_DONTNEED;
4463         i915_gem_object_put_pages(obj);
4464         i915_gem_object_free_mmap_offset(obj);
4465
4466         BUG_ON(obj->pages);
4467
4468         if (obj->base.import_attach)
4469                 drm_prime_gem_destroy(&obj->base, NULL);
4470
4471         if (obj->ops->release)
4472                 obj->ops->release(obj);
4473
4474         drm_gem_object_release(&obj->base);
4475         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4476
4477         kfree(obj->bit_17);
4478         i915_gem_object_free(obj);
4479
4480         intel_runtime_pm_put(dev_priv);
4481 }
4482
4483 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4484                                      struct i915_address_space *vm)
4485 {
4486         struct i915_vma *vma;
4487         list_for_each_entry(vma, &obj->vma_list, vma_link)
4488                 if (vma->vm == vm)
4489                         return vma;
4490
4491         return NULL;
4492 }
4493
4494 void i915_gem_vma_destroy(struct i915_vma *vma)
4495 {
4496         WARN_ON(vma->node.allocated);
4497
4498         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4499         if (!list_empty(&vma->exec_list))
4500                 return;
4501
4502         list_del(&vma->vma_link);
4503
4504         kfree(vma);
4505 }
4506
4507 static void
4508 i915_gem_stop_ringbuffers(struct drm_device *dev)
4509 {
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511         struct intel_engine_cs *ring;
4512         int i;
4513
4514         for_each_ring(ring, dev_priv, i)
4515                 intel_stop_ring_buffer(ring);
4516 }
4517
4518 int
4519 i915_gem_suspend(struct drm_device *dev)
4520 {
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522         int ret = 0;
4523
4524         mutex_lock(&dev->struct_mutex);
4525         if (dev_priv->ums.mm_suspended)
4526                 goto err;
4527
4528         ret = i915_gpu_idle(dev);
4529         if (ret)
4530                 goto err;
4531
4532         i915_gem_retire_requests(dev);
4533
4534         /* Under UMS, be paranoid and evict. */
4535         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4536                 i915_gem_evict_everything(dev);
4537
4538         i915_kernel_lost_context(dev);
4539         i915_gem_stop_ringbuffers(dev);
4540
4541         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4542          * We need to replace this with a semaphore, or something.
4543          * And not confound ums.mm_suspended!
4544          */
4545         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4546                                                              DRIVER_MODESET);
4547         mutex_unlock(&dev->struct_mutex);
4548
4549         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4550         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4551         flush_delayed_work(&dev_priv->mm.idle_work);
4552
4553         return 0;
4554
4555 err:
4556         mutex_unlock(&dev->struct_mutex);
4557         return ret;
4558 }
4559
4560 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4561 {
4562         struct drm_device *dev = ring->dev;
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4565         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4566         int i, ret;
4567
4568         if (!HAS_L3_DPF(dev) || !remap_info)
4569                 return 0;
4570
4571         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4572         if (ret)
4573                 return ret;
4574
4575         /*
4576          * Note: We do not worry about the concurrent register cacheline hang
4577          * here because no other code should access these registers other than
4578          * at initialization time.
4579          */
4580         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4581                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4582                 intel_ring_emit(ring, reg_base + i);
4583                 intel_ring_emit(ring, remap_info[i/4]);
4584         }
4585
4586         intel_ring_advance(ring);
4587
4588         return ret;
4589 }
4590
4591 void i915_gem_init_swizzling(struct drm_device *dev)
4592 {
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594
4595         if (INTEL_INFO(dev)->gen < 5 ||
4596             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4597                 return;
4598
4599         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4600                                  DISP_TILE_SURFACE_SWIZZLING);
4601
4602         if (IS_GEN5(dev))
4603                 return;
4604
4605         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4606         if (IS_GEN6(dev))
4607                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4608         else if (IS_GEN7(dev))
4609                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4610         else if (IS_GEN8(dev))
4611                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4612         else
4613                 BUG();
4614 }
4615
4616 static bool
4617 intel_enable_blt(struct drm_device *dev)
4618 {
4619         if (!HAS_BLT(dev))
4620                 return false;
4621
4622         /* The blitter was dysfunctional on early prototypes */
4623         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4624                 DRM_INFO("BLT not supported on this pre-production hardware;"
4625                          " graphics performance will be degraded.\n");
4626                 return false;
4627         }
4628
4629         return true;
4630 }
4631
4632 static int i915_gem_init_rings(struct drm_device *dev)
4633 {
4634         struct drm_i915_private *dev_priv = dev->dev_private;
4635         int ret;
4636
4637         ret = intel_init_render_ring_buffer(dev);
4638         if (ret)
4639                 return ret;
4640
4641         if (HAS_BSD(dev)) {
4642                 ret = intel_init_bsd_ring_buffer(dev);
4643                 if (ret)
4644                         goto cleanup_render_ring;
4645         }
4646
4647         if (intel_enable_blt(dev)) {
4648                 ret = intel_init_blt_ring_buffer(dev);
4649                 if (ret)
4650                         goto cleanup_bsd_ring;
4651         }
4652
4653         if (HAS_VEBOX(dev)) {
4654                 ret = intel_init_vebox_ring_buffer(dev);
4655                 if (ret)
4656                         goto cleanup_blt_ring;
4657         }
4658
4659         if (HAS_BSD2(dev)) {
4660                 ret = intel_init_bsd2_ring_buffer(dev);
4661                 if (ret)
4662                         goto cleanup_vebox_ring;
4663         }
4664
4665         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4666         if (ret)
4667                 goto cleanup_bsd2_ring;
4668
4669         return 0;
4670
4671 cleanup_bsd2_ring:
4672         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4673 cleanup_vebox_ring:
4674         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4675 cleanup_blt_ring:
4676         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4677 cleanup_bsd_ring:
4678         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4679 cleanup_render_ring:
4680         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4681
4682         return ret;
4683 }
4684
4685 int
4686 i915_gem_init_hw(struct drm_device *dev)
4687 {
4688         struct drm_i915_private *dev_priv = dev->dev_private;
4689         int ret, i;
4690
4691         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4692                 return -EIO;
4693
4694         if (dev_priv->ellc_size)
4695                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4696
4697         if (IS_HASWELL(dev))
4698                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4699                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4700
4701         if (HAS_PCH_NOP(dev)) {
4702                 if (IS_IVYBRIDGE(dev)) {
4703                         u32 temp = I915_READ(GEN7_MSG_CTL);
4704                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4705                         I915_WRITE(GEN7_MSG_CTL, temp);
4706                 } else if (INTEL_INFO(dev)->gen >= 7) {
4707                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4708                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4709                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4710                 }
4711         }
4712
4713         i915_gem_init_swizzling(dev);
4714
4715         ret = i915_gem_init_rings(dev);
4716         if (ret)
4717                 return ret;
4718
4719         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4720                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4721
4722         /*
4723          * XXX: Contexts should only be initialized once. Doing a switch to the
4724          * default context switch however is something we'd like to do after
4725          * reset or thaw (the latter may not actually be necessary for HW, but
4726          * goes with our code better). Context switching requires rings (for
4727          * the do_switch), but before enabling PPGTT. So don't move this.
4728          */
4729         ret = i915_gem_context_enable(dev_priv);
4730         if (ret && ret != -EIO) {
4731                 DRM_ERROR("Context enable failed %d\n", ret);
4732                 i915_gem_cleanup_ringbuffer(dev);
4733         }
4734
4735         return ret;
4736 }
4737
4738 int i915_gem_init(struct drm_device *dev)
4739 {
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         int ret;
4742
4743         mutex_lock(&dev->struct_mutex);
4744
4745         if (IS_VALLEYVIEW(dev)) {
4746                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4747                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4748                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4749                               VLV_GTLC_ALLOWWAKEACK), 10))
4750                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4751         }
4752
4753         i915_gem_init_userptr(dev);
4754         i915_gem_init_global_gtt(dev);
4755
4756         ret = i915_gem_context_init(dev);
4757         if (ret) {
4758                 mutex_unlock(&dev->struct_mutex);
4759                 return ret;
4760         }
4761
4762         ret = i915_gem_init_hw(dev);
4763         if (ret == -EIO) {
4764                 /* Allow ring initialisation to fail by marking the GPU as
4765                  * wedged. But we only want to do this where the GPU is angry,
4766                  * for all other failure, such as an allocation failure, bail.
4767                  */
4768                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4769                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4770                 ret = 0;
4771         }
4772         mutex_unlock(&dev->struct_mutex);
4773
4774         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4775         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4776                 dev_priv->dri1.allow_batchbuffer = 1;
4777         return ret;
4778 }
4779
4780 void
4781 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4782 {
4783         struct drm_i915_private *dev_priv = dev->dev_private;
4784         struct intel_engine_cs *ring;
4785         int i;
4786
4787         for_each_ring(ring, dev_priv, i)
4788                 intel_cleanup_ring_buffer(ring);
4789 }
4790
4791 int
4792 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4793                        struct drm_file *file_priv)
4794 {
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796         int ret;
4797
4798         if (drm_core_check_feature(dev, DRIVER_MODESET))
4799                 return 0;
4800
4801         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4802                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4803                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4804         }
4805
4806         mutex_lock(&dev->struct_mutex);
4807         dev_priv->ums.mm_suspended = 0;
4808
4809         ret = i915_gem_init_hw(dev);
4810         if (ret != 0) {
4811                 mutex_unlock(&dev->struct_mutex);
4812                 return ret;
4813         }
4814
4815         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4816
4817         ret = drm_irq_install(dev, dev->pdev->irq);
4818         if (ret)
4819                 goto cleanup_ringbuffer;
4820         mutex_unlock(&dev->struct_mutex);
4821
4822         return 0;
4823
4824 cleanup_ringbuffer:
4825         i915_gem_cleanup_ringbuffer(dev);
4826         dev_priv->ums.mm_suspended = 1;
4827         mutex_unlock(&dev->struct_mutex);
4828
4829         return ret;
4830 }
4831
4832 int
4833 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4834                        struct drm_file *file_priv)
4835 {
4836         if (drm_core_check_feature(dev, DRIVER_MODESET))
4837                 return 0;
4838
4839         mutex_lock(&dev->struct_mutex);
4840         drm_irq_uninstall(dev);
4841         mutex_unlock(&dev->struct_mutex);
4842
4843         return i915_gem_suspend(dev);
4844 }
4845
4846 void
4847 i915_gem_lastclose(struct drm_device *dev)
4848 {
4849         int ret;
4850
4851         if (drm_core_check_feature(dev, DRIVER_MODESET))
4852                 return;
4853
4854         ret = i915_gem_suspend(dev);
4855         if (ret)
4856                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4857 }
4858
4859 static void
4860 init_ring_lists(struct intel_engine_cs *ring)
4861 {
4862         INIT_LIST_HEAD(&ring->active_list);
4863         INIT_LIST_HEAD(&ring->request_list);
4864 }
4865
4866 void i915_init_vm(struct drm_i915_private *dev_priv,
4867                   struct i915_address_space *vm)
4868 {
4869         if (!i915_is_ggtt(vm))
4870                 drm_mm_init(&vm->mm, vm->start, vm->total);
4871         vm->dev = dev_priv->dev;
4872         INIT_LIST_HEAD(&vm->active_list);
4873         INIT_LIST_HEAD(&vm->inactive_list);
4874         INIT_LIST_HEAD(&vm->global_link);
4875         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4876 }
4877
4878 void
4879 i915_gem_load(struct drm_device *dev)
4880 {
4881         struct drm_i915_private *dev_priv = dev->dev_private;
4882         int i;
4883
4884         dev_priv->slab =
4885                 kmem_cache_create("i915_gem_object",
4886                                   sizeof(struct drm_i915_gem_object), 0,
4887                                   SLAB_HWCACHE_ALIGN,
4888                                   NULL);
4889
4890         INIT_LIST_HEAD(&dev_priv->vm_list);
4891         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4892
4893         INIT_LIST_HEAD(&dev_priv->context_list);
4894         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4895         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4896         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4897         for (i = 0; i < I915_NUM_RINGS; i++)
4898                 init_ring_lists(&dev_priv->ring[i]);
4899         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4900                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4901         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4902                           i915_gem_retire_work_handler);
4903         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4904                           i915_gem_idle_work_handler);
4905         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4906
4907         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4908         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4909                 I915_WRITE(MI_ARB_STATE,
4910                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4911         }
4912
4913         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4914
4915         /* Old X drivers will take 0-2 for front, back, depth buffers */
4916         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4917                 dev_priv->fence_reg_start = 3;
4918
4919         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4920                 dev_priv->num_fence_regs = 32;
4921         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4922                 dev_priv->num_fence_regs = 16;
4923         else
4924                 dev_priv->num_fence_regs = 8;
4925
4926         /* Initialize fence registers to zero */
4927         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4928         i915_gem_restore_fences(dev);
4929
4930         i915_gem_detect_bit_6_swizzle(dev);
4931         init_waitqueue_head(&dev_priv->pending_flip_queue);
4932
4933         dev_priv->mm.interruptible = true;
4934
4935         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4936         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4937         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4938         register_shrinker(&dev_priv->mm.shrinker);
4939
4940         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4941         register_oom_notifier(&dev_priv->mm.oom_notifier);
4942
4943         mutex_init(&dev_priv->fb_tracking.lock);
4944 }
4945
4946 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4947 {
4948         struct drm_i915_file_private *file_priv = file->driver_priv;
4949
4950         cancel_delayed_work_sync(&file_priv->mm.idle_work);
4951
4952         /* Clean up our request list when the client is going away, so that
4953          * later retire_requests won't dereference our soon-to-be-gone
4954          * file_priv.
4955          */
4956         spin_lock(&file_priv->mm.lock);
4957         while (!list_empty(&file_priv->mm.request_list)) {
4958                 struct drm_i915_gem_request *request;
4959
4960                 request = list_first_entry(&file_priv->mm.request_list,
4961                                            struct drm_i915_gem_request,
4962                                            client_list);
4963                 list_del(&request->client_list);
4964                 request->file_priv = NULL;
4965         }
4966         spin_unlock(&file_priv->mm.lock);
4967 }
4968
4969 static void
4970 i915_gem_file_idle_work_handler(struct work_struct *work)
4971 {
4972         struct drm_i915_file_private *file_priv =
4973                 container_of(work, typeof(*file_priv), mm.idle_work.work);
4974
4975         atomic_set(&file_priv->rps_wait_boost, false);
4976 }
4977
4978 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4979 {
4980         struct drm_i915_file_private *file_priv;
4981         int ret;
4982
4983         DRM_DEBUG_DRIVER("\n");
4984
4985         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4986         if (!file_priv)
4987                 return -ENOMEM;
4988
4989         file->driver_priv = file_priv;
4990         file_priv->dev_priv = dev->dev_private;
4991         file_priv->file = file;
4992
4993         spin_lock_init(&file_priv->mm.lock);
4994         INIT_LIST_HEAD(&file_priv->mm.request_list);
4995         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
4996                           i915_gem_file_idle_work_handler);
4997
4998         ret = i915_gem_context_open(dev, file);
4999         if (ret)
5000                 kfree(file_priv);
5001
5002         return ret;
5003 }
5004
5005 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5006                        struct drm_i915_gem_object *new,
5007                        unsigned frontbuffer_bits)
5008 {
5009         if (old) {
5010                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5011                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5012                 old->frontbuffer_bits &= ~frontbuffer_bits;
5013         }
5014
5015         if (new) {
5016                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5017                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5018                 new->frontbuffer_bits |= frontbuffer_bits;
5019         }
5020 }
5021
5022 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5023 {
5024         if (!mutex_is_locked(mutex))
5025                 return false;
5026
5027 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5028         return mutex->owner == task;
5029 #else
5030         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5031         return false;
5032 #endif
5033 }
5034
5035 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5036 {
5037         if (!mutex_trylock(&dev->struct_mutex)) {
5038                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5039                         return false;
5040
5041                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5042                         return false;
5043
5044                 *unlock = false;
5045         } else
5046                 *unlock = true;
5047
5048         return true;
5049 }
5050
5051 static int num_vma_bound(struct drm_i915_gem_object *obj)
5052 {
5053         struct i915_vma *vma;
5054         int count = 0;
5055
5056         list_for_each_entry(vma, &obj->vma_list, vma_link)
5057                 if (drm_mm_node_allocated(&vma->node))
5058                         count++;
5059
5060         return count;
5061 }
5062
5063 static unsigned long
5064 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5065 {
5066         struct drm_i915_private *dev_priv =
5067                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5068         struct drm_device *dev = dev_priv->dev;
5069         struct drm_i915_gem_object *obj;
5070         unsigned long count;
5071         bool unlock;
5072
5073         if (!i915_gem_shrinker_lock(dev, &unlock))
5074                 return 0;
5075
5076         count = 0;
5077         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5078                 if (obj->pages_pin_count == 0)
5079                         count += obj->base.size >> PAGE_SHIFT;
5080
5081         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5082                 if (!i915_gem_obj_is_pinned(obj) &&
5083                     obj->pages_pin_count == num_vma_bound(obj))
5084                         count += obj->base.size >> PAGE_SHIFT;
5085         }
5086
5087         if (unlock)
5088                 mutex_unlock(&dev->struct_mutex);
5089
5090         return count;
5091 }
5092
5093 /* All the new VM stuff */
5094 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5095                                   struct i915_address_space *vm)
5096 {
5097         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5098         struct i915_vma *vma;
5099
5100         if (!dev_priv->mm.aliasing_ppgtt ||
5101             vm == &dev_priv->mm.aliasing_ppgtt->base)
5102                 vm = &dev_priv->gtt.base;
5103
5104         list_for_each_entry(vma, &o->vma_list, vma_link) {
5105                 if (vma->vm == vm)
5106                         return vma->node.start;
5107
5108         }
5109         WARN(1, "%s vma for this object not found.\n",
5110              i915_is_ggtt(vm) ? "global" : "ppgtt");
5111         return -1;
5112 }
5113
5114 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5115                         struct i915_address_space *vm)
5116 {
5117         struct i915_vma *vma;
5118
5119         list_for_each_entry(vma, &o->vma_list, vma_link)
5120                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5121                         return true;
5122
5123         return false;
5124 }
5125
5126 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5127 {
5128         struct i915_vma *vma;
5129
5130         list_for_each_entry(vma, &o->vma_list, vma_link)
5131                 if (drm_mm_node_allocated(&vma->node))
5132                         return true;
5133
5134         return false;
5135 }
5136
5137 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5138                                 struct i915_address_space *vm)
5139 {
5140         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5141         struct i915_vma *vma;
5142
5143         if (!dev_priv->mm.aliasing_ppgtt ||
5144             vm == &dev_priv->mm.aliasing_ppgtt->base)
5145                 vm = &dev_priv->gtt.base;
5146
5147         BUG_ON(list_empty(&o->vma_list));
5148
5149         list_for_each_entry(vma, &o->vma_list, vma_link)
5150                 if (vma->vm == vm)
5151                         return vma->node.size;
5152
5153         return 0;
5154 }
5155
5156 static unsigned long
5157 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5158 {
5159         struct drm_i915_private *dev_priv =
5160                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5161         struct drm_device *dev = dev_priv->dev;
5162         unsigned long freed;
5163         bool unlock;
5164
5165         if (!i915_gem_shrinker_lock(dev, &unlock))
5166                 return SHRINK_STOP;
5167
5168         freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5169         if (freed < sc->nr_to_scan)
5170                 freed += __i915_gem_shrink(dev_priv,
5171                                            sc->nr_to_scan - freed,
5172                                            false);
5173         if (unlock)
5174                 mutex_unlock(&dev->struct_mutex);
5175
5176         return freed;
5177 }
5178
5179 static int
5180 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5181 {
5182         struct drm_i915_private *dev_priv =
5183                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5184         struct drm_device *dev = dev_priv->dev;
5185         struct drm_i915_gem_object *obj;
5186         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5187         unsigned long pinned, bound, unbound, freed;
5188         bool was_interruptible;
5189         bool unlock;
5190
5191         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5192                 schedule_timeout_killable(1);
5193                 if (fatal_signal_pending(current))
5194                         return NOTIFY_DONE;
5195         }
5196         if (timeout == 0) {
5197                 pr_err("Unable to purge GPU memory due lock contention.\n");
5198                 return NOTIFY_DONE;
5199         }
5200
5201         was_interruptible = dev_priv->mm.interruptible;
5202         dev_priv->mm.interruptible = false;
5203
5204         freed = i915_gem_shrink_all(dev_priv);
5205
5206         dev_priv->mm.interruptible = was_interruptible;
5207
5208         /* Because we may be allocating inside our own driver, we cannot
5209          * assert that there are no objects with pinned pages that are not
5210          * being pointed to by hardware.
5211          */
5212         unbound = bound = pinned = 0;
5213         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5214                 if (!obj->base.filp) /* not backed by a freeable object */
5215                         continue;
5216
5217                 if (obj->pages_pin_count)
5218                         pinned += obj->base.size;
5219                 else
5220                         unbound += obj->base.size;
5221         }
5222         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5223                 if (!obj->base.filp)
5224                         continue;
5225
5226                 if (obj->pages_pin_count)
5227                         pinned += obj->base.size;
5228                 else
5229                         bound += obj->base.size;
5230         }
5231
5232         if (unlock)
5233                 mutex_unlock(&dev->struct_mutex);
5234
5235         pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5236                 freed, pinned);
5237         if (unbound || bound)
5238                 pr_err("%lu and %lu bytes still available in the "
5239                        "bound and unbound GPU page lists.\n",
5240                        bound, unbound);
5241
5242         *(unsigned long *)ptr += freed;
5243         return NOTIFY_DONE;
5244 }
5245
5246 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5247 {
5248         struct i915_vma *vma;
5249
5250         /* This WARN has probably outlived its usefulness (callers already
5251          * WARN if they don't find the GGTT vma they expect). When removing,
5252          * remember to remove the pre-check in is_pin_display() as well */
5253         if (WARN_ON(list_empty(&obj->vma_list)))
5254                 return NULL;
5255
5256         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5257         if (vma->vm != obj_to_ggtt(obj))
5258                 return NULL;
5259
5260         return vma;
5261 }