drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct i915_gpu_error *error)
  91 {
  92         int ret;
  93
  94 #define EXIT_COND (!i915_reset_in_progress(error) || \
  95                    i915_terminally_wedged(error))
  96         if (EXIT_COND)
  97                 return 0;
  98
  99         /*
 100          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 101          * userspace. If it takes that long something really bad is going on and
 102          * we should simply try to bail out and fail as gracefully as possible.
 103          */
 104         ret = wait_event_interruptible_timeout(error->reset_queue,
 105                                                EXIT_COND,
 106                                                10*HZ);
 107         if (ret == 0) {
 108                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 109                 return -EIO;
 110         } else if (ret < 0) {
 111                 return ret;
 112         }
 113 #undef EXIT_COND
 114
 115         return 0;
 116 }
 117
 118 int i915_mutex_lock_interruptible(struct drm_device *dev)
 119 {
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         int ret;
 122
 123         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 124         if (ret)
 125                 return ret;
 126
 127         ret = mutex_lock_interruptible(&dev->struct_mutex);
 128         if (ret)
 129                 return ret;
 130
 131         WARN_ON(i915_verify_lists(dev));
 132         return 0;
 133 }
 134
 135 static inline bool
 136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 137 {
 138         return i915_gem_obj_ggtt_bound(obj) && !obj->active;
 139 }
 140
 141 int
 142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 143                     struct drm_file *file)
 144 {
 145         struct drm_i915_private *dev_priv = dev->dev_private;
 146         struct drm_i915_gem_init *args = data;
 147
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return -ENODEV;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         /* GEM with user mode setting was never supported on ilk and later. */
 156         if (INTEL_INFO(dev)->gen >= 5)
 157                 return -ENODEV;
 158
 159         mutex_lock(&dev->struct_mutex);
 160         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 161                                   args->gtt_end);
 162         dev_priv->gtt.mappable_end = args->gtt_end;
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         pinned = 0;
 178         mutex_lock(&dev->struct_mutex);
 179         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 180                 if (obj->pin_count)
 181                         pinned += i915_gem_obj_ggtt_size(obj);
 182         mutex_unlock(&dev->struct_mutex);
 183
 184         args->aper_size = dev_priv->gtt.base.total;
 185         args->aper_available_size = args->aper_size - pinned;
 186
 187         return 0;
 188 }
 189
 190 void *i915_gem_object_alloc(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 194 }
 195
 196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 197 {
 198         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 199         kmem_cache_free(dev_priv->slab, obj);
 200 }
 201
 202 static int
 203 i915_gem_create(struct drm_file *file,
 204                 struct drm_device *dev,
 205                 uint64_t size,
 206                 uint32_t *handle_p)
 207 {
 208         struct drm_i915_gem_object *obj;
 209         int ret;
 210         u32 handle;
 211
 212         size = roundup(size, PAGE_SIZE);
 213         if (size == 0)
 214                 return -EINVAL;
 215
 216         /* Allocate the new object */
 217         obj = i915_gem_alloc_object(dev, size);
 218         if (obj == NULL)
 219                 return -ENOMEM;
 220
 221         ret = drm_gem_handle_create(file, &obj->base, &handle);
 222         if (ret) {
 223                 drm_gem_object_release(&obj->base);
 224                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 225                 i915_gem_object_free(obj);
 226                 return ret;
 227         }
 228
 229         /* drop reference from allocate - handle holds it now */
 230         drm_gem_object_unreference(&obj->base);
 231         trace_i915_gem_object_create(obj);
 232
 233         *handle_p = handle;
 234         return 0;
 235 }
 236
 237 int
 238 i915_gem_dumb_create(struct drm_file *file,
 239                      struct drm_device *dev,
 240                      struct drm_mode_create_dumb *args)
 241 {
 242         /* have to work out size/pitch and return them */
 243         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 244         args->size = args->pitch * args->height;
 245         return i915_gem_create(file, dev,
 246                                args->size, &args->handle);
 247 }
 248
 249 int i915_gem_dumb_destroy(struct drm_file *file,
 250                           struct drm_device *dev,
 251                           uint32_t handle)
 252 {
 253         return drm_gem_handle_delete(file, handle);
 254 }
 255
 256 /**
 257  * Creates a new mm object and returns a handle to it.
 258  */
 259 int
 260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 261                       struct drm_file *file)
 262 {
 263         struct drm_i915_gem_create *args = data;
 264
 265         return i915_gem_create(file, dev,
 266                                args->size, &args->handle);
 267 }
 268
 269 static inline int
 270 __copy_to_user_swizzled(char __user *cpu_vaddr,
 271                         const char *gpu_vaddr, int gpu_offset,
 272                         int length)
 273 {
 274         int ret, cpu_offset = 0;
 275
 276         while (length > 0) {
 277                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 278                 int this_length = min(cacheline_end - gpu_offset, length);
 279                 int swizzled_gpu_offset = gpu_offset ^ 64;
 280
 281                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 282                                      gpu_vaddr + swizzled_gpu_offset,
 283                                      this_length);
 284                 if (ret)
 285                         return ret + length;
 286
 287                 cpu_offset += this_length;
 288                 gpu_offset += this_length;
 289                 length -= this_length;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 297                           const char __user *cpu_vaddr,
 298                           int length)
 299 {
 300         int ret, cpu_offset = 0;
 301
 302         while (length > 0) {
 303                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 304                 int this_length = min(cacheline_end - gpu_offset, length);
 305                 int swizzled_gpu_offset = gpu_offset ^ 64;
 306
 307                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 308                                        cpu_vaddr + cpu_offset,
 309                                        this_length);
 310                 if (ret)
 311                         return ret + length;
 312
 313                 cpu_offset += this_length;
 314                 gpu_offset += this_length;
 315                 length -= this_length;
 316         }
 317
 318         return 0;
 319 }
 320
 321 /* Per-page copy function for the shmem pread fastpath.
 322  * Flushes invalid cachelines before reading the target if
 323  * needs_clflush is set. */
 324 static int
 325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 326                  char __user *user_data,
 327                  bool page_do_bit17_swizzling, bool needs_clflush)
 328 {
 329         char *vaddr;
 330         int ret;
 331
 332         if (unlikely(page_do_bit17_swizzling))
 333                 return -EINVAL;
 334
 335         vaddr = kmap_atomic(page);
 336         if (needs_clflush)
 337                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 338                                        page_length);
 339         ret = __copy_to_user_inatomic(user_data,
 340                                       vaddr + shmem_page_offset,
 341                                       page_length);
 342         kunmap_atomic(vaddr);
 343
 344         return ret ? -EFAULT : 0;
 345 }
 346
 347 static void
 348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 349                              bool swizzled)
 350 {
 351         if (unlikely(swizzled)) {
 352                 unsigned long start = (unsigned long) addr;
 353                 unsigned long end = (unsigned long) addr + length;
 354
 355                 /* For swizzling simply ensure that we always flush both
 356                  * channels. Lame, but simple and it works. Swizzled
 357                  * pwrite/pread is far from a hotpath - current userspace
 358                  * doesn't use it at all. */
 359                 start = round_down(start, 128);
 360                 end = round_up(end, 128);
 361
 362                 drm_clflush_virt_range((void *)start, end - start);
 363         } else {
 364                 drm_clflush_virt_range(addr, length);
 365         }
 366
 367 }
 368
 369 /* Only difference to the fast-path function is that this can handle bit17
 370  * and uses non-atomic copy and kmap functions. */
 371 static int
 372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 373                  char __user *user_data,
 374                  bool page_do_bit17_swizzling, bool needs_clflush)
 375 {
 376         char *vaddr;
 377         int ret;
 378
 379         vaddr = kmap(page);
 380         if (needs_clflush)
 381                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 382                                              page_length,
 383                                              page_do_bit17_swizzling);
 384
 385         if (page_do_bit17_swizzling)
 386                 ret = __copy_to_user_swizzled(user_data,
 387                                               vaddr, shmem_page_offset,
 388                                               page_length);
 389         else
 390                 ret = __copy_to_user(user_data,
 391                                      vaddr + shmem_page_offset,
 392                                      page_length);
 393         kunmap(page);
 394
 395         return ret ? - EFAULT : 0;
 396 }
 397
 398 static int
 399 i915_gem_shmem_pread(struct drm_device *dev,
 400                      struct drm_i915_gem_object *obj,
 401                      struct drm_i915_gem_pread *args,
 402                      struct drm_file *file)
 403 {
 404         char __user *user_data;
 405         ssize_t remain;
 406         loff_t offset;
 407         int shmem_page_offset, page_length, ret = 0;
 408         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 409         int prefaulted = 0;
 410         int needs_clflush = 0;
 411         struct sg_page_iter sg_iter;
 412
 413         user_data = to_user_ptr(args->data_ptr);
 414         remain = args->size;
 415
 416         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 417
 418         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 419                 /* If we're not in the cpu read domain, set ourself into the gtt
 420                  * read domain and manually flush cachelines (if required). This
 421                  * optimizes for the case when the gpu will dirty the data
 422                  * anyway again before the next pread happens. */
 423                 if (obj->cache_level == I915_CACHE_NONE)
 424                         needs_clflush = 1;
 425                 if (i915_gem_obj_ggtt_bound(obj)) {
 426                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 427                         if (ret)
 428                                 return ret;
 429                 }
 430         }
 431
 432         ret = i915_gem_object_get_pages(obj);
 433         if (ret)
 434                 return ret;
 435
 436         i915_gem_object_pin_pages(obj);
 437
 438         offset = args->offset;
 439
 440         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 441                          offset >> PAGE_SHIFT) {
 442                 struct page *page = sg_page_iter_page(&sg_iter);
 443
 444                 if (remain <= 0)
 445                         break;
 446
 447                 /* Operation in this page
 448                  *
 449                  * shmem_page_offset = offset within page in shmem file
 450                  * page_length = bytes to copy for this page
 451                  */
 452                 shmem_page_offset = offset_in_page(offset);
 453                 page_length = remain;
 454                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 455                         page_length = PAGE_SIZE - shmem_page_offset;
 456
 457                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 458                         (page_to_phys(page) & (1 << 17)) != 0;
 459
 460                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 461                                        user_data, page_do_bit17_swizzling,
 462                                        needs_clflush);
 463                 if (ret == 0)
 464                         goto next_page;
 465
 466                 mutex_unlock(&dev->struct_mutex);
 467
 468                 if (!prefaulted) {
 469                         ret = fault_in_multipages_writeable(user_data, remain);
 470                         /* Userspace is tricking us, but we've already clobbered
 471                          * its pages with the prefault and promised to write the
 472                          * data up to the first fault. Hence ignore any errors
 473                          * and just continue. */
 474                         (void)ret;
 475                         prefaulted = 1;
 476                 }
 477
 478                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 479                                        user_data, page_do_bit17_swizzling,
 480                                        needs_clflush);
 481
 482                 mutex_lock(&dev->struct_mutex);
 483
 484 next_page:
 485                 mark_page_accessed(page);
 486
 487                 if (ret)
 488                         goto out;
 489
 490                 remain -= page_length;
 491                 user_data += page_length;
 492                 offset += page_length;
 493         }
 494
 495 out:
 496         i915_gem_object_unpin_pages(obj);
 497
 498         return ret;
 499 }
 500
 501 /**
 502  * Reads data from the object referenced by handle.
 503  *
 504  * On error, the contents of *data are undefined.
 505  */
 506 int
 507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 508                      struct drm_file *file)
 509 {
 510         struct drm_i915_gem_pread *args = data;
 511         struct drm_i915_gem_object *obj;
 512         int ret = 0;
 513
 514         if (args->size == 0)
 515                 return 0;
 516
 517         if (!access_ok(VERIFY_WRITE,
 518                        to_user_ptr(args->data_ptr),
 519                        args->size))
 520                 return -EFAULT;
 521
 522         ret = i915_mutex_lock_interruptible(dev);
 523         if (ret)
 524                 return ret;
 525
 526         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 527         if (&obj->base == NULL) {
 528                 ret = -ENOENT;
 529                 goto unlock;
 530         }
 531
 532         /* Bounds check source.  */
 533         if (args->offset > obj->base.size ||
 534             args->size > obj->base.size - args->offset) {
 535                 ret = -EINVAL;
 536                 goto out;
 537         }
 538
 539         /* prime objects have no backing filp to GEM pread/pwrite
 540          * pages from.
 541          */
 542         if (!obj->base.filp) {
 543                 ret = -EINVAL;
 544                 goto out;
 545         }
 546
 547         trace_i915_gem_object_pread(obj, args->offset, args->size);
 548
 549         ret = i915_gem_shmem_pread(dev, obj, args, file);
 550
 551 out:
 552         drm_gem_object_unreference(&obj->base);
 553 unlock:
 554         mutex_unlock(&dev->struct_mutex);
 555         return ret;
 556 }
 557
 558 /* This is the fast write path which cannot handle
 559  * page faults in the source data
 560  */
 561
 562 static inline int
 563 fast_user_write(struct io_mapping *mapping,
 564                 loff_t page_base, int page_offset,
 565                 char __user *user_data,
 566                 int length)
 567 {
 568         void __iomem *vaddr_atomic;
 569         void *vaddr;
 570         unsigned long unwritten;
 571
 572         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 573         /* We can use the cpu mem copy function because this is X86. */
 574         vaddr = (void __force*)vaddr_atomic + page_offset;
 575         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 576                                                       user_data, length);
 577         io_mapping_unmap_atomic(vaddr_atomic);
 578         return unwritten;
 579 }
 580
 581 /**
 582  * This is the fast pwrite path, where we copy the data directly from the
 583  * user into the GTT, uncached.
 584  */
 585 static int
 586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 587                          struct drm_i915_gem_object *obj,
 588                          struct drm_i915_gem_pwrite *args,
 589                          struct drm_file *file)
 590 {
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592         ssize_t remain;
 593         loff_t offset, page_base;
 594         char __user *user_data;
 595         int page_offset, page_length, ret;
 596
 597         ret = i915_gem_object_pin(obj, 0, true, true);
 598         if (ret)
 599                 goto out;
 600
 601         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 602         if (ret)
 603                 goto out_unpin;
 604
 605         ret = i915_gem_object_put_fence(obj);
 606         if (ret)
 607                 goto out_unpin;
 608
 609         user_data = to_user_ptr(args->data_ptr);
 610         remain = args->size;
 611
 612         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 613
 614         while (remain > 0) {
 615                 /* Operation in this page
 616                  *
 617                  * page_base = page offset within aperture
 618                  * page_offset = offset within page
 619                  * page_length = bytes to copy for this page
 620                  */
 621                 page_base = offset & PAGE_MASK;
 622                 page_offset = offset_in_page(offset);
 623                 page_length = remain;
 624                 if ((page_offset + remain) > PAGE_SIZE)
 625                         page_length = PAGE_SIZE - page_offset;
 626
 627                 /* If we get a fault while copying data, then (presumably) our
 628                  * source page isn't available.  Return the error and we'll
 629                  * retry in the slow path.
 630                  */
 631                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 632                                     page_offset, user_data, page_length)) {
 633                         ret = -EFAULT;
 634                         goto out_unpin;
 635                 }
 636
 637                 remain -= page_length;
 638                 user_data += page_length;
 639                 offset += page_length;
 640         }
 641
 642 out_unpin:
 643         i915_gem_object_unpin(obj);
 644 out:
 645         return ret;
 646 }
 647
 648 /* Per-page copy function for the shmem pwrite fastpath.
 649  * Flushes invalid cachelines before writing to the target if
 650  * needs_clflush_before is set and flushes out any written cachelines after
 651  * writing if needs_clflush is set. */
 652 static int
 653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 654                   char __user *user_data,
 655                   bool page_do_bit17_swizzling,
 656                   bool needs_clflush_before,
 657                   bool needs_clflush_after)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         if (unlikely(page_do_bit17_swizzling))
 663                 return -EINVAL;
 664
 665         vaddr = kmap_atomic(page);
 666         if (needs_clflush_before)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 670                                                 user_data,
 671                                                 page_length);
 672         if (needs_clflush_after)
 673                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 674                                        page_length);
 675         kunmap_atomic(vaddr);
 676
 677         return ret ? -EFAULT : 0;
 678 }
 679
 680 /* Only difference to the fast-path function is that this can handle bit17
 681  * and uses non-atomic copy and kmap functions. */
 682 static int
 683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 684                   char __user *user_data,
 685                   bool page_do_bit17_swizzling,
 686                   bool needs_clflush_before,
 687                   bool needs_clflush_after)
 688 {
 689         char *vaddr;
 690         int ret;
 691
 692         vaddr = kmap(page);
 693         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 694                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 695                                              page_length,
 696                                              page_do_bit17_swizzling);
 697         if (page_do_bit17_swizzling)
 698                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 699                                                 user_data,
 700                                                 page_length);
 701         else
 702                 ret = __copy_from_user(vaddr + shmem_page_offset,
 703                                        user_data,
 704                                        page_length);
 705         if (needs_clflush_after)
 706                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 707                                              page_length,
 708                                              page_do_bit17_swizzling);
 709         kunmap(page);
 710
 711         return ret ? -EFAULT : 0;
 712 }
 713
 714 static int
 715 i915_gem_shmem_pwrite(struct drm_device *dev,
 716                       struct drm_i915_gem_object *obj,
 717                       struct drm_i915_gem_pwrite *args,
 718                       struct drm_file *file)
 719 {
 720         ssize_t remain;
 721         loff_t offset;
 722         char __user *user_data;
 723         int shmem_page_offset, page_length, ret = 0;
 724         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 725         int hit_slowpath = 0;
 726         int needs_clflush_after = 0;
 727         int needs_clflush_before = 0;
 728         struct sg_page_iter sg_iter;
 729
 730         user_data = to_user_ptr(args->data_ptr);
 731         remain = args->size;
 732
 733         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 734
 735         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 736                 /* If we're not in the cpu write domain, set ourself into the gtt
 737                  * write domain and manually flush cachelines (if required). This
 738                  * optimizes for the case when the gpu will use the data
 739                  * right away and we therefore have to clflush anyway. */
 740                 if (obj->cache_level == I915_CACHE_NONE)
 741                         needs_clflush_after = 1;
 742                 if (i915_gem_obj_ggtt_bound(obj)) {
 743                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 744                         if (ret)
 745                                 return ret;
 746                 }
 747         }
 748         /* Same trick applies for invalidate partially written cachelines before
 749          * writing.  */
 750         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 751             && obj->cache_level == I915_CACHE_NONE)
 752                 needs_clflush_before = 1;
 753
 754         ret = i915_gem_object_get_pages(obj);
 755         if (ret)
 756                 return ret;
 757
 758         i915_gem_object_pin_pages(obj);
 759
 760         offset = args->offset;
 761         obj->dirty = 1;
 762
 763         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 764                          offset >> PAGE_SHIFT) {
 765                 struct page *page = sg_page_iter_page(&sg_iter);
 766                 int partial_cacheline_write;
 767
 768                 if (remain <= 0)
 769                         break;
 770
 771                 /* Operation in this page
 772                  *
 773                  * shmem_page_offset = offset within page in shmem file
 774                  * page_length = bytes to copy for this page
 775                  */
 776                 shmem_page_offset = offset_in_page(offset);
 777
 778                 page_length = remain;
 779                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 780                         page_length = PAGE_SIZE - shmem_page_offset;
 781
 782                 /* If we don't overwrite a cacheline completely we need to be
 783                  * careful to have up-to-date data by first clflushing. Don't
 784                  * overcomplicate things and flush the entire patch. */
 785                 partial_cacheline_write = needs_clflush_before &&
 786                         ((shmem_page_offset | page_length)
 787                                 & (boot_cpu_data.x86_clflush_size - 1));
 788
 789                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 790                         (page_to_phys(page) & (1 << 17)) != 0;
 791
 792                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 793                                         user_data, page_do_bit17_swizzling,
 794                                         partial_cacheline_write,
 795                                         needs_clflush_after);
 796                 if (ret == 0)
 797                         goto next_page;
 798
 799                 hit_slowpath = 1;
 800                 mutex_unlock(&dev->struct_mutex);
 801                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 802                                         user_data, page_do_bit17_swizzling,
 803                                         partial_cacheline_write,
 804                                         needs_clflush_after);
 805
 806                 mutex_lock(&dev->struct_mutex);
 807
 808 next_page:
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811
 812                 if (ret)
 813                         goto out;
 814
 815                 remain -= page_length;
 816                 user_data += page_length;
 817                 offset += page_length;
 818         }
 819
 820 out:
 821         i915_gem_object_unpin_pages(obj);
 822
 823         if (hit_slowpath) {
 824                 /*
 825                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 826                  * cachelines in-line while writing and the object moved
 827                  * out of the cpu write domain while we've dropped the lock.
 828                  */
 829                 if (!needs_clflush_after &&
 830                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 831                         i915_gem_clflush_object(obj);
 832                         i915_gem_chipset_flush(dev);
 833                 }
 834         }
 835
 836         if (needs_clflush_after)
 837                 i915_gem_chipset_flush(dev);
 838
 839         return ret;
 840 }
 841
 842 /**
 843  * Writes data to the object referenced by handle.
 844  *
 845  * On error, the contents of the buffer that were to be modified are undefined.
 846  */
 847 int
 848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 849                       struct drm_file *file)
 850 {
 851         struct drm_i915_gem_pwrite *args = data;
 852         struct drm_i915_gem_object *obj;
 853         int ret;
 854
 855         if (args->size == 0)
 856                 return 0;
 857
 858         if (!access_ok(VERIFY_READ,
 859                        to_user_ptr(args->data_ptr),
 860                        args->size))
 861                 return -EFAULT;
 862
 863         ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 864                                            args->size);
 865         if (ret)
 866                 return -EFAULT;
 867
 868         ret = i915_mutex_lock_interruptible(dev);
 869         if (ret)
 870                 return ret;
 871
 872         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 873         if (&obj->base == NULL) {
 874                 ret = -ENOENT;
 875                 goto unlock;
 876         }
 877
 878         /* Bounds check destination. */
 879         if (args->offset > obj->base.size ||
 880             args->size > obj->base.size - args->offset) {
 881                 ret = -EINVAL;
 882                 goto out;
 883         }
 884
 885         /* prime objects have no backing filp to GEM pread/pwrite
 886          * pages from.
 887          */
 888         if (!obj->base.filp) {
 889                 ret = -EINVAL;
 890                 goto out;
 891         }
 892
 893         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 894
 895         ret = -EFAULT;
 896         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 897          * it would end up going through the fenced access, and we'll get
 898          * different detiling behavior between reading and writing.
 899          * pread/pwrite currently are reading and writing from the CPU
 900          * perspective, requiring manual detiling by the client.
 901          */
 902         if (obj->phys_obj) {
 903                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 904                 goto out;
 905         }
 906
 907         if (obj->cache_level == I915_CACHE_NONE &&
 908             obj->tiling_mode == I915_TILING_NONE &&
 909             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 910                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 911                 /* Note that the gtt paths might fail with non-page-backed user
 912                  * pointers (e.g. gtt mappings when moving data between
 913                  * textures). Fallback to the shmem path in that case. */
 914         }
 915
 916         if (ret == -EFAULT || ret == -ENOSPC)
 917                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 918
 919 out:
 920         drm_gem_object_unreference(&obj->base);
 921 unlock:
 922         mutex_unlock(&dev->struct_mutex);
 923         return ret;
 924 }
 925
 926 int
 927 i915_gem_check_wedge(struct i915_gpu_error *error,
 928                      bool interruptible)
 929 {
 930         if (i915_reset_in_progress(error)) {
 931                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 932                  * -EIO unconditionally for these. */
 933                 if (!interruptible)
 934                         return -EIO;
 935
 936                 /* Recovery complete, but the reset failed ... */
 937                 if (i915_terminally_wedged(error))
 938                         return -EIO;
 939
 940                 return -EAGAIN;
 941         }
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Compare seqno against outstanding lazy request. Emit a request if they are
 948  * equal.
 949  */
 950 static int
 951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 952 {
 953         int ret;
 954
 955         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 956
 957         ret = 0;
 958         if (seqno == ring->outstanding_lazy_request)
 959                 ret = i915_add_request(ring, NULL);
 960
 961         return ret;
 962 }
 963
 964 /**
 965  * __wait_seqno - wait until execution of seqno has finished
 966  * @ring: the ring expected to report seqno
 967  * @seqno: duh!
 968  * @reset_counter: reset sequence associated with the given seqno
 969  * @interruptible: do an interruptible wait (normally yes)
 970  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 971  *
 972  * Note: It is of utmost importance that the passed in seqno and reset_counter
 973  * values have been read by the caller in an smp safe manner. Where read-side
 974  * locks are involved, it is sufficient to read the reset_counter before
 975  * unlocking the lock that protects the seqno. For lockless tricks, the
 976  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 977  * inserted.
 978  *
 979  * Returns 0 if the seqno was found within the alloted time. Else returns the
 980  * errno with remaining time filled in timeout argument.
 981  */
 982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 983                         unsigned reset_counter,
 984                         bool interruptible, struct timespec *timeout)
 985 {
 986         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 987         struct timespec before, now, wait_time={1,0};
 988         unsigned long timeout_jiffies;
 989         long end;
 990         bool wait_forever = true;
 991         int ret;
 992
 993         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 994                 return 0;
 995
 996         trace_i915_gem_request_wait_begin(ring, seqno);
 997
 998         if (timeout != NULL) {
 999                 wait_time = *timeout;
1000                 wait_forever = false;
1001         }
1002
1003         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1004
1005         if (WARN_ON(!ring->irq_get(ring)))
1006                 return -ENODEV;
1007
1008         /* Record current time in case interrupted by signal, or wedged * */
1009         getrawmonotonic(&before);
1010
1011 #define EXIT_COND \
1012         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013          i915_reset_in_progress(&dev_priv->gpu_error) || \
1014          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1015         do {
1016                 if (interruptible)
1017                         end = wait_event_interruptible_timeout(ring->irq_queue,
1018                                                                EXIT_COND,
1019                                                                timeout_jiffies);
1020                 else
1021                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1022                                                  timeout_jiffies);
1023
1024                 /* We need to check whether any gpu reset happened in between
1025                  * the caller grabbing the seqno and now ... */
1026                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1027                         end = -EAGAIN;
1028
1029                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1030                  * gone. */
1031                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1032                 if (ret)
1033                         end = ret;
1034         } while (end == 0 && wait_forever);
1035
1036         getrawmonotonic(&now);
1037
1038         ring->irq_put(ring);
1039         trace_i915_gem_request_wait_end(ring, seqno);
1040 #undef EXIT_COND
1041
1042         if (timeout) {
1043                 struct timespec sleep_time = timespec_sub(now, before);
1044                 *timeout = timespec_sub(*timeout, sleep_time);
1045                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046                         set_normalized_timespec(timeout, 0, 0);
1047         }
1048
1049         switch (end) {
1050         case -EIO:
1051         case -EAGAIN: /* Wedged */
1052         case -ERESTARTSYS: /* Signal */
1053                 return (int)end;
1054         case 0: /* Timeout */
1055                 return -ETIME;
1056         default: /* Completed */
1057                 WARN_ON(end < 0); /* We're not aware of other errors */
1058                 return 0;
1059         }
1060 }
1061
1062 /**
1063  * Waits for a sequence number to be signaled, and cleans up the
1064  * request and object lists appropriately for that event.
1065  */
1066 int
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1068 {
1069         struct drm_device *dev = ring->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         bool interruptible = dev_priv->mm.interruptible;
1072         int ret;
1073
1074         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1075         BUG_ON(seqno == 0);
1076
1077         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1078         if (ret)
1079                 return ret;
1080
1081         ret = i915_gem_check_olr(ring, seqno);
1082         if (ret)
1083                 return ret;
1084
1085         return __wait_seqno(ring, seqno,
1086                             atomic_read(&dev_priv->gpu_error.reset_counter),
1087                             interruptible, NULL);
1088 }
1089
1090 static int
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1092                                      struct intel_ring_buffer *ring)
1093 {
1094         i915_gem_retire_requests_ring(ring);
1095
1096         /* Manually manage the write flush as we may have not yet
1097          * retired the buffer.
1098          *
1099          * Note that the last_write_seqno is always the earlier of
1100          * the two (read/write) seqno, so if we haved successfully waited,
1101          * we know we have passed the last write.
1102          */
1103         obj->last_write_seqno = 0;
1104         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1105
1106         return 0;
1107 }
1108
1109 /**
1110  * Ensures that all rendering to the object has completed and the object is
1111  * safe to unbind from the GTT or access from the CPU.
1112  */
1113 static __must_check int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1115                                bool readonly)
1116 {
1117         struct intel_ring_buffer *ring = obj->ring;
1118         u32 seqno;
1119         int ret;
1120
1121         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1122         if (seqno == 0)
1123                 return 0;
1124
1125         ret = i915_wait_seqno(ring, seqno);
1126         if (ret)
1127                 return ret;
1128
1129         return i915_gem_object_wait_rendering__tail(obj, ring);
1130 }
1131
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133  * as the object state may change during this call.
1134  */
1135 static __must_check int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1137                                             bool readonly)
1138 {
1139         struct drm_device *dev = obj->base.dev;
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141         struct intel_ring_buffer *ring = obj->ring;
1142         unsigned reset_counter;
1143         u32 seqno;
1144         int ret;
1145
1146         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1147         BUG_ON(!dev_priv->mm.interruptible);
1148
1149         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1150         if (seqno == 0)
1151                 return 0;
1152
1153         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1154         if (ret)
1155                 return ret;
1156
1157         ret = i915_gem_check_olr(ring, seqno);
1158         if (ret)
1159                 return ret;
1160
1161         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1162         mutex_unlock(&dev->struct_mutex);
1163         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1164         mutex_lock(&dev->struct_mutex);
1165         if (ret)
1166                 return ret;
1167
1168         return i915_gem_object_wait_rendering__tail(obj, ring);
1169 }
1170
1171 /**
1172  * Called when user space prepares to use an object with the CPU, either
1173  * through the mmap ioctl's mapping or a GTT mapping.
1174  */
1175 int
1176 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1177                           struct drm_file *file)
1178 {
1179         struct drm_i915_gem_set_domain *args = data;
1180         struct drm_i915_gem_object *obj;
1181         uint32_t read_domains = args->read_domains;
1182         uint32_t write_domain = args->write_domain;
1183         int ret;
1184
1185         /* Only handle setting domains to types used by the CPU. */
1186         if (write_domain & I915_GEM_GPU_DOMAINS)
1187                 return -EINVAL;
1188
1189         if (read_domains & I915_GEM_GPU_DOMAINS)
1190                 return -EINVAL;
1191
1192         /* Having something in the write domain implies it's in the read
1193          * domain, and only that read domain.  Enforce that in the request.
1194          */
1195         if (write_domain != 0 && read_domains != write_domain)
1196                 return -EINVAL;
1197
1198         ret = i915_mutex_lock_interruptible(dev);
1199         if (ret)
1200                 return ret;
1201
1202         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1203         if (&obj->base == NULL) {
1204                 ret = -ENOENT;
1205                 goto unlock;
1206         }
1207
1208         /* Try to flush the object off the GPU without holding the lock.
1209          * We will repeat the flush holding the lock in the normal manner
1210          * to catch cases where we are gazumped.
1211          */
1212         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1213         if (ret)
1214                 goto unref;
1215
1216         if (read_domains & I915_GEM_DOMAIN_GTT) {
1217                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1218
1219                 /* Silently promote "you're not bound, there was nothing to do"
1220                  * to success, since the client was just asking us to
1221                  * make sure everything was done.
1222                  */
1223                 if (ret == -EINVAL)
1224                         ret = 0;
1225         } else {
1226                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1227         }
1228
1229 unref:
1230         drm_gem_object_unreference(&obj->base);
1231 unlock:
1232         mutex_unlock(&dev->struct_mutex);
1233         return ret;
1234 }
1235
1236 /**
1237  * Called when user space has done writes to this buffer
1238  */
1239 int
1240 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1241                          struct drm_file *file)
1242 {
1243         struct drm_i915_gem_sw_finish *args = data;
1244         struct drm_i915_gem_object *obj;
1245         int ret = 0;
1246
1247         ret = i915_mutex_lock_interruptible(dev);
1248         if (ret)
1249                 return ret;
1250
1251         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252         if (&obj->base == NULL) {
1253                 ret = -ENOENT;
1254                 goto unlock;
1255         }
1256
1257         /* Pinned buffers may be scanout, so flush the cache */
1258         if (obj->pin_count)
1259                 i915_gem_object_flush_cpu_write_domain(obj);
1260
1261         drm_gem_object_unreference(&obj->base);
1262 unlock:
1263         mutex_unlock(&dev->struct_mutex);
1264         return ret;
1265 }
1266
1267 /**
1268  * Maps the contents of an object, returning the address it is mapped
1269  * into.
1270  *
1271  * While the mapping holds a reference on the contents of the object, it doesn't
1272  * imply a ref on the object itself.
1273  */
1274 int
1275 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1276                     struct drm_file *file)
1277 {
1278         struct drm_i915_gem_mmap *args = data;
1279         struct drm_gem_object *obj;
1280         unsigned long addr;
1281
1282         obj = drm_gem_object_lookup(dev, file, args->handle);
1283         if (obj == NULL)
1284                 return -ENOENT;
1285
1286         /* prime objects have no backing filp to GEM mmap
1287          * pages from.
1288          */
1289         if (!obj->filp) {
1290                 drm_gem_object_unreference_unlocked(obj);
1291                 return -EINVAL;
1292         }
1293
1294         addr = vm_mmap(obj->filp, 0, args->size,
1295                        PROT_READ | PROT_WRITE, MAP_SHARED,
1296                        args->offset);
1297         drm_gem_object_unreference_unlocked(obj);
1298         if (IS_ERR((void *)addr))
1299                 return addr;
1300
1301         args->addr_ptr = (uint64_t) addr;
1302
1303         return 0;
1304 }
1305
1306 /**
1307  * i915_gem_fault - fault a page into the GTT
1308  * vma: VMA in question
1309  * vmf: fault info
1310  *
1311  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312  * from userspace.  The fault handler takes care of binding the object to
1313  * the GTT (if needed), allocating and programming a fence register (again,
1314  * only if needed based on whether the old reg is still valid or the object
1315  * is tiled) and inserting a new PTE into the faulting process.
1316  *
1317  * Note that the faulting process may involve evicting existing objects
1318  * from the GTT and/or fence registers to make room.  So performance may
1319  * suffer if the GTT working set is large or there are few fence registers
1320  * left.
1321  */
1322 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1323 {
1324         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1325         struct drm_device *dev = obj->base.dev;
1326         drm_i915_private_t *dev_priv = dev->dev_private;
1327         pgoff_t page_offset;
1328         unsigned long pfn;
1329         int ret = 0;
1330         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1331
1332         /* We don't use vmf->pgoff since that has the fake offset */
1333         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1334                 PAGE_SHIFT;
1335
1336         ret = i915_mutex_lock_interruptible(dev);
1337         if (ret)
1338                 goto out;
1339
1340         trace_i915_gem_object_fault(obj, page_offset, true, write);
1341
1342         /* Access to snoopable pages through the GTT is incoherent. */
1343         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1344                 ret = -EINVAL;
1345                 goto unlock;
1346         }
1347
1348         /* Now bind it into the GTT if needed */
1349         ret = i915_gem_object_pin(obj, 0, true, false);
1350         if (ret)
1351                 goto unlock;
1352
1353         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1354         if (ret)
1355                 goto unpin;
1356
1357         ret = i915_gem_object_get_fence(obj);
1358         if (ret)
1359                 goto unpin;
1360
1361         obj->fault_mappable = true;
1362
1363         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1364         pfn >>= PAGE_SHIFT;
1365         pfn += page_offset;
1366
1367         /* Finally, remap it using the new GTT offset */
1368         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1369 unpin:
1370         i915_gem_object_unpin(obj);
1371 unlock:
1372         mutex_unlock(&dev->struct_mutex);
1373 out:
1374         switch (ret) {
1375         case -EIO:
1376                 /* If this -EIO is due to a gpu hang, give the reset code a
1377                  * chance to clean up the mess. Otherwise return the proper
1378                  * SIGBUS. */
1379                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1380                         return VM_FAULT_SIGBUS;
1381         case -EAGAIN:
1382                 /* Give the error handler a chance to run and move the
1383                  * objects off the GPU active list. Next time we service the
1384                  * fault, we should be able to transition the page into the
1385                  * GTT without touching the GPU (and so avoid further
1386                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1387                  * with coherency, just lost writes.
1388                  */
1389                 set_need_resched();
1390         case 0:
1391         case -ERESTARTSYS:
1392         case -EINTR:
1393         case -EBUSY:
1394                 /*
1395                  * EBUSY is ok: this just means that another thread
1396                  * already did the job.
1397                  */
1398                 return VM_FAULT_NOPAGE;
1399         case -ENOMEM:
1400                 return VM_FAULT_OOM;
1401         case -ENOSPC:
1402                 return VM_FAULT_SIGBUS;
1403         default:
1404                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1405                 return VM_FAULT_SIGBUS;
1406         }
1407 }
1408
1409 /**
1410  * i915_gem_release_mmap - remove physical page mappings
1411  * @obj: obj in question
1412  *
1413  * Preserve the reservation of the mmapping with the DRM core code, but
1414  * relinquish ownership of the pages back to the system.
1415  *
1416  * It is vital that we remove the page mapping if we have mapped a tiled
1417  * object through the GTT and then lose the fence register due to
1418  * resource pressure. Similarly if the object has been moved out of the
1419  * aperture, than pages mapped into userspace must be revoked. Removing the
1420  * mapping will then trigger a page fault on the next user access, allowing
1421  * fixup by i915_gem_fault().
1422  */
1423 void
1424 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1425 {
1426         if (!obj->fault_mappable)
1427                 return;
1428
1429         if (obj->base.dev->dev_mapping)
1430                 unmap_mapping_range(obj->base.dev->dev_mapping,
1431                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1432                                     obj->base.size, 1);
1433
1434         obj->fault_mappable = false;
1435 }
1436
1437 uint32_t
1438 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1439 {
1440         uint32_t gtt_size;
1441
1442         if (INTEL_INFO(dev)->gen >= 4 ||
1443             tiling_mode == I915_TILING_NONE)
1444                 return size;
1445
1446         /* Previous chips need a power-of-two fence region when tiling */
1447         if (INTEL_INFO(dev)->gen == 3)
1448                 gtt_size = 1024*1024;
1449         else
1450                 gtt_size = 512*1024;
1451
1452         while (gtt_size < size)
1453                 gtt_size <<= 1;
1454
1455         return gtt_size;
1456 }
1457
1458 /**
1459  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1460  * @obj: object to check
1461  *
1462  * Return the required GTT alignment for an object, taking into account
1463  * potential fence register mapping.
1464  */
1465 uint32_t
1466 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1467                            int tiling_mode, bool fenced)
1468 {
1469         /*
1470          * Minimum alignment is 4k (GTT page size), but might be greater
1471          * if a fence register is needed for the object.
1472          */
1473         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1474             tiling_mode == I915_TILING_NONE)
1475                 return 4096;
1476
1477         /*
1478          * Previous chips need to be aligned to the size of the smallest
1479          * fence register that can contain the object.
1480          */
1481         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1482 }
1483
1484 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1485 {
1486         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1487         int ret;
1488
1489         if (obj->base.map_list.map)
1490                 return 0;
1491
1492         dev_priv->mm.shrinker_no_lock_stealing = true;
1493
1494         ret = drm_gem_create_mmap_offset(&obj->base);
1495         if (ret != -ENOSPC)
1496                 goto out;
1497
1498         /* Badly fragmented mmap space? The only way we can recover
1499          * space is by destroying unwanted objects. We can't randomly release
1500          * mmap_offsets as userspace expects them to be persistent for the
1501          * lifetime of the objects. The closest we can is to release the
1502          * offsets on purgeable objects by truncating it and marking it purged,
1503          * which prevents userspace from ever using that object again.
1504          */
1505         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1506         ret = drm_gem_create_mmap_offset(&obj->base);
1507         if (ret != -ENOSPC)
1508                 goto out;
1509
1510         i915_gem_shrink_all(dev_priv);
1511         ret = drm_gem_create_mmap_offset(&obj->base);
1512 out:
1513         dev_priv->mm.shrinker_no_lock_stealing = false;
1514
1515         return ret;
1516 }
1517
1518 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1519 {
1520         if (!obj->base.map_list.map)
1521                 return;
1522
1523         drm_gem_free_mmap_offset(&obj->base);
1524 }
1525
1526 int
1527 i915_gem_mmap_gtt(struct drm_file *file,
1528                   struct drm_device *dev,
1529                   uint32_t handle,
1530                   uint64_t *offset)
1531 {
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533         struct drm_i915_gem_object *obj;
1534         int ret;
1535
1536         ret = i915_mutex_lock_interruptible(dev);
1537         if (ret)
1538                 return ret;
1539
1540         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1541         if (&obj->base == NULL) {
1542                 ret = -ENOENT;
1543                 goto unlock;
1544         }
1545
1546         if (obj->base.size > dev_priv->gtt.mappable_end) {
1547                 ret = -E2BIG;
1548                 goto out;
1549         }
1550
1551         if (obj->madv != I915_MADV_WILLNEED) {
1552                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1553                 ret = -EINVAL;
1554                 goto out;
1555         }
1556
1557         ret = i915_gem_object_create_mmap_offset(obj);
1558         if (ret)
1559                 goto out;
1560
1561         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1562
1563 out:
1564         drm_gem_object_unreference(&obj->base);
1565 unlock:
1566         mutex_unlock(&dev->struct_mutex);
1567         return ret;
1568 }
1569
1570 /**
1571  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1572  * @dev: DRM device
1573  * @data: GTT mapping ioctl data
1574  * @file: GEM object info
1575  *
1576  * Simply returns the fake offset to userspace so it can mmap it.
1577  * The mmap call will end up in drm_gem_mmap(), which will set things
1578  * up so we can get faults in the handler above.
1579  *
1580  * The fault handler will take care of binding the object into the GTT
1581  * (since it may have been evicted to make room for something), allocating
1582  * a fence register, and mapping the appropriate aperture address into
1583  * userspace.
1584  */
1585 int
1586 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1587                         struct drm_file *file)
1588 {
1589         struct drm_i915_gem_mmap_gtt *args = data;
1590
1591         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1592 }
1593
1594 /* Immediately discard the backing storage */
1595 static void
1596 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1597 {
1598         struct inode *inode;
1599
1600         i915_gem_object_free_mmap_offset(obj);
1601
1602         if (obj->base.filp == NULL)
1603                 return;
1604
1605         /* Our goal here is to return as much of the memory as
1606          * is possible back to the system as we are called from OOM.
1607          * To do this we must instruct the shmfs to drop all of its
1608          * backing pages, *now*.
1609          */
1610         inode = file_inode(obj->base.filp);
1611         shmem_truncate_range(inode, 0, (loff_t)-1);
1612
1613         obj->madv = __I915_MADV_PURGED;
1614 }
1615
1616 static inline int
1617 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1618 {
1619         return obj->madv == I915_MADV_DONTNEED;
1620 }
1621
1622 static void
1623 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1624 {
1625         struct sg_page_iter sg_iter;
1626         int ret;
1627
1628         BUG_ON(obj->madv == __I915_MADV_PURGED);
1629
1630         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1631         if (ret) {
1632                 /* In the event of a disaster, abandon all caches and
1633                  * hope for the best.
1634                  */
1635                 WARN_ON(ret != -EIO);
1636                 i915_gem_clflush_object(obj);
1637                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1638         }
1639
1640         if (i915_gem_object_needs_bit17_swizzle(obj))
1641                 i915_gem_object_save_bit_17_swizzle(obj);
1642
1643         if (obj->madv == I915_MADV_DONTNEED)
1644                 obj->dirty = 0;
1645
1646         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1647                 struct page *page = sg_page_iter_page(&sg_iter);
1648
1649                 if (obj->dirty)
1650                         set_page_dirty(page);
1651
1652                 if (obj->madv == I915_MADV_WILLNEED)
1653                         mark_page_accessed(page);
1654
1655                 page_cache_release(page);
1656         }
1657         obj->dirty = 0;
1658
1659         sg_free_table(obj->pages);
1660         kfree(obj->pages);
1661 }
1662
1663 int
1664 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1665 {
1666         const struct drm_i915_gem_object_ops *ops = obj->ops;
1667
1668         if (obj->pages == NULL)
1669                 return 0;
1670
1671         BUG_ON(i915_gem_obj_ggtt_bound(obj));
1672
1673         if (obj->pages_pin_count)
1674                 return -EBUSY;
1675
1676         /* ->put_pages might need to allocate memory for the bit17 swizzle
1677          * array, hence protect them from being reaped by removing them from gtt
1678          * lists early. */
1679         list_del(&obj->global_list);
1680
1681         ops->put_pages(obj);
1682         obj->pages = NULL;
1683
1684         if (i915_gem_object_is_purgeable(obj))
1685                 i915_gem_object_truncate(obj);
1686
1687         return 0;
1688 }
1689
1690 static long
1691 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1692                   bool purgeable_only)
1693 {
1694         struct drm_i915_gem_object *obj, *next;
1695         struct i915_address_space *vm = &dev_priv->gtt.base;
1696         long count = 0;
1697
1698         list_for_each_entry_safe(obj, next,
1699                                  &dev_priv->mm.unbound_list,
1700                                  global_list) {
1701                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1702                     i915_gem_object_put_pages(obj) == 0) {
1703                         count += obj->base.size >> PAGE_SHIFT;
1704                         if (count >= target)
1705                                 return count;
1706                 }
1707         }
1708
1709         list_for_each_entry_safe(obj, next, &vm->inactive_list, mm_list) {
1710                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1711                     i915_gem_object_unbind(obj) == 0 &&
1712                     i915_gem_object_put_pages(obj) == 0) {
1713                         count += obj->base.size >> PAGE_SHIFT;
1714                         if (count >= target)
1715                                 return count;
1716                 }
1717         }
1718
1719         return count;
1720 }
1721
1722 static long
1723 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1724 {
1725         return __i915_gem_shrink(dev_priv, target, true);
1726 }
1727
1728 static void
1729 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1730 {
1731         struct drm_i915_gem_object *obj, *next;
1732
1733         i915_gem_evict_everything(dev_priv->dev);
1734
1735         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1736                                  global_list)
1737                 i915_gem_object_put_pages(obj);
1738 }
1739
1740 static int
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1742 {
1743         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1744         int page_count, i;
1745         struct address_space *mapping;
1746         struct sg_table *st;
1747         struct scatterlist *sg;
1748         struct sg_page_iter sg_iter;
1749         struct page *page;
1750         unsigned long last_pfn = 0;     /* suppress gcc warning */
1751         gfp_t gfp;
1752
1753         /* Assert that the object is not currently in any GPU domain. As it
1754          * wasn't in the GTT, there shouldn't be any way it could have been in
1755          * a GPU cache
1756          */
1757         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1758         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1759
1760         st = kmalloc(sizeof(*st), GFP_KERNEL);
1761         if (st == NULL)
1762                 return -ENOMEM;
1763
1764         page_count = obj->base.size / PAGE_SIZE;
1765         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1766                 sg_free_table(st);
1767                 kfree(st);
1768                 return -ENOMEM;
1769         }
1770
1771         /* Get the list of pages out of our struct file.  They'll be pinned
1772          * at this point until we release them.
1773          *
1774          * Fail silently without starting the shrinker
1775          */
1776         mapping = file_inode(obj->base.filp)->i_mapping;
1777         gfp = mapping_gfp_mask(mapping);
1778         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1779         gfp &= ~(__GFP_IO | __GFP_WAIT);
1780         sg = st->sgl;
1781         st->nents = 0;
1782         for (i = 0; i < page_count; i++) {
1783                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1784                 if (IS_ERR(page)) {
1785                         i915_gem_purge(dev_priv, page_count);
1786                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1787                 }
1788                 if (IS_ERR(page)) {
1789                         /* We've tried hard to allocate the memory by reaping
1790                          * our own buffer, now let the real VM do its job and
1791                          * go down in flames if truly OOM.
1792                          */
1793                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1794                         gfp |= __GFP_IO | __GFP_WAIT;
1795
1796                         i915_gem_shrink_all(dev_priv);
1797                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1798                         if (IS_ERR(page))
1799                                 goto err_pages;
1800
1801                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1802                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1803                 }
1804 #ifdef CONFIG_SWIOTLB
1805                 if (swiotlb_nr_tbl()) {
1806                         st->nents++;
1807                         sg_set_page(sg, page, PAGE_SIZE, 0);
1808                         sg = sg_next(sg);
1809                         continue;
1810                 }
1811 #endif
1812                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1813                         if (i)
1814                                 sg = sg_next(sg);
1815                         st->nents++;
1816                         sg_set_page(sg, page, PAGE_SIZE, 0);
1817                 } else {
1818                         sg->length += PAGE_SIZE;
1819                 }
1820                 last_pfn = page_to_pfn(page);
1821         }
1822 #ifdef CONFIG_SWIOTLB
1823         if (!swiotlb_nr_tbl())
1824 #endif
1825                 sg_mark_end(sg);
1826         obj->pages = st;
1827
1828         if (i915_gem_object_needs_bit17_swizzle(obj))
1829                 i915_gem_object_do_bit_17_swizzle(obj);
1830
1831         return 0;
1832
1833 err_pages:
1834         sg_mark_end(sg);
1835         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1836                 page_cache_release(sg_page_iter_page(&sg_iter));
1837         sg_free_table(st);
1838         kfree(st);
1839         return PTR_ERR(page);
1840 }
1841
1842 /* Ensure that the associated pages are gathered from the backing storage
1843  * and pinned into our object. i915_gem_object_get_pages() may be called
1844  * multiple times before they are released by a single call to
1845  * i915_gem_object_put_pages() - once the pages are no longer referenced
1846  * either as a result of memory pressure (reaping pages under the shrinker)
1847  * or as the object is itself released.
1848  */
1849 int
1850 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1851 {
1852         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1853         const struct drm_i915_gem_object_ops *ops = obj->ops;
1854         int ret;
1855
1856         if (obj->pages)
1857                 return 0;
1858
1859         if (obj->madv != I915_MADV_WILLNEED) {
1860                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1861                 return -EINVAL;
1862         }
1863
1864         BUG_ON(obj->pages_pin_count);
1865
1866         ret = ops->get_pages(obj);
1867         if (ret)
1868                 return ret;
1869
1870         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1871         return 0;
1872 }
1873
1874 void
1875 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1876                                struct intel_ring_buffer *ring)
1877 {
1878         struct drm_device *dev = obj->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         struct i915_address_space *vm = &dev_priv->gtt.base;
1881         u32 seqno = intel_ring_get_seqno(ring);
1882
1883         BUG_ON(ring == NULL);
1884         obj->ring = ring;
1885
1886         /* Add a reference if we're newly entering the active list. */
1887         if (!obj->active) {
1888                 drm_gem_object_reference(&obj->base);
1889                 obj->active = 1;
1890         }
1891
1892         /* Move from whatever list we were on to the tail of execution. */
1893         list_move_tail(&obj->mm_list, &vm->active_list);
1894         list_move_tail(&obj->ring_list, &ring->active_list);
1895
1896         obj->last_read_seqno = seqno;
1897
1898         if (obj->fenced_gpu_access) {
1899                 obj->last_fenced_seqno = seqno;
1900
1901                 /* Bump MRU to take account of the delayed flush */
1902                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1903                         struct drm_i915_fence_reg *reg;
1904
1905                         reg = &dev_priv->fence_regs[obj->fence_reg];
1906                         list_move_tail(&reg->lru_list,
1907                                        &dev_priv->mm.fence_list);
1908                 }
1909         }
1910 }
1911
1912 static void
1913 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1914 {
1915         struct drm_device *dev = obj->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct i915_address_space *vm = &dev_priv->gtt.base;
1918
1919         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1920         BUG_ON(!obj->active);
1921
1922         list_move_tail(&obj->mm_list, &vm->inactive_list);
1923
1924         list_del_init(&obj->ring_list);
1925         obj->ring = NULL;
1926
1927         obj->last_read_seqno = 0;
1928         obj->last_write_seqno = 0;
1929         obj->base.write_domain = 0;
1930
1931         obj->last_fenced_seqno = 0;
1932         obj->fenced_gpu_access = false;
1933
1934         obj->active = 0;
1935         drm_gem_object_unreference(&obj->base);
1936
1937         WARN_ON(i915_verify_lists(dev));
1938 }
1939
1940 static int
1941 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1942 {
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         struct intel_ring_buffer *ring;
1945         int ret, i, j;
1946
1947         /* Carefully retire all requests without writing to the rings */
1948         for_each_ring(ring, dev_priv, i) {
1949                 ret = intel_ring_idle(ring);
1950                 if (ret)
1951                         return ret;
1952         }
1953         i915_gem_retire_requests(dev);
1954
1955         /* Finally reset hw state */
1956         for_each_ring(ring, dev_priv, i) {
1957                 intel_ring_init_seqno(ring, seqno);
1958
1959                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1960                         ring->sync_seqno[j] = 0;
1961         }
1962
1963         return 0;
1964 }
1965
1966 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1967 {
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         int ret;
1970
1971         if (seqno == 0)
1972                 return -EINVAL;
1973
1974         /* HWS page needs to be set less than what we
1975          * will inject to ring
1976          */
1977         ret = i915_gem_init_seqno(dev, seqno - 1);
1978         if (ret)
1979                 return ret;
1980
1981         /* Carefully set the last_seqno value so that wrap
1982          * detection still works
1983          */
1984         dev_priv->next_seqno = seqno;
1985         dev_priv->last_seqno = seqno - 1;
1986         if (dev_priv->last_seqno == 0)
1987                 dev_priv->last_seqno--;
1988
1989         return 0;
1990 }
1991
1992 int
1993 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1994 {
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996
1997         /* reserve 0 for non-seqno */
1998         if (dev_priv->next_seqno == 0) {
1999                 int ret = i915_gem_init_seqno(dev, 0);
2000                 if (ret)
2001                         return ret;
2002
2003                 dev_priv->next_seqno = 1;
2004         }
2005
2006         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2007         return 0;
2008 }
2009
2010 int __i915_add_request(struct intel_ring_buffer *ring,
2011                        struct drm_file *file,
2012                        struct drm_i915_gem_object *obj,
2013                        u32 *out_seqno)
2014 {
2015         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2016         struct drm_i915_gem_request *request;
2017         u32 request_ring_position, request_start;
2018         int was_empty;
2019         int ret;
2020
2021         request_start = intel_ring_get_tail(ring);
2022         /*
2023          * Emit any outstanding flushes - execbuf can fail to emit the flush
2024          * after having emitted the batchbuffer command. Hence we need to fix
2025          * things up similar to emitting the lazy request. The difference here
2026          * is that the flush _must_ happen before the next request, no matter
2027          * what.
2028          */
2029         ret = intel_ring_flush_all_caches(ring);
2030         if (ret)
2031                 return ret;
2032
2033         request = kmalloc(sizeof(*request), GFP_KERNEL);
2034         if (request == NULL)
2035                 return -ENOMEM;
2036
2037
2038         /* Record the position of the start of the request so that
2039          * should we detect the updated seqno part-way through the
2040          * GPU processing the request, we never over-estimate the
2041          * position of the head.
2042          */
2043         request_ring_position = intel_ring_get_tail(ring);
2044
2045         ret = ring->add_request(ring);
2046         if (ret) {
2047                 kfree(request);
2048                 return ret;
2049         }
2050
2051         request->seqno = intel_ring_get_seqno(ring);
2052         request->ring = ring;
2053         request->head = request_start;
2054         request->tail = request_ring_position;
2055         request->ctx = ring->last_context;
2056         request->batch_obj = obj;
2057
2058         /* Whilst this request exists, batch_obj will be on the
2059          * active_list, and so will hold the active reference. Only when this
2060          * request is retired will the the batch_obj be moved onto the
2061          * inactive_list and lose its active reference. Hence we do not need
2062          * to explicitly hold another reference here.
2063          */
2064
2065         if (request->ctx)
2066                 i915_gem_context_reference(request->ctx);
2067
2068         request->emitted_jiffies = jiffies;
2069         was_empty = list_empty(&ring->request_list);
2070         list_add_tail(&request->list, &ring->request_list);
2071         request->file_priv = NULL;
2072
2073         if (file) {
2074                 struct drm_i915_file_private *file_priv = file->driver_priv;
2075
2076                 spin_lock(&file_priv->mm.lock);
2077                 request->file_priv = file_priv;
2078                 list_add_tail(&request->client_list,
2079                               &file_priv->mm.request_list);
2080                 spin_unlock(&file_priv->mm.lock);
2081         }
2082
2083         trace_i915_gem_request_add(ring, request->seqno);
2084         ring->outstanding_lazy_request = 0;
2085
2086         if (!dev_priv->ums.mm_suspended) {
2087                 i915_queue_hangcheck(ring->dev);
2088
2089                 if (was_empty) {
2090                         queue_delayed_work(dev_priv->wq,
2091                                            &dev_priv->mm.retire_work,
2092                                            round_jiffies_up_relative(HZ));
2093                         intel_mark_busy(dev_priv->dev);
2094                 }
2095         }
2096
2097         if (out_seqno)
2098                 *out_seqno = request->seqno;
2099         return 0;
2100 }
2101
2102 static inline void
2103 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2104 {
2105         struct drm_i915_file_private *file_priv = request->file_priv;
2106
2107         if (!file_priv)
2108                 return;
2109
2110         spin_lock(&file_priv->mm.lock);
2111         if (request->file_priv) {
2112                 list_del(&request->client_list);
2113                 request->file_priv = NULL;
2114         }
2115         spin_unlock(&file_priv->mm.lock);
2116 }
2117
2118 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2119 {
2120         if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
2121             acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
2122                 return true;
2123
2124         return false;
2125 }
2126
2127 static bool i915_head_inside_request(const u32 acthd_unmasked,
2128                                      const u32 request_start,
2129                                      const u32 request_end)
2130 {
2131         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2132
2133         if (request_start < request_end) {
2134                 if (acthd >= request_start && acthd < request_end)
2135                         return true;
2136         } else if (request_start > request_end) {
2137                 if (acthd >= request_start || acthd < request_end)
2138                         return true;
2139         }
2140
2141         return false;
2142 }
2143
2144 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2145                                 const u32 acthd, bool *inside)
2146 {
2147         /* There is a possibility that unmasked head address
2148          * pointing inside the ring, matches the batch_obj address range.
2149          * However this is extremely unlikely.
2150          */
2151
2152         if (request->batch_obj) {
2153                 if (i915_head_inside_object(acthd, request->batch_obj)) {
2154                         *inside = true;
2155                         return true;
2156                 }
2157         }
2158
2159         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2160                 *inside = false;
2161                 return true;
2162         }
2163
2164         return false;
2165 }
2166
2167 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2168                                   struct drm_i915_gem_request *request,
2169                                   u32 acthd)
2170 {
2171         struct i915_ctx_hang_stats *hs = NULL;
2172         bool inside, guilty;
2173
2174         /* Innocent until proven guilty */
2175         guilty = false;
2176
2177         if (ring->hangcheck.action != wait &&
2178             i915_request_guilty(request, acthd, &inside)) {
2179                 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2180                           ring->name,
2181                           inside ? "inside" : "flushing",
2182                           request->batch_obj ?
2183                           i915_gem_obj_ggtt_offset(request->batch_obj) : 0,
2184                           request->ctx ? request->ctx->id : 0,
2185                           acthd);
2186
2187                 guilty = true;
2188         }
2189
2190         /* If contexts are disabled or this is the default context, use
2191          * file_priv->reset_state
2192          */
2193         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2194                 hs = &request->ctx->hang_stats;
2195         else if (request->file_priv)
2196                 hs = &request->file_priv->hang_stats;
2197
2198         if (hs) {
2199                 if (guilty)
2200                         hs->batch_active++;
2201                 else
2202                         hs->batch_pending++;
2203         }
2204 }
2205
2206 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2207 {
2208         list_del(&request->list);
2209         i915_gem_request_remove_from_client(request);
2210
2211         if (request->ctx)
2212                 i915_gem_context_unreference(request->ctx);
2213
2214         kfree(request);
2215 }
2216
2217 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2218                                       struct intel_ring_buffer *ring)
2219 {
2220         u32 completed_seqno;
2221         u32 acthd;
2222
2223         acthd = intel_ring_get_active_head(ring);
2224         completed_seqno = ring->get_seqno(ring, false);
2225
2226         while (!list_empty(&ring->request_list)) {
2227                 struct drm_i915_gem_request *request;
2228
2229                 request = list_first_entry(&ring->request_list,
2230                                            struct drm_i915_gem_request,
2231                                            list);
2232
2233                 if (request->seqno > completed_seqno)
2234                         i915_set_reset_status(ring, request, acthd);
2235
2236                 i915_gem_free_request(request);
2237         }
2238
2239         while (!list_empty(&ring->active_list)) {
2240                 struct drm_i915_gem_object *obj;
2241
2242                 obj = list_first_entry(&ring->active_list,
2243                                        struct drm_i915_gem_object,
2244                                        ring_list);
2245
2246                 i915_gem_object_move_to_inactive(obj);
2247         }
2248 }
2249
2250 static void i915_gem_reset_fences(struct drm_device *dev)
2251 {
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         int i;
2254
2255         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2256                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2257
2258                 if (reg->obj)
2259                         i915_gem_object_fence_lost(reg->obj);
2260
2261                 i915_gem_write_fence(dev, i, NULL);
2262
2263                 reg->pin_count = 0;
2264                 reg->obj = NULL;
2265                 INIT_LIST_HEAD(&reg->lru_list);
2266         }
2267
2268         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2269 }
2270
2271 void i915_gem_reset(struct drm_device *dev)
2272 {
2273         struct drm_i915_private *dev_priv = dev->dev_private;
2274         struct i915_address_space *vm = &dev_priv->gtt.base;
2275         struct drm_i915_gem_object *obj;
2276         struct intel_ring_buffer *ring;
2277         int i;
2278
2279         for_each_ring(ring, dev_priv, i)
2280                 i915_gem_reset_ring_lists(dev_priv, ring);
2281
2282         /* Move everything out of the GPU domains to ensure we do any
2283          * necessary invalidation upon reuse.
2284          */
2285         list_for_each_entry(obj, &vm->inactive_list, mm_list)
2286                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2287
2288         /* The fence registers are invalidated so clear them out */
2289         i915_gem_reset_fences(dev);
2290 }
2291
2292 /**
2293  * This function clears the request list as sequence numbers are passed.
2294  */
2295 void
2296 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2297 {
2298         uint32_t seqno;
2299
2300         if (list_empty(&ring->request_list))
2301                 return;
2302
2303         WARN_ON(i915_verify_lists(ring->dev));
2304
2305         seqno = ring->get_seqno(ring, true);
2306
2307         while (!list_empty(&ring->request_list)) {
2308                 struct drm_i915_gem_request *request;
2309
2310                 request = list_first_entry(&ring->request_list,
2311                                            struct drm_i915_gem_request,
2312                                            list);
2313
2314                 if (!i915_seqno_passed(seqno, request->seqno))
2315                         break;
2316
2317                 trace_i915_gem_request_retire(ring, request->seqno);
2318                 /* We know the GPU must have read the request to have
2319                  * sent us the seqno + interrupt, so use the position
2320                  * of tail of the request to update the last known position
2321                  * of the GPU head.
2322                  */
2323                 ring->last_retired_head = request->tail;
2324
2325                 i915_gem_free_request(request);
2326         }
2327
2328         /* Move any buffers on the active list that are no longer referenced
2329          * by the ringbuffer to the flushing/inactive lists as appropriate.
2330          */
2331         while (!list_empty(&ring->active_list)) {
2332                 struct drm_i915_gem_object *obj;
2333
2334                 obj = list_first_entry(&ring->active_list,
2335                                       struct drm_i915_gem_object,
2336                                       ring_list);
2337
2338                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2339                         break;
2340
2341                 i915_gem_object_move_to_inactive(obj);
2342         }
2343
2344         if (unlikely(ring->trace_irq_seqno &&
2345                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2346                 ring->irq_put(ring);
2347                 ring->trace_irq_seqno = 0;
2348         }
2349
2350         WARN_ON(i915_verify_lists(ring->dev));
2351 }
2352
2353 void
2354 i915_gem_retire_requests(struct drm_device *dev)
2355 {
2356         drm_i915_private_t *dev_priv = dev->dev_private;
2357         struct intel_ring_buffer *ring;
2358         int i;
2359
2360         for_each_ring(ring, dev_priv, i)
2361                 i915_gem_retire_requests_ring(ring);
2362 }
2363
2364 static void
2365 i915_gem_retire_work_handler(struct work_struct *work)
2366 {
2367         drm_i915_private_t *dev_priv;
2368         struct drm_device *dev;
2369         struct intel_ring_buffer *ring;
2370         bool idle;
2371         int i;
2372
2373         dev_priv = container_of(work, drm_i915_private_t,
2374                                 mm.retire_work.work);
2375         dev = dev_priv->dev;
2376
2377         /* Come back later if the device is busy... */
2378         if (!mutex_trylock(&dev->struct_mutex)) {
2379                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2380                                    round_jiffies_up_relative(HZ));
2381                 return;
2382         }
2383
2384         i915_gem_retire_requests(dev);
2385
2386         /* Send a periodic flush down the ring so we don't hold onto GEM
2387          * objects indefinitely.
2388          */
2389         idle = true;
2390         for_each_ring(ring, dev_priv, i) {
2391                 if (ring->gpu_caches_dirty)
2392                         i915_add_request(ring, NULL);
2393
2394                 idle &= list_empty(&ring->request_list);
2395         }
2396
2397         if (!dev_priv->ums.mm_suspended && !idle)
2398                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2399                                    round_jiffies_up_relative(HZ));
2400         if (idle)
2401                 intel_mark_idle(dev);
2402
2403         mutex_unlock(&dev->struct_mutex);
2404 }
2405
2406 /**
2407  * Ensures that an object will eventually get non-busy by flushing any required
2408  * write domains, emitting any outstanding lazy request and retiring and
2409  * completed requests.
2410  */
2411 static int
2412 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2413 {
2414         int ret;
2415
2416         if (obj->active) {
2417                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2418                 if (ret)
2419                         return ret;
2420
2421                 i915_gem_retire_requests_ring(obj->ring);
2422         }
2423
2424         return 0;
2425 }
2426
2427 /**
2428  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2429  * @DRM_IOCTL_ARGS: standard ioctl arguments
2430  *
2431  * Returns 0 if successful, else an error is returned with the remaining time in
2432  * the timeout parameter.
2433  *  -ETIME: object is still busy after timeout
2434  *  -ERESTARTSYS: signal interrupted the wait
2435  *  -ENONENT: object doesn't exist
2436  * Also possible, but rare:
2437  *  -EAGAIN: GPU wedged
2438  *  -ENOMEM: damn
2439  *  -ENODEV: Internal IRQ fail
2440  *  -E?: The add request failed
2441  *
2442  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2443  * non-zero timeout parameter the wait ioctl will wait for the given number of
2444  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2445  * without holding struct_mutex the object may become re-busied before this
2446  * function completes. A similar but shorter * race condition exists in the busy
2447  * ioctl
2448  */
2449 int
2450 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2451 {
2452         drm_i915_private_t *dev_priv = dev->dev_private;
2453         struct drm_i915_gem_wait *args = data;
2454         struct drm_i915_gem_object *obj;
2455         struct intel_ring_buffer *ring = NULL;
2456         struct timespec timeout_stack, *timeout = NULL;
2457         unsigned reset_counter;
2458         u32 seqno = 0;
2459         int ret = 0;
2460
2461         if (args->timeout_ns >= 0) {
2462                 timeout_stack = ns_to_timespec(args->timeout_ns);
2463                 timeout = &timeout_stack;
2464         }
2465
2466         ret = i915_mutex_lock_interruptible(dev);
2467         if (ret)
2468                 return ret;
2469
2470         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2471         if (&obj->base == NULL) {
2472                 mutex_unlock(&dev->struct_mutex);
2473                 return -ENOENT;
2474         }
2475
2476         /* Need to make sure the object gets inactive eventually. */
2477         ret = i915_gem_object_flush_active(obj);
2478         if (ret)
2479                 goto out;
2480
2481         if (obj->active) {
2482                 seqno = obj->last_read_seqno;
2483                 ring = obj->ring;
2484         }
2485
2486         if (seqno == 0)
2487                  goto out;
2488
2489         /* Do this after OLR check to make sure we make forward progress polling
2490          * on this IOCTL with a 0 timeout (like busy ioctl)
2491          */
2492         if (!args->timeout_ns) {
2493                 ret = -ETIME;
2494                 goto out;
2495         }
2496
2497         drm_gem_object_unreference(&obj->base);
2498         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2499         mutex_unlock(&dev->struct_mutex);
2500
2501         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2502         if (timeout)
2503                 args->timeout_ns = timespec_to_ns(timeout);
2504         return ret;
2505
2506 out:
2507         drm_gem_object_unreference(&obj->base);
2508         mutex_unlock(&dev->struct_mutex);
2509         return ret;
2510 }
2511
2512 /**
2513  * i915_gem_object_sync - sync an object to a ring.
2514  *
2515  * @obj: object which may be in use on another ring.
2516  * @to: ring we wish to use the object on. May be NULL.
2517  *
2518  * This code is meant to abstract object synchronization with the GPU.
2519  * Calling with NULL implies synchronizing the object with the CPU
2520  * rather than a particular GPU ring.
2521  *
2522  * Returns 0 if successful, else propagates up the lower layer error.
2523  */
2524 int
2525 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2526                      struct intel_ring_buffer *to)
2527 {
2528         struct intel_ring_buffer *from = obj->ring;
2529         u32 seqno;
2530         int ret, idx;
2531
2532         if (from == NULL || to == from)
2533                 return 0;
2534
2535         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2536                 return i915_gem_object_wait_rendering(obj, false);
2537
2538         idx = intel_ring_sync_index(from, to);
2539
2540         seqno = obj->last_read_seqno;
2541         if (seqno <= from->sync_seqno[idx])
2542                 return 0;
2543
2544         ret = i915_gem_check_olr(obj->ring, seqno);
2545         if (ret)
2546                 return ret;
2547
2548         ret = to->sync_to(to, from, seqno);
2549         if (!ret)
2550                 /* We use last_read_seqno because sync_to()
2551                  * might have just caused seqno wrap under
2552                  * the radar.
2553                  */
2554                 from->sync_seqno[idx] = obj->last_read_seqno;
2555
2556         return ret;
2557 }
2558
2559 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2560 {
2561         u32 old_write_domain, old_read_domains;
2562
2563         /* Force a pagefault for domain tracking on next user access */
2564         i915_gem_release_mmap(obj);
2565
2566         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2567                 return;
2568
2569         /* Wait for any direct GTT access to complete */
2570         mb();
2571
2572         old_read_domains = obj->base.read_domains;
2573         old_write_domain = obj->base.write_domain;
2574
2575         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2576         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2577
2578         trace_i915_gem_object_change_domain(obj,
2579                                             old_read_domains,
2580                                             old_write_domain);
2581 }
2582
2583 /**
2584  * Unbinds an object from the GTT aperture.
2585  */
2586 int
2587 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2588 {
2589         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2590         struct i915_vma *vma;
2591         int ret;
2592
2593         if (!i915_gem_obj_ggtt_bound(obj))
2594                 return 0;
2595
2596         if (obj->pin_count)
2597                 return -EBUSY;
2598
2599         BUG_ON(obj->pages == NULL);
2600
2601         ret = i915_gem_object_finish_gpu(obj);
2602         if (ret)
2603                 return ret;
2604         /* Continue on if we fail due to EIO, the GPU is hung so we
2605          * should be safe and we need to cleanup or else we might
2606          * cause memory corruption through use-after-free.
2607          */
2608
2609         i915_gem_object_finish_gtt(obj);
2610
2611         /* release the fence reg _after_ flushing */
2612         ret = i915_gem_object_put_fence(obj);
2613         if (ret)
2614                 return ret;
2615
2616         trace_i915_gem_object_unbind(obj);
2617
2618         if (obj->has_global_gtt_mapping)
2619                 i915_gem_gtt_unbind_object(obj);
2620         if (obj->has_aliasing_ppgtt_mapping) {
2621                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2622                 obj->has_aliasing_ppgtt_mapping = 0;
2623         }
2624         i915_gem_gtt_finish_object(obj);
2625         i915_gem_object_unpin_pages(obj);
2626
2627         list_del(&obj->mm_list);
2628         /* Avoid an unnecessary call to unbind on rebind. */
2629         obj->map_and_fenceable = true;
2630
2631         vma = __i915_gem_obj_to_vma(obj);
2632         list_del(&vma->vma_link);
2633         drm_mm_remove_node(&vma->node);
2634         i915_gem_vma_destroy(vma);
2635
2636         /* Since the unbound list is global, only move to that list if
2637          * no more VMAs exist.
2638          * NB: Until we have real VMAs there will only ever be one */
2639         WARN_ON(!list_empty(&obj->vma_list));
2640         if (list_empty(&obj->vma_list))
2641                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2642
2643         return 0;
2644 }
2645
2646 int i915_gpu_idle(struct drm_device *dev)
2647 {
2648         drm_i915_private_t *dev_priv = dev->dev_private;
2649         struct intel_ring_buffer *ring;
2650         int ret, i;
2651
2652         /* Flush everything onto the inactive list. */
2653         for_each_ring(ring, dev_priv, i) {
2654                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2655                 if (ret)
2656                         return ret;
2657
2658                 ret = intel_ring_idle(ring);
2659                 if (ret)
2660                         return ret;
2661         }
2662
2663         return 0;
2664 }
2665
2666 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2667                                  struct drm_i915_gem_object *obj)
2668 {
2669         drm_i915_private_t *dev_priv = dev->dev_private;
2670         int fence_reg;
2671         int fence_pitch_shift;
2672         uint64_t val;
2673
2674         if (INTEL_INFO(dev)->gen >= 6) {
2675                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2676                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2677         } else {
2678                 fence_reg = FENCE_REG_965_0;
2679                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2680         }
2681
2682         if (obj) {
2683                 u32 size = i915_gem_obj_ggtt_size(obj);
2684
2685                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2686                                  0xfffff000) << 32;
2687                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2688                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2689                 if (obj->tiling_mode == I915_TILING_Y)
2690                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2691                 val |= I965_FENCE_REG_VALID;
2692         } else
2693                 val = 0;
2694
2695         fence_reg += reg * 8;
2696         I915_WRITE64(fence_reg, val);
2697         POSTING_READ(fence_reg);
2698 }
2699
2700 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2701                                  struct drm_i915_gem_object *obj)
2702 {
2703         drm_i915_private_t *dev_priv = dev->dev_private;
2704         u32 val;
2705
2706         if (obj) {
2707                 u32 size = i915_gem_obj_ggtt_size(obj);
2708                 int pitch_val;
2709                 int tile_width;
2710
2711                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2712                      (size & -size) != size ||
2713                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2714                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2715                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2716
2717                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2718                         tile_width = 128;
2719                 else
2720                         tile_width = 512;
2721
2722                 /* Note: pitch better be a power of two tile widths */
2723                 pitch_val = obj->stride / tile_width;
2724                 pitch_val = ffs(pitch_val) - 1;
2725
2726                 val = i915_gem_obj_ggtt_offset(obj);
2727                 if (obj->tiling_mode == I915_TILING_Y)
2728                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2729                 val |= I915_FENCE_SIZE_BITS(size);
2730                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2731                 val |= I830_FENCE_REG_VALID;
2732         } else
2733                 val = 0;
2734
2735         if (reg < 8)
2736                 reg = FENCE_REG_830_0 + reg * 4;
2737         else
2738                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2739
2740         I915_WRITE(reg, val);
2741         POSTING_READ(reg);
2742 }
2743
2744 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2745                                 struct drm_i915_gem_object *obj)
2746 {
2747         drm_i915_private_t *dev_priv = dev->dev_private;
2748         uint32_t val;
2749
2750         if (obj) {
2751                 u32 size = i915_gem_obj_ggtt_size(obj);
2752                 uint32_t pitch_val;
2753
2754                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2755                      (size & -size) != size ||
2756                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2757                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2758                      i915_gem_obj_ggtt_offset(obj), size);
2759
2760                 pitch_val = obj->stride / 128;
2761                 pitch_val = ffs(pitch_val) - 1;
2762
2763                 val = i915_gem_obj_ggtt_offset(obj);
2764                 if (obj->tiling_mode == I915_TILING_Y)
2765                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2766                 val |= I830_FENCE_SIZE_BITS(size);
2767                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2768                 val |= I830_FENCE_REG_VALID;
2769         } else
2770                 val = 0;
2771
2772         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2773         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2774 }
2775
2776 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2777 {
2778         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2779 }
2780
2781 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2782                                  struct drm_i915_gem_object *obj)
2783 {
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785
2786         /* Ensure that all CPU reads are completed before installing a fence
2787          * and all writes before removing the fence.
2788          */
2789         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2790                 mb();
2791
2792         switch (INTEL_INFO(dev)->gen) {
2793         case 7:
2794         case 6:
2795         case 5:
2796         case 4: i965_write_fence_reg(dev, reg, obj); break;
2797         case 3: i915_write_fence_reg(dev, reg, obj); break;
2798         case 2: i830_write_fence_reg(dev, reg, obj); break;
2799         default: BUG();
2800         }
2801
2802         /* And similarly be paranoid that no direct access to this region
2803          * is reordered to before the fence is installed.
2804          */
2805         if (i915_gem_object_needs_mb(obj))
2806                 mb();
2807 }
2808
2809 static inline int fence_number(struct drm_i915_private *dev_priv,
2810                                struct drm_i915_fence_reg *fence)
2811 {
2812         return fence - dev_priv->fence_regs;
2813 }
2814
2815 struct write_fence {
2816         struct drm_device *dev;
2817         struct drm_i915_gem_object *obj;
2818         int fence;
2819 };
2820
2821 static void i915_gem_write_fence__ipi(void *data)
2822 {
2823         struct write_fence *args = data;
2824
2825         /* Required for SNB+ with LLC */
2826         wbinvd();
2827
2828         /* Required for VLV */
2829         i915_gem_write_fence(args->dev, args->fence, args->obj);
2830 }
2831
2832 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2833                                          struct drm_i915_fence_reg *fence,
2834                                          bool enable)
2835 {
2836         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2837         struct write_fence args = {
2838                 .dev = obj->base.dev,
2839                 .fence = fence_number(dev_priv, fence),
2840                 .obj = enable ? obj : NULL,
2841         };
2842
2843         /* In order to fully serialize access to the fenced region and
2844          * the update to the fence register we need to take extreme
2845          * measures on SNB+. In theory, the write to the fence register
2846          * flushes all memory transactions before, and coupled with the
2847          * mb() placed around the register write we serialise all memory
2848          * operations with respect to the changes in the tiler. Yet, on
2849          * SNB+ we need to take a step further and emit an explicit wbinvd()
2850          * on each processor in order to manually flush all memory
2851          * transactions before updating the fence register.
2852          *
2853          * However, Valleyview complicates matter. There the wbinvd is
2854          * insufficient and unlike SNB/IVB requires the serialising
2855          * register write. (Note that that register write by itself is
2856          * conversely not sufficient for SNB+.) To compromise, we do both.
2857          */
2858         if (INTEL_INFO(args.dev)->gen >= 6)
2859                 on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
2860         else
2861                 i915_gem_write_fence(args.dev, args.fence, args.obj);
2862
2863         if (enable) {
2864                 obj->fence_reg = args.fence;
2865                 fence->obj = obj;
2866                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2867         } else {
2868                 obj->fence_reg = I915_FENCE_REG_NONE;
2869                 fence->obj = NULL;
2870                 list_del_init(&fence->lru_list);
2871         }
2872 }
2873
2874 static int
2875 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2876 {
2877         if (obj->last_fenced_seqno) {
2878                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2879                 if (ret)
2880                         return ret;
2881
2882                 obj->last_fenced_seqno = 0;
2883         }
2884
2885         obj->fenced_gpu_access = false;
2886         return 0;
2887 }
2888
2889 int
2890 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2891 {
2892         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2893         struct drm_i915_fence_reg *fence;
2894         int ret;
2895
2896         ret = i915_gem_object_wait_fence(obj);
2897         if (ret)
2898                 return ret;
2899
2900         if (obj->fence_reg == I915_FENCE_REG_NONE)
2901                 return 0;
2902
2903         fence = &dev_priv->fence_regs[obj->fence_reg];
2904
2905         i915_gem_object_fence_lost(obj);
2906         i915_gem_object_update_fence(obj, fence, false);
2907
2908         return 0;
2909 }
2910
2911 static struct drm_i915_fence_reg *
2912 i915_find_fence_reg(struct drm_device *dev)
2913 {
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         struct drm_i915_fence_reg *reg, *avail;
2916         int i;
2917
2918         /* First try to find a free reg */
2919         avail = NULL;
2920         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2921                 reg = &dev_priv->fence_regs[i];
2922                 if (!reg->obj)
2923                         return reg;
2924
2925                 if (!reg->pin_count)
2926                         avail = reg;
2927         }
2928
2929         if (avail == NULL)
2930                 return NULL;
2931
2932         /* None available, try to steal one or wait for a user to finish */
2933         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2934                 if (reg->pin_count)
2935                         continue;
2936
2937                 return reg;
2938         }
2939
2940         return NULL;
2941 }
2942
2943 /**
2944  * i915_gem_object_get_fence - set up fencing for an object
2945  * @obj: object to map through a fence reg
2946  *
2947  * When mapping objects through the GTT, userspace wants to be able to write
2948  * to them without having to worry about swizzling if the object is tiled.
2949  * This function walks the fence regs looking for a free one for @obj,
2950  * stealing one if it can't find any.
2951  *
2952  * It then sets up the reg based on the object's properties: address, pitch
2953  * and tiling format.
2954  *
2955  * For an untiled surface, this removes any existing fence.
2956  */
2957 int
2958 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2959 {
2960         struct drm_device *dev = obj->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         bool enable = obj->tiling_mode != I915_TILING_NONE;
2963         struct drm_i915_fence_reg *reg;
2964         int ret;
2965
2966         /* Have we updated the tiling parameters upon the object and so
2967          * will need to serialise the write to the associated fence register?
2968          */
2969         if (obj->fence_dirty) {
2970                 ret = i915_gem_object_wait_fence(obj);
2971                 if (ret)
2972                         return ret;
2973         }
2974
2975         /* Just update our place in the LRU if our fence is getting reused. */
2976         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2977                 reg = &dev_priv->fence_regs[obj->fence_reg];
2978                 if (!obj->fence_dirty) {
2979                         list_move_tail(&reg->lru_list,
2980                                        &dev_priv->mm.fence_list);
2981                         return 0;
2982                 }
2983         } else if (enable) {
2984                 reg = i915_find_fence_reg(dev);
2985                 if (reg == NULL)
2986                         return -EDEADLK;
2987
2988                 if (reg->obj) {
2989                         struct drm_i915_gem_object *old = reg->obj;
2990
2991                         ret = i915_gem_object_wait_fence(old);
2992                         if (ret)
2993                                 return ret;
2994
2995                         i915_gem_object_fence_lost(old);
2996                 }
2997         } else
2998                 return 0;
2999
3000         i915_gem_object_update_fence(obj, reg, enable);
3001         obj->fence_dirty = false;
3002
3003         return 0;
3004 }
3005
3006 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3007                                      struct drm_mm_node *gtt_space,
3008                                      unsigned long cache_level)
3009 {
3010         struct drm_mm_node *other;
3011
3012         /* On non-LLC machines we have to be careful when putting differing
3013          * types of snoopable memory together to avoid the prefetcher
3014          * crossing memory domains and dying.
3015          */
3016         if (HAS_LLC(dev))
3017                 return true;
3018
3019         if (!drm_mm_node_allocated(gtt_space))
3020                 return true;
3021
3022         if (list_empty(&gtt_space->node_list))
3023                 return true;
3024
3025         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3026         if (other->allocated && !other->hole_follows && other->color != cache_level)
3027                 return false;
3028
3029         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3030         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3031                 return false;
3032
3033         return true;
3034 }
3035
3036 static void i915_gem_verify_gtt(struct drm_device *dev)
3037 {
3038 #if WATCH_GTT
3039         struct drm_i915_private *dev_priv = dev->dev_private;
3040         struct drm_i915_gem_object *obj;
3041         int err = 0;
3042
3043         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3044                 if (obj->gtt_space == NULL) {
3045                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3046                         err++;
3047                         continue;
3048                 }
3049
3050                 if (obj->cache_level != obj->gtt_space->color) {
3051                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3052                                i915_gem_obj_ggtt_offset(obj),
3053                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3054                                obj->cache_level,
3055                                obj->gtt_space->color);
3056                         err++;
3057                         continue;
3058                 }
3059
3060                 if (!i915_gem_valid_gtt_space(dev,
3061                                               obj->gtt_space,
3062                                               obj->cache_level)) {
3063                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3064                                i915_gem_obj_ggtt_offset(obj),
3065                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3066                                obj->cache_level);
3067                         err++;
3068                         continue;
3069                 }
3070         }
3071
3072         WARN_ON(err);
3073 #endif
3074 }
3075
3076 /**
3077  * Finds free space in the GTT aperture and binds the object there.
3078  */
3079 static int
3080 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3081                             unsigned alignment,
3082                             bool map_and_fenceable,
3083                             bool nonblocking)
3084 {
3085         struct drm_device *dev = obj->base.dev;
3086         drm_i915_private_t *dev_priv = dev->dev_private;
3087         struct i915_address_space *vm = &dev_priv->gtt.base;
3088         u32 size, fence_size, fence_alignment, unfenced_alignment;
3089         bool mappable, fenceable;
3090         size_t gtt_max = map_and_fenceable ?
3091                 dev_priv->gtt.mappable_end : dev_priv->gtt.base.total;
3092         struct i915_vma *vma;
3093         int ret;
3094
3095         if (WARN_ON(!list_empty(&obj->vma_list)))
3096                 return -EBUSY;
3097
3098         fence_size = i915_gem_get_gtt_size(dev,
3099                                            obj->base.size,
3100                                            obj->tiling_mode);
3101         fence_alignment = i915_gem_get_gtt_alignment(dev,
3102                                                      obj->base.size,
3103                                                      obj->tiling_mode, true);
3104         unfenced_alignment =
3105                 i915_gem_get_gtt_alignment(dev,
3106                                                     obj->base.size,
3107                                                     obj->tiling_mode, false);
3108
3109         if (alignment == 0)
3110                 alignment = map_and_fenceable ? fence_alignment :
3111                                                 unfenced_alignment;
3112         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3113                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3114                 return -EINVAL;
3115         }
3116
3117         size = map_and_fenceable ? fence_size : obj->base.size;
3118
3119         /* If the object is bigger than the entire aperture, reject it early
3120          * before evicting everything in a vain attempt to find space.
3121          */
3122         if (obj->base.size > gtt_max) {
3123                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3124                           obj->base.size,
3125                           map_and_fenceable ? "mappable" : "total",
3126                           gtt_max);
3127                 return -E2BIG;
3128         }
3129
3130         ret = i915_gem_object_get_pages(obj);
3131         if (ret)
3132                 return ret;
3133
3134         i915_gem_object_pin_pages(obj);
3135
3136         vma = i915_gem_vma_create(obj, &dev_priv->gtt.base);
3137         if (vma == NULL) {
3138                 i915_gem_object_unpin_pages(obj);
3139                 return -ENOMEM;
3140         }
3141
3142 search_free:
3143         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
3144                                                   &vma->node,
3145                                                   size, alignment,
3146                                                   obj->cache_level, 0, gtt_max);
3147         if (ret) {
3148                 ret = i915_gem_evict_something(dev, size, alignment,
3149                                                obj->cache_level,
3150                                                map_and_fenceable,
3151                                                nonblocking);
3152                 if (ret == 0)
3153                         goto search_free;
3154
3155                 goto err_out;
3156         }
3157         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3158                                               obj->cache_level))) {
3159                 ret = -EINVAL;
3160                 goto err_out;
3161         }
3162
3163         ret = i915_gem_gtt_prepare_object(obj);
3164         if (ret)
3165                 goto err_out;
3166
3167         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3168         list_add_tail(&obj->mm_list, &vm->inactive_list);
3169         list_add(&vma->vma_link, &obj->vma_list);
3170
3171         fenceable =
3172                 i915_gem_obj_ggtt_size(obj) == fence_size &&
3173                 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3174
3175         mappable = i915_gem_obj_ggtt_offset(obj) + obj->base.size <=
3176                 dev_priv->gtt.mappable_end;
3177
3178         obj->map_and_fenceable = mappable && fenceable;
3179
3180         trace_i915_gem_object_bind(obj, map_and_fenceable);
3181         i915_gem_verify_gtt(dev);
3182         return 0;
3183
3184 err_out:
3185         i915_gem_vma_destroy(vma);
3186         i915_gem_object_unpin_pages(obj);
3187         drm_mm_remove_node(&vma->node);
3188         return ret;
3189 }
3190
3191 void
3192 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3193 {
3194         /* If we don't have a page list set up, then we're not pinned
3195          * to GPU, and we can ignore the cache flush because it'll happen
3196          * again at bind time.
3197          */
3198         if (obj->pages == NULL)
3199                 return;
3200
3201         /*
3202          * Stolen memory is always coherent with the GPU as it is explicitly
3203          * marked as wc by the system, or the system is cache-coherent.
3204          */
3205         if (obj->stolen)
3206                 return;
3207
3208         /* If the GPU is snooping the contents of the CPU cache,
3209          * we do not need to manually clear the CPU cache lines.  However,
3210          * the caches are only snooped when the render cache is
3211          * flushed/invalidated.  As we always have to emit invalidations
3212          * and flushes when moving into and out of the RENDER domain, correct
3213          * snooping behaviour occurs naturally as the result of our domain
3214          * tracking.
3215          */
3216         if (obj->cache_level != I915_CACHE_NONE)
3217                 return;
3218
3219         trace_i915_gem_object_clflush(obj);
3220
3221         drm_clflush_sg(obj->pages);
3222 }
3223
3224 /** Flushes the GTT write domain for the object if it's dirty. */
3225 static void
3226 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3227 {
3228         uint32_t old_write_domain;
3229
3230         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3231                 return;
3232
3233         /* No actual flushing is required for the GTT write domain.  Writes
3234          * to it immediately go to main memory as far as we know, so there's
3235          * no chipset flush.  It also doesn't land in render cache.
3236          *
3237          * However, we do have to enforce the order so that all writes through
3238          * the GTT land before any writes to the device, such as updates to
3239          * the GATT itself.
3240          */
3241         wmb();
3242
3243         old_write_domain = obj->base.write_domain;
3244         obj->base.write_domain = 0;
3245
3246         trace_i915_gem_object_change_domain(obj,
3247                                             obj->base.read_domains,
3248                                             old_write_domain);
3249 }
3250
3251 /** Flushes the CPU write domain for the object if it's dirty. */
3252 static void
3253 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3254 {
3255         uint32_t old_write_domain;
3256
3257         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3258                 return;
3259
3260         i915_gem_clflush_object(obj);
3261         i915_gem_chipset_flush(obj->base.dev);
3262         old_write_domain = obj->base.write_domain;
3263         obj->base.write_domain = 0;
3264
3265         trace_i915_gem_object_change_domain(obj,
3266                                             obj->base.read_domains,
3267                                             old_write_domain);
3268 }
3269
3270 /**
3271  * Moves a single object to the GTT read, and possibly write domain.
3272  *
3273  * This function returns when the move is complete, including waiting on
3274  * flushes to occur.
3275  */
3276 int
3277 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3278 {
3279         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3280         uint32_t old_write_domain, old_read_domains;
3281         int ret;
3282
3283         /* Not valid to be called on unbound objects. */
3284         if (!i915_gem_obj_ggtt_bound(obj))
3285                 return -EINVAL;
3286
3287         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3288                 return 0;
3289
3290         ret = i915_gem_object_wait_rendering(obj, !write);
3291         if (ret)
3292                 return ret;
3293
3294         i915_gem_object_flush_cpu_write_domain(obj);
3295
3296         /* Serialise direct access to this object with the barriers for
3297          * coherent writes from the GPU, by effectively invalidating the
3298          * GTT domain upon first access.
3299          */
3300         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3301                 mb();
3302
3303         old_write_domain = obj->base.write_domain;
3304         old_read_domains = obj->base.read_domains;
3305
3306         /* It should now be out of any other write domains, and we can update
3307          * the domain values for our changes.
3308          */
3309         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3310         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3311         if (write) {
3312                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3313                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3314                 obj->dirty = 1;
3315         }
3316
3317         trace_i915_gem_object_change_domain(obj,
3318                                             old_read_domains,
3319                                             old_write_domain);
3320
3321         /* And bump the LRU for this access */
3322         if (i915_gem_object_is_inactive(obj))
3323                 list_move_tail(&obj->mm_list,
3324                                &dev_priv->gtt.base.inactive_list);
3325
3326         return 0;
3327 }
3328
3329 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3330                                     enum i915_cache_level cache_level)
3331 {
3332         struct drm_device *dev = obj->base.dev;
3333         drm_i915_private_t *dev_priv = dev->dev_private;
3334         struct i915_vma *vma = __i915_gem_obj_to_vma(obj);
3335         int ret;
3336
3337         if (obj->cache_level == cache_level)
3338                 return 0;
3339
3340         if (obj->pin_count) {
3341                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3342                 return -EBUSY;
3343         }
3344
3345         if (vma && !i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3346                 ret = i915_gem_object_unbind(obj);
3347                 if (ret)
3348                         return ret;
3349         }
3350
3351         if (i915_gem_obj_ggtt_bound(obj)) {
3352                 ret = i915_gem_object_finish_gpu(obj);
3353                 if (ret)
3354                         return ret;
3355
3356                 i915_gem_object_finish_gtt(obj);
3357
3358                 /* Before SandyBridge, you could not use tiling or fence
3359                  * registers with snooped memory, so relinquish any fences
3360                  * currently pointing to our region in the aperture.
3361                  */
3362                 if (INTEL_INFO(dev)->gen < 6) {
3363                         ret = i915_gem_object_put_fence(obj);
3364                         if (ret)
3365                                 return ret;
3366                 }
3367
3368                 if (obj->has_global_gtt_mapping)
3369                         i915_gem_gtt_bind_object(obj, cache_level);
3370                 if (obj->has_aliasing_ppgtt_mapping)
3371                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3372                                                obj, cache_level);
3373
3374                 i915_gem_obj_ggtt_set_color(obj, cache_level);
3375         }
3376
3377         if (cache_level == I915_CACHE_NONE) {
3378                 u32 old_read_domains, old_write_domain;
3379
3380                 /* If we're coming from LLC cached, then we haven't
3381                  * actually been tracking whether the data is in the
3382                  * CPU cache or not, since we only allow one bit set
3383                  * in obj->write_domain and have been skipping the clflushes.
3384                  * Just set it to the CPU cache for now.
3385                  */
3386                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3387                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3388
3389                 old_read_domains = obj->base.read_domains;
3390                 old_write_domain = obj->base.write_domain;
3391
3392                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3393                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3394
3395                 trace_i915_gem_object_change_domain(obj,
3396                                                     old_read_domains,
3397                                                     old_write_domain);
3398         }
3399
3400         obj->cache_level = cache_level;
3401         i915_gem_verify_gtt(dev);
3402         return 0;
3403 }
3404
3405 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3406                                struct drm_file *file)
3407 {
3408         struct drm_i915_gem_caching *args = data;
3409         struct drm_i915_gem_object *obj;
3410         int ret;
3411
3412         ret = i915_mutex_lock_interruptible(dev);
3413         if (ret)
3414                 return ret;
3415
3416         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3417         if (&obj->base == NULL) {
3418                 ret = -ENOENT;
3419                 goto unlock;
3420         }
3421
3422         args->caching = obj->cache_level != I915_CACHE_NONE;
3423
3424         drm_gem_object_unreference(&obj->base);
3425 unlock:
3426         mutex_unlock(&dev->struct_mutex);
3427         return ret;
3428 }
3429
3430 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3431                                struct drm_file *file)
3432 {
3433         struct drm_i915_gem_caching *args = data;
3434         struct drm_i915_gem_object *obj;
3435         enum i915_cache_level level;
3436         int ret;
3437
3438         switch (args->caching) {
3439         case I915_CACHING_NONE:
3440                 level = I915_CACHE_NONE;
3441                 break;
3442         case I915_CACHING_CACHED:
3443                 level = I915_CACHE_LLC;
3444                 break;
3445         default:
3446                 return -EINVAL;
3447         }
3448
3449         ret = i915_mutex_lock_interruptible(dev);
3450         if (ret)
3451                 return ret;
3452
3453         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3454         if (&obj->base == NULL) {
3455                 ret = -ENOENT;
3456                 goto unlock;
3457         }
3458
3459         ret = i915_gem_object_set_cache_level(obj, level);
3460
3461         drm_gem_object_unreference(&obj->base);
3462 unlock:
3463         mutex_unlock(&dev->struct_mutex);
3464         return ret;
3465 }
3466
3467 /*
3468  * Prepare buffer for display plane (scanout, cursors, etc).
3469  * Can be called from an uninterruptible phase (modesetting) and allows
3470  * any flushes to be pipelined (for pageflips).
3471  */
3472 int
3473 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3474                                      u32 alignment,
3475                                      struct intel_ring_buffer *pipelined)
3476 {
3477         u32 old_read_domains, old_write_domain;
3478         int ret;
3479
3480         if (pipelined != obj->ring) {
3481                 ret = i915_gem_object_sync(obj, pipelined);
3482                 if (ret)
3483                         return ret;
3484         }
3485
3486         /* The display engine is not coherent with the LLC cache on gen6.  As
3487          * a result, we make sure that the pinning that is about to occur is
3488          * done with uncached PTEs. This is lowest common denominator for all
3489          * chipsets.
3490          *
3491          * However for gen6+, we could do better by using the GFDT bit instead
3492          * of uncaching, which would allow us to flush all the LLC-cached data
3493          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3494          */
3495         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3496         if (ret)
3497                 return ret;
3498
3499         /* As the user may map the buffer once pinned in the display plane
3500          * (e.g. libkms for the bootup splash), we have to ensure that we
3501          * always use map_and_fenceable for all scanout buffers.
3502          */
3503         ret = i915_gem_object_pin(obj, alignment, true, false);
3504         if (ret)
3505                 return ret;
3506
3507         i915_gem_object_flush_cpu_write_domain(obj);
3508
3509         old_write_domain = obj->base.write_domain;
3510         old_read_domains = obj->base.read_domains;
3511
3512         /* It should now be out of any other write domains, and we can update
3513          * the domain values for our changes.
3514          */
3515         obj->base.write_domain = 0;
3516         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3517
3518         trace_i915_gem_object_change_domain(obj,
3519                                             old_read_domains,
3520                                             old_write_domain);
3521
3522         return 0;
3523 }
3524
3525 int
3526 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3527 {
3528         int ret;
3529
3530         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3531                 return 0;
3532
3533         ret = i915_gem_object_wait_rendering(obj, false);
3534         if (ret)
3535                 return ret;
3536
3537         /* Ensure that we invalidate the GPU's caches and TLBs. */
3538         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3539         return 0;
3540 }
3541
3542 /**
3543  * Moves a single object to the CPU read, and possibly write domain.
3544  *
3545  * This function returns when the move is complete, including waiting on
3546  * flushes to occur.
3547  */
3548 int
3549 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3550 {
3551         uint32_t old_write_domain, old_read_domains;
3552         int ret;
3553
3554         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3555                 return 0;
3556
3557         ret = i915_gem_object_wait_rendering(obj, !write);
3558         if (ret)
3559                 return ret;
3560
3561         i915_gem_object_flush_gtt_write_domain(obj);
3562
3563         old_write_domain = obj->base.write_domain;
3564         old_read_domains = obj->base.read_domains;
3565
3566         /* Flush the CPU cache if it's still invalid. */
3567         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3568                 i915_gem_clflush_object(obj);
3569
3570                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3571         }
3572
3573         /* It should now be out of any other write domains, and we can update
3574          * the domain values for our changes.
3575          */
3576         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3577
3578         /* If we're writing through the CPU, then the GPU read domains will
3579          * need to be invalidated at next use.
3580          */
3581         if (write) {
3582                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3583                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3584         }
3585
3586         trace_i915_gem_object_change_domain(obj,
3587                                             old_read_domains,
3588                                             old_write_domain);
3589
3590         return 0;
3591 }
3592
3593 /* Throttle our rendering by waiting until the ring has completed our requests
3594  * emitted over 20 msec ago.
3595  *
3596  * Note that if we were to use the current jiffies each time around the loop,
3597  * we wouldn't escape the function with any frames outstanding if the time to
3598  * render a frame was over 20ms.
3599  *
3600  * This should get us reasonable parallelism between CPU and GPU but also
3601  * relatively low latency when blocking on a particular request to finish.
3602  */
3603 static int
3604 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3605 {
3606         struct drm_i915_private *dev_priv = dev->dev_private;
3607         struct drm_i915_file_private *file_priv = file->driver_priv;
3608         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3609         struct drm_i915_gem_request *request;
3610         struct intel_ring_buffer *ring = NULL;
3611         unsigned reset_counter;
3612         u32 seqno = 0;
3613         int ret;
3614
3615         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3616         if (ret)
3617                 return ret;
3618
3619         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3620         if (ret)
3621                 return ret;
3622
3623         spin_lock(&file_priv->mm.lock);
3624         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3625                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3626                         break;
3627
3628                 ring = request->ring;
3629                 seqno = request->seqno;
3630         }
3631         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3632         spin_unlock(&file_priv->mm.lock);
3633
3634         if (seqno == 0)
3635                 return 0;
3636
3637         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3638         if (ret == 0)
3639                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3640
3641         return ret;
3642 }
3643
3644 int
3645 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3646                     uint32_t alignment,
3647                     bool map_and_fenceable,
3648                     bool nonblocking)
3649 {
3650         int ret;
3651
3652         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3653                 return -EBUSY;
3654
3655         if (i915_gem_obj_ggtt_bound(obj)) {
3656                 if ((alignment && i915_gem_obj_ggtt_offset(obj) & (alignment - 1)) ||
3657                     (map_and_fenceable && !obj->map_and_fenceable)) {
3658                         WARN(obj->pin_count,
3659                              "bo is already pinned with incorrect alignment:"
3660                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3661                              " obj->map_and_fenceable=%d\n",
3662                              i915_gem_obj_ggtt_offset(obj), alignment,
3663                              map_and_fenceable,
3664                              obj->map_and_fenceable);
3665                         ret = i915_gem_object_unbind(obj);
3666                         if (ret)
3667                                 return ret;
3668                 }
3669         }
3670
3671         if (!i915_gem_obj_ggtt_bound(obj)) {
3672                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3673
3674                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3675                                                   map_and_fenceable,
3676                                                   nonblocking);
3677                 if (ret)
3678                         return ret;
3679
3680                 if (!dev_priv->mm.aliasing_ppgtt)
3681                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3682         }
3683
3684         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3685                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3686
3687         obj->pin_count++;
3688         obj->pin_mappable |= map_and_fenceable;
3689
3690         return 0;
3691 }
3692
3693 void
3694 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3695 {
3696         BUG_ON(obj->pin_count == 0);
3697         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
3698
3699         if (--obj->pin_count == 0)
3700                 obj->pin_mappable = false;
3701 }
3702
3703 int
3704 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3705                    struct drm_file *file)
3706 {
3707         struct drm_i915_gem_pin *args = data;
3708         struct drm_i915_gem_object *obj;
3709         int ret;
3710
3711         ret = i915_mutex_lock_interruptible(dev);
3712         if (ret)
3713                 return ret;
3714
3715         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3716         if (&obj->base == NULL) {
3717                 ret = -ENOENT;
3718                 goto unlock;
3719         }
3720
3721         if (obj->madv != I915_MADV_WILLNEED) {
3722                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3723                 ret = -EINVAL;
3724                 goto out;
3725         }
3726
3727         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3728                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3729                           args->handle);
3730                 ret = -EINVAL;
3731                 goto out;
3732         }
3733
3734         if (obj->user_pin_count == 0) {
3735                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3736                 if (ret)
3737                         goto out;
3738         }
3739
3740         obj->user_pin_count++;
3741         obj->pin_filp = file;
3742
3743         /* XXX - flush the CPU caches for pinned objects
3744          * as the X server doesn't manage domains yet
3745          */
3746         i915_gem_object_flush_cpu_write_domain(obj);
3747         args->offset = i915_gem_obj_ggtt_offset(obj);
3748 out:
3749         drm_gem_object_unreference(&obj->base);
3750 unlock:
3751         mutex_unlock(&dev->struct_mutex);
3752         return ret;
3753 }
3754
3755 int
3756 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3757                      struct drm_file *file)
3758 {
3759         struct drm_i915_gem_pin *args = data;
3760         struct drm_i915_gem_object *obj;
3761         int ret;
3762
3763         ret = i915_mutex_lock_interruptible(dev);
3764         if (ret)
3765                 return ret;
3766
3767         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3768         if (&obj->base == NULL) {
3769                 ret = -ENOENT;
3770                 goto unlock;
3771         }
3772
3773         if (obj->pin_filp != file) {
3774                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3775                           args->handle);
3776                 ret = -EINVAL;
3777                 goto out;
3778         }
3779         obj->user_pin_count--;
3780         if (obj->user_pin_count == 0) {
3781                 obj->pin_filp = NULL;
3782                 i915_gem_object_unpin(obj);
3783         }
3784
3785 out:
3786         drm_gem_object_unreference(&obj->base);
3787 unlock:
3788         mutex_unlock(&dev->struct_mutex);
3789         return ret;
3790 }
3791
3792 int
3793 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3794                     struct drm_file *file)
3795 {
3796         struct drm_i915_gem_busy *args = data;
3797         struct drm_i915_gem_object *obj;
3798         int ret;
3799
3800         ret = i915_mutex_lock_interruptible(dev);
3801         if (ret)
3802                 return ret;
3803
3804         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3805         if (&obj->base == NULL) {
3806                 ret = -ENOENT;
3807                 goto unlock;
3808         }
3809
3810         /* Count all active objects as busy, even if they are currently not used
3811          * by the gpu. Users of this interface expect objects to eventually
3812          * become non-busy without any further actions, therefore emit any
3813          * necessary flushes here.
3814          */
3815         ret = i915_gem_object_flush_active(obj);
3816
3817         args->busy = obj->active;
3818         if (obj->ring) {
3819                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3820                 args->busy |= intel_ring_flag(obj->ring) << 16;
3821         }
3822
3823         drm_gem_object_unreference(&obj->base);
3824 unlock:
3825         mutex_unlock(&dev->struct_mutex);
3826         return ret;
3827 }
3828
3829 int
3830 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3831                         struct drm_file *file_priv)
3832 {
3833         return i915_gem_ring_throttle(dev, file_priv);
3834 }
3835
3836 int
3837 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3838                        struct drm_file *file_priv)
3839 {
3840         struct drm_i915_gem_madvise *args = data;
3841         struct drm_i915_gem_object *obj;
3842         int ret;
3843
3844         switch (args->madv) {
3845         case I915_MADV_DONTNEED:
3846         case I915_MADV_WILLNEED:
3847             break;
3848         default:
3849             return -EINVAL;
3850         }
3851
3852         ret = i915_mutex_lock_interruptible(dev);
3853         if (ret)
3854                 return ret;
3855
3856         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3857         if (&obj->base == NULL) {
3858                 ret = -ENOENT;
3859                 goto unlock;
3860         }
3861
3862         if (obj->pin_count) {
3863                 ret = -EINVAL;
3864                 goto out;
3865         }
3866
3867         if (obj->madv != __I915_MADV_PURGED)
3868                 obj->madv = args->madv;
3869
3870         /* if the object is no longer attached, discard its backing storage */
3871         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3872                 i915_gem_object_truncate(obj);
3873
3874         args->retained = obj->madv != __I915_MADV_PURGED;
3875
3876 out:
3877         drm_gem_object_unreference(&obj->base);
3878 unlock:
3879         mutex_unlock(&dev->struct_mutex);
3880         return ret;
3881 }
3882
3883 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3884                           const struct drm_i915_gem_object_ops *ops)
3885 {
3886         INIT_LIST_HEAD(&obj->mm_list);
3887         INIT_LIST_HEAD(&obj->global_list);
3888         INIT_LIST_HEAD(&obj->ring_list);
3889         INIT_LIST_HEAD(&obj->exec_list);
3890         INIT_LIST_HEAD(&obj->vma_list);
3891
3892         obj->ops = ops;
3893
3894         obj->fence_reg = I915_FENCE_REG_NONE;
3895         obj->madv = I915_MADV_WILLNEED;
3896         /* Avoid an unnecessary call to unbind on the first bind. */
3897         obj->map_and_fenceable = true;
3898
3899         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3900 }
3901
3902 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3903         .get_pages = i915_gem_object_get_pages_gtt,
3904         .put_pages = i915_gem_object_put_pages_gtt,
3905 };
3906
3907 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3908                                                   size_t size)
3909 {
3910         struct drm_i915_gem_object *obj;
3911         struct address_space *mapping;
3912         gfp_t mask;
3913
3914         obj = i915_gem_object_alloc(dev);
3915         if (obj == NULL)
3916                 return NULL;
3917
3918         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3919                 i915_gem_object_free(obj);
3920                 return NULL;
3921         }
3922
3923         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3924         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3925                 /* 965gm cannot relocate objects above 4GiB. */
3926                 mask &= ~__GFP_HIGHMEM;
3927                 mask |= __GFP_DMA32;
3928         }
3929
3930         mapping = file_inode(obj->base.filp)->i_mapping;
3931         mapping_set_gfp_mask(mapping, mask);
3932
3933         i915_gem_object_init(obj, &i915_gem_object_ops);
3934
3935         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3936         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3937
3938         if (HAS_LLC(dev)) {
3939                 /* On some devices, we can have the GPU use the LLC (the CPU
3940                  * cache) for about a 10% performance improvement
3941                  * compared to uncached.  Graphics requests other than
3942                  * display scanout are coherent with the CPU in
3943                  * accessing this cache.  This means in this mode we
3944                  * don't need to clflush on the CPU side, and on the
3945                  * GPU side we only need to flush internal caches to
3946                  * get data visible to the CPU.
3947                  *
3948                  * However, we maintain the display planes as UC, and so
3949                  * need to rebind when first used as such.
3950                  */
3951                 obj->cache_level = I915_CACHE_LLC;
3952         } else
3953                 obj->cache_level = I915_CACHE_NONE;
3954
3955         return obj;
3956 }
3957
3958 int i915_gem_init_object(struct drm_gem_object *obj)
3959 {
3960         BUG();
3961
3962         return 0;
3963 }
3964
3965 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3966 {
3967         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3968         struct drm_device *dev = obj->base.dev;
3969         drm_i915_private_t *dev_priv = dev->dev_private;
3970
3971         trace_i915_gem_object_destroy(obj);
3972
3973         if (obj->phys_obj)
3974                 i915_gem_detach_phys_object(dev, obj);
3975
3976         obj->pin_count = 0;
3977         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3978                 bool was_interruptible;
3979
3980                 was_interruptible = dev_priv->mm.interruptible;
3981                 dev_priv->mm.interruptible = false;
3982
3983                 WARN_ON(i915_gem_object_unbind(obj));
3984
3985                 dev_priv->mm.interruptible = was_interruptible;
3986         }
3987
3988         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3989          * before progressing. */
3990         if (obj->stolen)
3991                 i915_gem_object_unpin_pages(obj);
3992
3993         if (WARN_ON(obj->pages_pin_count))
3994                 obj->pages_pin_count = 0;
3995         i915_gem_object_put_pages(obj);
3996         i915_gem_object_free_mmap_offset(obj);
3997         i915_gem_object_release_stolen(obj);
3998
3999         BUG_ON(obj->pages);
4000
4001         if (obj->base.import_attach)
4002                 drm_prime_gem_destroy(&obj->base, NULL);
4003
4004         drm_gem_object_release(&obj->base);
4005         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4006
4007         kfree(obj->bit_17);
4008         i915_gem_object_free(obj);
4009 }
4010
4011 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4012                                      struct i915_address_space *vm)
4013 {
4014         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4015         if (vma == NULL)
4016                 return ERR_PTR(-ENOMEM);
4017
4018         INIT_LIST_HEAD(&vma->vma_link);
4019         vma->vm = vm;
4020         vma->obj = obj;
4021
4022         return vma;
4023 }
4024
4025 void i915_gem_vma_destroy(struct i915_vma *vma)
4026 {
4027         WARN_ON(vma->node.allocated);
4028         kfree(vma);
4029 }
4030
4031 int
4032 i915_gem_idle(struct drm_device *dev)
4033 {
4034         drm_i915_private_t *dev_priv = dev->dev_private;
4035         int ret;
4036
4037         if (dev_priv->ums.mm_suspended) {
4038                 mutex_unlock(&dev->struct_mutex);
4039                 return 0;
4040         }
4041
4042         ret = i915_gpu_idle(dev);
4043         if (ret) {
4044                 mutex_unlock(&dev->struct_mutex);
4045                 return ret;
4046         }
4047         i915_gem_retire_requests(dev);
4048
4049         /* Under UMS, be paranoid and evict. */
4050         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4051                 i915_gem_evict_everything(dev);
4052
4053         i915_gem_reset_fences(dev);
4054
4055         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4056
4057         i915_kernel_lost_context(dev);
4058         i915_gem_cleanup_ringbuffer(dev);
4059
4060         /* Cancel the retire work handler, which should be idle now. */
4061         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4062
4063         return 0;
4064 }
4065
4066 void i915_gem_l3_remap(struct drm_device *dev)
4067 {
4068         drm_i915_private_t *dev_priv = dev->dev_private;
4069         u32 misccpctl;
4070         int i;
4071
4072         if (!HAS_L3_GPU_CACHE(dev))
4073                 return;
4074
4075         if (!dev_priv->l3_parity.remap_info)
4076                 return;
4077
4078         misccpctl = I915_READ(GEN7_MISCCPCTL);
4079         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4080         POSTING_READ(GEN7_MISCCPCTL);
4081
4082         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4083                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4084                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4085                         DRM_DEBUG("0x%x was already programmed to %x\n",
4086                                   GEN7_L3LOG_BASE + i, remap);
4087                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4088                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4089                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4090         }
4091
4092         /* Make sure all the writes land before disabling dop clock gating */
4093         POSTING_READ(GEN7_L3LOG_BASE);
4094
4095         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4096 }
4097
4098 void i915_gem_init_swizzling(struct drm_device *dev)
4099 {
4100         drm_i915_private_t *dev_priv = dev->dev_private;
4101
4102         if (INTEL_INFO(dev)->gen < 5 ||
4103             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4104                 return;
4105
4106         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4107                                  DISP_TILE_SURFACE_SWIZZLING);
4108
4109         if (IS_GEN5(dev))
4110                 return;
4111
4112         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4113         if (IS_GEN6(dev))
4114                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4115         else if (IS_GEN7(dev))
4116                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4117         else
4118                 BUG();
4119 }
4120
4121 static bool
4122 intel_enable_blt(struct drm_device *dev)
4123 {
4124         if (!HAS_BLT(dev))
4125                 return false;
4126
4127         /* The blitter was dysfunctional on early prototypes */
4128         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4129                 DRM_INFO("BLT not supported on this pre-production hardware;"
4130                          " graphics performance will be degraded.\n");
4131                 return false;
4132         }
4133
4134         return true;
4135 }
4136
4137 static int i915_gem_init_rings(struct drm_device *dev)
4138 {
4139         struct drm_i915_private *dev_priv = dev->dev_private;
4140         int ret;
4141
4142         ret = intel_init_render_ring_buffer(dev);
4143         if (ret)
4144                 return ret;
4145
4146         if (HAS_BSD(dev)) {
4147                 ret = intel_init_bsd_ring_buffer(dev);
4148                 if (ret)
4149                         goto cleanup_render_ring;
4150         }
4151
4152         if (intel_enable_blt(dev)) {
4153                 ret = intel_init_blt_ring_buffer(dev);
4154                 if (ret)
4155                         goto cleanup_bsd_ring;
4156         }
4157
4158         if (HAS_VEBOX(dev)) {
4159                 ret = intel_init_vebox_ring_buffer(dev);
4160                 if (ret)
4161                         goto cleanup_blt_ring;
4162         }
4163
4164
4165         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4166         if (ret)
4167                 goto cleanup_vebox_ring;
4168
4169         return 0;
4170
4171 cleanup_vebox_ring:
4172         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4173 cleanup_blt_ring:
4174         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4175 cleanup_bsd_ring:
4176         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4177 cleanup_render_ring:
4178         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4179
4180         return ret;
4181 }
4182
4183 int
4184 i915_gem_init_hw(struct drm_device *dev)
4185 {
4186         drm_i915_private_t *dev_priv = dev->dev_private;
4187         int ret;
4188
4189         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4190                 return -EIO;
4191
4192         if (dev_priv->ellc_size)
4193                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4194
4195         if (HAS_PCH_NOP(dev)) {
4196                 u32 temp = I915_READ(GEN7_MSG_CTL);
4197                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4198                 I915_WRITE(GEN7_MSG_CTL, temp);
4199         }
4200
4201         i915_gem_l3_remap(dev);
4202
4203         i915_gem_init_swizzling(dev);
4204
4205         ret = i915_gem_init_rings(dev);
4206         if (ret)
4207                 return ret;
4208
4209         /*
4210          * XXX: There was some w/a described somewhere suggesting loading
4211          * contexts before PPGTT.
4212          */
4213         i915_gem_context_init(dev);
4214         if (dev_priv->mm.aliasing_ppgtt) {
4215                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4216                 if (ret) {
4217                         i915_gem_cleanup_aliasing_ppgtt(dev);
4218                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4219                 }
4220         }
4221
4222         return 0;
4223 }
4224
4225 int i915_gem_init(struct drm_device *dev)
4226 {
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         int ret;
4229
4230         mutex_lock(&dev->struct_mutex);
4231
4232         if (IS_VALLEYVIEW(dev)) {
4233                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4234                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4235                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4236                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4237         }
4238
4239         i915_gem_init_global_gtt(dev);
4240
4241         ret = i915_gem_init_hw(dev);
4242         mutex_unlock(&dev->struct_mutex);
4243         if (ret) {
4244                 i915_gem_cleanup_aliasing_ppgtt(dev);
4245                 return ret;
4246         }
4247
4248         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4249         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4250                 dev_priv->dri1.allow_batchbuffer = 1;
4251         return 0;
4252 }
4253
4254 void
4255 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4256 {
4257         drm_i915_private_t *dev_priv = dev->dev_private;
4258         struct intel_ring_buffer *ring;
4259         int i;
4260
4261         for_each_ring(ring, dev_priv, i)
4262                 intel_cleanup_ring_buffer(ring);
4263 }
4264
4265 int
4266 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4267                        struct drm_file *file_priv)
4268 {
4269         struct drm_i915_private *dev_priv = dev->dev_private;
4270         int ret;
4271
4272         if (drm_core_check_feature(dev, DRIVER_MODESET))
4273                 return 0;
4274
4275         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4276                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4277                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4278         }
4279
4280         mutex_lock(&dev->struct_mutex);
4281         dev_priv->ums.mm_suspended = 0;
4282
4283         ret = i915_gem_init_hw(dev);
4284         if (ret != 0) {
4285                 mutex_unlock(&dev->struct_mutex);
4286                 return ret;
4287         }
4288
4289         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4290         mutex_unlock(&dev->struct_mutex);
4291
4292         ret = drm_irq_install(dev);
4293         if (ret)
4294                 goto cleanup_ringbuffer;
4295
4296         return 0;
4297
4298 cleanup_ringbuffer:
4299         mutex_lock(&dev->struct_mutex);
4300         i915_gem_cleanup_ringbuffer(dev);
4301         dev_priv->ums.mm_suspended = 1;
4302         mutex_unlock(&dev->struct_mutex);
4303
4304         return ret;
4305 }
4306
4307 int
4308 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4309                        struct drm_file *file_priv)
4310 {
4311         struct drm_i915_private *dev_priv = dev->dev_private;
4312         int ret;
4313
4314         if (drm_core_check_feature(dev, DRIVER_MODESET))
4315                 return 0;
4316
4317         drm_irq_uninstall(dev);
4318
4319         mutex_lock(&dev->struct_mutex);
4320         ret =  i915_gem_idle(dev);
4321
4322         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4323          * We need to replace this with a semaphore, or something.
4324          * And not confound ums.mm_suspended!
4325          */
4326         if (ret != 0)
4327                 dev_priv->ums.mm_suspended = 1;
4328         mutex_unlock(&dev->struct_mutex);
4329
4330         return ret;
4331 }
4332
4333 void
4334 i915_gem_lastclose(struct drm_device *dev)
4335 {
4336         int ret;
4337
4338         if (drm_core_check_feature(dev, DRIVER_MODESET))
4339                 return;
4340
4341         mutex_lock(&dev->struct_mutex);
4342         ret = i915_gem_idle(dev);
4343         if (ret)
4344                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4345         mutex_unlock(&dev->struct_mutex);
4346 }
4347
4348 static void
4349 init_ring_lists(struct intel_ring_buffer *ring)
4350 {
4351         INIT_LIST_HEAD(&ring->active_list);
4352         INIT_LIST_HEAD(&ring->request_list);
4353 }
4354
4355 void
4356 i915_gem_load(struct drm_device *dev)
4357 {
4358         drm_i915_private_t *dev_priv = dev->dev_private;
4359         int i;
4360
4361         dev_priv->slab =
4362                 kmem_cache_create("i915_gem_object",
4363                                   sizeof(struct drm_i915_gem_object), 0,
4364                                   SLAB_HWCACHE_ALIGN,
4365                                   NULL);
4366
4367         INIT_LIST_HEAD(&dev_priv->gtt.base.active_list);
4368         INIT_LIST_HEAD(&dev_priv->gtt.base.inactive_list);
4369         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4370         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4371         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4372         for (i = 0; i < I915_NUM_RINGS; i++)
4373                 init_ring_lists(&dev_priv->ring[i]);
4374         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4375                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4376         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4377                           i915_gem_retire_work_handler);
4378         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4379
4380         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4381         if (IS_GEN3(dev)) {
4382                 I915_WRITE(MI_ARB_STATE,
4383                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4384         }
4385
4386         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4387
4388         /* Old X drivers will take 0-2 for front, back, depth buffers */
4389         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4390                 dev_priv->fence_reg_start = 3;
4391
4392         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4393                 dev_priv->num_fence_regs = 32;
4394         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4395                 dev_priv->num_fence_regs = 16;
4396         else
4397                 dev_priv->num_fence_regs = 8;
4398
4399         /* Initialize fence registers to zero */
4400         i915_gem_reset_fences(dev);
4401
4402         i915_gem_detect_bit_6_swizzle(dev);
4403         init_waitqueue_head(&dev_priv->pending_flip_queue);
4404
4405         dev_priv->mm.interruptible = true;
4406
4407         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4408         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4409         register_shrinker(&dev_priv->mm.inactive_shrinker);
4410 }
4411
4412 /*
4413  * Create a physically contiguous memory object for this object
4414  * e.g. for cursor + overlay regs
4415  */
4416 static int i915_gem_init_phys_object(struct drm_device *dev,
4417                                      int id, int size, int align)
4418 {
4419         drm_i915_private_t *dev_priv = dev->dev_private;
4420         struct drm_i915_gem_phys_object *phys_obj;
4421         int ret;
4422
4423         if (dev_priv->mm.phys_objs[id - 1] || !size)
4424                 return 0;
4425
4426         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4427         if (!phys_obj)
4428                 return -ENOMEM;
4429
4430         phys_obj->id = id;
4431
4432         phys_obj->handle = drm_pci_alloc(dev, size, align);
4433         if (!phys_obj->handle) {
4434                 ret = -ENOMEM;
4435                 goto kfree_obj;
4436         }
4437 #ifdef CONFIG_X86
4438         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4439 #endif
4440
4441         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4442
4443         return 0;
4444 kfree_obj:
4445         kfree(phys_obj);
4446         return ret;
4447 }
4448
4449 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4450 {
4451         drm_i915_private_t *dev_priv = dev->dev_private;
4452         struct drm_i915_gem_phys_object *phys_obj;
4453
4454         if (!dev_priv->mm.phys_objs[id - 1])
4455                 return;
4456
4457         phys_obj = dev_priv->mm.phys_objs[id - 1];
4458         if (phys_obj->cur_obj) {
4459                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4460         }
4461
4462 #ifdef CONFIG_X86
4463         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4464 #endif
4465         drm_pci_free(dev, phys_obj->handle);
4466         kfree(phys_obj);
4467         dev_priv->mm.phys_objs[id - 1] = NULL;
4468 }
4469
4470 void i915_gem_free_all_phys_object(struct drm_device *dev)
4471 {
4472         int i;
4473
4474         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4475                 i915_gem_free_phys_object(dev, i);
4476 }
4477
4478 void i915_gem_detach_phys_object(struct drm_device *dev,
4479                                  struct drm_i915_gem_object *obj)
4480 {
4481         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4482         char *vaddr;
4483         int i;
4484         int page_count;
4485
4486         if (!obj->phys_obj)
4487                 return;
4488         vaddr = obj->phys_obj->handle->vaddr;
4489
4490         page_count = obj->base.size / PAGE_SIZE;
4491         for (i = 0; i < page_count; i++) {
4492                 struct page *page = shmem_read_mapping_page(mapping, i);
4493                 if (!IS_ERR(page)) {
4494                         char *dst = kmap_atomic(page);
4495                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4496                         kunmap_atomic(dst);
4497
4498                         drm_clflush_pages(&page, 1);
4499
4500                         set_page_dirty(page);
4501                         mark_page_accessed(page);
4502                         page_cache_release(page);
4503                 }
4504         }
4505         i915_gem_chipset_flush(dev);
4506
4507         obj->phys_obj->cur_obj = NULL;
4508         obj->phys_obj = NULL;
4509 }
4510
4511 int
4512 i915_gem_attach_phys_object(struct drm_device *dev,
4513                             struct drm_i915_gem_object *obj,
4514                             int id,
4515                             int align)
4516 {
4517         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4518         drm_i915_private_t *dev_priv = dev->dev_private;
4519         int ret = 0;
4520         int page_count;
4521         int i;
4522
4523         if (id > I915_MAX_PHYS_OBJECT)
4524                 return -EINVAL;
4525
4526         if (obj->phys_obj) {
4527                 if (obj->phys_obj->id == id)
4528                         return 0;
4529                 i915_gem_detach_phys_object(dev, obj);
4530         }
4531
4532         /* create a new object */
4533         if (!dev_priv->mm.phys_objs[id - 1]) {
4534                 ret = i915_gem_init_phys_object(dev, id,
4535                                                 obj->base.size, align);
4536                 if (ret) {
4537                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4538                                   id, obj->base.size);
4539                         return ret;
4540                 }
4541         }
4542
4543         /* bind to the object */
4544         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4545         obj->phys_obj->cur_obj = obj;
4546
4547         page_count = obj->base.size / PAGE_SIZE;
4548
4549         for (i = 0; i < page_count; i++) {
4550                 struct page *page;
4551                 char *dst, *src;
4552
4553                 page = shmem_read_mapping_page(mapping, i);
4554                 if (IS_ERR(page))
4555                         return PTR_ERR(page);
4556
4557                 src = kmap_atomic(page);
4558                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4559                 memcpy(dst, src, PAGE_SIZE);
4560                 kunmap_atomic(src);
4561
4562                 mark_page_accessed(page);
4563                 page_cache_release(page);
4564         }
4565
4566         return 0;
4567 }
4568
4569 static int
4570 i915_gem_phys_pwrite(struct drm_device *dev,
4571                      struct drm_i915_gem_object *obj,
4572                      struct drm_i915_gem_pwrite *args,
4573                      struct drm_file *file_priv)
4574 {
4575         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4576         char __user *user_data = to_user_ptr(args->data_ptr);
4577
4578         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4579                 unsigned long unwritten;
4580
4581                 /* The physical object once assigned is fixed for the lifetime
4582                  * of the obj, so we can safely drop the lock and continue
4583                  * to access vaddr.
4584                  */
4585                 mutex_unlock(&dev->struct_mutex);
4586                 unwritten = copy_from_user(vaddr, user_data, args->size);
4587                 mutex_lock(&dev->struct_mutex);
4588                 if (unwritten)
4589                         return -EFAULT;
4590         }
4591
4592         i915_gem_chipset_flush(dev);
4593         return 0;
4594 }
4595
4596 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4597 {
4598         struct drm_i915_file_private *file_priv = file->driver_priv;
4599
4600         /* Clean up our request list when the client is going away, so that
4601          * later retire_requests won't dereference our soon-to-be-gone
4602          * file_priv.
4603          */
4604         spin_lock(&file_priv->mm.lock);
4605         while (!list_empty(&file_priv->mm.request_list)) {
4606                 struct drm_i915_gem_request *request;
4607
4608                 request = list_first_entry(&file_priv->mm.request_list,
4609                                            struct drm_i915_gem_request,
4610                                            client_list);
4611                 list_del(&request->client_list);
4612                 request->file_priv = NULL;
4613         }
4614         spin_unlock(&file_priv->mm.lock);
4615 }
4616
4617 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4618 {
4619         if (!mutex_is_locked(mutex))
4620                 return false;
4621
4622 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4623         return mutex->owner == task;
4624 #else
4625         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4626         return false;
4627 #endif
4628 }
4629
4630 static int
4631 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4632 {
4633         struct drm_i915_private *dev_priv =
4634                 container_of(shrinker,
4635                              struct drm_i915_private,
4636                              mm.inactive_shrinker);
4637         struct drm_device *dev = dev_priv->dev;
4638         struct i915_address_space *vm = &dev_priv->gtt.base;
4639         struct drm_i915_gem_object *obj;
4640         int nr_to_scan = sc->nr_to_scan;
4641         bool unlock = true;
4642         int cnt;
4643
4644         if (!mutex_trylock(&dev->struct_mutex)) {
4645                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4646                         return 0;
4647
4648                 if (dev_priv->mm.shrinker_no_lock_stealing)
4649                         return 0;
4650
4651                 unlock = false;
4652         }
4653
4654         if (nr_to_scan) {
4655                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4656                 if (nr_to_scan > 0)
4657                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4658                                                         false);
4659                 if (nr_to_scan > 0)
4660                         i915_gem_shrink_all(dev_priv);
4661         }
4662
4663         cnt = 0;
4664         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4665                 if (obj->pages_pin_count == 0)
4666                         cnt += obj->base.size >> PAGE_SHIFT;
4667         list_for_each_entry(obj, &vm->inactive_list, global_list)
4668                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4669                         cnt += obj->base.size >> PAGE_SHIFT;
4670
4671         if (unlock)
4672                 mutex_unlock(&dev->struct_mutex);
4673         return cnt;
4674 }